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JP4461968B2 - Semiconductor light emitting device - Google Patents
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JP4461968B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP4461968B2
JP4461968B2 JP2004257935A JP2004257935A JP4461968B2 JP 4461968 B2 JP4461968 B2 JP 4461968B2 JP 2004257935 A JP2004257935 A JP 2004257935A JP 2004257935 A JP2004257935 A JP 2004257935A JP 4461968 B2 JP4461968 B2 JP 4461968B2
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semiconductor light
light emitting
portions
resist layer
emitting device
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JP2006073911A (en
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聡 畠中
崇彰 鬼塚
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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Description

本発明は、絶縁性基板上に搭載された半導体発光素子とこれを覆う樹脂パッケージとを備えた半導体発光装置に関する。   The present invention relates to a semiconductor light emitting device including a semiconductor light emitting element mounted on an insulating substrate and a resin package covering the semiconductor light emitting element.

電気機器の小型化にともなって、各種表示装置の光源として使用される半導体発光装置は、一層の小型化および薄型化が求められており、近年では、絶縁性基板上に半導体発光素子を搭載した面実装タイプの半導体発光装置が多く用いられている。   With the miniaturization of electrical equipment, semiconductor light-emitting devices used as light sources for various display devices are required to be further reduced in size and thickness. In recent years, semiconductor light-emitting elements are mounted on an insulating substrate. Surface mount type semiconductor light emitting devices are often used.

図4(A)は、従来の半導体発光装置の平断面図を示す。図4(A)に示すように、従来の半導体発光装置70は、絶縁性基板71と、絶縁性基板71に搭載された半導体発光素子72,73と、半導体発光素子72,73を覆う透光性の樹脂パッケージ74とを有している。   FIG. 4A is a plan sectional view of a conventional semiconductor light emitting device. As shown in FIG. 4A, a conventional semiconductor light emitting device 70 includes an insulating substrate 71, semiconductor light emitting elements 72 and 73 mounted on the insulating substrate 71, and translucent covering the semiconductor light emitting elements 72 and 73. Resin package 74.

絶縁性基板71は、両側に形成された端子部75〜78と、上面の中間部に形成された配線部79〜82とを備えている。端子部75〜78と配線部79〜82とは、接続部83〜86を介してそれぞれ接続されている。   The insulating substrate 71 includes terminal portions 75 to 78 formed on both sides and wiring portions 79 to 82 formed in the middle portion on the upper surface. Terminal portions 75 to 78 and wiring portions 79 to 82 are connected to each other through connecting portions 83 to 86.

絶縁性基板71の一側に配置された接続部83,84の上面には、略矩形の樹脂レジスト層87が形成され、他側に配置された接続部85,86の上面にも同様に、樹脂レジスト層88が形成されている。   A substantially rectangular resin resist layer 87 is formed on the upper surfaces of the connection portions 83 and 84 arranged on one side of the insulating substrate 71, and similarly, the upper surfaces of the connection portions 85 and 86 arranged on the other side are also similar. A resin resist layer 88 is formed.

樹脂レジスト層87,88によって、各端子部75〜78と配線部79〜82とは、表面が分離するように形成されている。   The terminal portions 75 to 78 and the wiring portions 79 to 82 are formed by the resin resist layers 87 and 88 so that the surfaces are separated.

樹脂パッケージ74の両側端は、端子部75〜78の内側(基板中央側)端と略一致するように配置され、樹脂レジスト層87,88の内側端は、樹脂パッケージ74の両側端より少し内側に配置されている。   Both side ends of the resin package 74 are arranged so as to substantially coincide with the inner side (substrate center side) ends of the terminal portions 75 to 78, and the inner ends of the resin resist layers 87 and 88 are slightly inside the both side ends of the resin package 74. Is arranged.

絶縁性基板71の端子部75〜78は、両側端面および裏面まで延長して断面溝形に形成されている。半導体発光装置70は、客先で他の電子機器を製造するための大型基板にリフロー等により搭載される。このとき、端子部75〜78の裏面および側端面は、半田によって大型基板に導通接続される。   The terminal portions 75 to 78 of the insulating substrate 71 are formed in a cross-sectional groove shape extending to both side end surfaces and the back surface. The semiconductor light emitting device 70 is mounted by reflow or the like on a large substrate for manufacturing other electronic devices at the customer site. At this time, the back surfaces and side end surfaces of the terminal portions 75 to 78 are conductively connected to the large substrate by soldering.

このとき、半田が表面に乗り上げることがあるが、樹脂レジスト層87,88が設けられているので、配線部79〜82に半田が侵入することがなくなる。   At this time, the solder may run on the surface, but since the resin resist layers 87 and 88 are provided, the solder does not enter the wiring portions 79 to 82.

目的は異なるが、絶縁性基板71の表面に樹脂レジスト層を設けた半導体発光装置として、例えば、特許文献1に記載したものがある。
特開平8−330637号公報(第2−4頁、第1図)
For example, Patent Document 1 discloses a semiconductor light emitting device in which a resin resist layer is provided on the surface of an insulating substrate 71, although the purpose is different.
JP-A-8-330637 (page 2-4, FIG. 1)

しかしながら、半導体発光装置の小型化に伴い、配線部や端子部等の導通パターンと樹脂レジスト層のパターンが微細化し、相対位置のずれが発生しやすくなる。   However, with the miniaturization of the semiconductor light emitting device, the conductive pattern such as the wiring portion and the terminal portion and the pattern of the resin resist layer are miniaturized, and the relative position is likely to shift.

図4(B)は、従来の半導体発光装置の樹脂レジスト層のパターンがずれた状態の平断面図を示す。図4(B)に示すように、例えば、樹脂レジスト層87,88が絶縁性基板71の一側の端子部75,76側にずれると、端子部75,76と配線部79,80の表面が接続され、端子部75,76の表面に乗り上げた半田が配線部79,80に侵入し、配線部79,80を覆って形成されている樹脂パッケージ74と配線部79とを剥離させ、配線部79などのワイヤボンディングエリアに半田が到達した場合には、ワイヤボンド部にストレスを与え、断線を引き起こすという問題が発生する。   FIG. 4B is a plan sectional view showing a state in which the pattern of the resin resist layer of the conventional semiconductor light emitting device is shifted. As shown in FIG. 4B, for example, when the resin resist layers 87 and 88 are shifted to the terminal portions 75 and 76 on one side of the insulating substrate 71, the surfaces of the terminal portions 75 and 76 and the wiring portions 79 and 80 are obtained. Is connected, and the solder that has run on the surfaces of the terminal portions 75 and 76 enters the wiring portions 79 and 80, and the resin package 74 and the wiring portion 79 formed to cover the wiring portions 79 and 80 are peeled off, thereby When the solder reaches the wire bonding area such as the portion 79, there is a problem that stress is applied to the wire bonding portion to cause disconnection.

ここで、特許文献1に記載された半導体発光装置は、樹脂パッケージの外側端(接合線)の全体を樹脂レジスト層で覆っているが、この場合は、以下のような問題が発生する。   Here, the semiconductor light emitting device described in Patent Document 1 covers the entire outer end (bonding line) of the resin package with a resin resist layer. In this case, the following problem occurs.

一般にこのような半導体発光装置は、集合基板に棒状に形成したものを切断して形成するが、特許文献1に記載された半導体発光装置の構成では、封止ライン上に樹脂レジスト層が敷設されているため、レジスト作成時のばらつきを考慮すると、ダイスボンドエリアやワイヤーボンドエリアなどの配線レイアウトに必要な範囲が小さくなるという問題がある。   In general, such a semiconductor light emitting device is formed by cutting a rod-shaped member formed on a collective substrate. However, in the configuration of the semiconductor light emitting device described in Patent Document 1, a resin resist layer is laid on a sealing line. Therefore, in consideration of variations in resist formation, there is a problem that a range necessary for wiring layout such as a die bond area and a wire bond area becomes small.

また、半導体発光装置の多色化の要請に応えるためには複数の素子を搭載する必要があり、さらに、部品の小型化の要請もあるが、半導体発光素子やワイヤのボンディング部分の必要面積に限界があるため、この面積を確保するためには、金型内に配置される樹脂レジスト層の面積は小さい方が好ましい。   In order to meet the demand for multicolored semiconductor light-emitting devices, it is necessary to mount multiple elements, and there is also a demand for miniaturization of parts. Since there is a limit, in order to secure this area, it is preferable that the area of the resin resist layer disposed in the mold is small.

そこで本発明は、レジスト層の面積を小さくした状態で、樹脂パッケージ内への半田侵入を防止する半導体発光装置を提供することを目的とする。   Accordingly, an object of the present invention is to provide a semiconductor light emitting device that prevents solder from entering a resin package in a state where the area of a resist layer is reduced.

本発明の半導体発光装置においては、絶縁性基板の端子部と配線部との接続部に隣接する位置にそれぞれ切欠き部を形成したものである。   In the semiconductor light emitting device of the present invention, notches are respectively formed at positions adjacent to the connecting portion between the terminal portion and the wiring portion of the insulating substrate.

この発明によれば、レジスト層の面積を小さくした状態で、樹脂パッケージ内への半田侵入を防止する半導体発光装置が得られる。   According to the present invention, it is possible to obtain a semiconductor light emitting device that prevents the solder from entering the resin package while reducing the area of the resist layer.

本発明によれば、端子部の接続部に隣接する位置に、切欠き部をそれぞれ形成しているので、樹脂レジスト層の位置がずれても、端子部と配線部の間に切欠き部による隙間が形成され、半田が配線部に侵入することがなくなり、樹脂パッケージの割れを防止することができる。   According to the present invention, since the notch portions are formed at positions adjacent to the connection portions of the terminal portions, even if the position of the resin resist layer is shifted, the notch portions are formed between the terminal portions and the wiring portions. A gap is formed so that solder does not enter the wiring portion, and cracking of the resin package can be prevented.

また、半導体発光素子を二台設け、端子部と配線部をL字状に接続すると、切欠き部の数が各接続部に対してそれぞれ1つずつで済み、導通パターンの形状を簡単にして、歩留まりを向上させることができる。   In addition, when two semiconductor light emitting elements are provided and the terminal portion and the wiring portion are connected in an L shape, the number of notches is only one for each connecting portion, and the shape of the conduction pattern is simplified. Yield can be improved.

本願の第1の発明は、絶縁性基板の表面の両側に対となる端子部が形成され、前記表面の中間部に形成された対となる配線部が、両前記端子部に接続部を介してそれぞれ接続され、各前記配線部を半導体発光素子にそれぞれ接続し、各前記配線部および前記半導体発光素子を覆う樹脂パッケージ部を形成し、各前記接続部を覆う樹脂レジスト層を形成した半導体発光装置において、前記端子部の前記接続部に隣接する位置には、切欠き部がそれぞれ形成されていることを特徴としたものであり、樹脂レジスト層の位置がずれても、端子部と配線部の間に切欠き部による隙間が形成されるので、半田が配線部に侵入することがなくなるという作用を有する。   In the first invention of the present application, a pair of terminal portions are formed on both sides of the surface of the insulating substrate, and a pair of wiring portions formed in an intermediate portion of the surface are connected to both the terminal portions via connection portions. A semiconductor light emitting device in which each of the wiring portions is connected to a semiconductor light emitting element, a resin package portion covering each of the wiring portions and the semiconductor light emitting element is formed, and a resin resist layer covering each of the connection portions is formed. In the apparatus, a notch portion is formed at a position adjacent to the connection portion of the terminal portion, and even if the position of the resin resist layer is shifted, the terminal portion and the wiring portion Since a gap due to the notch is formed between them, the solder does not enter the wiring part.

本願の第2の発明は、前記半導体発光素子は二台設けられ、前記端子部、前記配線部および前記接続部は二対ずつ設けられ、前記端子部と前記配線部はL字状に接続されていることを特徴としたものであり、端子部と配線部をL字状に接続しているので、切欠き部の数は各接続部に対してそれぞれ1つずつで済み、導通パターンの形状を簡単にすることができる。   According to a second invention of the present application, two semiconductor light emitting elements are provided, the terminal part, the wiring part, and the connection part are provided in pairs, and the terminal part and the wiring part are connected in an L shape. Since the terminal portion and the wiring portion are connected in an L shape, the number of notches is only one for each connecting portion, and the shape of the conductive pattern Can be easy.

以下、本発明の実施の形態について、図1から図3を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.

(第1の実施の形態)
図1(A)は本発明の第1の実施の形態の半導体発光装置の平断面図、(B)は、同半導体発光装置の樹脂レジスト層のパターンがずれた状態の平断面図を示す。図2は、本発明の第1の実施の形態の半導体発光装置の斜視図である。
(First embodiment)
FIG. 1A is a plan sectional view of the semiconductor light emitting device according to the first embodiment of the present invention, and FIG. 1B is a plan sectional view of the semiconductor light emitting device in which the pattern of the resin resist layer is shifted. FIG. 2 is a perspective view of the semiconductor light emitting device according to the first embodiment of the present invention.

図1および図2に示すように、第1の実施の形態の半導体発光装置1は、矩形の絶縁性基板2と、絶縁性基板2の中間部に搭載された矩形の半導体発光素子3,4と、半導体発光素子3,4を覆う矩形の樹脂パッケージ部5とを有している。   As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 according to the first embodiment includes a rectangular insulating substrate 2 and rectangular semiconductor light emitting elements 3 and 4 mounted on an intermediate portion of the insulating substrate 2. And a rectangular resin package part 5 that covers the semiconductor light emitting elements 3 and 4.

絶縁性基板2の表面の一側には、端子部6,7が形成され、他側には、端子部8,9が形成されている。端子部6〜9の内側(基板中央側)端は、樹脂パッケージ5の両側端と略一致するように配置されている。また、端子部6〜9は、それぞれ両側端面および裏面まで延長して断面溝形に形成されている。   Terminal portions 6 and 7 are formed on one side of the surface of the insulating substrate 2, and terminal portions 8 and 9 are formed on the other side. Inner ends (substrate center side) ends of the terminal portions 6 to 9 are arranged so as to substantially coincide with both side ends of the resin package 5. Moreover, the terminal parts 6-9 are each formed in the cross-sectional groove shape extended to a both-ends end surface and a back surface.

絶縁性基板2の中間部には、二対の配線部10,11が形成されている。配線部10,11は、それぞれ半導体発光素子3,4の底面に導電性ペースト12を介して接着される素子搭載部13,14と、半導体発光素子3,4にワイヤボンディングにより接続されるワイヤ接続部15,16とを有している。   Two pairs of wiring portions 10 and 11 are formed in the intermediate portion of the insulating substrate 2. The wiring parts 10 and 11 are respectively element mounting parts 13 and 14 bonded to the bottom surfaces of the semiconductor light emitting elements 3 and 4 via the conductive paste 12, and wire connections connected to the semiconductor light emitting elements 3 and 4 by wire bonding. Parts 15 and 16.

素子搭載部13,14およびワイヤ接続部15,16は、端子部6,7の近接する方の各端部および端子部8,9の近接する方の各端部にそれぞれL字状に接続されている。   The element mounting portions 13 and 14 and the wire connecting portions 15 and 16 are connected in an L shape to the end portions of the terminal portions 6 and 7 that are close to each other and the end portions of the terminal portions 8 and 9 that are close to each other. ing.

なお、端子部6〜9と配線部10,11との接続部分のうち、樹脂パッケージ部5の外側端に重なっている直線部分(図1中に二点鎖線で示す部分)を接続部17〜20としている。   Of the connecting portions between the terminal portions 6 to 9 and the wiring portions 10 and 11, straight portions (portions indicated by two-dot chain lines in FIG. 1) overlapping the outer ends of the resin package portion 5 are connected portions 17 to It is set to 20.

半導体発光素子3は、n電極とp電極を上面に備えたタイプの素子で、ワイヤ接続部15とn電極とをワイヤ27で接続している。また、素子搭載部13の接続部17に連通する部分の途中位置には、一端をp電極に接続したワイヤ29が接続されている。   The semiconductor light emitting element 3 is an element having an n electrode and a p electrode on the upper surface, and the wire connection portion 15 and the n electrode are connected by a wire 27. Further, a wire 29 having one end connected to the p-electrode is connected to an intermediate position of a portion communicating with the connection portion 17 of the element mounting portion 13.

半導体発光素子4は、n電極を下面に備え、p電極を上面に備えたタイプの素子で、ワイヤ接続部16とp電極とをワイヤ30で接続している。   The semiconductor light emitting element 4 is an element having an n electrode on the lower surface and a p electrode on the upper surface, and the wire connecting portion 16 and the p electrode are connected by a wire 30.

端子部6〜9の接続部17〜20に隣接する位置には、切欠き部21〜24がそれぞれ形成されている。切欠き部21〜24は同形状に形成されている。   Cutout portions 21 to 24 are formed at positions adjacent to the connection portions 17 to 20 of the terminal portions 6 to 9, respectively. The notches 21 to 24 are formed in the same shape.

切欠き部21,22および接続部17,18は、外側の2箇所の角部を丸めた略矩形状の樹脂レジスト層25で覆われている。また、切欠き部23,24および接続部19,20も、外側の2箇所の角部を丸めた略矩形状の樹脂レジスト層26で覆われている。   The notches 21 and 22 and the connecting portions 17 and 18 are covered with a substantially rectangular resin resist layer 25 having rounded corners at two outer sides. In addition, the notches 23 and 24 and the connecting portions 19 and 20 are also covered with a substantially rectangular resin resist layer 26 in which two corners on the outside are rounded.

切欠き部23,24は、角を丸めた台形状に形成されている。   The notches 23 and 24 are formed in a trapezoidal shape with rounded corners.

切欠き部23,24のX方向の最短距離bと、Y方向の外側端および端子部8,9の内側端の間のY方向の距離Tとは、端子部8,9が切断されない範囲に設定されている。   The shortest distance b in the X direction of the notches 23 and 24 and the distance T in the Y direction between the outer end in the Y direction and the inner ends of the terminal portions 8 and 9 are within a range in which the terminal portions 8 and 9 are not cut. Is set.

樹脂レジスト層26のX方向の幅Bは、樹脂レジスト層26を印刷するときの導通パターンに対するX方向の最大相対ずれ幅s1と、切欠き部23,24間の最短距離bとの和以上になるように設定している。   The width B in the X direction of the resin resist layer 26 is greater than or equal to the sum of the maximum relative displacement width s1 in the X direction with respect to the conductive pattern when the resin resist layer 26 is printed and the shortest distance b between the notches 23 and 24. It is set to be.

樹脂レジスト層26の内側端から切欠き部23,24の底辺までのY方向の距離tは、切欠き部23,24のY方向の距離Tと同じか、それより大きく設定され、また、距離Tは、樹脂レジスト層26を印刷するときの導通パターンに対するY方向の最大相対ずれ幅s2よりも大きくなるように設定されている。   The distance t in the Y direction from the inner end of the resin resist layer 26 to the bottom sides of the notches 23 and 24 is set to be equal to or larger than the distance T in the Y direction of the notches 23 and 24. T is set to be larger than the maximum relative deviation width s2 in the Y direction with respect to the conductive pattern when the resin resist layer 26 is printed.

なお、樹脂レジスト層26を印刷するときのずれ幅は、X方向もY方向も同じ程度と考えられるので、s1=s2として設定してよい。   It should be noted that the displacement width when printing the resin resist layer 26 is considered to be the same in both the X direction and the Y direction, and may be set as s1 = s2.

かかる構成によって、樹脂レジスト層26のX方向のずれ幅s1が、それぞれ±(B−b)/2ずつ、また、Y方向のずれ幅s2が−tの範囲内にあれば、ワイヤ搭載部15,16が端子部8,9の本体部に接続されることがなくなり、ワイヤ搭載部15,16に半田が侵入することを防止できる。また、切欠き部21,22のY方向の寸法も切欠き部23,24と同様に設定されているとすると、樹脂レジスト層25,26のY方向の許容ずれ範囲は、±tとなる。   With this configuration, if the displacement width s1 in the X direction of the resin resist layer 26 is ± (B−b) / 2, and the displacement width s2 in the Y direction is within the range of −t, the wire mounting portion 15 16 are not connected to the main body of the terminal portions 8 and 9, and solder can be prevented from entering the wire mounting portions 15 and 16. If the dimensions of the notches 21 and 22 in the Y direction are set in the same manner as the notches 23 and 24, the allowable deviation range in the Y direction of the resin resist layers 25 and 26 is ± t.

図1(B)に示すように、樹脂レジスト層25,26がY方向の+側にずれ、接続部17,18が露出した状態になっても、切欠き部21,22が形成されているので、端子部6,7と素子搭載部13,14の本体部との表面が連通することがなく、端子部6,7から素子搭載部13,14への半田の侵入を防止することができる。   As shown in FIG. 1B, the notch portions 21 and 22 are formed even when the resin resist layers 25 and 26 are shifted to the + side in the Y direction and the connection portions 17 and 18 are exposed. Therefore, the surfaces of the terminal portions 6 and 7 and the body portions of the element mounting portions 13 and 14 do not communicate with each other, and solder can be prevented from entering the element mounting portions 13 and 14 from the terminal portions 6 and 7. .

(第2の実施の形態)
図3は、第2の実施の形態の半導体発光装置の平面図である。図3に示すように、第2の実施の形態の半導体発光装置32は、半導体発光素子を1台のみ使用する構成となっている。
(Second Embodiment)
FIG. 3 is a plan view of the semiconductor light emitting device according to the second embodiment. As shown in FIG. 3, the semiconductor light emitting device 32 of the second embodiment is configured to use only one semiconductor light emitting element.

第2の実施の形態の半導体発光装置32は、絶縁性基板2に半導体発光素子4を搭載し、半導体発光素子4を樹脂パッケージ部33で覆って形成している。   The semiconductor light emitting device 32 according to the second embodiment is formed by mounting the semiconductor light emitting element 4 on the insulating substrate 2 and covering the semiconductor light emitting element 4 with a resin package portion 33.

絶縁性基板2は、両側に対となる略矩形の端子部34,35を形成し、中間部に配線部36を形成している。配線部36は、素子搭載部37およびワイヤ接続部38からなり、素子搭載部37およびワイヤ接続部38は、それぞれ端子部34,35に接続部39,40を介して接続されている。接続部39,40の両側には、それぞれ2箇所ずつの切欠き部41〜44が形成され、切欠き部41〜44および接続部39,40は、略矩形の樹脂レジスト層45,46によりそれぞれ覆われている。   The insulating substrate 2 is formed with a pair of substantially rectangular terminal portions 34 and 35 on both sides, and a wiring portion 36 in the middle portion. The wiring part 36 includes an element mounting part 37 and a wire connection part 38, and the element mounting part 37 and the wire connection part 38 are connected to terminal parts 34 and 35 via connection parts 39 and 40, respectively. Two cutout portions 41 to 44 are formed on both sides of the connection portions 39 and 40, respectively. The cutout portions 41 to 44 and the connection portions 39 and 40 are respectively formed by substantially rectangular resin resist layers 45 and 46. Covered.

このように、半導体発光素子が1台の場合でも、切欠き部を設けることにより、樹脂パッケージ部に半田が侵入することを防止することができる。   Thus, even when the number of semiconductor light emitting elements is one, by providing the notch portion, it is possible to prevent solder from entering the resin package portion.

第1の実施の形態の半導体発光装置1を使用して信頼性試験を行った。
(前処理)
温度65℃、湿度95%で2時間吸湿させ、外観検査により半田侵入を確認することを3回繰り返す。
(実測)
温度270℃に設定したリフロー槽を通過させ、半田侵入に関する外観検査および完全断線と半断線との確認を行うHOTチェックを4回行った。
(結果)
526台の半導体発光装置を用いて試験を行ったが、半田が侵入したものは1台もなかった。
A reliability test was performed using the semiconductor light emitting device 1 of the first embodiment.
(Preprocessing)
Moisture absorption is performed for 2 hours at a temperature of 65 ° C. and a humidity of 95%, and solder penetration is confirmed by appearance inspection three times.
(Actual measurement)
The sample was passed through a reflow tank set at a temperature of 270 ° C., and an HOT check was performed four times for visual inspection regarding solder penetration and confirmation of complete disconnection and half disconnection.
(result)
A test was conducted using 526 semiconductor light emitting devices, but none of the solders penetrated.

本発明は、大型基板にリフロー等による搭載時に、半田が配線部に侵入することがなくなり、樹脂パッケージの割れを防止することができるので、絶縁性基板上に搭載された半導体発光素子とこれを覆う樹脂パッケージとを備えた半導体発光装置に好適である。   In the present invention, when mounting on a large substrate by reflow or the like, the solder does not enter the wiring portion, and cracking of the resin package can be prevented, so that the semiconductor light emitting device mounted on the insulating substrate and the It is suitable for a semiconductor light emitting device provided with a resin package to be covered.

(A)は本発明の第1の実施の形態の半導体発光装置の平断面図、(B)は、同半導体発光装置の樹脂レジスト層のパターンがずれた状態の平断面図(A) is a cross-sectional plan view of the semiconductor light emitting device according to the first embodiment of the present invention, and (B) is a cross-sectional plan view of the semiconductor light emitting device in a state where the pattern of the resin resist layer is shifted. 本発明の第1の実施の形態の半導体発光装置の斜視図The perspective view of the semiconductor light-emitting device of the 1st Embodiment of this invention 第2の実施の形態の半導体発光装置の平面図Plan view of the semiconductor light emitting device of the second embodiment (A)は、従来の半導体発光装置の平断面図、(B)は、従来の半導体発光装置の樹脂レジスト層のパターンがずれた状態の平断面図(A) is a cross-sectional plan view of a conventional semiconductor light emitting device, and (B) is a cross-sectional plan view of the conventional semiconductor light emitting device with the resin resist layer pattern shifted.

符号の説明Explanation of symbols

1 半導体発光装置
2 絶縁性基板
3,4 半導体発光素子
5 樹脂パッケージ部
6,7 端子部
8,9 端子部
10,11 配線部
12 導電性ペースト
13,14 素子搭載部
15,16 ワイヤ接続部
17〜20 接続部
21〜24 切欠き部
25,26 樹脂レジスト層
27 ワイヤ
29 ワイヤ
30 ワイヤ
32 半導体発光装置
33 樹脂パッケージ部
34,35 端子部
36 配線部
37 素子搭載部
38 ワイヤ接続部
39,40 接続部
41〜44 切欠き部
45,46 樹脂レジスト層
DESCRIPTION OF SYMBOLS 1 Semiconductor light-emitting device 2 Insulating substrate 3, 4 Semiconductor light-emitting element 5 Resin package part 6, 7 Terminal part 8, 9 Terminal part 10, 11 Wiring part 12 Conductive paste 13, 14 Element mounting part 15, 16 Wire connection part 17 -20 connection portion 21-24 notch portion 25, 26 resin resist layer 27 wire 29 wire 30 wire 32 semiconductor light emitting device 33 resin package portion 34, 35 terminal portion 36 wiring portion 37 element mounting portion 38 wire connection portion 39, 40 connection Part 41 to 44 Notch part 45, 46 Resin resist layer

Claims (1)

絶縁性基板の表面の両側に対となる端子部が形成され、前記表面の中間部に形成された対となる配線部が、両前記端子部に接続部を介してそれぞれ接続され、各前記配線部を半導体発光素子にそれぞれ接続し、各前記配線部および前記半導体発光素子を覆う樹脂パッケージ部を形成し、各前記接続部を覆う樹脂レジスト層を形成した半導体発光装置において、
前記端子部の前記接続部に隣接する位置でかつ、前記絶縁性基板の端子部が形成された両側と垂直な両側面方向に、切欠き部がそれぞれ形成され
前記樹脂レジスト層の前記垂直な両側面方向の幅は、前記樹脂レジスト層を印刷するときの導通パターンに対する最大相対ずれ幅と、前記切欠き部間の最短距離との和以上になるように設定し、
前記樹脂レジスト層の内側端から切欠き部の底辺までの距離は、切欠き部の底辺までの距離と同じか、それより大きく設定され、切欠き部の底辺までの距離は、樹脂レジスト層を印刷するときの導通パターンに対する最大相対ずれ幅よりも大きくなるように設定されていることを特徴とする半導体発光装置。
A pair of terminal portions are formed on both sides of the surface of the insulating substrate, and a pair of wiring portions formed in the middle portion of the surface are respectively connected to both the terminal portions via connection portions, and each of the wirings In each of the semiconductor light emitting devices, each part is connected to a semiconductor light emitting element, a resin package part covering each wiring part and the semiconductor light emitting element is formed, and a resin resist layer covering each connection part is formed.
Notch portions are respectively formed at positions adjacent to the connection portions of the terminal portions and in both side surface directions perpendicular to both sides where the terminal portions of the insulating substrate are formed ,
The width of the resin resist layer in the direction of the two vertical sides is set to be equal to or greater than the sum of the maximum relative deviation width with respect to the conductive pattern when the resin resist layer is printed and the shortest distance between the notches. And
The distance from the inner edge of the resin resist layer to the bottom of the notch is set to be equal to or greater than the distance to the bottom of the notch, and the distance to the bottom of the notch is the distance from the resin resist layer. A semiconductor light emitting device, wherein the semiconductor light emitting device is set to be larger than a maximum relative deviation width with respect to a conductive pattern when printing .
JP2004257935A 2004-09-06 2004-09-06 Semiconductor light emitting device Expired - Fee Related JP4461968B2 (en)

Priority Applications (1)

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JP2004257935A JP4461968B2 (en) 2004-09-06 2004-09-06 Semiconductor light emitting device

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JP2004257935A JP4461968B2 (en) 2004-09-06 2004-09-06 Semiconductor light emitting device

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JP2006073911A JP2006073911A (en) 2006-03-16
JP4461968B2 true JP4461968B2 (en) 2010-05-12

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