JP4465196B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply circuit such as a DC-DC converter using a semiconductor switching element.

A power supply circuit capable of adjusting a voltage applied to a load is required in various cases. A technology that configures a power supply circuit using a PWM (Pulse Width Modulation) control method is widespread. In this method, a semiconductor switching element is inserted between a DC power supply and a load, and the semiconductor switching element is connected to the PWM control circuit. To turn it on and off intermittently. An example of this type of power supply circuit is reported in Patent Document 1.
JP 2001-274665 A

FIG. 9 shows an example of a DC-DC converter circuit that steps down by a PWM (Pulse Width Modulation) control method.
In this DC-DC converter, a first semiconductor switching element Q1 is inserted in series in a DC circuit connecting a DC power supply Vin and a DC load, and the first semiconductor switching element Q1 is intermittently turned on and off by a PWM control circuit. The voltage that is intermittently turned on and off is smoothed by the coil L1 and the capacitor C1, and the smoothed voltage is applied to the load. When the on duration of each time of the first semiconductor switching element Q1 is Ton, the off duration of each time is Toff, and the basic period is T (T = Ton + Toff), the voltage Vout applied to the load is Vout = (Ton / T ) Vin. Ton / T is called a duty factor, and by adjusting the value, the value of the voltage Vout applied to the load can be adjusted to an arbitrary value.
If the first semiconductor switching element Q1 is simply turned off, a large counter electromotive voltage is generated due to the inductance component of the load or wiring, and the first semiconductor switching element Q1 may be destroyed. Therefore, a circuit A for short-circuiting between the load terminals is provided so that when the first semiconductor switching element Q1 is turned off, a reflux current flows by bypassing the DC power supply and the first semiconductor switching element Q1. In order to prevent the short circuit A from being short-circuited when the first semiconductor switching element Q1 is turned on, the second semiconductor switching element Q2 is inserted into the short circuit A. The PWM control circuit alternately repeats a state in which the first semiconductor switching element is turned on and the second semiconductor switching element is turned off and a state in which the first semiconductor switching element is turned off and the second semiconductor switching element is turned on.

FIG. 10A shows the gate voltage applied to the gate of the first semiconductor switching element Q1, and FIG. 10B shows the gate voltage applied to the gate of the second semiconductor switching element Q2. Ton indicates the ON duration for each turn of the first semiconductor switching element Q1, Toff indicates the OFF duration, and T (T = Ton + Toff) indicates the basic period of PWM control. The second semiconductor switching element Q2 is turned off while the first semiconductor switching element Q1 is turned on, and is turned on while the first semiconductor switching element Q1 is turned off. The voltage Vout applied to the load is Vout = (Ton / T) Vin.
As shown in FIG. 9, the output voltage Vout of the DC-DC converter is constantly monitored, and the detected Vout is fed back to the PWM control circuit. In accordance with the detected output voltage Vout, the duration Ton in which the first semiconductor switching element Q1 is turned on and the second semiconductor switching element Q2 is turned off, and the first semiconductor switching element Q1 is turned off and the second semiconductor switching element is turned off. The duration Toff in the state in which the element Q2 is turned on is adjusted to increase or decrease, and the output voltage Vout is controlled to be constant.

FIG. 10C shows the magnitude of the current flowing through the second semiconductor switching element Q2, and FIG. 10D shows the voltage between the source and drain of the second semiconductor switching element Q2. As shown in FIG. 10C, when the first semiconductor switching element Q1 is turned off and the second semiconductor switching element Q2 is turned on, a feedback current flows through the second semiconductor switching element Q2. Thereafter, when the first semiconductor switching element Q1 is turned on and the second semiconductor switching element Q2 is turned off, a reverse recovery current flows through the turned-off second semiconductor switching element Q2 (encircled by a broken line ellipse shown in FIG. 10C). Current). The absolute value of the reverse recovery current increases first, then decreases and finally converges to zero. The decreasing rate of the reverse recovery current Ir that converges to 0 is referred to as a reverse recovery current change rate (dIr / dt). This reverse recovery current change rate generates a surge voltage of V _L = −L · dIr / dt by the parasitic inductance L existing in the DC-DC converter or the load wiring. As a result, as shown in FIG. 10D, a large surge voltage is generated at both ends of the second semiconductor switching element Q2. Usually, the surge voltage due to the reverse recovery current change rate (dIr / dt) is the largest and is called the recovery surge voltage.

If the recovery surge voltage generated at both ends of the second semiconductor switching element Q2 is large, the second semiconductor switching element Q2 is destroyed. There is a need for technology to suppress the recovery surge voltage.
In order to suppress the recovery surge voltage, a method of connecting a capacitor in parallel with the second semiconductor switching element Q2 is known. However, in the method of connecting capacitors, the number of parts increases.
An object of the present invention is to provide a power supply circuit such as a DC-DC converter that can suppress the magnitude of a recovery surge voltage generated when the second semiconductor switching element is turned off without increasing the number of components.

  A DC-DC converter according to the present invention includes a first semiconductor switching element connected in series between a DC power supply and a load, and a second semiconductor that bypasses the DC power supply and the first semiconductor switching element to short-circuit between load terminals. And a PWM control circuit that alternately repeats a state in which the first semiconductor switching element is turned on and the second semiconductor switching element is turned off, and a state in which the first semiconductor switching element is turned off and the second semiconductor switching element is turned on. Have.

One feature of the DC-DC converter according to the present invention is that the exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacity of the second semiconductor switching element is proportional to the reciprocal of the output capacity of the first semiconductor switching element. It is smaller than the exponent in the power of the drain-source voltage.
The semiconductor switching element has a characteristic of Cout = k · 1 / Vds ^α . Here, Cout is the output capacitance of the semiconductor switching element (gate-drain capacitance + source-drain capacitance), Vds is the drain-source voltage, and α is an index. As apparent from the above equation, the reciprocal (1 / Cout) of the output capacitance of the semiconductor switching element is proportional to the value obtained by raising the drain-source voltage Vds to the power of α.
In the present invention, with respect to the index α, the index α2 of the second semiconductor switching element is made smaller than the index α1 of the first semiconductor switching element.

In the DC-DC converter, the recovery surge voltage increases when the reverse recovery current change rate dIr / dt is large, and the recovery surge voltage decreases when the reverse recovery current change rate dIr / dt is small.
According to the studies by the present inventors, the rate of change dIr / dt of the reverse recovery current is a sensitivity when the output capacitance at the time of turn-off of the second semiconductor switching element changes following the change of the drain-source voltage Vds. It turned out to be strongly dependent on. That is, if the output capacitance at the time of turn-off of the second semiconductor switching element reacts sensitively to changes in the drain-source voltage Vds, the reverse recovery current change rate dIr / dt increases. Conversely, if the output capacitance at turn-off of the second semiconductor switching element is insensitive to changes in the drain-source voltage Vds, it has been found that the reverse recovery current change rate dIr / dt is small. is there.
As described above, the reciprocal of the output capacitance Cout of the semiconductor switching element is proportional to the value obtained by raising the drain-source voltage Vds to the power of α. If the exponent α is large, the output capacitance Cout changes sensitively with respect to the drain-source voltage Vds, and if the exponent α is small, the output capacitance Cout becomes insensitive to the drain-source voltage Vds.
Based on the above findings, the inventors have calculated an exponent α2 in the power of the drain-source voltage that is proportional to the reciprocal of the output capacitance at the time of turn-off of the second semiconductor switching element, at the time of turn-off of the first semiconductor switching element. By making it smaller than the exponent α1 in the power of the drain-source voltage proportional to the reciprocal of the output capacitance, the reverse recovery current change rate dIr / dt generated when the second semiconductor switching element is turned off can be reduced, and the recovery surge voltage can be reduced. It was confirmed that it could be kept small.

In the conventional DC-DC converter, the same transistor element is used for the first semiconductor switching element and the second semiconductor switching element. In the present invention, it is recognized that the first semiconductor switching element and the second semiconductor switching element have different generation factors of the surge voltage, and it is necessary to deal with each factor, and the reciprocal of the output capacity of the second semiconductor switching element is obtained. It is useful to make the index α2 in the power of the proportional drain-source voltage smaller than the index α1 in the power of the drain-source voltage proportional to the reciprocal of the output capacity of the first semiconductor switching element. As a result, the recovery surge voltage was successfully reduced.
According to the DC-DC converter having the features of the present invention, it is not necessary to connect an extra member such as a capacitor in parallel to the second semiconductor switching element, and a recovery surge voltage can be generated without increasing the number of components. Can be reduced.

Another feature of the present invention is that the trench gate electrode of the second semiconductor switching element is made deeper than the trench gate electrode of the first semiconductor switching element used in the DC-DC converter.
That is, both the first semiconductor switching element and the second semiconductor switching element are formed on the drain layer, the drift layer stacked on the drain layer, the body layer stacked on the drift layer, and the body layer surface. In the case of a vertical field effect transistor having a source region and a trench gate electrode formed in a trench that penetrates the source region and the body layer and reaches the drift layer and is covered with a gate insulating film The trench gate electrode of the second semiconductor switching element is made deeper than the trench gate electrode of the first semiconductor switching element.

The output capacitance of the semiconductor switching element is equal to the sum of the gate-drain capacitance and the source-drain capacitance. When the semiconductor switching element is formed of a vertical field effect transistor, the capacitance between the gate and the drain is substantially a pair of conductive surfaces facing each other across the gate insulating film formed on the bottom surface of the trench gate electrode. The capacitance between the source and the drain is substantially equal to the capacitance of the parasitic capacitor composed of a body, and the capacitance between the source and the drain is substantially a pair of conductors facing each other across the depletion layer extending from the pn junction surface of the drain layer and the body layer Is equal to the capacitance of the parasitic capacitor.
The capacitance caused by the gate insulating film is fixed by the thickness and material of the gate insulating film, and is constant with respect to the change in the drain-source voltage Vds. On the other hand, the capacitance caused by the depletion layer formed at the interface between the drain layer and the body layer changes following the change in the drain-source voltage Vds. This is because the thickness of the depletion layer formed on the pn junction surface changes following the drain-source voltage Vds.
It can be said that the output capacitance of the semiconductor switching element having a relatively large gate-drain capacitance and a relatively small source-drain capacitance is insensitive to the drain-source voltage Vds. The output capacitance of the semiconductor switching element having a relatively small capacitance between the gate and the drain and a relatively large capacitance between the source and the drain has a characteristic that changes sensitively with respect to the drain-source voltage Vds.

  In the case of a vertical field effect transistor including a trench gate electrode, the deeper the trench gate electrode penetrates into the drain layer, the larger the capacitance between the gate and the drain and the smaller the capacitance between the source and the drain. When the trench gate electrode of the second semiconductor switching element is deeper than the trench gate electrode of the first semiconductor switching element, the output capacitance at the turn-off time of the second semiconductor switching element is resistant to changes in the drain-source voltage Vds. As a result, the characteristics are easily maintained, and the generation of the recovery surge voltage can be effectively suppressed. An effect equivalent to externally attaching a condenser for suppressing the recovery surge voltage can be obtained, and the recovery surge voltage can be reduced without increasing the number of parts.

According to the DC-DC converter having the above characteristics, the recovery surge voltage generated when the second semiconductor switching element is turned off can be reduced. In addition, the surge voltage generated when the first semiconductor switching element is switched can be reduced. There is a need for a DC-DC converter that can be reduced.
In order to satisfy this requirement, the first semiconductor switching element includes a current sensing unit that detects the magnitude of the current flowing through the element, and the gate of the first semiconductor switching element is determined by the magnitude of the signal from the current sensing unit. It is preferable to add a gate resistance switching unit for switching the magnitude of the resistance to the DC-DC converter.

A surge voltage is also generated when the first semiconductor switching element of the DC-DC converter is turned off. Usually referred to as switching surge voltage. This switching surge voltage depends on the magnitude of the current change dI / dt when the current flowing through the first semiconductor switching element is turned off. That is, when dI / dt is large, a voltage of V = −L · dI / dt is generated at both ends of the parasitic inductance L, and a large surge voltage is generated at both ends of the first semiconductor switching element. Parasitic inductance is parasitic everywhere in the wiring from the positive terminal of the DC power source to the negative terminal of the DC power source via the first semiconductor switching element. Therefore, in order to reduce the switching surge voltage, it is important to reduce dI / dt.
In general, in order to reduce dI / dt, it is effective to increase the gate resistance of the first semiconductor switching element. However, when the gate resistance is increased, the switching loss due to the first semiconductor switching element increases. The method of adjusting the gate resistance does not achieve the suppression of the switching surge voltage and the reduction of the switching loss at the same time. Increasing the gate resistance can suppress the switching surge voltage, but the switching loss increases and the gate resistance increases. If the value is reduced, the switching loss can be reduced, but the switching surge voltage increases. The method of adjusting the gate resistance is in a trade-off relationship, and it is not possible to reduce both the switching surge voltage and the switching loss.

  When the cause of the occurrence of the switching surge voltage of the first semiconductor switching element is examined in detail, it can be seen that the switching surge voltage depends on the magnitude of the current flowing through the first semiconductor switching element. When the current flowing through the first semiconductor switching element is large, dI / dt increases, and when the current is small, dI / dt decreases. That is, when the current flowing through the first semiconductor switching element is large, a large switching surge voltage is generated, which is a problem. However, when the current flowing through the first semiconductor switching element is small, the switching surge voltage is decreased, There is little influence such as destruction of the semiconductor switching element. It can be seen that in order to suppress the breakdown of the field effect transistor due to the switching surge voltage, it is necessary to take measures to suppress the switching surge voltage only when the current flowing through the first semiconductor switching element is large. By doing so, it is possible to overcome the trade-off relationship that if the switching surge voltage is suppressed, the switching loss increases, and if the switching loss is reduced, the switching surge voltage increases. It can be seen that when the current flowing through the first semiconductor switching element is large, the gate resistance should be increased to reduce the switching surge voltage, and when the current is small, the gate resistance should be reduced to reduce the switching loss. It can be seen that the switching loss can be further reduced after the voltage is reduced.

  When the DC-DC converter includes a gate resistance switching unit that switches the magnitude of the gate resistance of the first semiconductor switching element according to the magnitude of the signal from the current sensing unit, when the current flowing through the first semiconductor switching element is large The gate resistance can be increased to reduce the switching surge voltage. When the current is small, the gate resistance can be reduced to reduce the switching loss, and the switching loss can be reduced while suppressing the switching surge voltage.

  According to the aspect of the present invention, it is possible to provide a power supply circuit such as a DC-DC converter in which the magnitude of the recovery surge voltage generated when the semiconductor switching element is turned off is suppressed without increasing the number of components.

The technical features described in the examples and the like are listed.
First Embodiment The impurity concentration of the drift layer is increased toward the drain side, and the trench gate electrode is formed to a depth at which the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ .
Second Embodiment The impurity concentration of the drift layer increases toward the drain side, and the trench gate electrode is formed to a depth at which the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ .

A preferred embodiment of the present invention will be described with reference to the drawings.
First Embodiment FIG. 1 shows a circuit diagram of a step-down chopper type DC-DC converter of a first embodiment. The step-down chopper type DC-DC converter of the first embodiment includes a PWM control logic unit 2, a circuit unit 4, and an active gate control unit 6, which steps down a DC power supply Vin of 42V DC and outputs an output voltage of DC 14V. Vout is applied to the load 47.

The circuit unit 4 bypasses the first semiconductor switching element Q11 inserted in series in the series circuit 10 connecting the DC power supply Vin and the load 47, and the DC power supply Vin and the first semiconductor switching element Q11, and between the terminals of the load. A short circuit 8 to be short-circuited, a second semiconductor switching element Q12 inserted in the short circuit 8, a coil L11 and a capacitor C11 constituting a smoothing circuit are provided.
The drain terminal of the first semiconductor switching element Q11 is connected to the plus terminal of the DC power supply Vin, the source terminal of the first semiconductor switching element Q11 and the drain terminal of the second semiconductor switching element Q12 are connected to one end of the load, and the second semiconductor The source terminal of the switching element Q12 is connected to the other end of the load and the negative terminal of the DC power source Vin.
A DC power supply 12 for applying a DC voltage between the source and gate of the second semiconductor switching element Q12 is prepared, and when the second semiconductor switch 14 is closed, the DC power supply 12 is connected to the source and gate of the second semiconductor switching element Q12. A DC voltage is applied between them. As a result, the source and drain of the second semiconductor switching element Q12 is turned on. The speed at which the source-gate voltage of the second semiconductor switching element Q12 changes when the second semiconductor switch 14 is closed is determined by the resistance value of the gate resistor 16.
Similarly, a DC power source 18 for applying a DC voltage between the source and gate of the first semiconductor switching element Q11 is prepared. When the first semiconductor switch 20 is closed, the DC power source 18 is connected to the first semiconductor switching element Q11. A DC voltage is applied between the source and gate. As a result, the source and drain of the first semiconductor switching element Q11 is turned on. The speed at which the source-gate voltage of the first semiconductor switching element Q11 changes when the first semiconductor switch 20 is closed is determined by the resistance value of the gate resistor 22.
With the first semiconductor switch 20 off of the second semiconductor switch 14 is controlled by PWM control logic unit 2, the PWM control logic unit 2, for turning off the second semiconductor switch 14 is turned on the first semiconductor switch 20 And the state which turns off the 1st semiconductor switch 20 and turns on the 2nd semiconductor switch 14 is repeated alternately.

The first semiconductor switching element Q11 is an n-type channel MOSFET, and FIG. The first semiconductor switching element Q11 is a vertical field effect transistor having a trench gate electrode 190 covered with a gate insulating film 191.
Reference numeral 120 denotes a drain layer made of n ⁺ type single crystal silicon or the like. On the back surface of the drain layer 120, for example, a drain electrode 110 made of aluminum is formed. On the drain layer 120, a drift layer 130 made of n ⁻ type single crystal silicon or the like is formed. A body layer 140 made of p ⁻ type single crystal silicon or the like is formed on drift layer 130. On top of the body layer 140, a source region 150 formed of n ⁺ -type single crystal silicon or the like, the body contact region 160 made of p ⁺ -type single crystal silicon or the like is formed.
A trench penetrating the source region 150 and the body layer 140 and entering the drift layer 130 is dug, and the wall surface and bottom surface of the trench are covered with a gate insulating film 191 made of silicon oxide. A trench whose surface is covered with a gate insulating film 191 is filled with a trench gate electrode 190 made of low-resistance polysilicon or the like.
A source electrode 180 is formed so as to be in contact with the source region 150 and the body contact region 160, and the source electrode 180 is insulated from the trench gate electrode 190 by an insulating interlayer film 170. The trench gate electrode 190 is connected to a gate pad (not shown) in a cross section (not shown).
In the first semiconductor switching element Q11, when a voltage of the DC power source 18 (FIG. 1) is applied between the trench gate electrode 190 and the source electrode 180, an n-type channel is formed in the body region 140 facing the trench gate electrode 190, The source electrode 180 and the drain electrode 110 are electrically connected.

The second semiconductor switching element Q12 is also an n-type channel MOSFET, and a cross-sectional view of the main part is shown in FIG.
Reference numeral 220 denotes a drain layer made of n ⁺ type single crystal silicon or the like. A drain electrode 210 made of, for example, aluminum is formed on the back surface of the drain layer 220. On the drain layer 220, a drift layer 230 made of n ⁻ -type single crystal silicon or the like is formed. On drift layer 230, body layer 240 made of p ⁻ type single crystal silicon or the like is formed. On top of the body layer 240, a source region 250 formed of n ⁺ -type single crystal silicon or the like, the body contact region 260 made of p ⁺ -type single crystal silicon or the like is formed.
A trench that penetrates the source region 250 and the body layer 240 and penetrates deeply into the drift layer 230 is dug, and the wall surface and bottom surface of the trench are covered with a gate insulating film 291 made of silicon oxide. The gate insulating film 291 is thin at a depth corresponding to the body layer 240, and is thick at a portion entering the drift layer 230. The thin gate insulating film 291 corresponding to the body layer 240 realizes a low gate-on voltage, and the thick gate insulating film 291 corresponding to the drift layer 230 realizes a high breakdown voltage of the second semiconductor switching element Q12. A trench whose surface and bottom are covered with a gate insulating film 291 is filled with a trench gate electrode 290 made of low-resistance polysilicon or the like.
A source electrode 280 is formed so as to be in contact with the source region 250 and the body contact region 260, and the source electrode 280 is insulated from the trench gate electrode 290 by an insulating interlayer film 270. The trench gate electrode 290 is connected to a gate pad (not shown) in a cross section (not shown).
When the voltage of the DC power supply 12 (FIG. 1) is applied between the trench gate electrode 290 and the source electrode 280, the second semiconductor switching element Q11 forms an n-type channel in the body region 240 facing the trench gate electrode 290, The source electrode 280 and the drain electrode 210 are electrically connected.
Trench gate electrode 290 of second semiconductor switching element Q12 extends from the interface between body layer 240 and drift layer 230 to a position deeper than the depletion layer extending to drift layer 230 when off. A MOSFET in which trench gate electrode 290 is formed deeply below drift layer 230 is referred to as DGMOSFET (Deep Gate MOSFET).
The impurity concentration of the drift layer 230 of the second semiconductor switching element Q12 increases toward the drain electrode 210 side, and the trench gate electrode 290 has a depth at which the impurity concentration of the drift layer 230 is 1 × 10 ¹⁷ cm ^−3. Is formed. More preferably, the trench gate electrode 290 is further extended to a depth at which the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ .

FIG. 3 shows the relationship between the output capacitance Cout (vertical axis) of the first semiconductor switching element Q11 and the second semiconductor switching element Q12 and the drain-source voltage Vds (horizontal axis).
It can be seen that there is a relationship of Cout = k1 / Vds ^0.5 between the output capacitance Cout of the first semiconductor switching element Q11 and the voltage Vds. In contrast, between the output capacitance Cout and the voltage Vds of the second semiconductor switching element Q12, it can be seen that there is a relation of Cout = k2 / Vds ^0.3.
In other words, the reciprocal of the output capacitance Cout of the first semiconductor switching element Q11 is proportional to the drain-source voltage multiplied by 0.5, and the reciprocal of the output capacitance Cout of the second semiconductor switching element Q12 is It is proportional to the voltage between sources multiplied by 0.3.
The exponent (0.5) in the power of the drain-source voltage proportional to the reciprocal of the output capacitance Cout of the first semiconductor switching element Q11 is the drain-source proportional to the reciprocal of the output capacitance Cout of the second semiconductor switching element Q12. It is larger than the exponent (0.3) in the power of voltage.
This is because the output capacitance Cout of the first semiconductor switching element Q11 changes sensitively to changes in the drain-source voltage, and the output capacitance Cout of the second semiconductor switching element Q12 changes in response to changes in the drain-source voltage. It means changing to insensitivity.
If the output capacitance Cout of the second semiconductor switching element Q12 is insensitive, the reverse recovery current change rate dIr / dt at the time of turn-off of the second semiconductor switching element Q12 can be suppressed small, and the recovery surge voltage can be suppressed. If the exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacitance Cout of the second semiconductor switching element Q12 is insensitive to 0.3 or less, the effect is prominent, and the reverse recovery current change at turn-off The rate dIr / dt is remarkably suppressed, and the recovery surge voltage can be remarkably suppressed.

The present inventors have found that the output capacitance at turn-off changes insensitively in the DGMOSFET shown in FIG. 2B, and when the DGMOSFET is used for the second semiconductor switching element Q12, the recovery surge voltage is remarkably suppressed. I found that I can do it.
When trench gate electrode 290 extends deeper than the depletion layer formed in the drift layer, the gate-drain capacitance due to gate insulating film 291 on the bottom surface of gate electrode 290 occupies most of the output capacitance. The capacitance of the gate insulating film 291 is determined by factors such as the thickness and material of the gate insulating film 291 and the impurity concentration in the vicinity, and is substantially constant with respect to the drain-source voltage. The output capacitance of the DGMOSFET does not change much with respect to the drain-source voltage.
The impurity concentration of the drift layer 230 of the DGMOSFET is not uniform, and becomes higher as it approaches the drain layer 220. The impurity concentration of the drift layer 230 in the vicinity of the interface between the drain layer 220 and the drift layer 230 is about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ . In general, the depletion layer formed in the drift layer 230 is formed up to an impurity concentration in the vicinity of 1 × 10 ¹⁷ cm ⁻³ . Therefore, the trench gate electrode 290 is preferably formed to a depth where the impurity concentration of the drift layer 230 reaches 1 × 10 ¹⁷ cm ⁻³ . In addition, it is preferable that it is formed deeper than that, and it is more preferable that it is formed to a depth reaching 1 × 10 ¹⁸ cm ⁻³ . It may extend until it contacts the drain layer 220.
The DGMOSFET not only reduces the recovery surge voltage but also has a feature of low on-resistance. For example, as shown in FIG. 2A, the on-resistance of the DGMOSFET is lower than that of a transistor in which the trench gate electrode 190 ends at a shallow level of the drift layer 130. Compared with the transistor shown in FIG. 2A, since the depletion layer broadly extends from the interface between the gate insulating film 291 and the drift layer 230 of the DGMOSFET to the drift layer 230, the impurity concentration of the drift layer 230 is not reduced. Can be high. As a result, the on-resistance of the DGMOSFET can be reduced.
In recent years, the DC power source Vin is high and the output voltage Vout tends to be small. Therefore, the duty factor tends to be small, and it is necessary to lengthen the on-time of the second semiconductor switching element Q12. Lowering the on-resistance of the second semiconductor switching element Q12 is effective for reducing the loss of the power supply device.

FIG. 4 shows the relationship between the exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacitance at the time of turn-off of the second semiconductor switching element Q12 and the recovery surge voltage generated at both ends of the second semiconductor switching element Q12. ing.
4 that the recovery surge voltage generated at both ends of the second semiconductor switching element Q12 is reduced as the index is smaller. It can be seen that the recovery surge voltage is significantly suppressed when the index is 0.3 or less.
This can be understood from the relationship with the depletion layer formed in the second semiconductor switching element Q12. That is, the reverse recovery current change rate dIr / dt is due to carriers being extracted from the depletion layer formed in the second semiconductor switching element Q12 when a reverse bias voltage is applied to the semiconductor switching element. Therefore, if a semiconductor switching element in which the change in the depletion layer region is small with respect to the change in the reverse bias voltage, that is, a semiconductor switching element in which the output capacitance at the turn-off is difficult to change with respect to the drain-source voltage, Becomes smaller. When a semiconductor switching element having a small change in the depletion layer region at turn-off is used, generation of a recovery surge voltage is suppressed.

The PWM control logic unit 2 in FIG. 1 controls on / off of the first semiconductor switch 20 and the second semiconductor switch 14. When the first semiconductor switch 20 is turned on, the first semiconductor switching element Q11 is turned on, and when the first semiconductor switch 20 is turned off, the first semiconductor switching element Q11 is turned off. When the second semiconductor switch 14 is turned on, the second semiconductor switching element Q12 is turned on, and when the second semiconductor switch 14 is turned off, the second semiconductor switching element Q12 is turned off. The PWM control logic unit 2 controls on / off of the first semiconductor switching element Q11 and the second semiconductor switching element Q12 via the first semiconductor switch 20 and the second semiconductor switch 14.
The PWM control logic unit 2 turns on the first semiconductor switching element Q11 and turns off the second semiconductor switching element Q12, and turns off the first semiconductor switching element Q11 and turns on the second semiconductor switching element Q12. The output voltage Vout is constantly controlled to 14V by repeating alternately.
The circuit unit 4 is provided with a voltmeter 46 for detecting the voltage Vout acting on the load 47, and a voltage proportional to the voltage Vout is sent to the PWM control logic unit 2.
The PWM control logic unit 2 has a reference voltage generation unit 24 and outputs a reference voltage Vref. The logic circuit indicated by reference numerals 26, 28, and 30 inputs a voltage of k (Vref−Vout) + Vref to one terminal of the comparators 34 and 42.
The PWM control logic unit 2 includes a triangular wave generating unit 32 that generates a triangular wave voltage at a reference period T, and the triangular wave voltage generated by the triangular wave generating unit 32 is input to the other terminals of the comparators 34 and 42. The triangular wave generator 32 outputs a triangular wave voltage at 100 kHz.
The comparator 34 outputs a high signal while k (Vref−Vout) + Vref> triangular wave voltage, and turns on the first semiconductor switch 20. 36 shows the output of the comparator 34, which is turned on during k (Vref−Vout) + Vref> triangular wave voltage (Ton period) and turned off during k (Vref−Vout) + Vref <triangular wave voltage (Toff period). . When Vout rises to 14 volts or more, k (Vref−Vout) + Vref decreases, so the period of k (Vref−Vout) + Vref> triangular wave voltage (Ton period) is shortened, and Vout is stepped down toward 14 volts. Is done. When Vout is stepped down to less than 14 volts, k (Vref−Vout) + Vref increases, so the period of k (Vref−Vout) + Vref> triangular wave voltage (Ton period) becomes long, and Vout is stepped up toward 14 volts. Is done. The PWM control logic unit 2 adjusts the output voltage Vout to 14 volts by increasing or decreasing the Ton period.
When k (Vref−Vout) + Vref> triangular wave voltage and the first semiconductor switch 20 is turned on, the voltage of the DC power supply 18 is applied between the source and gate of the first semiconductor switching element Q11, and the first semiconductor switching element Q11 The source-gate voltage rise rate is adjusted by the gate resistor 22.
When k (Vref−Vout) + Vref <triangular wave voltage and the first semiconductor switch 20 is turned off, the voltage of the DC power supply 18 is not applied between the source and gate of the first semiconductor switching element Q11. In this case, the source-gate voltage is discharged using the resistors 82, 84, 86, 88, 90. The decreasing speed of the source-gate voltage of the first semiconductor switching element Q11 is controlled by turning on / off the semiconductor switches 72, 74, 76, 78, 80.
The active gate control unit 6 switches on and off the semiconductor switches 72, 74, 76, 78, and 80 in time series after the first semiconductor switching element Q11 is turned off, and the source-gate voltage of the first semiconductor switching element Q11. Are switched in time series, and the switching surge voltage is suppressed by slowing the rate of change of the current flowing transiently after the first semiconductor switching element Q11 is turned off. When the switching surge voltage is suppressed, the switching loss due to the first semiconductor switching element Q11 increases. The active gate control unit 6 uses the resistors 82, 84, 86, 88, and 90 to realize a high gate resistance and suppress the switching surge voltage during a period in which the switching surge voltage needs to be suppressed. During the period when it is not necessary to suppress the switching surge voltage, a state in which the gate resistance is low is realized by using the resistors 82, 84, 86, 88, 90, and the switching loss is reduced. The active gate control unit 6 switches the gate resistance to active using the semiconductor switches 72, 74, 76, 78, and 80 and the resistors 82, 84, 86, 88, and 90, and suppresses switching surge voltage while switching loss. Reduce.
In order for the active gate control unit 6 to operate as intended, the output of the comparator 34 is inverted by the inverter 38 and then input to the comparators 52, 54, 56, 58 and 60.
The first semiconductor switching element Q11 has a current sensing unit that outputs a voltage proportional to the magnitude of the energized current, and a voltage Vcu proportional to the magnitude of the energized current of the first semiconductor switching element Q11 is a terminal. 48. The voltage Vcu is inverted by the inverter 50 and input to the comparators 52, 54, 56, 58 and 60.
In the comparators 52, 54, 56, 58, 60, the signal inverted by the inverter 38 is high (this corresponds to the Toff period of the first semiconductor switching element), and the inverted voltage Vcu is the reference value. When the following is true, a high signal is output to turn on the semiconductor switches 72, 74, 76, 78, and 80.
Immediately after the first semiconductor switching element Q11 is turned off, the current value flowing transiently through the first semiconductor switching element Q11 is large, the voltage inverted by the inverter 50 is low, and only the comparator 60 outputs a high signal. As a result, the gate resistance immediately after the first semiconductor switching element Q11 is turned off (referred to as the first period) is switched to a relatively high state, the first semiconductor switching element Q11 is turned off slowly, and the switching surge voltage is suppressed. The
When the current value flowing transiently through the first semiconductor switching element Q11 is slightly decreased after the first period has elapsed (referred to as the second period), the voltage inverted by the inverter 50 rises, and the comparators 60 and 58 generate high signals. Is output. As a result, the gate resistance in the second period of the first semiconductor switching element Q11 becomes a parallel resistance of the resistors 82 and 84, and the resistance value is lowered. The turn-off speed of the first semiconductor switching element Q11 is increased, and the switching loss is reduced.
When the current value flowing transiently through the first semiconductor switching element Q11 further decreases after the second period has elapsed (referred to as the third period), the voltage inverted by the inverter 50 increases, and the comparators 60, 58, and 56 are activated. A high signal is output. As a result, the gate resistance of the first semiconductor switching element Q11 in the third period becomes a parallel resistance of the resistors 82, 84 and 86, and the resistance value is further lowered. The turn-off speed of the first semiconductor switching element Q11 is further increased, and the switching loss is reduced.
When the current value flowing transiently through the first semiconductor switching element Q11 further decreases after the third period has elapsed (referred to as a fourth period), the voltage inverted by the inverter 50 increases, and the comparators 60, 58, 56 54 outputs a high signal. As a result, the gate resistance of the first semiconductor switching element Q11 in the fourth period becomes a parallel resistance of the resistors 82, 84, 86, and 88, and the resistance value is further lowered. The turn-off speed of the first semiconductor switching element Q11 is further increased, and the switching loss is reduced.
When the current value flowing transiently through the first semiconductor switching element Q11 further decreases after the fourth period has elapsed (referred to as the fifth period), the voltage inverted by the inverter 50 increases, and the comparators 60, 58, 56 All of 54 and 52 output a high signal. As a result, the gate resistance of the first semiconductor switching element Q11 in the fifth period becomes a parallel resistance of the resistors 82, 84, 86, 88, and 90, and the resistance value is further reduced. The turn-off speed of the first semiconductor switching element Q11 is further increased, and the switching loss is reduced.
The active gate control unit 6 switches on / off the semiconductor switches 72, 74, 76, 78, 80 in time series after the first semiconductor switching element Q11 is turned off, and immediately after the first semiconductor switching element Q11 is turned off. The switching surge voltage is suppressed by slowing the rate of change of the flowing current. When the transiently flowing current itself becomes small, the rate of change becomes small, so that the value of the gate resistance necessary for suppressing the switching surge voltage becomes small. The active gate control section 6 follows it to lower the gate resistance and reduce the switching loss.
The active gate control unit 6 needs to detect the current flowing through the first semiconductor switching element Q11. What kind of current detection device is provided is important from the viewpoint of miniaturization and the like. As a current detection device, there is a method of detecting a voltage drop due to the ON resistance of the first semiconductor switching element Q11. Further, there is a method of providing a current sensing semiconductor element in parallel with the first semiconductor switching element Q11 and estimating the current flowing through the first semiconductor switching element Q11 from the current flowing through the current sensing semiconductor element. In the present embodiment, a method of providing a current sensing semiconductor device in the first semiconductor switching element Q11 itself is used. According to this embodiment, it is not necessary to add a new element.
In this embodiment, the gate resistance is switched to five stages, but the number of switching stages is not limited to five. A plurality of gate resistors may be provided as necessary.

Next, the magnitude of the surge voltage was compared between the DC-DC converter provided with the active gate drive system and each DC-DC converter not provided.
At the timing shown in FIG. 5, a load voltage was applied to the load of each DC-DC converter and the load current was varied. When the elapsed time is 1 msec, the magnitude of the load current fluctuates temporarily, and the current flowing through the first semiconductor switching element Q11 of each DC-DC converter increases.
FIG. 6A shows the magnitude of the surge voltage generated at both ends of the first semiconductor switching element Q11 of the DC-DC converter not provided with the active gate drive system. When the elapsed time is 1 msec, the magnitude of the load current fluctuates temporarily, the current flowing through the first semiconductor switching element Q11 increases, and a surge voltage is generated at both ends of the first semiconductor switching element Q11 accordingly. Yes.
On the other hand, FIG. 6B shows the change in surge voltage when the gate resistance of the first semiconductor switching element Q11 is actively driven, which is based on the power supply device of the first embodiment. In this case as well, although a surge voltage is generated with a change in the magnitude of the load current, it can be seen that the magnitude of the peak is smaller than that in FIG.
FIG. 6 shows that the surge voltage is suppressed by actively driving the gate resistance.

The chain line in FIG. 7 shows the cumulative loss of a DC-DC converter that does not have an active gate drive system. The cumulative loss is an integral value of loss per time. On the other hand, the solid line in FIG. 7 represents the cumulative loss of the DC-DC converter provided with the active gate drive system. The elapsed time shown on the horizontal axis of FIG. 7 corresponds to FIG. 5 and FIG. It can be seen from FIG. 7 that cumulative loss is reduced by providing the active gate drive system. When the load current fluctuates (the elapsed time shown in FIG. 7 is about 1 msec), the loss per time is larger when the active gate control is provided. This is because a gate resistance having a large resistance value is temporarily used in order to reduce the surge voltage of the first semiconductor switching element Q11. However, in other elapsed time, the use of a gate resistance having a small resistance value and the fact that the on-resistance is reduced by using the DGMOSFET for the second semiconductor switching element Q12 are finally combined. The cumulative loss of the DC-DC converter is reduced.
As shown in FIG. 1, the second semiconductor switching element Q <b> 12 is controlled by the comparator 42. The comparator 42 outputs a high signal while k (Vref−Vout) + Vref <triangular wave voltage, and turns on the second semiconductor switch 14. 36 shows the output of the comparator 34, which is turned on while k (Vref−Vout) + Vref <triangular wave voltage, and turned off while k (Vref−Vout) + Vref> triangular wave voltage. That is, the Ton period in which the first semiconductor switching element Q11 is turned off is turned off, and the Toff period in which the first semiconductor switching element Q11 is turned off is turned on. When the comparator 42 outputs a high signal, the second semiconductor switch 14 is turned on and the second semiconductor switching element Q12 is turned on. When the comparator 42 outputs a low signal, the second semiconductor switch 14 is turned off and the second semiconductor switching element Q12 is turned off. As a result, if the first semiconductor switching element Q11 is turned on, the second semiconductor switching element Q12 is turned off, and if the first semiconductor switching element Q11 is turned off, the second semiconductor switching element Q12 is turned on.
During the period (Ton period) in which the first semiconductor switching element Q11 is turned on and the second semiconductor switching element Q12 is turned off, the power source of the DC power source Vin is applied to the smoothing circuits L11 and C11. During the period in which the first semiconductor switching element Q11 is turned off and the second semiconductor switching element Q12 is turned on (Toff period), the DC power source Vin is not applied to the smoothing circuits L11 and C11, and the charge of the capacitor C11 is charged. Is discharged. A feedback current also flows during the Toff period. Since a feedback current flows through the second semiconductor switching element Q12, a high voltage is prevented from acting on the electronic element.
Immediately after the second semiconductor switching element Q12 is turned off, a current continuously flows through the second semiconductor switching element Q12. A reverse recovery current (current surrounded by a dashed ellipse shown in FIG. 10C) flows through the turned-off second semiconductor switching element Q2. The absolute value of the reverse recovery current increases first, then decreases and finally converges to zero. The rate of decrease of the reverse recovery current Ir that converges to 0 is referred to as the reverse recovery current change rate (dIr / dt), and this reverse recovery current change rate is determined by the parasitic inductance L present in the DC-DC converter and load wiring. V _L = −L · dIr / dt, a recovery surge voltage is generated.
In the present embodiment, the second semiconductor switching element Q12 that is less sensitive as the exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacitance Cout of the second semiconductor switching element Q12 is 0.3 or less is used. Therefore, the reverse recovery current change rate dIr / dt at turn-off is remarkably suppressed, and the recovery surge voltage can be remarkably suppressed. This is as described with reference to FIG.

Second Embodiment FIG. 8 (a) schematically shows a drive circuit diagram for driving a three-phase motor, and FIG. 8 (b) shows a main circuit diagram thereof.
In the three-phase motor drive circuit shown in FIG. 8A, one ends of loads R1 to R3 (three-phase motor coils) are connected to a common point C. A unit circuit U1 in which a first transistor Q20 and a second transistor Q21 are connected in series, a unit circuit U2 in which a first transistor Q22 and a second transistor Q23 are connected in series, a first transistor Q24 and a second transistor Q25 Unit circuits U3 connected in series are connected in parallel. One end of the parallel circuit is connected to one end of the DC power supply, and the other end is connected to the other end of the DC power supply. The three middle points of each of the unit circuits U1, U2, U are connected to the other ends (terminals not connected to the common point C) of the loads R1 to R3.
The six transistors Q20 and Q21, Q22 and Q23, and Q24 and Q25 are switched on and off in time series as shown in FIG. 8C by the PWM control circuit. When the on / off of the six transistors is switched in time series as shown in FIG. 8C, a rotating magnetic field is created by the coils R1 to R3 of the three-phase motor, and the three-phase motor rotates.
A principal circuit diagram surrounded by a broken line in FIG. 8A is shown in FIG.
When the transistor Q20 is turned off and the transistor Q21 is turned on (when switching between the periods T1 and T2 in FIG. 8C), the transient current I20 continues to flow through the transistor Q20 and is generated when it converges to zero. A recovery surge voltage having a large change rate dIr / dt is generated. Similarly, when transistor Q20 is turned on and transistor Q21 is turned off (when switching between periods T3 and T1 in FIG. 8C), transient current I21 continues to flow through transistor Q21 and occurs when it converges to zero. A recovery surge voltage having a large reverse recovery current change rate dIr / dt is generated.
Also in the above embodiment, if the transistors Q20 and Q21, Q22 and Q23, and Q24 and Q25 are composed of transistors whose output capacitances are difficult to change against changes in drain-source voltage, recovery that occurs at both ends of the transistors. Surge voltage can be reduced. For example, if the transistors Q20 and Q21, Q22 and Q23, and Q24 and Q25 are formed of DGMOSFET, the recovery surge voltage can be reduced.
In the above circuit, the transistors Q20 and Q21, Q22 and Q23, and Q24 and Q25 are all transistors whose output capacitance is difficult to change against the change in drain-source voltage (the drain-source voltage proportional to the inverse of the output capacitance). (Multiplier having a multiplier of 0.3 or less) is advantageous, but if the recovery surge voltage generated when the second transistors Q21, Q23, Q25 are turned off is serious, only the second transistors Q21, Q23, Q25 have drains. A transistor whose output capacitance does not easily change against the change of the source voltage may be used. If the recovery surge voltage generated when the first transistors Q20, Q22, Q24 are turned off is severe, the first transistors Q20, Q22, The output capacitance is hard to change against the change of drain-source voltage only in Q24 Transistors may be utilized.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
A semiconductor switching element whose output capacitance is maintained almost constant against changes in drain-source voltage is not limited to DGMOSFET. The output capacitance of the semiconductor switching element varies depending on the shape of the gate electrode, the shape and thickness of the gate insulating film, the distribution of impurity concentration in the drift layer, and the like. In this embodiment, the DGMOSFET is employed as an example of the semiconductor switching element in which the output capacitance is maintained substantially constant. However, the output capacitance is maintained substantially constant with respect to the drain-source voltage even in other configurations. If a semiconductor switching element is used, the recovery surge voltage can be suppressed.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The circuit diagram of the DC-DC converter of 1st Example is shown. (A) is a fragmentary cross-sectional view of the transistor Q11 of the first embodiment, and (b) is a fragmentary cross-sectional view of the transistor Q12 of the first embodiment. The relationship of the output capacitance with respect to the drain-source voltage of the transistor Q11 and the transistor Q12 is shown. The relationship between the exponent and the surge voltage in the power of the drain-source voltage proportional to the inverse of the output capacitance is shown. The change with time of load voltage and load current is shown. (A) shows the voltage of the transistor when the active gate drive system is not provided. (B) shows the voltage of the transistor Q11 of the first embodiment. The cumulative loss of the DC-DC converter of the first embodiment is shown. (A) shows a three-phase motor drive circuit, (b) shows a circuit diagram of a main part thereof, and (C) shows an on / off relationship that is switched in time series. The circuit diagram of a step-down chopper type DC-DC converter is shown. (A) shows the gate voltage of the transistor Q1, (b) shows the gate voltage of the transistor Q2, (c) shows the current value of the transistor Q2, and (d) shows the voltage across the transistor Q2.

Explanation of symbols

210: drain electrode 220: drain layer 230: drift layer 240: body layer 250: source region 260: body contact region 270: insulating interlayer 280: source electrode 290: gate electrode 291: gate insulating film

Claims (3)

A first semiconductor switching element connected in series between a DC power supply and a load; a second semiconductor switching element that bypasses the DC power supply and the first semiconductor switching element to short-circuit between load terminals; and a first semiconductor switching element And a PWM control circuit that alternately repeats a state in which the second semiconductor switching element is turned off and a state in which the first semiconductor switching element is turned off and the second semiconductor switching element is turned on,
The exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacitance of the second semiconductor switching element is smaller than the exponent in the power of the drain-source voltage proportional to the reciprocal of the output capacitance of the first semiconductor switching element. DC-DC converter characterized by this. A first semiconductor switching element connected in series between a DC power supply and a load; a second semiconductor switching element that bypasses the DC power supply and the first semiconductor switching element to short-circuit between load terminals; and a first semiconductor switching element And a PWM control circuit that alternately repeats a state in which the second semiconductor switching element is turned off and a state in which the first semiconductor switching element is turned off and the second semiconductor switching element is turned on,
The first semiconductor switching element and the second semiconductor switching element include a drain layer, a drift layer stacked on the drain layer, a body layer stacked on the drift layer, a source region formed on the surface of the body layer, A field effect transistor having a source region and a trench gate electrode formed in a trench that reaches the drift layer through the body layer and is covered with a gate insulating film;
A DC-DC converter characterized in that the trench gate electrode of the second semiconductor switching element is deeper than the trench gate electrode of the first semiconductor switching element. The first semiconductor switching element includes a current sensing unit that detects a magnitude of a current flowing through the element,
  3. The DC-DC converter according to claim 1, further comprising a gate resistance switching unit that switches a magnitude of the gate resistance of the first semiconductor switching element according to the magnitude of a signal from the current sensing unit.

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