JP4465539B2 - Memory control apparatus and method - Google Patents

Description

  The present invention relates to a memory control apparatus and method for controlling access to a memory.

  In recent years, with an increase in the speed of semiconductor integrated circuits, there is a demand for an increase in memory bus speed. Furthermore, with the growing interest in environmental issues such as global warming, the demand for lower power consumption is also increasing.

  Conventionally, in order to determine the memory access timing, a timing value consisting of the characteristics of the memory controller and the memory device is input to the memory controller and determined. For this reason, when the operating frequency of the memory device, the type of the memory device to be used, the connection configuration of the memory device, and the like are changed, there is a problem that the setting cannot be used as it is.

  As a method for solving such a problem, for example, as proposed in Patent Document 1, a weight control unit is provided to detect the number of weights suitable for the installed memory and to insert a weight. There is a device.

Further, as a technique for reducing power consumption, there are a power cutoff using an enable signal, a stop of clock supply by clock gating, a configuration with a high Vt (threshold voltage) transistor, and the like.
JP-A-9-106370

  However, if a wait is inserted into a high-speed system bus in order to respond to a request to increase the speed of the memory bus, data transfer is performed with the number of cycles accessible to the low-speed memory bus, and the data transfer time increases. This causes a decrease in system processing speed. In addition, the reduction in power consumption is effective in suppressing standby power consumption due to leakage current, but there is a problem in that it is less effective in reducing power consumption during operation.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory control apparatus and method that can achieve high speed access to the memory and low power consumption.

  A memory control device according to the present invention is a memory control device for controlling access to a memory, wherein memory voltage supply means for supplying a voltage as a power supply voltage to the memory, and weight insertion for inserting a weight for accessing the memory A memory access test means for controlling each of the memory voltage supply means and the weight insertion means to perform an access test on the memory and determining a supply voltage of the memory voltage supply means according to the test result, The memory access test means controls the weight insertion means to a state without weight insertion, and detects a minimum voltage of the supply voltage of the memory voltage supply means when the access test result is accessible. And the first test means substantially increases the supply voltage of the memory voltage supply means. If the result of the access test is inaccessible at the voltage, the supply voltage of the memory voltage supply means when the weight insertion means is controlled to be in a state with wait insertion and the result of the access test becomes accessible Second test means for detecting the lowest voltage of the memory, and voltage determining means for determining the supply voltage of the memory voltage supply means based on the first test means or the lowest voltage detected by the second test means. It is characterized by.

  The memory control method according to the present invention is a memory control method for controlling access to a memory, wherein the memory voltage supply means is used when the result of an access test to the memory becomes accessible by controlling to a state without wait insertion. A first test step for detecting a minimum voltage supplied as a power supply voltage to the memory from the memory, and a result of the access test when the output voltage of the memory voltage supply means in the first test step is substantially an upper limit voltage. If access is impossible, a second test step of detecting a minimum voltage of the supply voltage of the memory voltage supply means when the result of the access test becomes accessible by controlling to a state with wait insertion, and the first Supply of the memory voltage supply means based on the lowest voltage detected in the test step or the second test step It is characterized by comprising a voltage determination step of determining the pressure, the.

  According to the present invention, first, when the minimum voltage of the supply voltage to the accessible memory can be detected without waiting, the supply voltage to the memory is determined based on the minimum detection voltage, If the minimum accessible voltage cannot be detected, the minimum supply voltage to the accessible memory can be detected in the wait state. Since the supply voltage is determined, the power consumption of the memory can be kept low and the memory access speed can be increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a memory control apparatus as a first embodiment of the present invention. The memory control device is a device provided in a system such as a communication system, and includes a memory controller 100, a memory module 110, and a memory supply voltage control circuit 120.

  The memory controller 100 includes a system bus interface 101 that performs data transmission with a system CPU (not shown) and a system bus, a data transmission / reception module 102 that performs data transmission with the memory module 110, and data access to the memory module 110. A memory access test circuit 103 that performs a test, and a parameter setting register 104 that stores parameters for performing data access to the memory module 110 are provided.

  Further, the memory access test circuit 103 includes a memory test circuit 105, a memory supply voltage control signal generation circuit 106, and a memory weight adjustment circuit 107.

  As the memory test circuit 105, for example, an actual speed operation memory BIST (built in self-test) circuit used for a manufacturing test of the memory module 110 can be used.

  The memory controller 100 is connected to the system bus via the system bus interface 101, connected to the memory module 110 via the data transmission / reception module 102, and via the memory supply voltage control signal generation circuit 106 in the memory access test circuit 103. The memory supply voltage control circuit 120 is connected. The memory controller 100 is supplied with a system voltage Vc as a power supply voltage.

  The memory module 110 is supplied with the memory voltage Vm generated by the memory supply voltage control circuit 120 as a power supply voltage.

  Next, a memory access test operation of the memory control device having such a configuration will be described. The memory access test operation is performed as an initial operation when the system power is turned on, for example.

  First, for the memory access test, a lower limit voltage operable as the memory voltage Vm is supplied from the memory supply voltage control circuit 120 to the memory module 110 (step S1). A memory test circuit 105 provided in the memory access test circuit 103 performs an access test on the memory module 110 via the data transmission / reception module 102 to determine whether or not the access test is normally completed (step). S2). When the access test is normally completed (access is possible), when there is no wait (wait), the memory module 110 within the range of one cycle from the rising edge of the system clock to the next rising edge when a read instruction is issued from the CPU. There is data output. When there is a wait, the data output from the memory module 110 is within the range of two cycles from the rising edge of the system clock when the reading instruction is issued from the CPU to the rising edge of the next two cycles. The weight is a period corresponding to one cycle (1 cycle access).

  Usually, the memory module has a feature that the access time becomes shorter as the supplied voltage increases. Therefore, when the access test cannot be completed normally, the memory supply voltage control signal generation circuit 106 in the memory access test circuit 103 increases the memory voltage Vm supplied to the memory module 110 by a predetermined voltage. The control circuit 120 is controlled (step S3).

  After execution of step S3, the memory supply voltage control signal generation circuit 106 determines whether or not the memory voltage Vm supplied to the memory module 110 has reached the upper limit voltage (step S4). Since there is an upper limit for the operating voltage of the memory module 110 and the suppliable voltage of the memory supply voltage control circuit 120, as long as the memory voltage Vm does not reach the upper limit voltage, the process returns to step S2 to determine whether the access test has been completed normally. Is determined. On the other hand, when the memory voltage Vm reaches the upper limit voltage, the memory weight adjustment circuit 107 sets the weight (step S5). When executing step S5, the process returns to step S1 to control the memory supply voltage control circuit 120 so that the memory supply voltage control signal generation circuit 106 sets the voltage Vm supplied to the memory module 110 to the operable lower limit voltage.

  Thereafter, by executing step S2, the memory access test circuit 103 again performs an access test on the memory module 110 via the data transmission / reception module 102, and determines whether or not the access test has been completed normally. .

  Thereafter, the processing is repeated in the order of steps S3, S4, S5, S1, and S2 until it is determined in step S2 that the access test has been normally completed, and the memory voltage supplied to the memory module 110 each time it is repeated. Vm is increased.

  If it is determined in step S2 that the access test has been normally completed, the memory access test circuit 103 determines the current set value (minimum voltage) of the memory voltage Vm for the memory supply voltage control circuit 120 when the access test has been normally completed. ), A voltage value added with a voltage margin for securing the operation margin and noise margin of the memory module 110 is set as the final set value of the memory voltage Vm (step S6), and is written in the parameter setting register 104 (step S7). ).

  As shown in FIG. 3, if a read instruction from the CPU is generated at the rising point T1 of the system clock, the conventional apparatus, for example, receives data from the memory module in response to the read instruction as shown in FIG. The output is a period indicated by Valid immediately after the next clock rising time T2, and the data output from the memory controller to the CPU is a period indicated by Valid immediately after the clock rising time T3 which is further delayed by one cycle. Become.

  On the other hand, in the memory control device of the first embodiment, when the access test is normally completed only by increasing the memory voltage Vm without setting the wait within one cycle from the rising point T1 of the system clock, As shown in FIG. 3B, the data output from the memory module 110 in response to the read instruction is a period indicated by Valid from before the time T2, and the data output from the memory controller 100 to the CPU is the rising edge of the clock. The period indicated by Valid immediately after time T2 is set. Note that the voltage rise controllable range in FIG. 3 is a range from the lower limit voltage to the upper limit voltage.

  In the memory control device according to the first embodiment, when the access test is normally completed by setting the wait after reaching the upper limit in the increase control of the memory voltage Vm within the cycle from the clock rising time T1. In response to the read instruction, the data output from the memory module 110 is a period indicated by Valid having a start time within one cycle from the time T2, as shown in FIG. Data output to the CPU is a period indicated by Valid immediately after the clock rise time T3.

  As described above, according to the first embodiment, the optimum supply voltage to the memory supply voltage control circuit 120 is determined based on the result of the access test in the memory access test circuit 103 provided in the memory controller 100. As a result, the access time of the memory module 110 is improved, unnecessary weight insertion becomes unnecessary, and the data transfer time of the memory bus can be shortened.

  Even when the access voltage of the memory module 110 cannot be improved by optimizing the supply voltage in the memory supply voltage control circuit 120, for example, exceeding the controllable voltage range, compared with the conventional method. Since the supply voltage to the memory module 110 can be optimized, the operation power consumption of the memory module 110 can be reduced.

  FIG. 4 shows another embodiment (second embodiment) of the present invention. The memory control device of FIG. 4 is a device that can individually set the system voltage Vc and the system clock frequency. In addition to the configuration of the device of FIG. 1, the memory control device 210 and the system supply voltage generation circuit 220 are provided. It has.

  A system clock is supplied from the clock generation circuit 210 to the memory controller 100 and the memory module 110.

  The memory controller 100 is supplied with the power supply voltage Vc from the system supply voltage generation circuit 220.

  A frequency setting register 211 in the clock generation circuit 210 and a voltage setting register 221 in the system supply voltage generation circuit 220 are connected to the memory access test circuit 103 in the memory controller 100. The clock generation circuit 210 stores the set value of the system clock frequency in the frequency setting register 211. The system supply voltage generation circuit 220 stores the set value of the system voltage Vc in the voltage setting register 221. A frequency setting signal indicating the setting value of the system clock frequency is supplied from the frequency setting register 211 to the memory access test circuit 103, and a voltage setting signal indicating the setting value of the system voltage Vc is accessed from the voltage setting register 221 as a memory access. It is supplied to the test circuit 103.

  The configuration of the memory access test circuit 103 is the same as that of the apparatus of FIG.

  Next, the operation of the memory control device of FIG. 4 having such a configuration will be described.

  As shown in FIG. 5, the memory access test circuit 103 determines whether or not the system voltage Vc has increased or decreased according to the voltage setting signal obtained from the voltage setting register 221 in the system supply voltage generation circuit 220. (Step S11). If there is no change in the system voltage Vc, it is determined whether or not the system clock frequency has increased or decreased according to the frequency setting signal obtained from the frequency setting register 211 in the clock generation circuit 210 (step S12). If there is no change in the system clock frequency, the process is temporarily terminated.

  When the system voltage Vc increases or when the system clock frequency increases, step S2 is executed and the memory test circuit 105 provided in the memory access test circuit 103 is connected to the memory module 110 via the data transmission / reception module 102. An access test is carried out for whether or not the access test is normally completed. If the access test is not completed normally, the process is repeated in the order of steps S3, S4, S5, S1, and S2 until it is determined in step S2 that the access test has been completed normally. The memory voltage Vm supplied to the memory module 110 is increased.

  If it is determined in step S2 that the access test has been completed normally, the memory access test circuit 103 executes the above-described steps S6 and S7 to determine the final set value of the memory voltage Vm and store it in the parameter setting register. 104 is written.

  When the system voltage Vc decreases in step S11 or when the system clock frequency decreases in step S12, the memory wait adjustment circuit 107 clears the wait setting to make no wait (step S13). After execution of step S13, whether or not the memory test circuit 105 provided in the memory access test circuit 103 performs an access test on the memory module 110 via the data transmission / reception module 102 and the access test is normally completed. Is determined (step S14).

  If the access test is not normally completed in step S14, the process proceeds to execution of step S3, and the above steps S3, S4, S5, S1 are performed until it is determined in step S2 that the access test is normally completed. , S2 are repeated in this order.

  When the access test is normally completed in step S14, the memory supply voltage control signal generation circuit 106 controls the memory supply voltage control circuit 120 so as to decrease the memory voltage Vm supplied to the memory module 110 by a predetermined voltage (step S14). S15).

  After execution of step S15, the memory supply voltage control signal generation circuit 106 determines whether or not the memory voltage Vm supplied to the memory module 110 has reached the lower limit voltage (step S16). Unless the memory voltage Vm reaches the lower limit voltage, the process returns to step S14 to determine whether or not the access test is normally completed. On the other hand, when the memory voltage Vm reaches the lower limit voltage, the lower limit voltage operable as the memory voltage Vm is supplied from the memory supply voltage control circuit 120 to the memory module 110 (step S17), and the execution of steps S6 and S7 is performed. Thus, the final set value of the memory voltage Vm is determined and written to the parameter setting register 104.

  In the second embodiment, as shown in FIG. 6 (a), if a read instruction is issued from the CPU at the rise time T1 of the system clock before the frequency is changed, there is no wait setting, so the rise When the access test is normally completed within one cycle from the time T1, the data output from the memory module 110 in response to the read instruction is a period indicated by Valid before the next rise time T2, and the memory Data output from the controller 100 to the CPU is a period indicated by Valid immediately after the clock rise time T2.

  After that, if the frequency of the system clock is lowered as shown in FIG. 6B, the memory voltage Vm is lowered according to the result of the memory access test in step S14 (when the access test is not completed normally). As a result, the memory voltage Vm is increased according to the result of the memory access test in step S2, and thus, from the memory module 110 within one cycle from the system clock rising time T1 to the next rising time T2 ′ after the change in the number of cycles. There will be data output. Therefore, in the example shown in FIG. 6B, the data output from the memory module 110 is changed to the period indicated by Valid immediately before the time T2 ′, and the data output from the memory controller 100 to the CPU is the clock rising time T2. 'The period indicated by Valid from immediately after.

  Further, in the second embodiment, as shown in FIG. 7A, if a read instruction is issued from the CPU at the rise time T1 of the system clock before the frequency is changed, there is a wait setting. Therefore, when the access test is normally completed within two cycles from the rise time T1, the data output from the memory module 110 in response to the read instruction is a period indicated by Valid immediately after the next rise time T2, Data output from the memory controller 100 to the CPU is a period indicated by Valid immediately after the rising edge T3 of the clock delayed by one cycle.

  Thereafter, if the frequency of the system clock is lowered as shown in FIG. 7B, the wait setting is canceled in step S13, and the memory voltage Vm is lowered according to the result of the memory access test in step S14 (access test). Is not completed normally, the memory voltage Vm is increased in accordance with the result of the memory access test in step S2), whereby the system clock rise time T1 after the change in the number of cycles is changed to the next rise time T2 ′. The data output from the memory module 110 is made within one cycle. Therefore, in the example shown in FIG. 7B, the data output from the memory module 110 is changed to the period indicated by Valid immediately before the time T2 ′, and the data output from the memory controller 100 to the CPU is the clock rising time T2. 'The period indicated by Valid from immediately after.

  As described above, according to the second embodiment, the memory access test circuit 103 accesses the memory module 110 by performing the access test reflecting the setting values of the frequency setting register 211 and the voltage setting register 221. In addition to parameter optimization, it is possible to optimize the supply voltage Vm to the memory module 110 in response to changes in the operating clock frequency and voltage, as shown in FIG. As described above, for example, when the access time of the memory module 110 is sufficient due to a reduction in the system clock frequency, the supply voltage is optimized by controlling the supply voltage to the memory module 110 low. This can also reduce the power consumption of the memory module 110. So obtained Te Align.

  Further, as shown in FIG. 7B, when the wait set at the time of high frequency becomes unnecessary due to the reduction of the system clock frequency, the number of clock cycles required for memory access can be improved. Therefore, the data transfer time of the memory bus can be shortened.

  In the first and second embodiments described above, insertion of one weight is shown. However, the number of weights is not limited to this and may be two or more.

  The present invention is applicable to all semiconductor integrated circuits that use a memory module and perform memory access.

It is a block diagram which shows the 1st Example of this invention. 2 is a flowchart showing a memory access test operation of a memory controller in the apparatus of FIG. It is a figure which shows the data output timing with respect to a system clock. It is a block diagram which shows the 2nd Example of this invention. 5 is a flowchart showing a memory access test operation of a memory controller in the apparatus of FIG. It is a figure which shows the data output timing with respect to the system clock before the change of the frequency of a system clock, and a change. It is a figure which shows the data output timing with respect to the system clock before the change of the frequency of a system clock, and a change.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory controller 110 Memory module 120 Memory supply voltage control circuit 210 Clock generation circuit 220 System supply voltage generation circuit

Claims (5)

A memory control device for controlling access to a memory,
Memory voltage supply means for supplying a voltage as a power supply voltage to the memory;
Weight insertion means for inserting a weight for accessing the memory;
A memory access test means for controlling each of the memory voltage supply means and the weight insertion means to perform an access test on the memory and determining a supply voltage of the memory voltage supply means according to a test result;
The memory access test means controls the weight insertion means to a state without weight insertion, and detects a minimum voltage of the supply voltage of the memory voltage supply means when the access test result is accessible. Means,
If the access test result is inaccessible when the supply voltage of the memory voltage supply means is substantially the upper limit voltage by the first test means, the weight insertion means is controlled to be in a state with wait insertion and the access test is performed. Second test means for detecting a minimum voltage of the supply voltage of the memory voltage supply means when the result of
And a voltage determining unit that determines a supply voltage of the memory voltage supply unit based on a minimum voltage detected by the first test unit or the second test unit.   2. The memory control device according to claim 1, wherein the voltage determination unit determines a supply voltage of the memory voltage supply unit by adding a margin voltage to the minimum voltage.   Each of the first and second test means sets a voltage supplied as the power supply voltage from the memory voltage supply means to the memory in a stepwise manner from a lower limit voltage to the upper limit voltage, and the access test is performed for each voltage setting. The memory control device according to claim 1, wherein: The memory access test means includes detection means for detecting that either one of a system voltage and a system clock frequency of a system including the memory control device is changed or increased,
The first test means controls the weight insertion means to be in a state without weight insertion when the detection means detects that either one of the system voltage or the frequency of the system clock has changed. 2. The memory control device according to claim 1, wherein a minimum voltage of a supply voltage of the memory voltage supply means when the access test result is accessible is detected. A memory control method for controlling access to a memory,
A first test step for detecting a minimum voltage supplied as a power supply voltage from the memory voltage supply means to the memory when the result of the access test to the memory becomes accessible by controlling to a state without weight insertion; ,
If the access test result is inaccessible when the output voltage of the memory voltage supply means in the first test step is almost the upper limit voltage, the access test result is accessible by controlling to a state with wait insertion. A second test step of detecting a minimum voltage of the supply voltage of the memory voltage supply means when
And a voltage determining step of determining a supply voltage of the memory voltage supply means based on the lowest voltage detected in the first test step or the second test step.

Images