JP4477191B2 - Insulated gate semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate semiconductor device made of a GaN compound semiconductor and having high breakdown voltage and excellent noise resistance.
[0002]
[Related background]
A MOS field effect transistor (MOS-FET) is a semiconductor device having an insulated gate structure composed of a metal, an oxide film, and a semiconductor, and controls the carrier density in the channel region under the gate electrode by the field effect. Thus, the current I _D flowing between the source and drain regions is controlled.
[0003]
In this type of MOS-FET, especially for high power power FETs, the on-resistance between the source and drain, that is, the resistance of the channel under the gate electrode, which is one of the important parameters, should be made sufficiently small. is required. Incidentally, in order to reduce the channel resistance, it is only necessary to shorten the length L, widen the channel width W, and further increase the channel thickness d. However, although the channel length L and its width W can be dealt with by pattern design for realizing the element structure, the thickness d is the voltage applied to the gate electrode and the semiconductor layer in which the channel region is formed. It is determined by the carrier concentration and is generally very thin, about 1 μm. For this reason, in order to increase the thickness d of the channel, it is necessary to increase the carrier concentration by, for example, a double diffusion process of impurities, and the manufacturing process cannot be denied.
[0004]
[Problems to be solved by the invention]
Recently, nitride compound semiconductors such as GaN, AlGaN, InGaAlN and the like have attracted attention. This type of GaN-based compound semiconductor has a theoretically elucidated that the on-resistance during operation is one order of magnitude lower than that of conventional semiconductors such as GaAs and Si, and that it can operate at high temperature, high voltage and high current. It has been.
[0005]
However, the manufacturing process of a semiconductor device using a GaN-based compound semiconductor is still in the process of research and development, and various problems remain in how to realize a semiconductor device having an insulated gate structure. In addition, when the resistance of the channel is reduced, there is a problem that problems such as malfunctions with respect to noise generally occur. Incidentally, in a Si-based MOS-FET, a diode is formed between the source and drain by short-circuiting the source region with respect to the substrate on which the channel region is formed, thereby ensuring noise resistance. ing. However, a problem remains in how to provide a diode in a GaN-based compound semiconductor.
[0006]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an insulated gate semiconductor device made of a GaN compound semiconductor and having high breakdown voltage and excellent noise resistance.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the insulated gate semiconductor device according to the present invention shortens the channel length by reducing the length of the semiconductor layer in the vicinity of the gate where the channel region is formed, thereby reducing the on-resistance. In addition, a pn junction diode connected in parallel between a gate electrode and a source electrode is formed in a semiconductor layer having an insulated gate structure.
[0008]
In particular, according to the present invention, a first semiconductor layer made of a GaN-based semiconductor with a low impurity concentration and the first semiconductor layer are made of a GaN-based semiconductor with a high conductivity concentration of reverse conductivity. A second semiconductor layer embedded in the first semiconductor layer, and a high impurity concentration GaN-based semiconductor having the same conductivity as the first semiconductor layer, and embedded in the second semiconductor layer. Forming a source region and defining a length of a channel region formed in the second semiconductor, and a high impurity concentration GaN semiconductor having the same conductivity as the first semiconductor layer. A fourth semiconductor layer formed by being embedded in the first semiconductor layer away from the second semiconductor layer, or provided on the back surface of the first semiconductor layer to form the drain region; , Formed in the second semiconductor layer A fifth semiconductor layer having a conductivity opposite to that of the second semiconductor layer embedded in the side portion of the channel region to be formed, and the fifth semiconductor layer embedded in the fifth semiconductor layer and connected to the gate electrode A semiconductor device comprising a second semiconductor layer and a sixth semiconductor layer having the same conductivity and having a GaN-based insulated gate structure formed on the semiconductor layer having the GaN-based insulated gate structure; A pn junction diode connected in parallel with a source electrode is formed, and the pn junction diode is formed between the fifth semiconductor layer and the sixth semiconductor layer. To do.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
A power MOS-FET which is a GaN-based insulated gate semiconductor device according to a reference example of the present invention will be described below with reference to the drawings.
FIG. 1 is a view showing a schematic element structure of an insulated gate semiconductor device made of a GaN-based semiconductor according to this reference example , and FIG. 2 is an exploded view showing a schematic manufacturing procedure thereof. This MOS-FET is manufactured by crystal growth of a GaN-based semiconductor layer using, for example, a gas source molecular beam epitaxial growth method (MBE), and is manufactured using a metal organic chemical vapor deposition method (MOCVD). Is also possible.
[0011]
Incidentally, in this reference example , an MBE apparatus provided with an ultrahigh vacuum apparatus having a growth chamber and a patterning chamber was used. In forming the GaN film, an organic metal gas such as triethylgallium or trimethylgallium is used as the Ga source, and dimethylhydrazine is used as the nitrogen source. However, it is of course possible to use monomethylhydrazine, ammonia or the like as the nitrogen source. Further, monosilane was used as the n-type dopant, and organic Mg such as dicyclopentadienyl Mg was used as the p-type dopant.
[0012]
In the GaN MOS-FET according to this reference example , first, a conductive p-type conductive Si substrate 1 is prepared in a growth chamber, and radicalized nitrogen (4 × 10 ⁻⁴ Pa≈3 × 10 ⁻⁶ Torr) is prepared. And GaN (6.6 × 10 ⁻⁵ Pa≈5 × 10 ⁻⁷ Torr), a GaN buffer layer 2 having a thickness of 5 nm is formed on the Si substrate 1 at a growth temperature of 640 ° C. by molecular beam epitaxy. To do. Next, Ga (1.3 × 10 ⁻⁴ Pa≈1 × 10 ⁻⁶ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈5 × 10 ⁻⁵ Torr) are used on the GaN buffer layer 2, and An n ⁻ -GaN layer 3 as a first semiconductor layer is grown to a thickness of 3000 nm using Si (6.6 × 10 ⁻⁷ Pa≈5 × 10 ⁻⁹ Torr) as a dopant [see FIG. 2 (a)] .
[0013]
Next, patterning is performed on the surface of the n ⁻ -GaN layer 3 to form a rectangular groove in a region where the source electrode is to be formed, and the carrier concentration as the second semiconductor layer is 2 × 10 ¹⁸ cm ⁻ in the groove. ^A high impurity concentration p-GaN layer 4 made of 3 is formed to a thickness of 1000 nm [see FIG. 2 (b)]. The formation (growth) of the p-GaN layer 4 consists of Ga (1.3 × 10 ⁻⁴ Pa≈1 × 10 ⁻⁶ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈5 × 10 ⁻⁵ Torr). And Mg (1.3 × 10 ⁻⁸ Pa≈8 × 10 ⁻¹⁰ Torr) as a dopant and a growth temperature of 850 ° C.
[0014]
Thereafter, patterning is further performed on the surface of the n ⁻ -GaN layer 3 formed by embedding the p-GaN layer 4, and grooves are respectively formed in the region for forming the source electrode and the region for forming the drain region. In this case, since the p-GaN layer 4 is already embedded in the region where the source electrode is to be formed, one of the grooves is formed in the p-GaN layer 4. In particular, the groove formed in the p-GaN layer 4 is provided so that the length of the channel defined by the gate electrode described later and formed in the p-GaN layer 4 is as short as 50 nm or less.
[0015]
After the grooves are formed in this manner, the carrier concentration of the third semiconductor layer forming the source region and the fourth semiconductor layer forming the drain region in these grooves is a high concentration of 5 × 10 ¹⁸ cm ^−3. The n ⁺ -GaN layers 5 and 6 having an impurity concentration are formed to a thickness of, for example, 500 nm [see FIG. 2 (c)]. The formation of these n ⁺ -GaN layers 5 and 6 includes Ga (1.3 × 10 ⁻⁴ Pa≈1 × 10 ⁻⁶ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈5 × 10 ⁻⁵ Torr). ) And Si (1.2 × 10 ⁻⁷ Pa≈9 × 10 ⁻⁹ Torr) as a dopant at a growth temperature of 850 ° C.
[0016]
In this manner, the p − GaN layer 4 as the second semiconductor layer is embedded in the n ⁻ −GaN layer 3 which is the first semiconductor layer, and further, a third source region is formed in the p−GaN layer 4. the n ⁺ -GaN layer 6 as a fourth semiconductor layer forming a drain region in -GaN layer 3 ^- in the n ⁺ -GaN layer 5 as a semiconductor layer, and the n by away from the p-GaN layer 4 If the respective buried layers are formed, the surface is then patterned, and the width between the p-GaN layer 4 and the n ⁺ -GaN layer 6 of the n ⁻ -GaN layer 3 as shown in FIG. A rectangular groove 7 of about 1 μm is formed by etching. Then, SiO ₂ as an insulating gate film 8 is deposited on the trench 7 to a thickness of 100 nm.
[0017]
Thereafter, an insulating film 9 is formed on the surface, and this insulating film 9 is patterned to expose the surface of the n ⁺ -GaN layer 5 forming the source region and the surface of the n ⁺ -GaN layer 6 forming the drain region. [See FIG. 2 (e)], as shown in FIG. 1, the gate electrode G is formed on the surface of the insulating gate film 8, the source electrode S is formed on the surface of the n ⁺ -GaN layer 5, and the n ⁺ -GaN layer 6 is further formed. A drain electrode D is deposited on the surface of each.
[0018]
Thus, according to the semiconductor device manufactured as described above and having the insulated gate structure of the element structure as shown in FIG. 1, the insulating gate film 8 of the p-GaN layer 4 and the n ⁺ -GaN layer 5 are sandwiched. A narrow region becomes a channel region. Then, it flows from the source region (n ⁺ -GaN layer 5) into the n ⁻ -GaN layer 3 below the trench 7 through the channel region (p-GaN layer 4), and further to the drain region (n ⁺ -GaN layer 6). A MOS-FET in which a current flows laterally is realized. Particularly, since the channel region is formed in a narrow region of the p-GaN layer 4 sandwiched between the insulating gate film 8 and the n ⁺ -GaN layer 5, the channel length L can be sufficiently shortened. Combined with the use of a GaN-based semiconductor, a power FET capable of controlling a large current with a high breakdown voltage can be realized.
[0019]
Further, according to the element structure described above, a pn junction diode (zener diode) 10 is formed between the n ⁺ -GaN layer 5 embedded in the p-GaN layer 4 and the p-GaN layer 4, and this pn The junction diode 10 acts in parallel between the source and the gate. As a result, even if noise having a spiked high voltage is applied to the source electrode S or the like by the pn junction diode 10, the voltage is suppressed, so that malfunction due to noise is effectively prevented. Therefore, it is possible to realize a grooved short channel power FET having a high breakdown voltage and excellent noise resistance.
[0020]
Incidentally, the reference example described above is an insulated gate FET having a lateral structure, but the embodiment of the present invention can be realized as an insulated gate FET having a vertical structure. In this case, for example, an element structure as shown in FIG. In this case, although not shown in particular, for example, an n-type Si substrate is prepared, and radical (4 × 10 ⁻⁴ Pa≈3 × 10 ⁻⁶ Torr) and Ga (6.6 ×) are prepared on the Si substrate. The GaN buffer layer is formed to a thickness of 5 nm using 10 ⁻⁵ Pa≈5 × 10 ⁻⁷ Torr), and Si (6.6 × 10 ⁻⁷ Pa≈5 × 10 ⁻⁹ Torr) is added as a dopant. at a growth temperature of 850 ° C. to GaN buffer layer, n of Si-doped as the first semiconductor layer ^- growing -GaN layer 3 to 3000nm thick.
[0021]
Thereafter, the source region and the region where the gate portion of the n ⁻ -GaN layer 3 is to be formed are selectively etched to form a groove, and Ga (6.6 × 10 ⁻⁵ Pa≈5 × 10 ⁻⁷ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈5 × 10 ⁻⁵ Torr) and Mg (6.6 × 10 ⁻⁷ Pa≈5 × 10 ⁻⁹ Torr) as a dopant, A p-GaN layer 4 as a second semiconductor layer is grown at a growth temperature of 850 ° C.
[0022]
Next, a trench is formed in a region where the source region and gate portion of the p-GaN layer 4 are to be formed, and an n ⁺ -GaN layer 5 is grown as a third semiconductor layer in the trench. At this time, a groove is also formed on the side of the region where the source region is to be formed, and the n ⁺ -GaN layer 10 is simultaneously grown in the groove when the n ⁺ -GaN layer 5 is grown to form a pn junction diode. Therefore, a fifth semiconductor layer is used. The formation of these n ⁺ -GaN layers 5 and 10 includes Ga (6.6 × 10 ⁻⁴ Pa≈5 × 10 ⁻⁷ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈5 × 10 ⁻⁵ Torr). ) And Mg (6.6 × 10 ⁻⁷ Pa≈5 × 10 ⁻⁹ Torr) as a dopant at a growth temperature of 850 ° C.
[0023]
Thereafter, a groove is selectively formed in the n ⁺ -GaN layer 10, and Ga (6.6 × 10 ⁻⁵ Pa≈5 × 10 ⁻⁷ Torr) and ammonia (6.6 × 10 ⁻³ Pa≈) are formed in the groove. 5 × 10 ⁻⁵ Torr), and Mg (6.6 × 10 ⁻⁷ Pa≈5 × 10 ⁻⁹ Torr) as a dopant, p is used as the sixth semiconductor layer for forming the pn junction diode described above. -The GaN layer 11 is grown.
[0024]
Thereafter, SiO 2 as a protective film is deposited to a thickness of about 100 nm on the entire surface of the epitaxial layer described above by thermochemical deposition, and this is patterned to form the surface of the p-GaN layer 11 and the source region described above. The surface of the n ⁺ -GaN layer 5 is selectively exposed. When the surface of the n ⁺ -GaN layer 5 is exposed by patterning, the p-GaN layer 4 at the edge of the n ⁺ -GaN layer 5 is slightly exposed. The surface of the n ⁺ -GaN layer 5 to expose them, and the surface of the p-GaN layer 11, respectively deposited a source electrode S and the auxiliary electrode B as shown in FIG. 3, also the n ⁺ -GaN A gate electrode G is deposited on the upper surface of the insulating gate film 8 deposited on the surface of the layer 5. The gate electrode G and the auxiliary electrode B described above are electrically connected, and a pn junction diode composed of the n ⁺ -GaN layer 10 and the p-GaN layer 11 is connected between the gate electrode G and the source electrode S. Connect in parallel.
[0025]
Then removed and the Si substrate and the GaN buffer layer as described above, n of Si-doped ^- after forming the n ⁺ -GaN layer 6 forming a drain region on the back side of the -GaN layer 3, the n ⁺ -GaN layer 6 A drain electrode D is formed on the back side of the substrate. The n ⁺ -GaN layer 6 is formed on the GaN buffer layer prior to the growth of the Si-doped n ⁻ -GaN layer 3 and the Si ⁺ is formed on the n ⁺ -GaN layer 6. A doped n ⁻ -GaN layer 3 may be grown.
[0026]
Thus, according to the GaN-based semiconductor device manufactured in this way, a vertical structure MOS-FET in which current flows from the source region formed on the front surface to the drain region provided on the back surface side is realized. The The channel length is defined by the protruding length of the source electrode S provided so as to protrude from the surface of the n ⁺ -GaN layer 5 to the surface of the p-GaN layer 4 and is sufficiently short. A pn junction diode 10 composed of an n ⁺ -GaN layer 10 and a p-GaN layer 11 embedded in the p-GaN layer 4 of the semiconductor layer having such a vertical insulated gate structure, Since the gate electrode G and the source electrode S act in parallel, the noise resistance can be sufficiently increased as in the previous embodiment.
[0027]
Incidentally, it was confirmed that the GaN-based power MOS-FETs having the short channel structure manufactured as described above have a breakdown voltage of 500 V or more and operate reliably at an ON voltage of 30 mV or less. Moreover, it was confirmed that no malfunction occurred even for pulse noise of about 100 V, and a power MOS-FET with high breakdown voltage and excellent noise resistance could be realized using a GaN-based semiconductor.
[0028]
The power MOS-FET having such an element structure is useful in constructing an inverter circuit for driving a fluorescent lamp, for example, as shown in FIG. That is, in this type of inverter circuit, the frequency characteristic of the ballast circuit changes abruptly depending on whether the lamp is lit or not, and in a transient state where the lighting frequency shifts to the protection frequency when the lamp is not lit, the phase advance current is It flows into the power MOS-FET. Then, there is a risk that the power MOS-FET may be destroyed due to a through current flowing in the parasitic diode of the power MOS-FET. However, the GaN-based power MOS-FET having the above-described element structure has a high withstand voltage, low loss, and excellent noise resistance. Therefore, there is no fear of the above-described problems, and an inverter circuit for driving a fluorescent lamp is constructed. The effect that it is suitable for doing etc. is produced.
[0029]
The present invention is not limited to the embodiment described above. Here, a p-channel MOS-FET has been described as an example, but it is of course possible to construct an n-channel MOS-FET by reversing the conductivity of the semiconductor layer. Here, GaN is used for the n layer, but InGaN, InGaAlN, AlGaN, InGaNAs, InGaNP, etc. doped with Si or the like may be used. Similarly, Mg-doped InGaN, InGaAlN, AlGaN, InGaNAs, InGaNP, or the like can be used as the p layer. Furthermore, it is possible to use not only Si but also a conductive substrate such as SiC, GaAs, and GaPGaN as the conductive substrate. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
[0030]
【The invention's effect】
As described above, according to the present invention, a semiconductor device having a short channel type insulated gate structure is realized using a GaN-based compound semiconductor, and further, the semiconductor element structure acts in parallel between the source and the gate. A pn junction diode is provided. Therefore, it is possible to construct a high-power semiconductor device having an element structure excellent in noise resistance while utilizing the advantage that a GaN-based semiconductor has a high breakdown voltage and low on-resistance, and constitutes an inverter circuit. There are effects such as being suitable.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic element structure of a GaN-based insulated gate semiconductor device according to a reference example .
2 is an exploded view showing a schematic manufacturing procedure of the insulated gate semiconductor device shown in FIG. 1; FIG.
FIG. 3 shows a schematic device structure of an insulated gate semiconductor device of a vertical structure according to the implementation embodiments of the present invention.
FIG. 4 is a diagram showing an example of an inverter circuit for driving a fluorescent lamp configured using the insulated gate semiconductor device according to the present invention.

Claims (1)

A first semiconductor layer made of a low impurity concentration GaN-based semiconductor;
The first semiconductor layer is made of a GaN-based semiconductor having high conductivity and a reverse conductivity, and a second semiconductor layer embedded in the first semiconductor layer;
The first semiconductor layer is made of a GaN-based semiconductor having the same conductivity and high impurity concentration, is embedded in the second semiconductor layer to form a source region, and a channel region formed in the second semiconductor. A third semiconductor layer defining a length;
The first semiconductor layer is made of a GaN-based semiconductor having the same conductivity and high impurity concentration, and is embedded in the first semiconductor layer away from the second semiconductor layer, or of the first semiconductor layer. A fourth semiconductor layer provided on the back surface and forming the drain region ;
A fifth semiconductor layer having a conductivity opposite to that of the second semiconductor layer embedded in the side portion of the channel region formed in the second semiconductor layer;
A GaN-based insulated gate structure comprising: a second semiconductor layer embedded in the fifth semiconductor layer and connected to the gate electrode; and a sixth semiconductor layer having the same conductivity as the second semiconductor layer. A semiconductor device,
Forming a pn junction diode connected in parallel between the gate electrode and the source electrode in the semiconductor layer having the GaN-based insulated gate structure ;
The insulated gate semiconductor device , wherein the pn junction diode is formed between the fifth semiconductor layer and the sixth semiconductor layer .

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