JP4479619B2 - Circuit diagram creation support device and circuit layout verification device - Google Patents

Description

The present invention relates to a circuit layout verification apparatus for verifying by checking the circuit diagram creation support apparatus and circuit diagram and layout diagram for creating supporting schematics.

  When designing a semiconductor integrated circuit such as an IC or LSI, system design, functional design, etc. are performed, then circuit design is performed, and a circuit diagram is created by a circuit diagram creation support device, and layout design is performed based on the circuit diagram, for example. And a layout diagram is created by the layout creation support device. When creating such a circuit diagram or layout diagram, a CAD tool installed in a computer such as a PC or EWS is used. In order to verify the consistency between the circuit diagram and the layout diagram, a circuit layout verification device has been developed. An example of this layout verification apparatus is disclosed in Patent Document 1.

According to Patent Document 1, LVS (Layout Versus Schematic) verification is performed, and equipotential tracking of the wiring portion is performed, and a list of conductor figures is created for each block based on the extracted results. And the wire breakage is automatically verified.
JP 2004-118348 A

In Patent Document 1, in order to perform equipotential tracking of wiring, the verifier needs to correctly indicate the position coordinates and terminal coordinates of each terminal. In this case, if this verification method is applied in a semiconductor integrated circuit such as an IC or LSI, it is necessary to correctly specify a large number of position coordinates, terminal coordinates, etc., so that the verifier incorrectly specifies the position coordinates and terminal coordinates. There is also a risk of it. If at least one of the position coordinates, terminal coordinates, etc. is not correctly indicated, there is a problem that the verification process cannot be correctly determined.
That is, although it is necessary to correctly indicate position coordinates, terminal coordinates, etc., it takes time to correctly specify a large number of position coordinates, etc., which is inefficient. Furthermore, since the consistency between the circuit diagram and the layout diagram cannot be confirmed without performing other verification processing disclosed in Patent Document 1 in addition to LVS verification, it takes much longer time.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit diagram creation support apparatus and layout diagram creation support that can greatly reduce the work time when creating or verifying a circuit diagram or layout diagram. An apparatus and a circuit layout verification apparatus are provided.

  The invention described in claim 1 is directed to a circuit diagram creation support apparatus for supporting creation of a circuit diagram in a semiconductor integrated circuit such as an IC or LSI. The first aspect of the invention operates as follows. When a branch symbol that functions as a wiring element between circuit symbols is input to the circuit diagram creation support apparatus, the accepting unit accepts the branch symbol. Then, the circuit diagram creation support apparatus regards a node between circuit symbols as a plurality of nodes divided by the branch symbol when a branch symbol is arranged between circuit symbols as a circuit diagram.

  When the circuit layout verification apparatus performs verification between a circuit diagram and a layout diagram, if a branch symbol is arranged between circuit symbols, a node between the plurality of circuit symbols is divided into a plurality of branch symbols. Verification is performed in a state regarded as a node. Therefore, it is not necessary for the verifier to specify the position coordinates and the terminal coordinates, so that the position coordinates and the terminal coordinates are not erroneously designated. As a result, the working time when creating or verifying a circuit diagram or layout diagram can be greatly reduced. In addition, it is not necessary to perform another verification process for LVS verification, and it is not necessary to provide a separate verification program in the circuit layout verification apparatus.

When a circuit designer or layout designer designs a circuit, specify a relatively wide wiring width for a node with a large current capacity through which a relatively large amount of current flows, and specify a relatively thin pattern in the opposite case. There are many cases. However, in general, the circuit designer and layout designer are often different persons, and when the circuit designer creates a circuit diagram, the wiring width cannot be specified in the semiconductor integrated circuit, and wiring is performed separately from the circuit diagram. It becomes necessary to specify the width. Therefore, a means Receptionist, it is desirable to accept a wire width information set for the branch symbol on the circuit diagram. That is, if the wiring width information is set for the branch symbol, the intention of the circuit designer can be transmitted to the layout designer.

  At this time, when the circuit layout verification apparatus performs verification between the circuit diagram and the layout diagram, if a branch symbol is provided between the layout symbols, a node between the plurality of layout symbols is divided by the branch symbol. The verification process is performed in a state that the nodes are regarded as a plurality of nodes. Therefore, it is not necessary for the verifier to specify the position coordinates and the terminal coordinates, so that the position coordinates and the terminal coordinates are not erroneously designated. As a result, the work time for verifying the circuit diagram and the layout diagram can be greatly reduced. In addition, it is not necessary to perform another verification process for the LVS verification, and the circuit layout verification apparatus does not need a separate verification program.

Further, it is desirable to set the length of the branch symbol between the layout symbols to the length of the preset unit width of the wiring elements constituting the layout symbol. In this case, since the length of the branch symbol becomes the shortest length of the unit width of the layout symbol, the layout designer can easily design the layout.

The invention according to claim 2 verifies a circuit diagram and a layout diagram in a semiconductor integrated circuit such as an IC and an LSI designed in advance, and connects a circuit symbol constituting the circuit diagram and a layout symbol node constituting the layout diagram. It is intended for a circuit layout verification apparatus provided with verification means for verifying state consistency. According to the second aspect of the present invention, when the verification means includes a branch symbol between the circuit symbols or the layout symbols, the verification means determines that a plurality of nodes are regarded as a plurality of nodes by the branch symbols. Since the consistency of the connection state of the nodes is verified, it is not necessary for the verifier to specify the position coordinates and the terminal coordinates. As a result, the work time for verifying the circuit diagram and the layout diagram can be greatly reduced. In addition, it is not necessary to perform another verification process for the LVS verification, and a verification program is not required for the circuit layout verification apparatus.

  Hereinafter, an embodiment applied to a design support apparatus having all the functions of a circuit diagram creation support apparatus, a layout creation support apparatus, and a circuit layout verification apparatus of the present invention will be described with reference to FIGS. Although circuit diagrams and layout diagrams are often designed by another person, in this embodiment, an embodiment in which all of circuit diagram creation, layout creation, and circuit layout verification are executed in the same apparatus will be described. FIG. 4 shows an example of a schematic configuration and a circuit diagram of the design support apparatus.

  As shown in FIG. 4, the design support apparatus 1 is an apparatus for supporting the design of the semiconductor integrated circuit 2, and is composed of a computer such as a PC (Personal Computer) or an EWS (Engineering WorkStation). The semiconductor integrated circuit 2 is intended for a multilayer structure (for example, a three-layer structure), and a CAD (Computer Aided Design) tool is incorporated in the design support apparatus 1.

  The circuit design support function, the layout design support function, and the circuit layout verification function are realized by a program incorporated in the design support apparatus 1. The design support apparatus 1 has a function of accepting a circuit symbol 5 (see FIG. 2) as a circuit diagram and a function of accepting a layout symbol 6 (see FIG. 3) as a layout diagram.

The design support apparatus 1 includes an input device 3 configured by, for example, a keyboard, a mouse, a digitizer, and a display device 4 configured by, for example, a liquid crystal display.
The input device 3 inputs electrical connection information when the designer combines and designs the circuit symbols 5 or inputs layout information indicating the relative arrangement relationship of the layout symbols 6 constituting the semiconductor integrated circuit 2. Is provided to do.

  The circuit symbols 5 and layout symbols 6 correspond to symbols such as circuit elements such as FETs, bipolar transistors, resistors and capacitors, terminals of the circuit elements, GND terminals, power supply terminals, test terminals, and the like. Yes.

  The circuit designer performs system design and functional design, designs a circuit from the design contents, and creates a circuit diagram A (see FIG. 2). The layout designer performs layout design from the created circuit diagram and creates a layout diagram B (see FIG. 3). The design support apparatus 1 described above is used to perform this series of operations.

  A series of design work performed by a circuit designer, layout designer, and verifier will be described below. A circuit designer performs circuit design using the design support apparatus 1. FIG. 2 shows an example of a screen displayed on the display device 4 when circuit design is performed. In FIG. 2, the circuit designer arranges the input terminal symbol IN1 and the output terminal symbols OUT1 to OUT4 on the screen of the display device 4 with respect to the design support apparatus 1, and also includes the transistor symbol Tr1 and the resistance symbols R1 and R2. Is arranged on the screen. Among these, the input terminal symbol IN1 and the output terminal symbols OUT1 to OUT4 are symbols having one terminal. A transistor symbol Tr1 indicates a symbol of a three-terminal BJT transistor. Resistance symbols R1 and R2 are two-terminal resistance symbols.

  The branch symbols V <b> 1 to V <b> 3 are two-terminal node symbols, and are treated as, for example, weak resistances as wiring elements in the design support apparatus 1. As shown in FIG. 3, the branch symbols V1 to V3 are arranged between the wirings on the layout diagram B, and the branch symbols V1 to V3 are not affected to the actual internal design of the semiconductor integrated circuit 2. The length d of V3 (the length in the horizontal direction in FIG. 3) is set short. The lengths d of the branch symbols V1 to V3 are fixedly set to, for example, the unit width of the wiring (grid width: for example, pattern width), and are extremely shorter than the resistance symbols R1 and R2. Furthermore, the length is extremely shorter than the wiring actually disposed in the integrated circuit 2. The branch symbols V1 to V3 are configured in a layer different from the wiring.

  When the circuit designer uses the branch symbols V1 to V3, it is used when the layout pattern in the semiconductor integrated circuit 2 is designed and the wiring pattern width or the like is characteristically changed. As shown in FIG. 2, the input terminal symbol is connected to the node N2 to which the base of the transistor symbol Tr1 is connected, the node N3 to which the resistance symbol R1 is connected, and the node N4 to which the resistance symbol R2 is connected. Branch symbols V1 to V3 are used when it is desired to change or specify the allowable amount (wiring width) of the current flowing from IN1. At this time, since the lengths of the branch symbols V1 to V3 are fixedly set to the minimum line width of the wiring, they are easily arranged on the layout diagram B.

  In FIG. 2, branch symbols V1 to V3 are arranged as follows. A branch symbol V1 is arranged between the input terminal node IN1 and the base node N2 of the transistor symbol Tr1. A branch symbol V2 is disposed at a node N3 where the input terminal node IN1 and the resistance symbol R1 are connected. A branch symbol V3 is arranged at a node N4 to which the input terminal node IN1 and the resistance symbol R2 are connected. The design support apparatus 1 accepts these branch symbols V1 to V3 as a circuit diagram A.

  These branch symbols V1 to V3 are respectively attached with wiring width information. The wiring width information indicates information on a relative width or an absolute width of a metal film (aluminum wiring) functioning as a wiring inside the semiconductor integrated circuit device. For example, as shown in FIG. 2, when “20” is set for the branch symbol V1 and “40” is set for the branch symbol V2, the wiring width of the branch symbol V2 is set to the wiring width of the branch symbol V1. It can be easily grasped that the wiring width of the ratio twice is relatively required. Further, when “100” is assigned to the branch symbol V3, it is necessary that the wiring width of the branch symbol V3 is five times as large as the wiring width of the branch symbol V1. Easy to grasp.

  FIG. 1 schematically shows a flow of circuit diagram creation, layout diagram creation, and verification. When the circuit designer A completes the circuit diagram A by the design support apparatus 1, the circuit designer stores it as circuit diagram data D1. At this time, the net list L1 is created by the net lister N built in the design support apparatus 1. In the net list L1, information on nodes corresponding to the terminals of the circuit symbols 5 is stored. For example, since the branch symbol V1 is arranged between the nodes N1 and N2, information of the nodes N1 and N2 is stored in the netlist L1 corresponding to the branch symbol V1.

  Further, since the transistor symbol Tr1 has a base corresponding to the node N2, an emitter corresponding to the node N5, and a collector corresponding to the node N6, the nodes N2, N5 and N6 are stored corresponding to the respective terminals of the transistor symbol Tr1.

  Since resistance symbol R1 is arranged between nodes N3 and N7, nodes N3 and N7 are stored in netlist L1 corresponding to resistance symbol R1. Since resistance symbol R2 is arranged between nodes N4 and N8, nodes N4 and N8 are stored in netlist L1 corresponding to resistance symbol R1. Similarly, node N1 is stored in netlist L1 corresponding to input terminal symbol IN1. Further, the nodes N5 to N8 are stored corresponding to the output terminal symbols OUT1 to OUT4, respectively.

  Thereafter, the layout designer creates a layout B based on the circuit diagram A drawn by the circuit designer. When the layout designer creates the layout B, the design support apparatus 1 is used. In practice, the design support apparatus 1 has been provided with a circuit-layout creation support function. For this reason, when the layout designer creates the layout diagram B after the circuit diagram A is created by the circuit designer, the design support apparatus 1 uses the layout diagram B (layout) from the circuit diagram data D1 according to the layout designer's instruction. Data D2) is created as an auxiliary. Specifically, when the design support apparatus 1 automatically creates the layout data D2 from the circuit diagram data D1, the layout diagram B (layout data D2) based on the netlist L1 created based on the circuit diagram data D1. Create

  However, even if the layout designer uses the circuit-layout creation assistance function by the design assistance apparatus 1, it cannot be designed in detail up to the actual internal state of the semiconductor integrated circuit 2. The layout diagram B created is corrected to correct the layout diagram B.

  At this time, the layout designer performs the layout design based on the circuit diagram A shown in FIG. 2, but since the wiring width information is attached to the branch symbols V1 to V3, the branch symbol V1 as shown in FIG. It is easy to set the wiring width around V3. That is, the layout designer can easily create the layout diagram B by setting the branch symbols V1 to V3 to widths corresponding to the wiring width information.

  If the design support apparatus 1 is set not to accept the branch symbols V1 to V3, the node N1 and the nodes N2 to N4 in the circuit diagram A are the same node. At this time, even if the layout designer creates the layout diagram B based on the circuit diagram A, if the wiring width information is not properly transmitted from the circuit designer to the layout designer, the layout designer Since the designer cannot grasp the wiring width, the layout diagram B is designed with an appropriate wiring width.

  In particular, when the wiring width of the ground and the power supply line is not set appropriately, there is a risk that digital noise may affect the surroundings and cause various problems in the actual circuit. In this case, for example, a reconsideration between the circuit designer and the layout designer is required, and work efficiency is lowered. According to this embodiment, the layout designer can set the branch symbols V1 to V3 to a width corresponding to the wiring width information and create the layout diagram B (layout data D2), so that work efficiency can be improved.

  The layout data D2 is data in which the layout is stored in a state of being divided into a plurality of layers, and is used for forming the layers for forming the transistor symbol Tr1 and the resistance symbols R1 and R2 and the branch symbols V1 to V3. Each symbol is stored for each wiring dummy layer. The layout data D2 is graphic data (GDS2 data or the like) indicating a layout corresponding to the circuit diagram A.

  When the layout designer completes the design of the layout diagram B (layout data D2), the design support apparatus 1 extracts circuit connection information based on the layout data D2 (see S in FIG. 1). Next, the design support apparatus 1 creates a net list L2 using the net lister N. Since the net list L2 created at this time is created based on the layout data D2, the layout designed by the layout designer is reflected.

  On the other hand, as described above, the netlist L1 reflects the circuit diagram A designed by the circuit designer. Thereafter, the design support apparatus 1 performs LVS verification according to the instruction of the verifier. Then, the design support apparatus 1 collates the netlists L1 and L2 by LVS verification (see K in FIG. 1).

  During the LVS verification process, the design support apparatus 1 determines whether or not the potentials of the corresponding nodes between the netlists L1 and L2 are equal. Therefore, the design support apparatus 1 determines that the nodes that are physically connected in the LVS verification have the same potential, and thus is determined to be OK. For example, in FIG. 2, in the case of a circuit not provided with the branch symbols V1 to V3, the collation result is OK regardless of the wiring connection state for the same node. That is, the collation result is determined to be OK regardless of the form of the wiring width. However, in this embodiment, since the branch symbols V1 to V3 are provided, the nodes of the circuit diagram A and the layout diagram B can be distinguished, and the LVS verification is performed for each of the nodes N1 to N8.

The design support apparatus 1 informs that the netlists L1 and L2 are collated by the LVS verification and, if the collation is possible, “OK”. If the design support apparatus 1 cannot collate, the design support apparatus 1 notifies the collation error to the outside.
For example, although the circuit designer has used the branch symbols V1 to V3 to normally divide the nodes N2 to N4 in the circuit diagram A and arrange the circuits, the layout designer can use the node N2a in the layout diagram B. When N4a (nodes N2 to N4 in the circuit diagram A) is wired so as to be short-circuited, a verification error is notified.

Further, for example, the circuit designer conversely wires the nodes N2 to N4 in the circuit diagram A so as to short-circuit (short), and the layout designer uses the branch symbols V1 to V3 to use the node N2a in the layout diagram B. The collation error is also notified when .about.N4 is normally divided. Circuit designers and layout designers can feed back the collation results and redesign.
In addition, when the netlists L1 and L2 are collated by the LVS verification, the design support apparatus 1 also collates relative or absolute wiring width information set in the branch symbols V1 to V3. That is, the wiring width information set for the branch symbols V1 to V3 in the circuit diagram A and the widths of the branch symbols V1 to V3 in the layout diagram B (length in the vertical direction in FIG. 3) fall within a predetermined error range. Check whether or not If it is not actually within the error range, the design is repeated with feedback.
When the collation result is OK, a circuit is manufactured in the semiconductor package based on the layout diagram B. In this case, the branch symbols V1 to V3 have a length d (lateral length d in FIG. 3) fixed to the minimum line width of the aluminum wiring (grid width for design in layout diagram B). Since it is set and is extremely shorter than the length arranged as the aluminum wiring in the layout diagram B, it is convenient for the layout designer to create the actual layout diagram B.

In the technology so far, since a circuit designer created a circuit diagram at the circuit design stage and connected wiring between elements in the circuit diagram, a method for instructing a wiring method on the circuit diagram has not been established. When it is necessary to physically divide a plurality of equipotential wirings having the same electrical potential, it is necessary for the layout designer to perform layout wiring while being aware of the circuit diagram A. Moreover, since automatic verification cannot be performed, it is necessary to visually check the circuit diagram A and the layout diagram B. However, in recent years, there has been a trend toward large-scale circuits and multi-layered wiring, so that it is not possible to deal with a huge amount of wiring, and it takes a very long time.
According to the present embodiment, a plurality of branch symbols V1 to V3 are arranged as wiring elements between the node N1 and the nodes N2 to N4 on the circuit diagram A, respectively. Since the node N1 and the nodes N2 to N4 are received as separate nodes divided by the branch symbols V1 to V3, the layout designer can easily perform the layout design with reference to the circuit diagram A. Thereby, work time can be reduced significantly.

  Further, a plurality of branch symbols V1 to V3 are arranged as wiring elements between the plurality of layout symbols 6 in the design support apparatus 1, and similarly, the design support apparatus 1 internally includes the node N1 and the nodes N2 to N4. Are received as separate nodes divided by the branch symbols V1 to V3, the netlist L1 created based on the circuit diagram data D1 and the netlist L2 created based on the layout data D2 are LVS. Verification processing can be performed simply by verification. Therefore, it is not necessary to prepare a separate program in the design support apparatus 1 in addition to the LVS verification process. Since it is not necessary for the verifier to specify the coordinates, human errors can be reduced as much as possible.

  When the layout designer performs the layout design, the layout diagram B can be created while confirming the wiring width information of the circuit diagram A, so that the work efficiency is improved.

<Usage of branch symbols>
FIG. 5A and FIG. 5B show another usage pattern of the branch symbol.
For example, in order to protect the circuit from instantaneous voltage and current coming from the outside of the semiconductor integrated circuit, a surge absorption circuit for absorbing surge current may be provided. At this time, if the layout (physical arrangement state) of the circuit block in the semiconductor integrated circuit is poor, there is a high possibility that elements constituting the circuit block are destroyed. However, when the circuit designer designs only the circuit diagram, the circuit design philosophy is often not transmitted to the layout designer, and when the layout designer designs the layout, the circuit design philosophy by the circuit designer is the semiconductor integrated circuit 2. There is also a possibility that it is not reflected in the substantial circuit. This is because the circuit designer may want to arrange the nodes physically separated even if the nodes are electrically connected.

Therefore, the circuit designer arranges the branch symbols V described above as shown in FIG. 5A in order to instruct the layout designer to lay out the circuit blocks. FIG. 5A shows an example of a circuit diagram A. FIG. 5B shows an example of the layout diagram B.
As shown in FIG. 5A, the circuit blocks 11 to 13 are electrically connected to each other by wiring. These circuit blocks 11 to 13 are provided with mutually independent circuits. In addition, although embodiment applied to the circuit blocks 11-13 is shown, these may be a single element.

The circuit block 11 is an input circuit for the semiconductor integrated circuit, and is a circuit block that receives an input signal from the outside of the semiconductor integrated circuit. The circuit block 12 is a surge absorbing circuit block for absorbing a surge current flowing through the circuit block 11. The circuit block 13 is an output circuit that receives a signal from the circuit block 11 and outputs the signal after predetermined processing.
Among these circuit blocks 11 to 13, one branch symbol V is arranged between the circuit blocks 11 and 12. One branch symbol V is arranged between the circuit blocks 12 and 13. Further, two branch symbols V are arranged between the circuit blocks 11 and 13.

  The circuit designer designs the circuit diagram A in FIG. 5A and gives it to the layout designer. Then, the layout designer designs the layout diagram B shown in FIG. 5B based on the circuit diagram A. Note that FIG. 5B is a schematic layout diagram, and it should be noted that this is different from an actual circuit block arrangement relationship.

  At this time, the layout designer can arrange the circuit blocks 11 and 12 at positions close to each other by referring to the circuit diagram A, and can arrange the circuit blocks 12 and 13 at positions close to each other. it can. That is, even if the layout designer does not know that the circuit block 12 is a surge absorbing circuit, the circuit designer's circuit design concept can be transmitted to the layout designer, and work efficiency can be improved.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
Although the embodiment in which the branch symbols V1 to V3 are arranged between the input terminal symbol IN1 and the transistor symbol Tr1 and the resistance symbols R1 and R2 is shown, the present invention is not limited to this. It can be applied to various circuits. For example, the external power connection terminal of the semiconductor integrated circuit 2 and the power supply terminal node of the functional block, the external ground connection terminal of the semiconductor integrated circuit 2 and the ground node of the functional block, and harmonic noise caused by a clock signal having a relatively high frequency are generated. The present invention can also be applied to wiring around the wiring through which the clock signal easily flows. Furthermore, it is possible to apply the branch symbols V1 to V3 when it is desired to provide a dedicated wiring for an element that requires accuracy.

For example, a ground of an analog circuit system or a digital circuit system is a circuit that is easily affected by various noises when the wiring connection state is poor. In this case, even if the circuit designer draws a circuit diagram, the ground design is often not done, so the layout designer cannot efficiently work at the stage of drawing the layout diagram. Therefore, if the design support apparatus 1 accepts the branch symbols V1 to V3, the wiring width of the ground and the power supply line can be easily changed. The same applies to the ground of the power system circuit.
Although the embodiment in which the branch symbols V1 to V3 are two terminals has been described, the present invention is not limited to this, and may be a branch symbol having three or more terminals. In the above-described embodiment, the wiring width information is attached to the branch symbols V1 to V3. However, the present invention is not limited to this, and the branch symbols V1 to V3 may be applied to those having no wiring width information. The present invention may be applied to a case in which wiring thickness information is attached instead of or in addition to width information.

Flowchart of verification of circuit diagram and layout diagram according to one embodiment of the present invention Diagram showing an example of a circuit diagram Diagram showing an example of layout diagram The figure which shows the display aspect of a structure and circuit diagram of a design support apparatus (A) And (b) is a figure which shows the example of usage

Explanation of symbols

  In the drawings, reference numeral 1 denotes a design support device (circuit diagram creation support device, layout creation support device, circuit layout verification device, reception unit, verification unit).

Claims (2)

A circuit diagram creation support device for creating a circuit diagram in a semiconductor integrated circuit such as an IC or LSI by combining a circuit symbol having a predetermined function and having one or more nodes,
Receiving means capable of receiving the circuit symbol as the circuit diagram;
The receiving means is configured to receive a branch symbol that has a plurality of nodes and functions as a wiring element between the plurality of circuit symbols on the circuit diagram, and the branch symbols are arranged between the circuit symbols. The nodes between the circuit symbols are regarded as a plurality of nodes divided by the branch symbols,
The accepting means accepts wiring width information set for a branch symbol on the circuit diagram , and transmits the intention of the circuit designer to the layout designer . Validate circuit diagrams and layout diagrams in semiconductor integrated circuits such as ICs and LSIs designed in advance, and verify the consistency of the connection status of the circuit symbols constituting the circuit diagrams and the nodes of the layout symbols constituting the layout diagrams. In a circuit layout verification apparatus provided with verification means for
The verification means matches the connection state of the node between the circuit symbol and the layout symbol in a state in which the branch symbol is regarded as a plurality of nodes when the branch symbol is arranged between the circuit symbols or between the layout symbols. Verify the sex,
The circuit verification apparatus according to claim 1, wherein the verification means collates the wiring information set in the branch symbol of the circuit diagram and the width of the branch symbol of the layout diagram within a predetermined error range .

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