JP4484891B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a package structure of a semiconductor device and a method for manufacturing the same, and more particularly to a package structure suitable for application to a CSP type integrated circuit package.

  With the demand for downsizing and speeding up of electronic information equipment, technological development for reducing the size of a semiconductor device mounted on the electronic information equipment is thriving. From the viewpoint of high-density mounting, the mounting method that omits the conventional package form that physically and chemically protects the integrated circuit chip with a package, such as bare chip mounting, is considered the ultimate. Has not yet been widely adopted in general consumer equipment. CSP (Chip Size Package) is a package in which the size of an integrated circuit package is increased to a level that is equal to or slightly larger than the chip size. Since the CSP has a package structure in which the integrated circuit chip is covered with a resin or other sealing material as in the conventional package, the CSP is more reliable and easy to handle than the bare chip mounting.

  FIG. 7 shows an example of a conventional CSP type package. On an insulating substrate 3 made of polyimide film on which a copper pattern 4 is formed, an integrated circuit chip 2 is attached via an adhesive generally called a die paste 9. One end of the copper pattern 4 is located below the integrated circuit chip 2 and is connected to the solder bumps 7 through through holes 3 a formed in the insulating substrate 3.

Here, the step of attaching the integrated circuit chip to the insulating substrate is performed according to the following procedure. That is,
(1) A liquid adhesive made of a thermosetting resin such as epoxy is dropped on one or several places on the insulating substrate.
(2) The integrated circuit chip is pressed from above on the surface of the insulating substrate onto which the adhesive is dropped, and the liquid adhesive is spread over substantially the entire area of the lower surface of the chip.
(3) In this state, the chip is fixed by raising the ambient temperature and curing the liquid adhesive.

  In this case, in the step (2), a hollow portion where the adhesive does not spread may occur in a region under the integrated circuit chip surrounded by the copper pattern. This is because the adhesive in the region is pulled between the copper pattern and the integrated circuit chip due to the surface tension of the adhesive. When a cavity is formed under the chip in this way, water vapor is generated here. During solder reflow during package mounting, water vapor in the cavity expands, causing separation between the insulating substrate and the integrated circuit chip.

  Further, the cavity weakens the physical pressure resistance strength of the integrated circuit chip. When an insulating substrate on which an integrated circuit chip is mounted is placed in a mold and resin is injected into the mold, the integrated circuit chip may be broken by the pressure.

  The object of the present invention is to completely eliminate or minimize the cavities generated under the integrated circuit chip, thereby avoiding chip peeling and cracking problems caused by the cavities, and reducing the manufacturing yield of integrated circuit packages. It is to improve.

  Another object of the present invention is to realize the above object without decreasing the productivity of the package and without increasing the package cost.

  The present invention is suitable for application to a package having external connection terminals such as solder bumps directly under an integrated circuit chip in order to make the package as close to the chip size as possible, such as a CSP type package. However, the present invention is widely applicable to all semiconductor devices having a structure in which at least a part of the conductor pattern on the insulating substrate is located under the integrated circuit chip. The insulating substrate on which the integrated circuit chip is mounted has a conductive pattern for electrically connecting the electrode pad of the chip and the external connection terminal on the chip mounting surface side. It has a pattern in the area. The pattern divides the area into a plurality of small areas. The integrated circuit chip is attached to the insulating substrate via an adhesive layer, that is, a die paste so as to cover a part of the conductor pattern, the pattern, and the divided small regions.

  With the above pattern, the area under the chip is divided into a plurality of small areas, and the generation of cavities under the chip is completely or minimized. That is, the die paste before curing in each of the small regions is surrounded by the pattern, and as a result, there is almost no movement amount of the die paste due to surface tension. If the die paste before curing is stable in each small region, the generation of cavities can be suppressed.

  The pattern can be composed of one continuous pattern or a plurality of divided patterns, but is preferably composed of a plurality of block-shaped patterns arranged in a staggered pattern. Further, the block-like pattern may be a substantially square pattern having a diameter of 0.1 to 1.0 mm, preferably 0.3 to 0.5 mm.

  The pattern is not particularly limited as long as there is no problem in bonding to the insulating substrate and the die paste, but the same material as the conductive pattern is formed on the insulating substrate simultaneously with the formation of the conductive pattern. Is advantageous in terms of manufacturing.

  The plurality of small regions formed under the integrated circuit chip do not need to be completely divided by the pattern, and the adhesive in one region cannot move to the adjacent region due to the surface tension. What is necessary is just to be divided into. Each region surrounded by the block-like pattern preferably has a diameter of 0.9 mm or less.

  Further, the present invention is suitable for application to a semiconductor device in which an integrated circuit chip is mounted on an insulating substrate with its circuit forming surface facing up. However, the integrated circuit chip is placed with the circuit forming surface facing the insulating substrate. The present invention is also useful for a so-called flip chip type semiconductor device to be mounted. As the insulating substrate, a hard substrate made of an epoxy resin or the like, and a flexible substrate using a polyimide film or the like can be used.

  According to the present invention, the cavity generated under the integrated circuit chip can be completely eliminated or minimized. As a result, the problem of chip peeling and cracking caused by the cavity can be avoided, and the manufacturing yield of the integrated circuit package can be improved.

  In order to realize the present invention, it is only necessary to form a predetermined pattern under the integrated circuit chip, so that the productivity of the semiconductor device is not lowered and the production cost is not increased.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 show a semiconductor device of a CSP type package to which the present invention is applied. The semiconductor device 1 includes an insulating substrate 3 that is slightly larger in plan than the integrated circuit chip 2. In one embodiment, the insulating substrate 3 is a polyimide film piece having a 12 mm square and a thickness of 0.075 mm.

  A large number of copper patterns 4 for electrically connecting the integrated circuit chip 2 and solder bumps 7 as external connection terminals are formed on the surface of the insulating substrate 3. One end of each copper pattern 4 is located on a through hole 3a formed in the insulating substrate 3, and is connected to the solder bump 7 through the through hole 3a. In the present specification, this region is hereinafter referred to as a bump connection land 4b. The bump connection lands 4b of each copper pattern are continuously arranged along each side of the insulating substrate 3 corresponding to the position of the through hole 3a, and are arranged in three rows orthogonal to the direction of the arrangement. Has been placed.

  The other end of the copper pattern 4 extends toward the outside of the insulating substrate 3 and reaches the end. A region 4 a wider than the line width of the pattern is formed on the inner side from the end of the copper pattern 4. One end of the conductor wire 5 extending from the electrode pad 2a formed on the circuit forming surface side of the integrated circuit chip 2 is connected to this wide region. Hereinafter, this region is referred to as a wire connection land 4a. In addition, the part from the wire connection land 4a of the copper pattern 4 to the edge part of the insulating substrate 3 is a part used as a test terminal in a part of the manufacturing process. One end is a bump connection land 4b, and the other end is a wire connection land 4a. In the embodiment, the copper pattern 4 has a line width of about 0.04 mm, the bump connection land 4b has a width of about 0.3 mm, and the wire connection land 4a has a width of about 0.1 mm. The pitch between adjacent bump connection lands 4b is about 0.5 mm.

  In the central region surrounded by the copper pattern 4 on the surface of the insulating substrate 3, a large number of rectangular patterns 6 are two-dimensionally arranged at regular intervals. The rectangular pattern 6 is a copper foil pattern made of the same material as the copper pattern 4, and is formed on the insulating substrate 3 together with the copper pattern 4 as will be clarified in the manufacturing process of the semiconductor device 1 described later. The arrangement of the rectangular pattern 6 and the copper pattern 4 is clearly shown in the plan view of the insulating substrate shown in FIG. As is apparent from this figure, the rectangular patterns 6 are staggered, that is, arranged so that the relationship between adjacent rows is staggered, and as a result, out of the regions surrounded by the copper pattern 4, the rectangular pattern 6 The area excluding this part is divided into a large number of small areas. Hereinafter, each area is referred to as a divided area A. Each divided area A is surrounded by four rectangular patterns 6. Since the individual rectangular patterns 6 are arranged away from the adjacent rectangular patterns 6, one divided area A is spatially continuous with the adjacent divided areas.

  FIG. 5 shows the relationship between the arrangement of the rectangular patterns 6 and the cavities that can be formed in the divided areas A surrounded by the rectangular patterns. In the figure, the outer shape of the largest cavity that can be formed in the divided region A is indicated by a virtual line V. The size of the cavity V is determined by the arrangement of the rectangular patterns 6, that is, the pitch P, and the size of each rectangular pattern 6, that is, the side length L. It must be avoided that the cavity V is in contact with the adjacent cavity V and one large cavity is formed. In order to arrange the cavities at a distance that does not contact each other, the diameter D of the cavities and the length L of the sides of the rectangular pattern 6 need to satisfy 0.4D <L (Equation 1). On the other hand, from the test results, the diameter D of one cavity that can be formed is satisfied in order to satisfy Level 4 (left at 30 ° C./60% for 48 hours) in the moisture-proof packaging level of JEDEC (Joint Electron Device Engineering Council) As a result, it was found that 0.9mm or less was good. By substituting this into Equation 1, L> 0.36 mm is obtained. In one embodiment, the length L of the rectangular pattern 6 is about 0.4 mm, and the pitch P between the patterns is about 1.0 mm.

  As shown in FIGS. 2 and 3, a solder mask 8 made of epoxy resin is applied to the entire surface of the insulating substrate 3 on which the copper pattern 4 and the rectangular pattern 6 are formed. For bonding the conductor wire 5, the solder mask on the wire connection land 4a of the copper pattern is removed. The integrated circuit chip 2 is bonded onto the insulating substrate 3 by a die paste 9 made of a liquid epoxy resin dropped on the solder mask 8. Accordingly, all the rectangular patterns 6 and the bump connection lands 4b of the copper pattern are located below the integrated circuit chip 2. In the plan view shown in FIG. 4, a region on the insulating substrate 3 on which the integrated circuit chip 2 is mounted is indicated by a virtual line C.

  Next, a method for manufacturing the semiconductor device 1 will be described in accordance with the manufacturing process shown in FIG. First, a through hole 3a is formed in an insulating substrate 3 made of a polyimide film piece (step (A)). The through hole 3a can be formed using a punching process using a punching member or a photolithography technique. A copper foil 11 is laminated on the entire surface of the insulating substrate 3 in which the through holes 3a are formed (step (B)). A part of the copper foil 11 is etched using a photolithography technique to obtain a copper pattern 4 and a rectangular pattern 6 on the insulating substrate 3 (step (C)). A solder mask 8 is applied to the surface of the insulating substrate 3 on which the copper pattern 4 and the rectangular pattern 6 are formed, except for the outer peripheral portion where the wire connection land 4a of the copper pattern 4 is formed (step (D)). Thereafter, Ni or Au plating is applied to the exposed copper pattern 4 (wire connection land 4a).

  Next, a die paste 9 made of an epoxy resin is dropped onto the region of the insulating substrate 3 where the integrated circuit chip 2 is mounted by the dispenser 12 (step (E)). The supply of the die paste 9 needs to consider the amount and the dropping position so that the die paste spreads uniformly under the integrated circuit chip. Before the liquid die paste 9 is cured, the integrated circuit chip 2 manufactured in another process is pressed from above with a certain pressure, and the die paste 9 is spread over the entire lower surface of the integrated circuit chip 2 (step (F)). . At this time, the gap between the rectangular patterns 6, that is, the die paste in the divided area A shown in FIG. 5 does not move beyond the surrounding rectangular pattern 6, so that a cavity is formed in each divided area A. Is avoided. In this state, the ambient temperature is raised by a heater or the like, the die paste 9 is cured, and the integrated circuit chip 2 is fixed on the insulating substrate 3.

  After bonding the electrode pad 2a of the integrated circuit chip 2 and the wire connection land 4a of the copper pattern 4 with the conductor wire 5, the chip is sealed with the mold resin 13 (step (G)). Finally, the solder paste 14 is filled in the through hole 3a of the insulating substrate 3, the solder bumps 7 are transferred, and further melted to join the solder bumps 7 and the bump connection lands 4b (step (H)). The semiconductor device 1 is completed through the above steps.

  The embodiment of the present invention has been described with reference to the drawings. It is clear that the scope of application of the present invention is not limited to the matters shown in the above embodiment. In the present invention, it is important to have a pattern that divides the region under the chip into a plurality of portions in order to suppress the generation of cavities in the region under the integrated circuit chip completely or to a minimum. As long as the above-described object is achieved, the pattern can take various ideal shapes, and may be continuous or divided into a plurality of patterns. In the above embodiment, the solder mask 8 layer is provided on the insulating substrate 3. However, the present invention functions effectively even in a semiconductor device that does not include the solder mask 8 layer. Moreover, in the said embodiment, the semiconductor device provided with three rows of solder bumps as an external connection terminal was shown. However, the number and type of external connection terminals are not important in the present invention, and the present invention can be applied to a package having one or two rows of solder bumps or a PGA (Pin Grid Array) type package. .

It is a perspective view which fractures | ruptures and shows a part of semiconductor device of the CSP type package to which this invention is applied. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1. It is sectional drawing which expands and shows the principal part of FIG. It is a top view of the insulated substrate for showing arrangement | positioning of a rectangular pattern and a copper pattern. It is a conceptual diagram which shows the relationship between arrangement | positioning of a rectangular pattern, and the cavity which can be formed in a division area. It is a figure which shows the manufacturing process of a semiconductor device. It is sectional drawing which shows an example of the conventional CSP type | mold package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Integrated circuit chip 2a Electrode pad 3 Insulating substrate 3a Through hole 4 Copper pattern 4a Wire connection land 4b Bump connection land 5 Conductor wire 6 Rectangular pattern 7 Solder bump 8 Solder mask 9 Die paste 10 Adhesive layer 11 Copper foil 12 Dispenser 13 Mold resin 14 Solder paste A Divided area

Claims (12)

An insulating substrate;
An integrated circuit chip mounted on the insulating substrate via an adhesive layer;
A plurality of conductor pattern elements formed on the surface side of the insulating substrate on which the integrated circuit chip is mounted, wherein at least a part of the conductor pattern elements are located under the integrated circuit chip;
In the region of the insulating substrate which is surrounded by at least a portion of the conductive pattern elements under the integrated circuit chip, a plurality of pattern elements which are placed so as to divide the region into a plurality of small areas,
With
A semiconductor device in which the pattern element is not electrically connected to the external connection terminal and the conductor pattern element is electrically connected to the external connection terminal. The semiconductor device according to claim 1, wherein the divided small region has a circular region, and the plurality of circular regions are spaced apart by the plurality of pattern elements. The semiconductor device according to claim 1, wherein the pattern elements are arranged in a staggered pattern. The semiconductor device according to claim 1, wherein the pattern element is a rectangular pattern. The semiconductor device according to claim 1, wherein the integrated circuit chip is mounted on the insulating substrate with a circuit formation surface facing upward. The insulating substrate has a through hole under a part of each of the conductor pattern elements, and the conductor pattern from the surface opposite to the surface of the insulating substrate on which the integrated circuit chip is mounted via the through hole. 6. The semiconductor device according to claim 1, further comprising a solder bump for external connection joined to the element. A plurality of conductors that electrically connect the plurality of electrode pads of the integrated circuit chip and the plurality of conductor pattern elements, respectively, and a portion of the conductor pattern elements located under the integrated circuit chip are A first connection portion that is located in the integrated circuit chip mounting region of the insulating substrate and is electrically connected to the external connection terminal; and a conductor that is positioned outside the integrated circuit chip mounting region of the insulating substrate and connected to the conductor. 2. A back surface opposite to an element forming surface on which the plurality of electrode pads of the integrated circuit chip are formed is bonded to the insulating substrate by the adhesive layer. The semiconductor device described. 8. The semiconductor device according to claim 7, wherein a sealing resin for sealing the integrated circuit chip is formed on a surface of the insulating substrate on which the integrated circuit chip is mounted. The semiconductor device according to claim 8, wherein the external connection terminal is disposed on a surface of the insulating substrate opposite to a surface to which the integrated circuit chip is bonded. The semiconductor device according to claim 1, wherein the plurality of pattern elements are separate from the plurality of conductor pattern elements. The semiconductor device according to claim 1, wherein the plurality of pattern elements are arranged in a staggered relationship with adjacent columns . The semiconductor device according to claim 1, wherein the plurality of conductor pattern elements and the plurality of pattern elements are formed of the same material.