JP4485783B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for suppressing generation of a residue when removing a resist.

  As the semiconductor integrated circuit is miniaturized and highly integrated, the interval between the wirings is narrowed, so that the RC delay due to the increase in the resistance and capacitance of the wiring cannot be ignored. For this reason, it is necessary to reduce the electric parasitic capacitance generated between the wirings in order to miniaturize the semiconductor integrated circuit. In order to reduce the electric parasitic capacitance between the wirings, it is necessary to reduce the specific resistance of the wiring material or the relative dielectric constant of the interlayer insulating film.

  For 0.13 μm device wiring, in order to reduce the specific resistance of the wiring material, the Al wiring is changed to Cu wiring formed by using the damascene method, and in order to reduce the relative dielectric constant, silicon is used. Changes have been made from oxide films (relative permittivity: 4.2) to fluorine-containing silicon oxide films (relative permittivity: 3.7).

In addition, in the next generation 90 nm device and later, an insulating film (hereinafter referred to as a low-k film) having a relative dielectric constant smaller than that of the fluorine-containing silicon oxide film is required, and the carbon-containing silicon oxide is used as the low-k film. Film (film in which the dielectric constant is reduced by replacing the terminal of silicon in the silicon oxide film with an alkyl group (for example, —CH ₃ group) and reducing the density and porosity of the silicon oxide film) and coating Organic polymers are being studied.

  As is well known, in such a method for manufacturing a semiconductor integrated circuit device, a lithography technique is used when forming a circuit pattern. The resist, which is an important member in the process using the lithography technology, is first formed by patterning by exposure and development, and then used as an etching mask when etching the insulating film that is the base of the resist, and is removed after the etching. The

  Here, as a method of removing the resist, for example, as described in Patent Document 1, a method of removing the resist by ashing using plasma made of oxygen gas or plasma mainly containing oxygen gas is generally used. (For example, refer to Patent Document 1).

  In the process using the lithography technique, if the deviation of the resist pattern is outside the design allowable range, a resist regeneration process may be performed in which the resist pattern is formed again after removing the resist pattern. In the method of removing the resist in such a resist regeneration step, as described above, after performing ashing using plasma made of oxygen gas or the like, polymer cleaning or water cleaning is performed as necessary.

  Hereinafter, a method for manufacturing a semiconductor device according to a conventional resist recycling method will be described with reference to FIGS.

  5A to 5E are process cross-sectional views showing a series of processes from formation of a wiring pattern using a damascene method used in a 0.13 μm device to resist regeneration.

  First, as shown in FIG. 5A, a first interlayer insulating film 101 made of, for example, a silicon oxide film is deposited on the silicon substrate 100. Next, a second interlayer insulating film 102 made of, for example, a fluorine-containing silicon oxide film is deposited on the first interlayer insulating film 101.

  Next, as shown in FIG. 5B, after applying an antireflection film 103 on the second interlayer insulating film 102, a resist 104 necessary for forming a wiring pattern is applied. An oxynitride oxide film deposited by a CVD method may be used as the antireflection film. However, since the oxynitride oxide film has poor adhesion to the resist, it is necessary to perform an adhesion treatment between the oxynitride oxide film and the resist. is there.

  Next, as shown in FIG. 5C, a wiring pattern 105 is formed by lithography (exposure and development).

  Next, as shown in FIG. 5D, if the deviation of the wiring pattern 105 is outside the design allowable range, the wiring pattern 105 made of the antireflection film 103 and the resist 104 is performed by ashing using plasma made of oxygen gas. And remove. In this ashing, an RF bias is used to increase the ashing rate.

  Next, as shown in FIG. 5 (e), polymer washing or water washing is performed as necessary to obtain a state before the wiring pattern 105 is formed (FIG. 5 (e) or FIG. 5 (a)). Then, the wiring pattern 105 is formed again by performing the steps shown in FIGS. 5A to 5C again.

  In this way, resist regeneration is performed in a 0.13 μm device.

  However, in a 90 nm device using a low-k film as an interlayer insulating film, unlike the 0.13 μm device, plasma ashing using an RF bias cannot be performed. This is because the effective dielectric constant of the low-k film increases when plasma ashing using an RF bias is performed in a 90 nm device using the low-k film. For this reason, in a 90 nm device using a low-k film as an interlayer insulating film, it is common to perform reactive ion etching (RIE) without using an RF bias.

  A conventional method for manufacturing a semiconductor device used for a 90 nm device using a low-k film as an interlayer insulating film will be described below with reference to FIGS. 6 (a) to 6 (e).

  First, as shown in FIG. 6A, a first interlayer insulating film 201 made of, for example, a silicon oxide film is deposited on a silicon substrate 200. Next, a second interlayer insulating film 202 made of, for example, a carbon-containing silicon oxide film is deposited on the first interlayer insulating film 201.

  Next, as shown in FIG. 6B, after applying an antireflection film 203 on the second interlayer insulating film 202, a resist 204 necessary for forming a wiring pattern is applied.

  Next, as shown in FIG. 6C, a wiring pattern 205 is formed by lithography (exposure and development).

Next, as shown in FIG. 6 (d), if the misalignment of the formed wiring pattern 205 is outside the design tolerance, in order to remove the antireflection film 203 and the wiring pattern 205 made of the resist 204, After ashing using plasma made of oxygen gas, if necessary, the steps from polymer washing or water washing to forming the wiring pattern 205 again are repeated.
JP 2003-059977 A

  As described above, in the conventional method for manufacturing a semiconductor device used for a 90 nm device using a low-k film as an interlayer insulating film, when the wiring pattern 205 is removed, plasma ashing is performed, as shown in FIG. The polymer such as an oxynitride film constituting the antireflection film 203 removed on the wiring pattern 205 adheres to the side wall of the wiring pattern 205, and the reaction between the polymer attached to the side wall of the wiring pattern 205 and the resist constituting the wiring pattern 205 occurs. An object 206 (fence) is formed.

  That is, in plasma ashing, overashing is usually performed due to the steps of the wiring pattern 205, and at that time, the polymer removed by the overashing adheres to the sidewall of the wiring pattern 205. A part of the polymer adhering to the side wall of the wiring pattern 205 is removed together with the wiring pattern 205 at the time of overashing, but overashing is performed on the low-k film constituting the second interlayer insulating film 202. Since the process is performed within a range not damaging, the polymer adheres to the side wall of the wiring pattern 205. As shown in FIG. 6E, it is difficult to completely remove the reaction product 206 generated due to this, even after the plasma ashing is completed, and the reaction product 206 becomes a residue. .

  Reactive organisms 206 that form a residue form a fence, and film peeling occurs at the interface with the film deposited thereon due to the fence.

  In view of the above, a first object of the present invention is to provide a method for manufacturing a semiconductor device that realizes high yield and high reliability by removing a resist without generating a residue.

  A second object of the present invention is to use a resist without generating a residue while suppressing an increase in the dielectric constant of the low dielectric constant film when a low dielectric constant film such as a low-k film is used as an interlayer insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device that realizes a high yield and high reliability by removing the above.

  In order to solve the above-described problems, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming a resist pattern on a low dielectric constant film formed on a substrate, and a resist solvent. And a step of removing the resist pattern.

  According to the first method for manufacturing a semiconductor device of the present invention, since the resist pattern is removed using the resist solvent, generation of residues can be prevented. That is, as in the conventional example, when the resist pattern is removed by ashing, a part of the film serving as the base of the resist pattern is removed by ashing and adheres to the side wall of the resist pattern to form a residue. In the first method for manufacturing a semiconductor device according to the present invention, since the resist pattern is removed using a resist solvent, the underlying film is not removed when the resist pattern is removed, and the underlying resist pattern is formed. Since there is no resist pattern itself that is a target to which the film is later removed and adhered, generation of residues can be prevented. Therefore, since the resist pattern can be removed without generating a residue, it is possible to prevent film peeling caused by the residue forming a fence or the like, and thus manufacturing a semiconductor device that achieves high yield and high reliability. A method can be provided. Also, since the resist pattern is removed using a resist solvent without ashing, the time for ashing can be shortened, so that damage to the low dielectric constant film formed under the resist pattern can be reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  In the first method for manufacturing a semiconductor device according to the present invention, before the step of forming the resist pattern, after the step of forming the antireflection film on the low dielectric constant film and the step of removing the resist pattern, A step of removing the antireflection film by ashing, and the step of forming the resist pattern is preferably a step of forming a resist pattern on the antireflection film.

  In this way, when removing the antireflection film underlying the resist pattern by ashing, the resist pattern itself, to which a part of the antireflection film removed by ashing adheres, is removed, and thus generation of residue Can be prevented. Therefore, since the resist pattern can be removed without generating a residue, it is possible to prevent film peeling caused by the residue forming a fence or the like, and thus manufacturing a semiconductor device that achieves high yield and high reliability. A method can be provided.

In the first method for fabricating a semiconductor device according to the present invention, ashing is performed using O ₂ , H ₂ , H ₂ O. N ₂ or He gas, or O ₂ , H ₂ , H ₂ O It is preferable to use a mixed gas formed by combining two or more kinds of gases composed of N ₂ or He.

  In the first method for fabricating a semiconductor device according to the present invention, the low dielectric constant film is preferably a silicon oxide film containing carbon.

  In the first method for manufacturing a semiconductor device according to the present invention, the resist solvent preferably contains a quaternary ammonium salt.

  If it does in this way, removal of a resist pattern can be removed effectively.

  A second method for manufacturing a semiconductor device according to the present invention includes a step of forming a low dielectric constant film on a substrate, a step of forming a first resist pattern on the low dielectric constant film, and a low dielectric constant film. On the other hand, etching is performed using the first resist pattern as a mask to form a lower layer wiring groove in the first low dielectric constant film, and after forming the lower layer wiring groove, the first solvent pattern is used using a resist solvent. The method includes a step of removing the resist pattern, and a step of forming a lower layer wiring by embedding the first conductive film in the lower layer wiring trench.

  According to the second method for manufacturing a semiconductor device of the present invention, the side walls of the first resist pattern generated during the etching together with the first resist pattern used in forming the lower layer wiring trench by the resist solvent. Since deposits can be removed, generation of residues can be prevented. Further, even when a low dielectric constant film or the like serving as a base of the first resist pattern is removed later, the first resist pattern itself to be attached does not exist, and thus the generation of a residue is prevented. Can do. Therefore, since the first resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like. Therefore, a semiconductor that realizes high yield and high reliability. An apparatus manufacturing method can be provided. In addition, since the removal of the first resist pattern is performed using a resist solvent without ashing, the time for ashing can be shortened. Therefore, damage to the low dielectric constant film formed under the first resist pattern is reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  In the second method of manufacturing a semiconductor device according to the present invention, before the step of forming the first resist pattern, a step of forming a first antireflection film on the low dielectric constant film, and a first resist And a step of removing the first antireflection film by ashing after the step of removing the pattern, and the step of forming the first resist pattern includes the step of forming the first resist pattern on the first antireflection film. It is preferable that it is a process of forming.

  In this case, when the first antireflection film serving as the base of the first resist pattern is removed by ashing, the first resist to which a part of the first antireflection film removed by ashing adheres. Since the pattern itself is removed, generation of residues can be prevented. Therefore, since the first resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like. Therefore, a semiconductor that realizes high yield and high reliability. An apparatus manufacturing method can be provided.

  In the second method for manufacturing a semiconductor device according to the present invention, a step of forming an interlayer insulating film on the lower wiring and the low dielectric constant film, and a step of forming a second resist pattern on the interlayer insulating film Etching the interlayer insulating film using the second resist pattern as a mask to form a wiring connection hole in the interlayer insulating film; and after forming the wiring connection hole, a second step is performed using a resist solvent. Preferably, the method further comprises a step of removing the resist pattern and a step of forming at least a wiring plug by embedding the second conductive film in the wiring connection hole.

  In this way, the resist solvent can remove the deposit on the side wall of the second resist pattern generated during the etching together with the second resist pattern used in forming the wiring connection hole, so that a residue is generated. Can be prevented. In addition, even when the low dielectric constant film or the like serving as the base of the second resist pattern is removed later, the second resist pattern itself to be attached does not exist, so that generation of a residue is prevented. Can do. Therefore, since the second resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like, and thus a semiconductor that achieves high yield and high reliability. An apparatus manufacturing method can be provided. Further, since the removal of the second resist pattern is performed using a resist solvent without performing ashing, the time for ashing can be shortened, so that damage to the low dielectric constant film formed under the second resist pattern is reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  In the second method of manufacturing a semiconductor device according to the present invention, before the step of forming the second resist pattern, a step of forming a second antireflection film on the interlayer insulating film, and a second resist pattern And a step of removing the second antireflection film by ashing after the step of removing the second antireflection film, and the step of forming the second resist pattern includes forming the second resist pattern on the second antireflection film. It is preferable that it is the process of forming.

  In this case, when the second antireflection film serving as the base of the second resist pattern is removed by ashing, the second resist to which a part of the second antireflection film removed by ashing adheres. Since the pattern itself is removed, generation of residues can be prevented. Therefore, since the second resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like, and thus a semiconductor that achieves high yield and high reliability. An apparatus manufacturing method can be provided.

  A third method for manufacturing a semiconductor device according to the present invention includes a step of forming a low dielectric constant film on a lower layer wiring formed on a substrate, and a first resist pattern on the low dielectric constant film. Forming a wiring connection hole in the low dielectric constant film by performing etching on the low dielectric constant film using the first resist pattern as a mask; And a step of removing the first resist pattern.

  According to the third method for manufacturing a semiconductor device of the present invention, the resist solvent causes the first resist pattern used in forming the wiring connection hole to be a connection hole to the lower layer wiring and the first resist pattern used in the etching. Since the deposits on the side walls of the first resist pattern can be removed, generation of residues can be prevented. Further, even when a low dielectric constant film or the like serving as a base of the first resist pattern is removed later, the first resist pattern itself to be attached does not exist, and thus the generation of a residue is prevented. Can do. Accordingly, since the first resist pattern can be removed without generating a residue, it is possible to prevent the film from peeling off due to the residue forming a fence or the like, and thus a semiconductor device that realizes a high yield and high reliability. The manufacturing method of can be provided. In addition, since the removal of the first resist pattern is performed using a resist solvent without ashing, the time for ashing can be shortened. Therefore, damage to the low dielectric constant film formed under the first resist pattern is reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  In the third method for manufacturing a semiconductor device according to the present invention, before the step of forming the first resist pattern, a step of forming a first antireflection film on the low dielectric constant film, and a first resist And a step of removing the first antireflection film by ashing after the step of removing the pattern, and the step of forming the first resist pattern includes the step of forming the first resist pattern on the first antireflection film. It is preferable that it is a process of forming.

  In this case, when the first antireflection film serving as the base of the first resist pattern is removed by ashing, the first resist to which a part of the first antireflection film removed by ashing adheres. Since the pattern itself is removed, generation of residues can be prevented. Therefore, since the first resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like. Therefore, a semiconductor that realizes high yield and high reliability. An apparatus manufacturing method can be provided.

  In the third method for manufacturing a semiconductor device according to the present invention, after removing the first resist pattern, a step of forming a second resist pattern on the low dielectric constant film, and for the low dielectric constant film, Etching the second resist pattern as a mask to form an upper wiring groove in the low dielectric constant film; forming the upper wiring groove and then removing the second resist pattern using a resist solvent; It is preferable to further include a step of forming a wiring plug and an upper layer wiring by embedding a conductive film in the wiring connection hole and the upper layer wiring groove.

  In this case, the resist solvent can remove the deposit on the side wall of the second resist pattern generated during the etching together with the second resist pattern used in forming the upper wiring groove, and thus generation of a residue. Can be prevented. In addition, even when the low dielectric constant film or the like serving as the base of the second resist pattern is removed later, the second resist pattern itself to be attached does not exist, so that generation of a residue is prevented. Can do. Therefore, since the second resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like, and thus a semiconductor that achieves high yield and high reliability. An apparatus manufacturing method can be provided. Further, since the removal of the second resist pattern is performed using a resist solvent without performing ashing, the time for ashing can be shortened, so that damage to the low dielectric constant film formed under the second resist pattern is reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  In the third method of manufacturing a semiconductor device according to the present invention, before the step of forming the second resist pattern, a step of forming a second antireflection film on the low dielectric constant film, and a second resist And a step of removing the second antireflection film by ashing after the step of removing the pattern, and the step of forming the second resist pattern includes the second resist pattern on the second antireflection film. It is preferable that it is a process of forming.

  In this case, when the second antireflection film serving as the base of the second resist pattern is removed by ashing, the second resist to which a part of the second antireflection film removed by ashing adheres. Since the pattern itself is removed, generation of residues can be prevented. Therefore, since the second resist pattern can be removed without generating a residue, the film can be prevented from peeling off when the residue forms a fence or the like, and thus a semiconductor that achieves high yield and high reliability. An apparatus manufacturing method can be provided.

  In the third method of manufacturing a semiconductor device according to the present invention, the step of forming the first resist pattern includes the step of regenerating the first resist pattern after removing the first resist pattern using a resist solvent. It is preferable to include.

  In this way, even when the first resist pattern is regenerated, it is possible to prevent generation of residues and reduce damage to the low dielectric constant film.

  In the third method for manufacturing a semiconductor device according to the present invention, the step of forming the second resist pattern includes the step of regenerating the second resist pattern after removing the second resist pattern using a resist solvent. It is preferable to include.

  In this way, even when the second resist pattern is reproduced, it is possible to prevent generation of residues and reduce damage to the low dielectric constant film.

  In the first to third methods for manufacturing a semiconductor device according to the present invention, the low dielectric constant film is preferably a silicon oxide film containing carbon.

  In the first to third semiconductor device manufacturing methods according to the present invention, the resist solvent preferably contains a quaternary ammonium salt.

  In this way, the resist pattern can be effectively removed.

In the first to third methods of manufacturing a semiconductor device according to the present invention, the ashing is performed using a gas composed of O ₂ , H ₂ , H ₂ O, N ₂ or He, or O ₂ , H ₂ , H ₂ O, It is preferable to carry out using a mixed gas formed by combining two or more kinds of gases of N ₂ or He.

  According to the method for manufacturing a semiconductor device according to the present invention, since the resist pattern is removed using the resist solvent, generation of a residue can be prevented. That is, as in the conventional example, when the resist pattern is removed by ashing, a part of the film serving as the base of the resist pattern is removed by ashing and adheres to the side wall of the resist pattern to form a residue. In the method for manufacturing a semiconductor device according to the present invention, since the resist pattern is removed using a resist solvent, the base film is not removed when the resist pattern is removed, and the base film of the resist pattern is not removed later. Since there is no resist pattern itself to be removed and attached, generation of residues can be prevented. Therefore, since the resist pattern can be removed without generating a residue, it is possible to prevent film peeling caused by the residue forming a fence or the like, and thus manufacturing a semiconductor device that achieves high yield and high reliability. A method can be provided. Also, since the resist pattern is removed using a resist solvent without ashing, the time for ashing can be shortened, so that damage to the low dielectric constant film formed under the resist pattern can be reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS.

  1A to 1E are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, the present invention is applied to a method for regenerating a resist film. It is a figure for demonstrating a case.

  First, as shown in FIG. 1A, a first interlayer insulating film 11 made of, for example, a silicon oxide film is deposited on a silicon substrate 10. Next, on the first interlayer insulating film 11, a low dielectric constant film having a thickness of, for example, 500 nm and a weak atomic bond made of a silicon oxide film containing carbon (hereinafter referred to as a carbon-containing silicon oxide film). 12 (low-k film) is deposited. Next, a second interlayer insulating film 13 made of a silicon oxide film having a thickness of 50 nm, for example, is deposited on the low dielectric constant film 12. The second interlayer insulating film 13 has a role of suppressing deterioration of the film quality of the low dielectric constant film 12 by plasma ashing described later.

  Next, as shown in FIG. 1B, after the antireflection film 14 is applied on the second interlayer insulating film 13 so as to have a film thickness of 80 nm, the film thickness is set to 350 nm. A resist film 15 necessary for forming the resist pattern is applied.

  Next, as shown in FIG. 1C, the resist film 15 is subjected to lithography (exposure and development) to form a resist pattern 16 made of the resist film 15.

  If the misalignment of the resist pattern 16 is outside the design allowable range, the antireflection film 14 and the resist pattern 16 must be formed again after removing the antireflection film 14 and the resist pattern 16. In the following description, it is assumed that the resist pattern 14 is formed again.

  Next, as shown in FIG. 1D, when the resist pattern 16 is formed again, the resist pattern 16 shown in FIG. 1C is first removed using a resist solvent such as thinner. . Here, the type of the resist solvent may be a commonly used solvent, but a resist solvent containing a quaternary ammonium salt is preferably used. Further, for example, when the resist film 15 constituting the resist pattern 16 is made of ArF resist (acrylic resin), it is preferable to use a glycol ether solvent, and the resist film 15 constituting the resist pattern 16 is KrF. In the case of a resist (phenolic resin), it is preferable to use an amide solvent. Thereby, the resist pattern 16 can be effectively removed.

Next, as shown in FIG. 1E, the antireflection film 14 is removed by performing plasma ashing using, for example, plasma made of oxygen gas. Here, in the plasma ashing, reactive plasma ashing without using an RF bias is performed in order to suppress an increase in the dielectric constant of the low dielectric constant film 12. Further, as the gas constituting the plasma, in addition to the O ₂ gas, for example, H ₂ , H ₂ O N ₂ or He may be used, for example, N ₂ / H ₂ , H ₂ / He, NH ₃ , CF ₄ / O ₂ , SF ₆ / O ₂ , or O ₂ / H ₂ O. O ₂ , H ₂ , H ₂ O, etc. Alternatively, a mixed gas obtained by combining two or more kinds of gases composed of N ₂ or He may be used.

  Next, after returning to the state shown in FIG. 1A by performing polymer washing or water washing as necessary, a resist film 15 is applied and a resist pattern 16 is formed again as described above.

  As described above, according to the method for manufacturing a semiconductor device according to the first embodiment, first, the resist pattern 16 is removed using a resist solvent, so that generation of a residue can be prevented. That is, as in the conventional example, when the resist pattern 16 is removed by plasma ashing, as described in the conventional example, a part of the antireflection film 14 serving as a base of the resist pattern is removed by ashing, and the resist pattern 16 is removed. Although the resist pattern 16 is removed using a resist solvent in the semiconductor device according to the first embodiment, the antireflective film serving as a base when the resist pattern 16 is removed. Further, when the antireflection film 14 is removed by ashing, the resist pattern 16 is completely removed. Therefore, the antireflection film removed by ashing on the side wall of the resist pattern 16 is not removed. 14 etc. do not adhere. In this manner, since the resist can be removed without generating a residue, film peeling caused by the residue forming a fence or the like can be prevented, so that a semiconductor device that achieves high yield and high reliability can be obtained. A manufacturing method can be provided.

  Further, according to the semiconductor device manufacturing method of the first embodiment, the resist pattern 16 is removed using a resist solvent without performing plasma ashing, and plasma ashing is performed only when removing the antireflection film 14. Therefore, since the time for performing plasma ashing can be shortened, damage to the low dielectric constant film formed below the antireflection film 14 such as deterioration of the film quality and increase of the dielectric constant can be reduced. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS.

  2A to 2F are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. Specifically, the present invention removes a resist pattern after etching processing. It is a figure for demonstrating the case where it applies to the method to do.

  First, as shown in FIG. 2A, a first interlayer insulating film 21 made of, for example, a silicon oxide film is deposited on the silicon substrate 20. Next, a low dielectric constant film 22 (low-k film) having a weak atomic bond made of a carbon-containing silicon oxide film having a thickness of, for example, 500 nm is deposited on the first interlayer insulating film 21. Next, a second interlayer insulating film 23 made of a silicon oxide film having a thickness of 50 nm, for example, is deposited on the low dielectric constant film 22. The second interlayer insulating film 23 has a role of suppressing deterioration of the film quality of the low dielectric constant film 22 by plasma ashing described later.

  Next, as shown in FIG. 2B, after the antireflection film 24 is applied on the second interlayer insulating film 23 so that the film thickness becomes 80 nm, the film thickness becomes 350 nm, for example. A resist film 25 necessary for forming a predetermined resist pattern is applied.

  Next, as shown in FIG. 2C, a resist pattern 26 made of the resist film 25 is formed by performing lithography (exposure and development) on the resist film 25. If the misalignment of the resist pattern 26 is outside the design allowable range, the antireflection film 24 and the resist pattern 26 are removed after removing the antireflection film 24 and the resist pattern 26 as in the first embodiment. It is possible to form again.

  Next, as shown in FIG. 2D, the antireflection film 24, the second interlayer insulating film 23, and the low dielectric constant film 22 are etched using the resist pattern 26 as a mask, for example, a wiring trench. Form. In this etching, the polymer or the like removed by the etching adheres to the side wall of the resist pattern 26, thereby forming a reaction product 27 between the resist film 25 constituting the resist pattern 26 and the deposit such as a polymer. The

  Next, the resist pattern 26 and the antireflection film 24 used for the etching mask are removed. First, as shown in FIG. 2E, the resist pattern 26 shown in FIG. 2D is removed using a resist solvent such as thinner. Further, as the resist solvent, a liquid having high resist releasability may be used. This is because, unlike the removal of the resist pattern 16 in the first embodiment, the reaction product 27 is formed on the side wall of the resist pattern 26 as described above. Here, the type of resist solvent may be a commonly used solvent, but is preferably a resist solvent containing a quaternary ammonium salt. For example, when the resist film 25 constituting the resist pattern 26 is made of ArF resist (acrylic resin), it is preferable to use a glycol ether solvent, and the resist film 25 constituting the resist pattern 26 is KrF. In the case of a resist (phenolic resin), it is preferable to use an amide solvent. Thereby, the resist pattern 26 can be effectively removed.

Next, with respect to the antireflection film 24, as shown in FIG. 2 (f), for example, the antireflection film 24 is removed by performing plasma ashing using plasma of oxygen gas. Here, in the plasma ashing, reactive plasma ashing without using an RF bias is performed in order to suppress an increase in the dielectric constant of the low dielectric constant film 22. Further, as the gas constituting the plasma, in addition to the O ₂ gas, for example, H ₂ , H ₂ O N ₂ or He may be used, for example, N ₂ / H ₂ , H ₂ / He, NH ₃ , CF ₄ / O ₂ , SF ₆ / O ₂ , or O ₂ / H ₂ O. O ₂ , H ₂ , H ₂ O, etc. Alternatively, a mixed gas in which two or more kinds of gases composed of N ₂ or He are combined may be used.

  Next, after returning to the state shown in FIG. 2A by performing polymer washing or water washing as necessary, a resist film 25 is applied and a resist pattern 26 is formed again as described above.

  As described above, according to the method for manufacturing a semiconductor device according to the second embodiment, when removing the resist pattern 26 used for etching, the resist pattern 26 is removed using a resist solvent, and thus generation of a residue is prevented. Can be prevented. That is, when the resist pattern is removed by plasma ashing as in the conventional example, as described in the conventional example, a part of the antireflection film that becomes the base of the resist pattern is removed by ashing to the side wall of the resist pattern. In the semiconductor device according to the second embodiment, the resist pattern 26 is removed using a resist solvent, so that the resist pattern 26 can be removed together with the reaction product 27 attached to the side wall. At the same time, when the antireflection film 24 is removed by ashing, the resist pattern 26 is completely removed, so that the antireflection film 24 removed by ashing does not adhere to the sidewall of the resist pattern 26. As described above, since the resist pattern 26 can be removed without generating a residue, it is possible to prevent the film from being peeled off when the residue forms a fence or the like. Therefore, a semiconductor that realizes high yield and high reliability. An apparatus manufacturing method can be provided.

  Further, according to the semiconductor device manufacturing method of the second embodiment, the resist pattern 26 is removed using a resist solvent without performing plasma ashing, and plasma ashing is performed only when removing the antireflection film 14. Therefore, since the time for performing plasma ashing can be shortened, damage such as deterioration in film quality and increase in dielectric constant can be reduced with respect to the low dielectric constant film formed below the antireflection film 14. It is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

(Third embodiment)
Hereinafter, a method for fabricating a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS.

  3A to 3H are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Specifically, a copper wiring is formed using a single damascene method. It is a figure for demonstrating the case where this invention is applied.

  First, as shown in FIG. 3A, a low dielectric constant film 31 (low-k film) having a weak atomic bond such as a carbon-containing silicon oxide film is deposited on the silicon substrate 30. Next, a damage preventing film 32 made of a silicon oxide film having a thickness of, for example, 50 nm is deposited on the low dielectric constant film 31 for the purpose of suppressing deterioration of the film quality of the low dielectric constant 31.

  Next, as shown in FIG. 3B, an antireflection film 33 is applied on the damage prevention film 32. Next, after applying a resist film necessary for forming a wiring groove pattern, the resist film is subjected to lithography (exposure and development) to form a resist pattern 34 (a first resist pattern) that becomes a wiring groove pattern. Correspondingly the same shall apply hereinafter).

  Here, if the misalignment of the resist pattern 34 is outside the design allowable range, the antireflection film 33 and the resist pattern 34 must be formed again after removing the antireflection film 33 and the resist pattern 34.

  Therefore, when forming the resist pattern 34 again, although not shown, first, the resist pattern 34 shown in FIG. 3B is removed using a resist solvent such as thinner. Here, the type of resist solvent may be a commonly used solvent, but is preferably a resist solvent containing a quaternary ammonium salt. For example, when the resist film constituting the resist pattern 34 is made of ArF resist (acrylic resin), it is preferable to use a glycol ether solvent, and the resist film constituting the resist pattern 34 is a KrF resist ( In the case of a phenol resin, it is preferable to use an amide solvent. Thereby, the resist pattern 34 can be effectively removed.

Next, for example, plasma ashing using plasma made of oxygen gas is performed to remove the antireflection film 33. Here, in the plasma ashing, reactive plasma ashing without using an RF bias is performed in order to suppress an increase in the dielectric constant of the low dielectric constant film 31. Further, as the gas constituting the plasma, in addition to the O ₂ gas, for example, H ₂ , H ₂ O N ₂ or He may be used, for example, N ₂ / H ₂ , H ₂ / He, NH ₃ , CF ₄ / O ₂ , SF ₆ / O ₂ , or O ₂ / H ₂ O. O ₂ , H ₂ , H ₂ O, etc. Alternatively, a mixed gas in which two or more kinds of gases composed of N ₂ or He are combined may be used.

  Then, after returning to the state shown in FIG. 3A by performing polymer washing or water washing as necessary, a resist film is applied and the resist pattern 34 is formed again, as described above. The state shown in FIG.

  Next, as shown in FIG. 3C, the antireflection film 33, the damage prevention film 32, and the low dielectric constant film 31 are subjected to dry etching using the resist pattern 34 as a mask, thereby forming the lower wiring trench 35. Form. In this case, although not shown, a reaction product of the resist film and the polymer removed by etching adheres to the side wall of the resist pattern 34.

  Next, the resist pattern 34, the antireflection film 33, and the damage prevention film 32 are removed. At this time, similarly to the case where the misalignment of the resist pattern 34 is outside the design allowable range, the resist pattern 34 is removed together with the reaction product adhering to the sidewall using a resist solvent, and the antireflection film 33 and The damage prevention film 32 can be removed.

  Next, as shown in FIG. 3 (d), a barrier metal film made of, for example, a Ta / TaN laminated film and a copper film are formed on the low dielectric constant film 31 so as to bury the lower wiring groove 35 partway by sputtering. A seed film is deposited in order from the bottom (not shown). Next, a copper film is formed on the seed film so that the lower wiring groove 35 is completely filled by electrolytic plating, and then protrudes from the lower wiring groove 35 on the low dielectric constant film 31 by CMP. The lower layer wiring 36 is formed by removing the copper film and flattening the surface of the low dielectric constant film 31.

  Next, as shown in FIG. 3E, an interlayer insulating film 37 made of, for example, a silicon oxide film is formed on the low dielectric constant film 31 and the lower layer wiring 36. The interlayer insulating film 37 preferably has a role of preventing deterioration of the film quality of the low dielectric constant film 31 and a role of preventing copper diffusion.

  Next, an antireflection film 38 is applied on the interlayer insulating film 37. Thereafter, after applying a resist film necessary for forming a connection hole pattern on the antireflection film 38, the resist film 39 is subjected to lithography (exposure and development) to form a resist pattern 39 (a connection hole pattern). Corresponding to the second resist pattern, the same shall apply hereinafter). If the misalignment of the resist pattern 39 is outside the design tolerance, the resist pattern 39 is removed using a resist solvent and plasma ashing is performed in the same manner as in the case where the resist pattern 34 is outside the design tolerance. Thus, the antireflection film 38 can be removed. Thereafter, the steps until the resist pattern 39 is formed again are repeated.

  Next, as shown in FIG. 3F, plasma dry etching is performed on the antireflection film 38 and the interlayer insulating film 37 using the resist pattern 39 as a mask to expose the surface of the lower layer wiring 36. Form. In this case, although not shown, a reaction product of the resist film and the polymer removed by etching adheres to the side wall of the resist pattern 39.

  Next, as shown in FIG. 3G, the antireflection film 38 and the resist pattern 39 are removed. In this case as well, the resist pattern 39 is removed together with the reaction product adhering to the side wall using a resist solvent in the same manner as described above, and the antireflection film 38 is removed by plasma ashing.

  Next, as shown in FIG. 3 (h), a conductive film 41 having a structure similar to that of the lower layer wiring 36 is embedded in the wiring connection hole 40, whereby the lower layer wiring 36 and the interlayer insulating film 37 are formed. A wiring plug and an upper layer wiring are formed.

  As described above, according to the method of manufacturing a semiconductor device according to the third embodiment, when the resist pattern (34, 39) is regenerated in the method of forming a copper wiring using the single damascene method, first, the resist Since the resist pattern (34, 39) is removed using a solvent, generation of a residue can be prevented. That is, when the resist pattern is removed by plasma ashing as in the conventional example, as described in the conventional example, a part of the antireflection film that becomes the base of the resist pattern is removed by ashing, and the sidewall of the resist pattern is removed. In the semiconductor device according to the third embodiment, since the resist pattern (34, 39) is removed using a resist solvent, the base pattern is removed when the resist pattern (34, 39) is removed. When the antireflection film (33, 38) is removed by ashing, the resist pattern (34, 39) is completely removed. Therefore, the antireflection film (33, 38) removed by ashing does not adhere to the side walls of the resist pattern (34, 39). As described above, since the resist pattern (34, 39) can be removed without generating a residue, the residue can prevent film peeling caused by forming a fence or the like. Therefore, high yield and high reliability can be prevented. The manufacturing method of the semiconductor device which implement | achieves can be provided.

  Further, when removing the resist pattern (34, 39) used for etching, first, the resist pattern (34, 39) is removed using a resist solvent, so that generation of a residue can be prevented. That is, since the resist pattern (34, 39) is removed using a resist solvent, the resist pattern (34, 39) can be removed together with the reaction product attached to the side wall. Further, when the antireflection film (33, 38) is removed by ashing, since the resist pattern (34, 39) is completely removed, the antireflection film removed on the side wall of the resist pattern (34, 39). The film 24 does not adhere. As described above, since the resist pattern can be removed without generating a residue, it is possible to prevent the film from peeling off due to the residue forming a fence or the like. Therefore, a semiconductor device that realizes high yield and high reliability. The manufacturing method of can be provided.

  Furthermore, according to the semiconductor device manufacturing method of the third embodiment, the resist pattern (34, 39) is removed using a resist solvent without performing plasma ashing, and the antireflection film (33, 38) is removed. Since the plasma ashing is performed only at the time of the plasma, the time for performing the plasma ashing can be shortened. Therefore, the deterioration of the film quality and the dielectric constant of the low dielectric constant film formed below the antireflection film (33, 38) are achieved. Therefore, it is possible to provide a method for manufacturing a semiconductor device that achieves high yield and high reliability.

(Fourth embodiment)
A method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described below with reference to FIGS.

  4A to 4H are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. Specifically, copper wiring is formed using a dual damascene method. It is a figure for demonstrating the case where this invention is applied.

  First, as shown in FIG. 4A, a first interlayer insulating film 51 made of, for example, a silicon oxide film is deposited on the silicon substrate 50. Next, after applying an antireflection film (not shown) on the first interlayer insulating film 51, a resist film (not shown) necessary for forming a wiring groove pattern is applied, and the resist film is applied to the resist film. On the other hand, lithography (exposure and development) is performed to form a resist pattern to be a wiring groove pattern. Next, dry etching is performed on the antireflection film and the first interlayer insulating film 51 using the resist pattern as a mask to form a lower layer wiring groove. Thereafter, the resist pattern and the antireflection film are removed. Here, a low dielectric constant film (low-k film) can also be used as the first interlayer insulating film 51. However, in this case, the resist pattern is out of the design allowable range, so that the resist pattern is removed. In the case where the resist pattern is removed after etching, the resist pattern may be removed using a resist solvent and the antireflection film may be removed by plasma ashing as in the third embodiment.

  Next, a barrier metal film made of, for example, a Ta / TaN laminated film and a copper seed film are sequentially deposited from the bottom on the first interlayer insulating film 51 so as to bury the lower layer wiring groove partway by sputtering. Then, a copper film is formed on the seed film by electrolytic plating so that the lower wiring groove is completely filled. Thereafter, the lower wiring 52 is formed by planarizing the surface of the first interlayer insulating film 51 by removing the copper film protruding from the lower wiring groove on the first interlayer insulating film 51 by CMP. To do.

  Next, as shown in FIG. 4B, for example, a silicon carbide film having a thickness of 50 nm is formed on the lower wiring 52 and the first interlayer insulating film 51 for the purpose of preventing copper diffusion. An insulating barrier film 53 is deposited. Next, a low dielectric constant film (low-k film) 54 having a weak atomic bond, such as a carbon-containing silicon oxide film having a thickness of 600 nm, for example, is deposited on the insulating barrier film 53. Next, a damage prevention film 55 made of a silicon oxide film having a thickness of 50 nm, for example, is deposited on the low dielectric constant film 54 for the purpose of suppressing deterioration of the film quality of the low dielectric constant film 54.

  Next, as shown in FIG. 4C, an antireflection film 56 is applied on the damage prevention film 55. Next, after applying a resist film necessary for forming a connection hole pattern, the resist film is subjected to lithography (exposure and development) to form a resist pattern 57 (a first resist pattern) that becomes a connection hole pattern. Correspondingly the same shall apply hereinafter).

  If the misalignment of the resist pattern 57 is outside the design allowable range, the antireflection film 56 and the resist pattern 57 must be formed again after the antireflection film 56 and the resist pattern 57 are removed.

  Therefore, when forming the resist pattern 57 again, although not shown, first, the resist pattern 57 shown in FIG. 4C is removed using a resist solvent such as thinner. Here, the type of resist solvent may be a commonly used solvent, but is preferably a resist solvent containing a quaternary ammonium salt. For example, when the resist film constituting the resist pattern 57 is made of an ArF resist (acrylic resin), it is preferable to use a glycol ether solvent, and the resist film constituting the resist pattern 57 is a KrF resist ( In the case of a phenol resin, it is preferable to use an amide solvent. Thereby, the resist pattern 57 can be effectively removed.

Next, for example, plasma ashing using plasma made of oxygen gas is performed to remove the antireflection film 56. Here, in the plasma ashing, reactive plasma ashing without using an RF bias is performed in order to suppress an increase in the dielectric constant of the low dielectric constant film 54. Further, as the gas constituting the plasma, in addition to the O ₂ gas, for example, H ₂ , H ₂ O N ₂ or He may be used, for example, N ₂ / H ₂ , H ₂ / He, NH ₃ , CF ₄ / O ₂ , SF ₆ / O ₂ , or O ₂ / H ₂ O. O ₂ , H ₂ , H ₂ O, etc. Alternatively, a mixed gas in which two or more kinds of gases composed of N ₂ or He are combined may be used.

  Then, after returning to the state shown in FIG. 4 (b) by performing polymer washing or water washing as necessary, as described above, a resist film is applied and a resist pattern 57 is formed again. The state shown in FIG.

  Next, as shown in FIG. 4D, the wiring connection hole 58 is formed by dry etching the antireflection film 56, the damage prevention film 55, and the low dielectric constant film 54 using the resist pattern 57 as a mask. Form. In this case, although not shown, a reaction product of the resist film and the polymer removed by etching adheres to the side wall of the resist pattern 57.

  Next, the resist pattern 57 and the antireflection film 56 are removed. At this time, in the same manner as when the misalignment of the resist pattern 57 is outside the design allowable range, the resist pattern 57 is removed together with the reaction product adhering to the sidewall using a resist solvent, and the antireflection film 56 is removed by plasma ashing. Can be removed.

  Next, as shown in FIG. 4E, an organic material such as a resist is applied to the entire surface of the substrate so as to fill the wiring connection hole 58, and then anisotropic etching is performed to connect the wiring. A resist plug 59 is formed in the hole 58. The resist plug 59 has a role of preventing the insulating barrier film 53 from penetrating by etching when forming an upper layer wiring groove to be described later.

  Next, an antireflection film 60 is applied on the damage prevention film 55 and the resist plug 59. Next, after applying a resist film necessary for forming the upper wiring groove pattern, the resist film is subjected to lithography (exposure and development) to thereby form a resist pattern 61 (second resist) that becomes the upper wiring groove pattern. Corresponding to the pattern, the same shall apply hereinafter).

  Next, as shown in FIG. 4F, the upper wiring trench 62 is formed by performing dry etching on the antireflection film 60, the damage prevention film 55, and the low dielectric constant film 54 using the resist pattern 61 as a mask. Form. In this case, although not shown, reaction products of the resist film and the polymer removed by etching adhere to the side walls of the resist pattern 62.

  Next, the resist pattern 61 and the antireflection film 60 are removed. At this time, similarly to the case where the misalignment of the resist pattern 61 is outside the design allowable range, the resist pattern 61 is removed together with the reaction product adhering to the side wall using a resist solvent, and the antireflection film 60 is removed by plasma ashing. Can be removed.

  Next, as shown in FIG. 4G, anisotropic etching is performed on the entire surface of the substrate so that the remaining damage prevention film 55 is removed and the surface of the lower layer wiring 52 is exposed. Then, the resist plug 59 remaining on the insulating barrier film 53 is removed.

  Next, as shown in FIG. 4H, for example, Ta / TaN is formed on the low dielectric constant film 54 and the lower layer wiring 52 so as to bury the wiring connection hole 58 and the upper layer wiring groove 62 halfway by sputtering. A barrier metal film made of a laminated film and a seed film made of copper are sequentially deposited from the bottom (not shown). Next, a copper film is formed on the seed film so that the wiring connection hole 58 and the upper wiring groove 62 are completely filled by electrolytic plating, and then the upper wiring groove is formed on the surface of the low dielectric constant film 54 by CMP. By removing the copper film protruding from 62 and flattening the surface of the low dielectric constant 54, a conductor 63 composed of a wiring plug and an upper wiring is formed.

  As described above, according to the method of manufacturing a semiconductor device according to the fourth embodiment, in the method of forming a copper wiring using the dual damascene method, when the resist pattern (57, 61) is regenerated, first, the resist Since the resist pattern (57, 61) is removed using a solvent, generation of a residue can be prevented. That is, when the resist pattern is removed by plasma ashing as in the conventional example, as described in the conventional example, a part of the antireflection film that becomes the base of the resist pattern is removed by ashing, and the side wall of the resist pattern is removed. In the semiconductor device according to the fourth embodiment, since the resist pattern is removed using a resist solvent, an antireflection film that becomes a base when removing the resist pattern (57, 61). (56, 60) is not removed, and when the antireflection film (56, 60) is removed by ashing, the resist pattern (57, 61) is completely removed. The antireflection film (56, 60) removed by ashing does not adhere to the side walls of (57, 61). In this manner, since the resist can be removed without generating a residue, film peeling caused by the residue forming a fence or the like can be prevented, so that a semiconductor device that achieves high yield and high reliability can be obtained. A manufacturing method can be provided.

  Further, when removing the resist pattern (57, 61) used for etching, first, the resist pattern (57, 61) is removed using a resist solvent, so that generation of a residue can be prevented. That is, since the resist pattern (57, 61) is removed using the resist solvent, the resist pattern (57, 61) can be removed together with the reaction product attached to the side wall. Further, when the antireflection film (56, 60) is removed by ashing, the resist pattern (57, 61) is completely removed, so that the side walls of the resist pattern (57, 61) are removed by ashing. The antireflection film 24 does not adhere. As described above, since the resist pattern (57, 61) can be removed without generating a residue, the residue can prevent film peeling caused by forming a fence, so that high yield and high reliability can be achieved. A method for manufacturing a semiconductor device can be provided.

  Furthermore, according to the semiconductor device manufacturing method of the fourth embodiment, the resist pattern (57, 61) is removed using a resist solvent without performing plasma ashing, and the antireflection film (56, 60) is removed. Since the plasma ashing is performed only at this time, the time for performing the plasma ashing can be shortened. Therefore, damage to the low dielectric constant film formed below the antireflection film (56, 60) can be reduced. A method for manufacturing a semiconductor device that achieves high yield and high reliability can be provided.

In the first to fourth embodiments described above, the low dielectric constant film replaces, for example, the end of silicon in the silicon oxide film with an alkyl group —CH ₃ group, and reduces the density and porosity of the silicon oxide film. In the above description, the carbon-containing silicon oxide film, which is a film having a reduced dielectric constant, has been described. However, a coating organic polymer or the like may be used.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to remove the resist without leaving a residue and shorten the plasma ashing time to reduce damage to the low dielectric constant film. . Therefore, the method for manufacturing a semiconductor device according to the present invention is useful for realizing a high yield and high reliability of a semiconductor device using a low dielectric constant film.

It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is process sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

10, 20, 30, 50 Silicon substrate 11, 21 First interlayer insulating film 12, 22 Low dielectric constant film 13, 23 Second interlayer insulating film 14, 24, 33, 38, 56, 60 Antireflection film 15, 25 Resist films 16 and 26 Resist pattern 27 Reaction products 31 and 54 Low dielectric constant films 32 and 55 Damage prevention films 34 and 57 Resist pattern (first resist pattern)
35 Lower layer wiring groove pattern 36, 52 Lower layer wiring 37 Interlayer insulating film 39, 61 Resist pattern (second resist pattern)
40, 58 Wiring connection hole pattern 41 Conductive film 51 Interlayer insulating film 53 Insulating barrier film 59 Resist plug 62 Upper layer wiring groove 63 Conductor

Claims (12)

A step (a) of forming a resist pattern on a low dielectric constant film formed on a substrate;
(B) forming a wiring groove in the low dielectric constant film by etching the low dielectric constant film using the resist pattern as a mask;
Using a resist solvent containing a thinner, a glycol ether solvent or an amide solvent, and a quaternary ammonium salt, and the step (c) of removing the resist pattern,
The step (c) is a step of removing the resist pattern and removing a reaction product formed on the resist pattern in the step (b) in the same step. Manufacturing method. Forming an antireflection film on the low dielectric constant film before the step (a) of forming the resist pattern;
A step of removing the antireflection film by ashing after the step (c) of removing the resist pattern;
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (a) of forming the resist pattern is a step of forming the resist pattern on the antireflection film. The ashing is performed by combining two or more kinds of gases of O ₂ , H ₂ , H ₂ O, N ₂ or He, or O ₂ , H ₂ , H ₂ O, N ₂ or He. The method for manufacturing a semiconductor device according to claim 2, wherein the method is performed using a mixed gas.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the low dielectric constant film is a silicon oxide film containing carbon.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (a) is a step of forming the resist pattern on the low dielectric constant film through an insulating film made of a silicon oxide film. Method. A step (a) of forming a first resist pattern on the low dielectric constant film formed on the substrate;
A step (b) of removing the first resist pattern by using a resist solvent containing a thinner, a glycol ether solvent or an amide solvent, and a quaternary ammonium salt ;
A step (c) of forming a second resist pattern on the low dielectric constant film;
(D) forming a wiring groove in the low dielectric constant film by etching the low dielectric constant film using the second resist pattern as a mask;
And (e) removing the second resist pattern using a resist solvent,
The step (e) is a step of removing the second resist pattern and removing a reaction product formed on the second resist pattern by the step (d) in the same step. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 6 , wherein the low dielectric constant film is a silicon oxide film containing carbon. The step (a) is a step of forming the first resist pattern on the low dielectric constant film via an insulating film made of a silicon oxide film,
Wherein step (c), the on the low dielectric constant film with an insulating film made of the silicon oxide film according to claim 6, characterized in that the step of forming the second resist pattern A method for manufacturing a semiconductor device. A step (a) of forming a first antireflection film on the low dielectric constant film formed on the substrate;
Forming a first resist pattern on the first antireflection film (b);
(C) removing the first resist pattern using a resist solvent containing a thinner, a glycol ether solvent or an amide solvent, and a quaternary ammonium salt ;
Removing the first antireflection film by ashing (d);
Forming a second antireflection film on the low dielectric constant film (e);
A step (f) of forming a second resist pattern on the second antireflection film;
Forming a wiring trench in the low dielectric constant film by etching the low dielectric constant film using the second resist pattern as a mask; and
And a step (h) of removing the second resist pattern using a resist solvent,
The step (h) is a step of removing the second resist pattern and removing a reaction product formed on the second resist pattern by the step (g) in the same step. A method of manufacturing a semiconductor device. The ashing is performed by combining two or more kinds of gases of O ₂ , H ₂ , H ₂ O, N ₂ or He, or O ₂ , H ₂ , H ₂ O, N ₂ or He. The method for manufacturing a semiconductor device according to claim 9 , wherein the method is performed using a mixed gas. The method of manufacturing a semiconductor device according to claim 9 , wherein the low dielectric constant film is a silicon oxide film containing carbon. The step (a) is a step of forming the first antireflection film on the low dielectric constant film through an insulating film made of a silicon oxide film,
Wherein step (e), wherein the above low dielectric constant film, to claim 9, characterized in that via an insulating film made of the silicon oxide film is a step of forming the second antireflection film Semiconductor device manufacturing method.

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