JP4487481B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which planar devices such as a trench lateral power MOSFET and a planar MOSFET are integrated on the same semiconductor substrate and a manufacturing method thereof.
[0002]
[Prior art]
In general, a power MOSFET is provided with an extended drain region in order to increase the breakdown voltage. FIG. 265 is a longitudinal sectional view showing a configuration of a conventional n-channel planar power MOSFET. As shown in FIG. 265, the N-type extended drain region 12 is formed between the gate electrodes 16 and 16 of adjacent elements sharing the N-type drain region 13 and the drain electrode 17 along the surface of the P-type semiconductor substrate 11. It is provided so as to surround the drain region 13. The P-type base region 14, the N-type source region 15, and the source electrode 18 are provided on the side away from the extended drain region 12.
[0003]
The gate electrode 16 extends on the thick field oxide film 10 connected to the gate oxide film 19 and constitutes a field plate. In the present specification, the planar device does not include a power device such as a planar power MOSFET.
[0004]
The planar power MOSFET is manufactured by a process substantially similar to that of a planar device such as BiCMOS. Therefore, it is easy to obtain a one-chip power IC by fabricating a planar power MOSFET together with a planar device on the same semiconductor substrate. However, as described above, in the planar power MOSFET, since the extended drain region 12 is provided along the substrate surface, a one-chip power IC composed of the planar power MOSFET and the planar device has a low degree of integration. There is.
[0005]
Therefore, a trench lateral power MOSFET (hereinafter referred to as TLPM) has been proposed that can be highly integrated and has an advantage that the on-resistance per unit area is smaller than that of a planar power MOSFET. FIG. 266 shows a vertical cross-sectional configuration of a conventional n-channel TLPM. A trench 30 is formed in the P-type semiconductor substrate 21. The N-type extended drain region 22 is provided along the lower portion and the bottom portion of the sidewall of the trench 30.
[0006]
A P-type body region 24 is provided outside the extended drain region 22. An N-type drain region 23 is provided inside the extended drain region 22. Further, a gate oxide film 29, a gate electrode 26, an interlayer insulating film 31, and a drain polysilicon 32 are provided inside the trench 30 in order from the outside. A P-type channel region 33 is provided outside the trench 30, and an N-type source region 25 is provided thereon. The outside of the source region 25 is a P-type plug region 34. The source electrode 28 is in contact with the source region 25 and the plug region 34 in common. The drain electrode 27 is electrically connected to the drain region 23 through the drain polysilicon 32.
[0007]
A manufacturing process of the TLPM shown in FIG. 266 will be described. 267 to 274 are longitudinal sectional views in the middle of manufacturing the TLPM shown in FIG. 266. First, a mask oxide film 41 is formed on the surface of the semiconductor substrate 21, and a trench 30 is formed in the opening by RIE (reactive ion etching) (FIG. 267). A buffer oxide film 42 is formed inside the trench 30, and B ₁₁ Is doped (FIG. 268) to form the body region 24. Next, P ₃₁ Is doped (FIG. 269) to form the extended drain region 22. Then, after removing the buffer oxide film 42, a gate oxide film 29 is formed inside the trench 30 (FIG. 270).
[0008]
Next, polysilicon 43 is deposited on the inside of the trench 30 and on the substrate surface (FIG. 271), and is etched back to form the gate electrode 26 only on both side wall portions of the trench 30 (FIG. 272). Subsequently, the interlayer insulating film 31 is laminated by a film forming method such as LPCVD or P-TEOSCVD so that the bottom of the trench is thinner than the surface of the substrate (FIG. 273). Then, the interlayer insulating film 31 is etched back to open a contact hole penetrating the interlayer insulating film 31 and the gate oxide film 29 at the bottom of the trench.
[0009]
A drain region 23 is formed at the bottom of the trench via a contact hole at the bottom of the trench. Thereafter, the central portion of the trench 30 is filled with the drain polysilicon 32 (FIG. 274). Thereafter, contact holes are opened in the interlayer insulating film 31 covering the substrate surface, and a channel region 33, a source region 25, and a plug region 34 are formed. Finally, the metal is patterned to form the source electrode 28 and the drain electrode 27, and the TLPM configured as shown in FIG. 266 is completed.
[0010]
In the above-described type of TLPM (referred to as the first type), the drain region 23 is provided at the bottom of the trench. ing. As shown in FIG. 275, in the second type TLPM, the N-type source region 25 is provided at the bottom of the trench 30 formed in the P-type semiconductor substrate 21. In addition, a P-type base region 45 is provided so as to surround the source region 25 along the lower portion and the bottom portion of the sidewall of the trench 30.
[0011]
An N-type extended drain region 22 is provided outside the trench 30. An N-type drain region 23 is provided in the substrate surface layer of the extended drain region 22. Inside the trench 30, a gate oxide film 29, a gate electrode 26, an interlayer insulating film 31 and a source polysilicon 46 are provided in order from the outside. Source electrode 28 is electrically connected to source region 25 through source polysilicon 46. The drain electrode 27 is in contact with the drain region 23.
[0012]
As described above, in the first type TLPM, the gate electrode 26 is provided outside the drain polysilicon 32 via the interlayer insulating film 31, and further, the extended drain region is provided outside via the gate oxide film 29. 22 is provided. Therefore, in the first type of TLPM, the feedback capacitance between the gate and the drain, which causes a decrease in switching characteristics, is not only between the gate electrode 26 and the extended drain region 22, but also the drain polysilicon 32 and the gate electrode. 26 also exists. On the other hand, in the second type TLPM, the feedback capacitance between the gate and the drain is only present between the gate electrode 26 and the extended drain region 22, and therefore, compared with the first type TLPM, There is an advantage that the switching characteristics are greatly improved.
[0013]
[Problems to be solved by the invention]
However, the manufacturing process described above for the first type of TLPM is a process for manufacturing a single TLPM, and is not shared with a manufacturing process for a general planar device such as a CMOS or BiCMOS. Although the description of the manufacturing process of the second type TLPM is omitted, it is almost the same as the manufacturing process of the first type TLPM, and this is also the manufacturing of a general planar type device such as CMOS or BiCMOS. Not shared with processes. Therefore, conventionally, in order to configure a one-chip power IC with TLPM and a planar type device, the TLPM and the planar type device are manufactured by separate processes and electrically connected to each other. Must be electrically connected to a common printed circuit board by bonding wires.
[0014]
Therefore, not only the cost is increased, but also disadvantages such as a decrease in the degree of integration and an increase in the on-resistance due to the bonding wire are brought about, and the advantage of TLPM that the high integration is possible and the on-resistance per unit area is small enough There is a problem that it cannot be used.
[0015]
The present invention has been made in view of the above problems, and is a semiconductor device capable of realizing downsizing, low on-resistance, and low cost of an IC chip having a TLPM and a planar device on the same semiconductor substrate. The purpose is to provide. It is another object of the present invention to provide a method for manufacturing a semiconductor device that can manufacture an IC chip having a small TLPM and a planar device on the same semiconductor substrate at low cost.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, the gate electrode of the TLPM and the gate electrode of the planar device are formed by patterning the same polysilicon layer, and the drain and source electrodes of the TLPM and the drain of the planar device are formed. The electrode and the source electrode are formed by patterning the same metal wiring layer. According to the present invention, the TLPM and the planar device are electrically connected to each other via the metal wiring layer constituting the drain electrode and the source electrode and the polysilicon layer constituting the gate electrode.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a longitudinal sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, P well regions 52 and 53 and an N well region 54 are formed on the surface layer of a P-type semiconductor substrate 51, and one P well region 52 has a first type, that is, a trench bottom. A TLPM 100 having a drain contact is formed, an N channel MOSFET (hereinafter referred to as NMOS) 200 is formed in the other P well region 53, and a P channel MOSFET (hereinafter referred to as PMOS) 300 is formed in the N well region 54. Is formed.
[0018]
In the following description, for the sake of convenience, the P well region in which the TLPM is formed is distinguished as the first P well region 52, and the P well region in which the NMOS is formed is distinguished as the second P well region 53. The TLPM 100, the NMOS 200, and the PMOS 300 are separated by a selective oxide film (LOCOS) 63.
[0019]
First, the TLPM 100 will be described. In the first P well region 52, a trench 130 having substantially the same depth as that of the first P well region 52 is formed. The sides and bottom of the trench 130 are surrounded by a P-type field region 144. An N-type extended drain region 122 shallower than the field region 144 is provided along the side and bottom of the trench 130. An N-type drain region 123 is provided inside the extended drain region 122. Inside the trench 130, a gate oxide film 129, a gate electrode 126, an oxide film (a part of a shadow oxide film 68 described later), an interlayer insulating film 131, and a drain polysilicon 132 are provided in this order from the outside.
[0020]
In the substrate surface layer, a P-type channel region 133 is provided outside the trench 130, and an N-type source region 125 is provided in the surface layer. The outside of the source region 125 is a P-type plug region 134. The source electrode 128 penetrates through the interlayer insulating film 131 and the passivation film 71 and is in common contact with the source region 125 and the plug region 134. Thus, since the source region 125, the plug region 134, and the source electrode 128 are in electrical contact with each other, the grounding with the substrate 51 is good, and the breakdown voltage does not decrease even with a large current. The drain electrode 127 penetrates the passivation film 71 and is electrically connected to the drain region 123 through the drain polysilicon 132.
[0021]
Next, the NMOS 200 will be described. A P-type channel region 233 is formed in the surface layer of the second P-well region 53, and an N-type drain region 223 and an N-type source region 225 are formed therein. A gate oxide film 229 is formed on the substrate surface between the drain region 223 and the source region 225, and a gate electrode 226 is formed thereon. The drain electrode 227 and the source electrode 228 pass through the interlayer insulating film 131 and the passivation film 71 and are in contact with the drain region 223 and the source region 225, respectively.
[0022]
Next, the PMOS 300 will be described. An N-type channel region 333 is formed in the surface layer of the N-well region 54, and a P-type drain region 323 and a P-type source region 325 are formed therein. A gate oxide film 329 is formed on the substrate surface between the drain region 323 and the source region 325, and a gate electrode 326 is formed thereon. The drain electrode 327 and the source electrode 328 pass through the interlayer insulating film 131 and the passivation film 71 and are in contact with the drain region 323 and the source region 325, respectively.
[0023]
A manufacturing process of the semiconductor device shown in FIG. 1 will be described. 2 to 27 are longitudinal sectional views of the semiconductor device shown in FIG. First, the N well region 54 is selectively formed on the surface layer of the semiconductor substrate 51, and the first P well region 52 and the second P well region 53 are formed using the selective oxide film 55 formed on the substrate surface as a mask. (FIG. 2). Thereafter, the selective oxide film 55 is completely removed (FIG. 3).
[0024]
Subsequently, a buffer oxide film 56 is formed on the substrate surface (FIG. 4), and a mask oxide film 57 is formed thereon (FIG. 5). Further, a mask 58 having an opening for forming a trench is provided on the mask oxide film 57 (FIG. 6). The mask oxide film 57 is patterned using this mask 58, and after removing the mask 58, trench etching is performed by RIE to form a trench 130 in the first P well region 52. A buffer oxide film 59 is formed inside the trench 130 (FIG. 7), and B is formed at the bottom of the trench. ₁₁ Is doped (FIG. 8) to form a field region 144 (FIG. 9). Thereafter, the mask oxide film 57 and the buffer oxide films 56 and 59 are completely removed (FIG. 10).
[0025]
Subsequently, a buffer oxide film 60 is formed on the substrate surface and inside the trench 130 (FIG. 11), and a silicon nitride film 61 is formed thereon. Further thereon, a mask 62 having an element isolation region opened is provided (FIG. 12). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 13). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 14).
[0026]
Subsequently, a mask 64 having an opening above the trench 130 is formed on the substrate surface, and P ₃₁ Is doped (FIG. 15) to form an extended drain region 122 (FIG. 16). Thereafter, a mask 65 having openings in the channel regions of TLPM and NMOS is formed on the substrate surface. B ₁₁ (FIG. 17), a TLPM channel region 133 is formed in the first P well region 52, and simultaneously, an NMOS channel region 233 is formed in the second P well region 53. Then, the mask 65 is removed (FIG. 18).
[0027]
Subsequently, a mask 66 having a PMOS channel region opened is formed on the substrate surface. ₃₁ (FIG. 19), a PMOS channel region 333 is formed in the N well region. Then, the buffer oxide film 60 is removed, and a common thin oxide film to be the gate oxide films 129, 229, and 329 of TLPM, NMOS, and PMOS is formed inside the trench 130 and on the substrate surface, and a polysilicon layer 143 is formed thereon. Are stacked (FIG. 20). Note that the order of the steps in FIGS. 15 and 16 and FIGS. 17 and 18 may be reversed.
[0028]
Further, a mask 67 is formed only on the gate electrodes of NMOS and PMOS (FIG. 21). The polysilicon layer 143 is etched using the mask 67, and a TLPM gate electrode 126, an NMOS gate electrode 226, and a PMOS gate electrode 326 are simultaneously formed by self-alignment inside the trench 130. Then, the mask 67 is removed (FIG. 22).
[0029]
A shadow oxide film 68 is formed to cover the gate electrode 126 of TLPM, the gate electrode 226 of NMOS, and the gate electrode 326 of PMOS. After that, a mask 69 is formed on the substrate surface by opening the source region and drain region of TLPM and the NMOS formation region. As ₇₅ (FIG. 23), a TLPM drain region 123 is formed at the bottom of the trench 130, a TLPM source region 125 is formed outside the trench 130, and a source region 225 and a drain region 223 are formed in the NMOS channel region 233 simultaneously. Then, the mask 69 is removed.
[0030]
Subsequently, a mask 70 in which a plug region of TLPM and a PMOS formation region are opened is formed on the substrate surface. B ₁₁ (FIG. 24), a plug region 134 is formed outside the TLPM source region 125, and a source region 325 and a drain region 323 are simultaneously formed in the PMOS channel region 333. The mask 70 is removed, and an interlayer insulating film 131 is stacked on the entire surface of the substrate (FIG. 25). Then, a portion of the interlayer insulating film 131 inside the trench 130 is etched by self-alignment to open a contact hole, and the trench is filled with drain polysilicon 132 (FIG. 26). Then, a passivation film 71 is formed on the entire surface of the substrate (FIG. 27). Note that the order of the steps of FIG. 23 and FIG. 24 may be reversed.
[0031]
Subsequently, the passivation film 71 is patterned to open contact holes. Further, a metal is patterned thereon, a drain electrode 127 that contacts the TLPM drain polysilicon 132, a source electrode 128 that contacts the TLPM source region 125 and the plug region 134 in common, and a drain that contacts the NMOS drain region 223. An electrode 227, a source electrode 228 in contact with the NMOS source region 225, a drain electrode 327 in contact with the PMOS drain region 323, and a source electrode 328 in contact with the PMOS source region 325 are formed simultaneously. In this manner, a semiconductor device in which the TLPM 100, the NMOS 200, and the PMOS 300 are integrated on the same semiconductor substrate 51 as shown in FIG. 1 is completed.
[0032]
In the TLPM 100 shown in FIG. 1, the trench 130 is formed with substantially the same depth as the first P well region 52. However, like the TLPM 101 shown in FIG. The drain region 123 may be formed deeper than the TLPM 100 shown in FIG. On the other hand, the first P well region 52 is formed shallower than in the case of the TLPM 100 shown in FIG. 1 as in the TLPM 102 shown in FIG. 29, and the trench 130 penetrates the first P well region 52. It may be configured.
[0033]
Further, as in the case of the TLPM 103 illustrated in FIG. 30, a P-type body region 124 that surrounds the extended drain region 122 may be provided. In this case, in the process shown in FIG. ₃₁ Instead of forming the extended drain region 122 by doping, the extended drain region 122 may be formed after the body region 124 is formed. With such a configuration, there is an advantage that a TLPM having a high breakdown voltage and a low on-resistance can be obtained even with a dose amount of a relatively high concentration N-type impurity. Similarly, even when the concentration of the extended drain region 122 is increased to reduce the on-resistance in FIG. 28, the breakdown voltage can be maintained by forming the first P well region 52 deeper than the extended drain region 122.
[0034]
Further, as shown in FIG. 31, a plurality of TLPMs 102 (only two appear in the illustrated example) of the same conductivity type channel may be provided in the same well region 52. In this case, a plurality of trenches are formed in the same well region 52 in the steps shown in FIGS. 6 and 7, and thereafter, a plurality of processes are simultaneously performed on the trench 130 in the steps shown in FIG. What is necessary is just to apply with respect to a trench. With this configuration, the TLPMs 102 and 102 can be large current elements. The TLPM may have the configuration of TLPM 100 or TLPM 101.
[0035]
Further, as shown in FIG. 32, the bipolar transistor 400 may be integrated with the TLPM 101 on the same semiconductor substrate 51. In the example shown in FIG. 32, the bipolar transistor 400 is formed in the third P well region 72. In the third P well region 72, a first P type offset region 401 and an N well region 402 are formed. In the N well region 402, an N type collector region 403 and a second P type offset region 404 are formed. A P-type base region 405 and an N-type emitter region 406 are formed in the second P-type offset region 404. A substrate pickup electrode 408 is electrically connected to the first P-type offset region 401 via a high-concentration P-type contact region 407.
[0036]
In addition, collector electrode 409, base electrode 410, and emitter electrode 411 are in contact with collector region 403, base region 405, and emitter region 406, respectively. These substrate pickup electrode 408, collector electrode 409, base electrode 410 and emitter electrode 411 are TLPM 101, PMOS 300 and NMOS (200) drain electrodes 127, 327 (227) and source electrodes 128, 328 (228) not shown in the figure. ) At the same time. The TLPM may have a configuration of TLPM 100, TLPM 102, or TLPM 103.
[0037]
Further, as shown in FIG. 33, the resistance element 500 may be integrated with the TLPM 101 on the same semiconductor substrate 51. In the example shown in FIG. 33, the resistance element 500 is formed in the fourth P well region 73. An N well region 501 is formed in the fourth P well region 73. In the N well region 501, high concentration N type contact regions 503 and 504 separated by a P type offset region 502 are formed. Electrodes 505 and 506 are in contact with the N-type contact regions 503 and 504. The electrodes 505 and 506 are formed simultaneously with the TLPM 101, the PMOS 300, and the drain electrodes 127 and 327 (227) and the source electrodes 128 and 328 (228) of the NMOS (200) not shown in the drawing. The TLPM may have a configuration of TLPM 100, TLPM 102, or TLPM 103.
[0038]
Further, as shown in FIG. 34, the capacitance 600 may be integrated with the TLPM 101 on the same semiconductor substrate 51. In the example shown in FIG. 34, the capacitance 600 is formed in the fifth P well region 74. An N well region 601 is formed in the fifth P well region 74. A high concentration N-type contact region 602 is formed in the N well region 601. An electrode 603 is in contact with the N-type contact region 602. The electrode 603 is formed simultaneously with the TLPM 101, the PMOS 300, and the gate electrodes 126 and 326 (226) of the NMOS (200) not shown in the drawing. The TLPM may have a configuration of TLPM 100, TLPM 102, or TLPM 103.
[0039]
FIG. 35 is a diagram schematically showing a size comparison between a power module to which the semiconductor device according to the present invention is applied and a power module using a conventional planar type power MOSFET. As shown in FIG. 35, in the power module 1 to which the semiconductor device according to the present invention is applied, the size of the IC chip is 2.1 mm × 3.5 mm, and the power unit 2 configured by the above-described TLPMs 101 to 103 and the like. The area is 3.2mm ² The area of the control unit 3 including the NMOS 200, the PMOS 300, the bipolar transistor 400, the resistance element 500, the capacitance 600, and the like is 4 mm. ² It is.
[0040]
On the other hand, in the power module 4 using the conventional planar type power MOSFET, the size of the IC chip is 3.5 mm × 3.5 mm, and the area of the power unit 5 constituted by the planar type power MOSFET or the like is 8 mm. ² And the area of the control unit 6 is 4 mm. ² It is.
[0041]
According to the first embodiment described above, the gate electrode 126 of the TLPMs 100, 101, 102, 103, the gate electrode 226 of the NMOS 200, and the gate electrode 326 of the PMOS 300 are formed by patterning the same polysilicon layer 143. , 102, 103 drain electrode 127 and source electrode 128, NMOS 200 drain electrode 227 and source electrode 228, and PMOS 300 drain electrode 327 and source electrode 328 are formed by patterning the same metal wiring layer. The TLPM 100 and the NMOS 200 and the PMOS 300 can be electrically connected to each other through the wiring layer and the polysilicon layer 143. Therefore, since it is not necessary to perform wire bonding to the printed circuit board as in the prior art, it is possible to obtain a one-chip power IC that is small in size, low on-resistance, and low in cost.
[0042]
Further, according to the first embodiment, the channel region 133 of the TLPM 100 and the channel region 233 of the NMOS 200 are formed simultaneously, the gate electrode 126 of the TLPM 100, the gate electrode 226 of the NMOS 200, and the gate electrode 326 of the PMOS 300 are formed simultaneously. The drain region 123 and the source region 125 of the TLPM 100, the source region 225 and the drain region 223 of the NMOS 200 are formed at the same time, the plug region 134 of the TLPM 100, the source region 325 and the drain region 323 of the PMOS 300 are formed at the same time, and the drain of the TLPM 100 The electrode 127 and the source electrode 128, the drain electrode 227 and the source electrode 228 of the NMOS 200, and the drain electrode 327 and the source electrode 328 of the PMOS 300 are the same. Because it is formed, it is possible to suppress the cost increase due to increase in the manufacturing process.
[0043]
Embodiment 2. FIG.
FIG. 36 is a longitudinal sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment is different from the first embodiment shown in FIG. 1 in that a TLPM 104 having no field region is formed as a TLPM, and this TLPM 104 is substantially constant including the lower portion of the trench 130. It is formed in the P well region 75 having a depth of. The other configuration of the TLPM 104 is the same as that of the TLPM 100 of the semiconductor device shown in FIG. In addition, about the structure similar to Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.
[0044]
A manufacturing process of the semiconductor device shown in FIG. 36 will be described. 37 to 47 are longitudinal sectional views of the semiconductor device shown in FIG. First, an N well region 54 is selectively formed on the surface layer of the semiconductor substrate 51, and a selective oxide film 55 is formed on the surface of the N well region 54 by diffusion oxidation (FIG. 37). Thereafter, a mask 58 having an opening in the trench formation region is formed on the substrate surface (FIG. 38). Using this mask 58, trench etching is performed to form a trench 130 (FIG. 39). Then, the mask 58 is removed (FIG. 40).
[0045]
Subsequently, a buffer oxide film 59 is formed on the side wall of the trench 130, and the selective oxide film 55 is used as a mask in the outer region of the trench 130, the bottom of the trench and the NMOS formation region. ₁₁ The first P well region 75 and the second P well region 53 are formed (FIG. 42). Then, after the selective oxide film 55 and the buffer oxide film 59 are completely removed (FIG. 43), a buffer oxide film 60 is formed on the substrate surface and inside the trench 130 (FIG. 44). A silicon nitride film 61 is formed thereon (FIG. 45), patterning is performed to form a mask having an element isolation region opened (FIG. 46), and thermal oxidation is performed to form a selective oxide film 63 for element isolation. Form (FIG. 47).
[0046]
Thereafter, the steps shown in FIGS. 15 to 27 of the first embodiment are sequentially performed, and further, the passivation film 71 is formed and each drain electrode and each source electrode are formed, whereby the semiconductor device having the configuration shown in FIG. 36 is obtained. Complete.
[0047]
According to the second embodiment described above, as in the first embodiment, in addition to the effect of obtaining a one-chip power IC that is small in size, low on-resistance, and low in cost, the depth of the P well region 75 is obtained. Is substantially constant including the lower portion of the trench 130, so that there is an effect that the TLPM 104 of any output stage in which punch-through and latch-up do not occur can be obtained without providing a field region.
[0048]
Embodiment 3 FIG.
In the semiconductor device according to the third embodiment of the present invention, after the P well regions 52 and 53 and the N well region 54 are formed, a selective oxide film 63 for element isolation is formed, and then a trench 130 is formed. . Accordingly, the vertical cross-sectional configuration of the completed semiconductor device is the same as that of the first embodiment shown in FIG. Note that components similar to those in the first embodiment are denoted by the same reference numerals as those in the first embodiment.
[0049]
48 to 61 are longitudinal sectional views of the semiconductor device according to the third embodiment of the present invention in the middle of manufacture. First, the N well region 54 and the P well regions 52 and 53 are selectively formed on the surface layer of the semiconductor substrate 51 in the same manner as the steps shown in FIGS. An oxide film 56 is formed (FIG. 48). A silicon nitride film 61 is formed thereon, and a mask 62 having an element isolation region opened is provided thereon (FIG. 49). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 50). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 51). Thereafter, the silicon nitride film 61 is removed (FIG. 52).
[0050]
Again, a silicon nitride film 76 is laminated on the substrate surface, and a mask oxide film 57 is further laminated thereon (FIG. 53). Further thereon, a mask 58 having an opening in the trench formation region is provided (FIG. 54). The mask oxide film 57 is patterned using this mask 58, and after removing the mask 58, trench etching is performed to form a trench 130 (FIG. 55). Then, the mask oxide film 57 and the silicon nitride film 76 are removed (FIG. 56), and the buffer oxide film 56 on the substrate surface is removed leaving the selective oxide film 63 (FIG. 57).
[0051]
Subsequently, a buffer oxide film 59 is formed inside the trench 130, and a mask 77 covering the substrate surface is formed except for the trench 130 (FIG. 58). B at the bottom of the trench using mask 77 ₁₁ Is doped (FIG. 59) to form a field region 144. Then, the mask 77 is removed (FIG. 60). Subsequently, a mask 64 having an opening above the trench 130 is formed on the substrate surface, and P ₃₁ Is doped (FIG. 61).
[0052]
As a result, the extended drain region 122 is formed as shown in FIG. 16, and thereafter, the steps shown in FIGS. 17 to 27 of the first embodiment are performed in order, and further the formation of the passivation film, each drain electrode, A semiconductor device is completed by forming each source electrode. According to the third embodiment, similarly to the first embodiment, a one-chip power IC that is small in size, low in on-resistance, and low in cost can be obtained.
[0053]
Embodiment 4 FIG.
FIG. 62 is a longitudinal sectional view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. The semiconductor device according to the fourth embodiment differs from the first embodiment shown in FIG. 1 in that a TLPM is formed in the second P well region 53 instead of the NMOS 200, and this TLPM and the first P well region 28, the TLPM 101 shown in FIG. 28 is formed. Since the configuration of the TLPM 101 is duplicated, description thereof is omitted. In addition, about the structure similar to Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.
[0054]
A manufacturing process of the semiconductor device shown in FIG. 62 will be described. 63 to 70 are longitudinal sectional views of the semiconductor device shown in FIG. First, similarly to the steps shown in FIGS. 2 to 5 of the first embodiment, an N well region 54 and P well regions 52 and 53 are selectively formed on the surface layer of the semiconductor substrate 51, and buffer oxidation is performed on the substrate surface. A film 56 and a mask oxide film 57 are sequentially formed. Further, a mask 58 having an opening in the trench formation region is provided on the mask oxide film 57 (FIG. 63).
[0055]
By patterning mask oxide film 57, removing mask 58, and trench etching, trenches 130 are formed in first P well region 52 and second P well region 53, respectively. A buffer oxide film 59 is formed inside each trench 130 (FIG. 64), and B is formed at the bottom of each trench. ₁₁ Is doped (FIG. 65) to form a field region 144 corresponding to each trench 130 (FIG. 66).
[0056]
After removing mask oxide film 57 and buffer oxide films 56 and 59, a selective oxide film 63 for element isolation is formed in the same manner as in the steps shown in FIGS. Then, a mask 64 having an opening above each trench 130 is formed on the substrate surface, and P ₃₁ (FIG. 67), and an extended drain region 122 is formed corresponding to each trench 130 (FIG. 68). Thereafter, a mask 65 having an opening in the channel region of each TLPM is formed on the substrate surface, and B ₁₁ Is doped (FIG. 69). Thereby, the channel region 133 of each TLPM is formed in the first P well region 52 and the second P well region 53 (FIG. 70).
[0057]
After removing the mask 65, the steps shown in FIGS. 15 to 27 of the first embodiment are sequentially performed on each TLPM, and further, the passivation film 71, the drain electrodes, and the source electrodes are formed. A semiconductor device having the structure shown in FIG. 62 is completed. In order to increase the concentration of the extended drain region 122 and reduce the on-resistance, the P well regions 52 and 53 are formed deeper than the extended drain region 122 instead of the TLPM 101 of FIG. May be formed in the P well regions 52 and 53. 62 may be replaced by the TLPM 100 in FIG. 1, the TLPM 103 in FIG. 30, or the TLPM 102 in FIG. According to the fourth embodiment, similarly to the first embodiment, a one-chip power IC that is small in size, low in on-resistance, and low in cost can be obtained.
[0058]
Embodiment 5 FIG.
FIG. 71 is a longitudinal sectional view showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. The semiconductor device according to the fifth embodiment is different from the first embodiment shown in FIG. 1 in that a TLPM 301 is formed in the N well region 54 instead of the PMOS 300. The N-type drain region 123 of the TLPM 100 formed in the first P-well region 52 shown in FIG. 71 is the same as the N-type drain region 123 of the TLPM 100 shown in FIG. In addition, about the structure similar to Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.
[0059]
The TLPM 301 will be described. A trench 330 is formed in the N well region 54. The side and bottom of the trench 330 are surrounded by a field region 344. A P-type extended drain region 352 that is shallower than the field region 344 is provided along the side and bottom of the trench 330. A P-type drain region 353 is provided inside the extended drain region 352. Inside the trench 330, a gate oxide film 359, a gate electrode 356, an oxide film (a part of a shadow oxide film 68 described later), an interlayer insulating film 131, and a drain polysilicon 362 are provided in this order from the outside.
[0060]
In the substrate surface layer, an N-type channel region 363 is provided outside the trench 330, and a P-type source region 355 is provided in the surface layer. The outside of the source region 355 is an N-type plug region 364. The source electrode 358 penetrates the interlayer insulating film 131 and the passivation film 71 and is in contact with the source region 355 and the plug region 364 in order to improve the grounding with the substrate 51 and prevent the breakdown voltage from being lowered even with a large current. is doing. The drain electrode 357 penetrates the passivation film 71 and is electrically connected to the drain region 353 through the drain polysilicon 362.
[0061]
A manufacturing process of the semiconductor device shown in FIG. 71 will be described. 72 to 90 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. First, similarly to the steps shown in FIGS. 2 to 5 of the first embodiment, an N well region 54 and P well regions 52 and 53 are selectively formed on the surface layer of the semiconductor substrate 51, and buffer oxidation is performed on the substrate surface. A film 56 and a mask oxide film 57 are sequentially formed. Further, a mask 58 having an opening in the trench formation region is provided on the mask oxide film 57 (FIG. 72). By patterning mask oxide film 57, removing mask 58, and trench etching, trench 130 is formed in first P well region 52 and trench 330 is formed in N well region 54. Then, a buffer oxide film 59 is formed inside each of the trenches 130 and 330 (FIG. 73).
[0062]
Subsequently, the trench 330 in the N well region 54 is closed by the mask 78, and B is formed at the bottom of the trench 130 in the first P well region 52. ₁₁ Are ion-implanted (FIG. 74). After removing the mask 78, the trench 130 in the first P well region 52 is closed by the mask 79, and P is formed at the bottom of the trench 330 in the N well region 54. ₃₁ Are ion-implanted (FIG. 75). By removing the mask 79 and performing thermal diffusion, field regions 144 and 344 are formed corresponding to the trenches 130 and 330 (FIG. 76). Note that the order of the process of FIG. 74 and the process of FIG. 75 may be reversed.
[0063]
After removing mask oxide film 57 and buffer oxide films 56 and 59, a selective oxide film 63 for element isolation is formed in the same manner as in the steps shown in FIGS. Then, a mask 80 having an opening above the trench 130 of the first P well region 52 is formed on the substrate surface, and P ₃₁ Are ion-implanted (FIG. 77). After removing the mask 80, a mask 81 having an opening above the trench 330 in the N well region 54 is formed on the substrate surface, and B ₁₁ Are ion-implanted (FIG. 78). The extended drain regions 122 and 352 are formed corresponding to the trenches 130 and 330 by removing the mask 81 and performing thermal diffusion.
[0064]
Thereafter, on the substrate surface, a mask 65 is formed in which the channel region of TLPM formed in the first P well region 52 and the NMOS formation region of the second P well region 53 are opened, and B ₁₁ Are ion-implanted (FIG. 79). After removing the mask 65, a mask 82 having an opening in the channel region of the TLPM formed in the N well region 54 is formed on the substrate surface. ₃₁ Are ion-implanted (FIG. 80). By removing the mask 82 and performing thermal diffusion, a TLPM channel region 133 is formed in the first P well region 52, an NMOS channel region 233 is formed in the second P well region 53, and an N well A TLPM channel region 363 is formed in the region 54 (FIG. 81). Note that the order of the steps of FIG. 79 and FIG. 80 may be reversed.
[0065]
After the buffer oxide film 60 is removed, a common thin oxide film that becomes the TLPM and NMOS gate oxide films 129, 359, and 229 is formed inside the trenches 130 and 330 and on the substrate surface, respectively, and the polysilicon layer 143 is formed thereon. Are stacked (FIG. 82). Further thereon, a mask 67 is formed only on the NMOS gate electrode (FIG. 83). The polysilicon layer 143 is etched using the mask 67, and the gate electrodes 126 and 356 of the TLPM and the gate electrode 226 of the NMOS are simultaneously formed by self-alignment inside the trenches 130 and 330 (FIG. 84).
[0066]
The mask 67 is removed, and a shadow oxide film 68 is formed to cover the TLPM gate electrode 126, the NMOS gate electrode 226, and the TLPM gate electrode 356 (FIG. 85). Thereafter, on the substrate surface, a mask 69 is formed in which the source region and drain region of the TLPM formed in the first P well region 52 and the NMOS formation region are opened, and As is formed. ₇₅ Are ion-implanted (FIG. 86). After the mask 69 is removed, a mask 70 in which a plug region of TLPM formed in the first P well region 52 and a source region and a drain region of TLPM formed in the N well region 54 are opened on the substrate surface. Form B ₁₁ Are ion-implanted (FIG. 87).
[0067]
By removing the mask 70 and performing thermal diffusion, the drain region 123, source region 125, and plug region 134 of TLPM formed in the first P well region 52, source region 225, drain region 223 of NMOS, and N A drain region 353, a source region 355, and a plug region 364 of TLPM formed in the well region 54 are formed simultaneously (FIG. 88). Note that the order of the process of FIG. 86 and the process of FIG. 87 may be reversed.
[0068]
Subsequently, an interlayer insulating film 131 is laminated on the entire surface of the substrate, and portions inside the trenches 130 and 330 of the interlayer insulating film 131 are etched by self-alignment to open contact holes, and further, the inside of each trench is drain polysilicon. It fills with 132,362 (FIG. 89). Then, a passivation film 71 is formed on the entire surface of the substrate (FIG. 90).
[0069]
Subsequently, the passivation film 71 is patterned to open contact holes. Further, a metal is patterned thereon to form a TLPM drain electrode 127 and a source electrode 128 formed in the first P well region 52, a TLPM drain electrode 357 and a source electrode 358 formed in the N well region 54, and An NMOS drain electrode 227 and a source electrode 228 are formed simultaneously. In this manner, a semiconductor device in which the TLPM 100, the NMOS 200, and the TLPM 301 are integrated on the same semiconductor substrate 51 as shown in FIG. 71 is completed. In the example shown in FIG. 71, the P-well region 52 in which the TLPM 100 is formed and the N-well region 54 in which the TLPM 301 is formed are adjacent to each other, but the same applies when not adjacent to each other.
[0070]
In the TLPM 100 of FIG. 71, even when the concentration of the extended drain region 122 is increased to reduce the on-resistance, the breakdown voltage can be maintained by forming the first P well region 52 deeper than the extended drain region 122. .
[0071]
In FIG. 71, when forming a DC-DC converter having an N-type TLPM 100 and a P-type TLPM 301, the N well region 54 is formed deeper than the P-type extended drain region 352, and the extended drain region is formed. Assume that 352 is formed in the N-well region 54. By doing so, the following effects can be obtained. That is, in order to form a DC-DC converter, the drain electrodes 127 and 357 of the N-type TLPM 100 and the P-type TLPM 301 need to have the same potential. Therefore, when the extended drain region 352 is formed deeper than the N well region 54, the extended drain region 352 and the P-type substrate 51 are connected to have the same potential. On the other hand, since the source electrode 128 of the N-type TLPM 100 is at the same potential as the substrate 51, the drain electrodes 127 and 357 are short-circuited with the source electrode 128 through the substrate 51 and do not function as a DC-DC converter.
[0072]
For this inconvenience, since the N drain region 352 and the substrate 51 can be separated by forming the N well region 54 deeper than the extended drain region 352, the drain electrodes 127 and 352 are short-circuited with the source electrode 128. Can be prevented.
[0073]
Note that an N-type body region 354 surrounding the extended drain region 352 may be provided as in the TLPM 302 shown in FIG. In this case, after forming the field regions 144 and 344 and the selective oxide film 63 for element isolation, the mask 83 is used to form B at the bottom of the trench 130 in the first P well region 52. ₁₁ After the mask 83 is removed, the mask 84 is used to form P at the bottom of the trench 330 in the N well region 54. ₃₁ Are ion-implanted (FIG. 93). Note that the order of the process of FIG. 92 and the process of FIG. 93 may be reversed.
[0074]
Then, body regions 124 and 354 are formed corresponding to the trenches 130 and 330 by thermal diffusion (FIG. 94). After removal of the mask 84, P is applied to the bottom of the trench 130 in the first P well region 52 using the mask 80. ₃₁ (FIG. 95). After removing the mask 80, the mask 81 is used to form B at the bottom of the trench 330 in the N well region 54. ₁₁ Are ion-implanted (FIG. 96). Note that the order of the steps of FIG. 94 and FIG. 95 may be reversed.
[0075]
Then, extended drain regions 122 and 352 are formed corresponding to the trenches 130 and 330 by thermal diffusion. Thereafter, using the mask 65, the channel forming region of TLPM formed in the first P well region 52 and the NMOS forming region of the second P well region 53 are made B ₁₁ Are ion-implanted (FIG. 97). Thereafter, the steps shown in FIGS. 80 to 90 are sequentially performed to form each drain electrode and each source electrode.
[0076]
According to the fifth embodiment, TLPM 100 or 103 and TLPM 301 and 302 having different conductivity types are formed in P well region 52 and N well region 54, respectively. A one-chip power IC with low cost and low cost can be obtained.
[0077]
Embodiment 6 FIG.
FIG. 98 is a longitudinal sectional view showing the configuration of the semiconductor device according to the sixth embodiment of the present invention. As shown in FIG. 98, P well regions 52 and 53 and an N well region 54 are formed in a surface layer of a P type semiconductor substrate 51. The first P well region 52 has a second type, that is, the bottom of a trench. A TLPM 1100 of a source contact type is formed, an NMOS 200 is formed in the second P well region 53, and a PMOS 300 is formed in the N well region 54. The TLPM 1100, the NMOS 200, and the PMOS 300 are separated by a selective oxide film 63.
[0078]
The TLPM 1100 will be described. A trench 1030 is formed in the first P well region 52. An N-type source region 1025 is provided at the bottom of the trench 1030. A P-type base region 1045 is provided along the lower side and the bottom of the side wall of the trench 1030 so as to surround the source region 1025. An N-type extended drain region 1022 deeper than the first P well region 52 is provided outside the trench 1030.
[0079]
An N-type drain region 1023 is provided in the substrate surface layer of the extended drain region 1022. Inside the trench 1030, a gate oxide film 1029, a gate electrode 1026, an interlayer insulating film 1031 (a part of a shadow oxide film 68 described later), and source polysilicon 1046 are provided in this order from the outside. The source electrode 1028 penetrates the passivation film 71 to contact the source polysilicon 1046 and is electrically connected to the source region 1025 through the source polysilicon 1046. The drain electrode 1027 passes through the passivation film 71 and the interlayer insulating film 131 and is in contact with the drain region 1023.
[0080]
Since the NMOS 200 and the PMOS 300 are the same as those in the first embodiment, description thereof is omitted. In addition, about the structure similar to Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.
[0081]
A manufacturing process of the semiconductor device shown in FIG. 98 will be described. 99 to 118 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. First, as shown in FIG. 2, phosphorus is applied to the surface layer of the semiconductor substrate 51, for example, at a dose of 0.3 × 10. ¹³ ~ 1.5 × 10 ¹³ cm ^-2 The N well region 54 is selectively formed by ion implantation and diffusion. Subsequently, using the selective oxide film 55 formed on the N well region 54 as a mask, boron is dosed, for example, by 0.5 × 10 5. ¹³ ~ 1.5 × 10 ¹³ cm ^-2 The first P well region 52 and the second P well region 53 are formed by ion implantation and diffusion. Thereafter, as shown in FIG. 3, the selective oxide film 55 is completely removed.
[0082]
Subsequently, a buffer oxide film 56 is formed on the substrate surface. Then, a mask 2001 having a desired pattern is formed thereon, and an N-type impurity such as phosphorus is dosed to the first P well region 52 using the mask 2001, for example, at a dose of 0.4 × 10. ¹³ ~ 1.8 × 10 ¹³ cm ^-2 Then, ions are implanted (FIG. 99). Thereafter, the implanted impurity is diffused to form the extended drain region 1022. After removing the mask 2001, a mask oxide film 57 having a thickness of 1 μm, for example, is stacked on the buffer oxide film 56 (FIG. 100).
[0083]
Next, a mask 58 having an opening in the trench formation region is provided on the mask oxide film 57 (FIG. 101). Using this mask 58, the mask oxide film 57 is patterned, and after removing the mask 58, trench etching is performed by RIE to form, for example, a depth of 2.0 μm and a width of 3.0 μm in the first P well region 52. A trench 1030 is formed. Thereafter, all of the oxide film on the substrate surface including the mask oxide film 57 is removed (FIG. 102).
[0084]
Subsequently, a buffer oxide film 60 is formed on the substrate surface and inside the trench 1030 (FIG. 103), and a silicon nitride film 61 is formed thereon. Further thereon, a mask 62 having an element isolation region opened is provided (FIG. 104). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 105). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 106).
[0085]
After removing the silicon nitride film 61 and performing sacrificial oxidation, a mask 65 is formed having openings above the trench 1030 and above the region that becomes the NMOS channel region. Using this mask 65, boron (B ₁₁ ) And the like, for example, a dose amount of 0.4 × 10 ¹⁴ ~ 1x10 ¹⁴ cm ^-2 The base region 1045 is formed on the bottom surface of the trench of the first P well region 52, and at the same time, the NMOS channel region 233 is formed in the second P well region 53. Then, as shown in FIG. Then, the mask 65 is removed (FIG. 108). In this way, since the channel regions of the TLPM 1100 and the NMOS 200 can be formed simultaneously using one mask 65, the cost per wafer is reduced.
[0086]
Subsequently, a mask 66 having a region that becomes a channel region of the PMOS is formed on the substrate surface, and phosphorus (P ₃₁ ) And the like are ion-implanted (FIG. 109) and diffused to form a PMOS channel region 333 in the N-well region. After the mask 66 and the thin oxide film on the substrate surface and inside the trench are removed, a gate oxide film 1029 having a thickness of, for example, 0.06 to 0.1 μm is formed on the TLPM, and a thickness of 0 and the like are respectively formed on the NMOS and PMOS. Gate oxide films 229 and 329 having a thickness of 0.02 to 0.1 μm are formed. Here, the gate oxide films 1029, 229, and 329 of TLPM, NMOS, and PMOS may be formed simultaneously without using a mask. Then, cost is reduced by simplifying the process. Note that the order of forming the base region 1045 and the channel region 233 and the channel region 333 may be reversed.
[0087]
Subsequently, a polysilicon layer 143 is stacked (FIG. 110), and a mask 67 is formed only on the portion of the polysilicon layer 143 that becomes the gate electrodes of NMOS and PMOS (FIG. 111). Using this mask 67, anisotropic etching of the polysilicon layer 143 is performed by, for example, RIE. Accordingly, the TLPM gate electrode 1026 is formed by self-alignment inside the trench 1030 simultaneously with the formation of the NMOS gate electrode 226 and the PMOS gate electrode 326. Therefore, the cost is reduced by simplifying the process. Then, the mask 67 is removed (FIG. 112).
[0088]
Subsequently, a shadow oxide film 68 is formed to cover the TLPM gate electrode 1026, the NMOS gate electrode 226, and the PMOS gate electrode 326 (FIG. 113). Thereafter, a mask 69 is formed on the substrate surface by opening the source region and drain region of TLPM and the NMOS formation region, and arsenic (As ₇₅ ) And the like are ion-implanted (FIG. 114) and diffused. As a result, a TLPM source region 1025 is formed at the bottom of the trench 1030, a TLPM drain region 1023 is formed outside the trench 1030, and a source region 225 and a drain region 223 are simultaneously formed in the NMOS channel region 233.
[0089]
After the mask 69 is removed, a mask 70 having a PMOS formation region opened is formed on the substrate surface. And boron (B ₁₁ ) And the like are ion-implanted (FIG. 115). After the impurity is diffused to form the source region 325 and the drain region 323 in the PMOS channel region 333, the mask 70 is removed (FIG. 116). Subsequently, an interlayer insulating film 131 is stacked on the entire surface of the substrate, and an inner portion of the interlayer insulating film 131 inside the trench 1030 is etched by self-alignment to open a contact hole. Further, the inside of the trench is filled with source polysilicon 1046 (FIG. 117). Then, a passivation film 71 is formed on the entire surface of the substrate (FIG. 118). Note that the formation of the source region 1025, the drain region 1023, the source region 225, and the drain region 223 may be reversed from the formation of the source region 325 and the drain region 323.
[0090]
Subsequently, the passivation film 71 is patterned to open contact holes. Further, a metal is patterned thereon, a source electrode 1028 that contacts the TLPM source polysilicon 1046, a drain electrode 1027 that contacts the TLPM drain region 1023, a drain electrode 227 that contacts the NMOS drain region 223, and an NMOS source A source electrode 228 in contact with the region 225, a drain electrode 327 in contact with the PMOS drain region 323, and a source electrode 328 in contact with the PMOS source region 325 are formed at the same time. In this manner, a semiconductor device in which the TLPM 1100, the NMOS 200, and the PMOS 300 are integrated on the same semiconductor substrate 51 as shown in FIG. 98 is completed.
[0091]
According to the manufacturing process described above, the diffusion length of impurities in the depth direction from the substrate surface for each of the two P well regions 52 and 53, the N well region 54, the extended drain region 1022 and the base region 1045 is, for example, Devices of 2.3 to 2.6 μm, 3.4 to 4.5 μm, 1.8 to 2.1 μm and 1.1 to 1.2 μm are obtained. In addition, the element withstand voltage is about 30 to 40 V, and the on-resistance is 10 to 20 mΩ · mm. ² TLPM1100 is obtained. Compared with the conventional planar type power MOSFET shown in FIG. 265, the on-resistance is 1/2 to 1/3 with the same element breakdown voltage. In the TLPM 100 of FIG. 98, even when the concentration of the extended drain region 1022 is increased to reduce the on-resistance, the breakdown voltage can be maintained by forming the first P well region 52 deeper than the extended drain region 1022. .
[0092]
The P-type base region 1045 and the substrate 51 may be grounded as follows. First, when the passivation film 71 is patterned to open a contact hole, a contact is opened at a position different from that on TLPM, PMOS, or NMOS, and a P-type plug region is formed in the opening. Thereafter, when patterning the metal, the metal is also left on the P-type plug region to form an electrode. By grounding this electrode, it is possible to prevent the P-type region 1045 from floating in the channel formation region and to prevent the TLPM 1100 from lowering the withstand voltage.
[0093]
Here, after forming the selective oxide film 63 for element isolation, the trench 1030 can also be formed. That is, according to the order shown in FIGS. 2, 3, 99 and 100, N well region 54 and P well regions 52 and 53 are selectively formed on the surface layer of semiconductor substrate 51, and buffer oxide film 56 is formed. The extended drain region 1022 is formed. A silicon nitride film 61 is formed thereon, and a mask 62 having an element isolation region opened is provided thereon (FIG. 119). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 120). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 121). Thereafter, the silicon nitride film 61 is removed (FIG. 122).
[0094]
Again, a silicon nitride film 76 is laminated on the substrate surface, and a mask oxide film 57 is further laminated thereon (FIG. 123). Further thereon, a mask 58 having an opening in the trench formation region is provided (FIG. 124). The mask oxide film 57 is patterned using this mask 58, and after removing the mask 58, trench etching is performed to form a trench 1030 (FIG. 125). Then, the mask oxide film 57 and the silicon nitride film 76 are removed (FIG. 126), and the buffer oxide film 56 on the substrate surface is removed leaving the selective oxide film 63 (FIG. 127). Thereafter, buffer oxidation is performed again, and as shown in FIG. 107, a mask 65 is formed with openings above the trench 1030 and above the region to become the NMOS channel region, and boron (B ₁₁ ) And the like are ion-implanted. The subsequent steps are the same as those shown in FIG.
[0095]
According to the sixth embodiment described above, the gate electrode 1026 of the TLPM 1100, the gate electrode 226 of the NMOS 200, and the gate electrode 326 of the PMOS 300 are formed by patterning the same polysilicon layer 143, and the drain electrode 1027 and the source electrode 1028 of the TLPM 1100 are formed. Since the drain electrode 227 and the source electrode 228 of the NMOS 200 and the drain electrode 327 and the source electrode 328 of the PMOS 300 are formed by patterning the same metal wiring layer, the TLPM 1100 is interposed through this metal wiring layer and the polysilicon layer 143. And the NMOS 200 and the PMOS 300 can be electrically connected to each other. Therefore, since it is not necessary to perform wire bonding to the printed circuit board as in the prior art, it is possible to obtain a one-chip power IC that is small in size, low on-resistance, and low in cost.
[0096]
Further, according to the sixth embodiment, the base region 1045 of the TLPM 1100 and the channel region 233 of the NMOS 200 are formed simultaneously, the gate electrode 1026 of the TLPM 1100, the gate electrode 226 of the NMOS 200, and the gate electrode 326 of the PMOS 300 are formed simultaneously. The drain region 1023 and the source region 1025 of the TLPM 1100, the source region 225 and the drain region 223 of the NMOS 200 are formed at the same time, the drain electrode 1027 and the source electrode 1028 of the TLPM 1100, the drain electrode 227 and the source electrode 228 of the NMOS 200, and the PMOS 300 Since the drain electrode 327 and the source electrode 328 are formed at the same time, an increase in cost due to an increase in manufacturing steps can be suppressed.
[0097]
Embodiment 7 FIG.
FIG. 128 is a longitudinal sectional view showing the configuration of the semiconductor device according to the seventh embodiment of the present invention. As shown in FIG. 128, P well regions 52, 53 and an N well region 54 are formed on the surface layer of a P type semiconductor substrate 51, and a source contact is made at the bottom of the trench in the first P well region 52. (Second type) first TLPM 1101 is formed, NMOS 200 is formed in second P well region 53, and source contact is made at the bottom of the trench in N well region 54 (second type) second. TLPM 1300 is formed. The first TLPM 1101, the NMOS 200, and the second TLPM 1300 are separated from each other by a selective oxide film 63.
[0098]
The first TLPM 1101 is substantially the same as the TLPM 1100 described in the sixth embodiment (see FIG. 98). However, in the TLPM 1100 of the sixth embodiment, the N-type source region 1025 is in the first P well region 52. On the other hand, in the first TLPM 1101 of the seventh embodiment, the N-type source region 1025 extends over the first P-well region 52 and the N-type extended drain region 1022. Other configurations of the first TLPM 1101 are the same as those of the TLPM 1100 described in the sixth embodiment, and thus the same reference numerals are given and description thereof is omitted.
[0099]
The second TLPM 1300 will be described. A trench 1330 is formed in the N well region 54. A P-type source region 1325 is provided at the bottom of the trench 1330. An N-type base region 1345 is provided along the bottom of the trench 1330 so as to surround the source region 1325. A P-type extended drain region 1322 deeper than the N well region 54 is provided outside the trench 1330 in the N well region 54.
[0100]
A P-type drain region 1323 is provided in the substrate surface layer of the extended drain region 1322. Inside the trench 1330, a gate oxide film 1329, a gate electrode 1326, an interlayer insulating film 1331 (a part of a shadow oxide film 68 described later), and a source polysilicon 1346 are provided in this order from the outside. Source electrode 1328 penetrates passivation film 71 to contact source polysilicon 1346 and is electrically connected to source region 1325 through source polysilicon 1346. The drain electrode 1327 passes through the passivation film 71 and the interlayer insulating film 131 and is in contact with the drain region 1323.
[0101]
Since the NMOS 200 is the same as that of the first embodiment, the description thereof is omitted. In addition, about the structure similar to Embodiment 1, the code | symbol same as Embodiment 1 is attached | subjected and description is abbreviate | omitted.
[0102]
A manufacturing process of the semiconductor device shown in FIG. 128 will be described. 129 to 148 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. 128. First, according to the order shown in FIGS. 2, 3 and 99, N well region 54 and P well regions 52 and 53 are selectively formed on the surface layer of semiconductor substrate 51, and buffer oxide film 56 is formed. In the P well region 52, phosphorus (P ₃₁ ) And the like, for example, a dose amount of 0.4 × 10 ¹³ ~ 1.8 × 10 ¹³ cm ^-2 Ion implantation.
[0103]
Subsequently, after removing the mask 2001, a mask 2002 having a desired pattern is formed, and boron (B) is formed in the N well region 54 using the mask 2002. ₁₁ ) And the like, for example, a dose of 0.6 × 10 ¹³ ~ 1.8 × 10 ¹³ cm ^-2 Then, ions are implanted (FIG. 129). Thereafter, the implanted impurity is diffused to form an N-type extended drain region 1022 and a P-type extended drain region 1322. After removing the mask 2002, a mask oxide film 57 having a thickness of 1 μm, for example, is stacked on the buffer oxide film 56 (FIG. 130).
[0104]
Next, a mask 58 having a trench formation region opened is provided on the mask oxide film 57 (FIG. 131). Using this mask 58, the mask oxide film 57 is patterned, and after removing the mask 58, trench etching is performed by RIE to form the trench 1030 in the first P well region 52, and at the same time in the N well region 54. A trench 1330 is formed. Here, in order to distinguish the two trenches, the trench 1030 in the first P well region 52 is referred to as a first trench 1030, and the trench 1330 in the N well region 54 is referred to as a second trench 1330. Thereafter, all the oxide film on the substrate surface including the mask oxide film 57 is removed (FIG. 132).
[0105]
Subsequently, a buffer oxide film 60 is formed on the substrate surface and inside the trenches 1030 and 1330 (FIG. 133), and a silicon nitride film 61 is formed thereon (FIG. 134). Further thereon, a mask 62 having an element isolation region opened is provided (FIG. 135). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 136). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 137).
[0106]
After removing the silicon nitride film 61 and performing sacrificial oxidation, a mask 65 is formed with openings above the first trench 1030 and above the region that becomes the channel region of the NMOS. Using this mask 65, boron (B ₁₁ ) And the like, for example, a dose amount of 0.4 × 10 ¹⁴ ~ 1x10 ¹⁴ cm ^-2 Then, ion implantation is performed (FIG. 138). Subsequently, the mask 65 is removed, and a mask 2003 having an opening above the second trench 1330 is formed. Using this mask 2003, phosphorus (P ₃₁ ) And the like, for example, a dose amount of 0.4 × 10 ¹⁴ ~ 1x10 ¹⁴ cm ^-2 Then, ion implantation is performed (FIG. 139).
[0107]
Thereafter, the implanted impurities are diffused. As a result, a P-type base region 1045 and an N-type base region 1345 are formed on the bottom surface of the first trench 1030 and the bottom surface of the second trench 1330, respectively, and at the same time, an NMOS channel region 233 in the second P-well region 53. Is formed. Then, the mask 2003 is removed (FIG. 140). Note that the order of the process in FIG. 138 and the process in FIG. 139 may be reversed.
[0108]
Next, after removing the thin oxide film on the substrate surface and inside the trenches 1030 and 1330, a first TLPM gate oxide film 1029, an NMOS gate oxide film 229, and a second TLPM gate oxide film 1329 are formed. Here, the first TLPM, the second TLPM, and the NMOS gate oxide films 1029, 1329, and 229 may be simultaneously formed without using a mask. Then, cost is reduced by simplifying the process.
[0109]
Subsequently, a polysilicon layer 143 is stacked (FIG. 141), and a mask 67 is formed only on a portion of the polysilicon layer 143 that becomes an NMOS gate electrode (FIG. 142). Using this mask 67, anisotropic etching of the polysilicon layer 143 is performed by, for example, RIE. Accordingly, the first TLPM gate electrode 1026 and the second TLPM gate electrode 1326 are formed by self-alignment inside the first and second trenches 1030 and 1330 simultaneously with the formation of the NMOS gate electrode 226. . Therefore, the cost is reduced by simplifying the process. Then, the mask 67 is removed (FIG. 143).
[0110]
Subsequently, a shadow oxide film 68 is formed to cover the gate electrodes 1026 and 1326 of the first and second TLPM and the gate electrode 226 of the NMOS (FIG. 144). Thereafter, a mask 69 having an opening in the source region and drain region of the first TLPM and the NMOS formation region is formed on the substrate surface, and arsenic (As ₇₅ ) And the like are ion-implanted (FIG. 145). Subsequently, a mask 2004 in which the source region and the drain region of the second TLPM are opened is formed, and boron (B ₁₁ ) And the like are ion-implanted (FIG. 146). Note that the order of the process in FIG. 145 and the process in FIG. 146 may be reversed.
[0111]
Subsequently, the implanted impurities are diffused. Accordingly, the source region 1025 of the first TLPM at the bottom of the first trench 1030, the drain region 1023 of the first TLPM outside the first trench 1030, and the second TLPM at the bottom of the second trench 1330. A source region 1325, a drain region 1323 of the second TLPM outside the second trench 1330, and a source region 225 and a drain region 223 are simultaneously formed in the channel region 233 of the NMOS. Then, the mask 2004 is removed (FIG. 147).
[0112]
Subsequently, an interlayer insulating film 131 is stacked on the entire surface of the substrate, and the inner portions of the interlayer insulating film 131 inside the first and second trenches 1030 and 1330 are etched by self-alignment to open contact holes. Further, the inside of the first trench 1030 is filled with the source polysilicon 1046, and the inside of the second trench 1330 is filled with the source polysilicon 1346 (FIG. 148). Then, a passivation film 71 is formed on the entire surface of the substrate and patterned to open a contact hole.
[0113]
Further, a metal is patterned thereon to form a source electrode 1028 that contacts the source polysilicon 1046 of the first TLPM, a drain electrode 1027 that contacts the drain region 1023 of the first TLPM, and a source polysilicon 1346 of the second TLPM. A source electrode 1328 that contacts the drain region 1323, a drain electrode 1327 that contacts the drain region 1323 of the second TLPM, a drain electrode 227 that contacts the drain region 223 of the NMOS, and a source electrode 228 that contacts the source region 225 of the NMOS. . In this manner, a semiconductor device in which the first TLPM 1101, the NMOS 200, and the second TLPM 1300 are integrated on the same semiconductor substrate 51 as shown in FIG. 128 is completed.
[0114]
According to the manufacturing process described above, the two P-well regions 52 and 53, the N-well region 54, the N-type extended drain region 1022, the P-type extended drain region 1322, the P-type base region 1045, and the N-type base region 1345 The diffusion length of impurities in the depth direction from the surface is, for example, 2.3 to 2.6 μm, 3.4 to 4.5 μm, 1.8 to 2.1 μm, 2.3 to 2.6 μm, 1 Devices of 1-1.2 μm and 1.0-1.1 μm are obtained. In addition, the element withstand voltage is about 30 to 40 V, and the on-resistance is 10 to 20 mΩ · mm. ² The first TLPM 1101 is obtained. In addition, the device withstand voltage is about 30 to 40 V, and the on-resistance is 20 to 30 mΩ · mm. ² The second TLPM 1300 is obtained. Compared with the conventional planar type power MOSFET shown in FIG. 265, the on-resistance is 1/2 to 1/3 with the same element breakdown voltage. In the TLPM 101 of FIG. 128, even when the concentration of the extended drain region 1002 is increased to reduce the on-resistance, the breakdown voltage can be maintained by forming the first P well region 52 deeper than the extended drain region 1022. .
[0115]
In order to ground the P-type base region 1045 of the TLPM 1101, the substrate 51, and the N-type base region 1345 of the TLPM 1300, the following may be performed. First, the well regions 52 and 54 are formed deeper than the extended drain regions 1022 and 1322, respectively, and are connected to the P-type base region 1045 and the N-type base region 1345, respectively. Then, when the contact hole is opened by patterning the passivation film 71, an opening is also formed on the well regions 52 and 54 to form a P-type plug region and an N-type plug region, respectively. Thereafter, when patterning the metal, the metal is also left on the P-type plug region and the N-type plug region to form electrodes. By grounding these electrodes, floating of the P-type base region 1045 and the N-type base region 1345 in the channel formation region can be prevented, and a decrease in breakdown voltage of the TLPMs 1101 and 1300 can be prevented.
[0116]
According to the seventh embodiment described above, a one-chip power IC that is small in size, low on-resistance, and low in cost can be obtained while suppressing an increase in cost due to an increase in manufacturing steps. Further, since the p-channel TLPM and the n-channel TLPM can be integrated on the same semiconductor substrate, the degree of integration is greatly improved, and a power IC in which a conventional p-channel planar power MOSFET and an n-channel planar power MOSFET are integrated. As compared with the above, the area of the power MOSFET portion can be reduced to about 40%.
[0117]
Embodiment 8 FIG.
FIG. 149 is a longitudinal sectional view showing the configuration of the semiconductor device according to the eighth embodiment of the present invention. As shown in FIG. 149, the semiconductor device according to the eighth embodiment is obtained by integrating the PMOS 300 of the semiconductor device according to the first embodiment in the semiconductor device according to the seventh embodiment. That is, the first P well region 52, the first N well region 54, the second P well region 53, and the second N well region 85 are formed in this order on the surface layer of the P type semiconductor substrate 51. . Then, a first TLPM 1101 of a type (second type) that makes a source contact at the bottom of the trench is formed in the first P well region 52, and a source contact is made at the bottom of the trench in the first N well region 54. A second TLPM 1300 of the type (second type) is formed.
[0118]
Further, the NMOS 200 is formed in the second P well region 53, and the PMOS 300 is formed in the second N well region 85. The first TLPM 1101, the second TLPM 1300, the NMOS 200, and the PMOS 300 are separated from each other by a selective oxide film 63. The configurations of the first TLPM 1101 and the second TLPM 1300 have already been described in the seventh embodiment, and the configurations of the NMOS 200 and the PMOS 300 have been described in the first embodiment, and thus description thereof is omitted here. To do.
[0119]
A manufacturing process of the semiconductor device illustrated in FIG. 149 will be described. 150 to 173 are longitudinal sectional views of the semiconductor device shown in FIG. First, the first N well region 54 and the second N well region 85 are selectively formed on the surface layer of the semiconductor substrate 51, and the selective oxide film 55 formed on the N well regions 54 and 85 is used as a mask. First P well region 52 and second P well region 53 are formed (FIG. 150). Thereafter, the selective oxide film 55 is completely removed (FIG. 151).
[0120]
Next, a buffer oxide film 56 is formed on the substrate surface. Then, a mask 2001 having a desired pattern is formed thereon, and phosphorus (P) is formed in the first P well region 52 using the mask 2001. ₃₁ ) And the like are ion-implanted (FIG. 152). Subsequently, after removing the mask 2001, a mask 2002 having a desired pattern is formed, and boron (B) is formed in the first N well region 54 using the mask 2002. ₁₁ ) And the like are ion-implanted (FIG. 153). Thereafter, the implanted impurity is diffused to form an N-type extended drain region 1022 and a P-type extended drain region 1322. After removing the mask 2002, a mask oxide film 57 is stacked on the buffer oxide film 56 (FIG. 154).
[0121]
Next, a mask 58 having a trench formation region opened is provided on the mask oxide film 57 (FIG. 155). The mask oxide film 57 is patterned using this mask 58, and after removing the mask 58, trench etching is performed by RIE to form the first trench 1030 in the first P well region 52, and at the same time, the first A second trench 1330 is formed in the N well region 54. Thereafter, all oxide films on the substrate surface including the mask oxide film 57 are removed (FIG. 156).
[0122]
Subsequently, a buffer oxide film 60 is formed on the substrate surface and inside the trenches 1030 and 1330 (FIG. 157), and a silicon nitride film 61 is formed thereon (FIG. 158). Further thereon, a mask 62 having an element isolation region opened is provided (FIG. 159). The silicon nitride film 61 is patterned using the mask 62, and the mask 62 is removed (FIG. 160). Thermal oxidation is performed using the silicon nitride film 61 remaining on the substrate surface as a mask to form a selective oxide film 63 for element isolation (FIG. 161).
[0123]
After removing the silicon nitride film 61 and performing sacrificial oxidation, a mask 65 is formed with openings above the first trench 1030 and above the region that becomes the channel region of the NMOS. Using this mask 65, boron (B ₁₁ ) Or the like is ion-implanted (FIG. 162). Then, the implanted impurity is diffused to form a P-type base region 1045 on the bottom surface of the first trench 1030, and an NMOS channel region 233 is formed in the second P-well region 53, and the mask 65 is removed. (FIG. 163).
[0124]
Next, a mask 2005 is formed with openings above the second trench 1330 and above the region to be the PMOS channel region. Using this mask 2005, phosphorus (P ₃₁ ) Or the like is ion-implanted (FIG. 164). Thereafter, the implanted impurities are diffused to form an N-type base region 1345 on the bottom surface of the second trench 1330, and a PMOS channel region 333 is formed in the second N-well region 85.
[0125]
After removing the mask 2005 and removing the thin oxide film on the substrate surface and inside the trenches 1030 and 1330, the first TLPM gate oxide film 1029, the second TLPM gate oxide film 1329, the NMOS gate oxide film 229, and A PMOS gate oxide film 329 is formed. (FIG. 165). Here, the first TLPM, the second TLPM, the NMOS and the PMOS gate oxide films 1029, 1329, 229, and 329 may be formed simultaneously without using a mask. Then, cost is reduced by simplifying the process. Note that the order of the steps in FIGS. 162 and 163 and the steps in FIGS. 164 and 165 may be reversed.
[0126]
Next, a polysilicon layer 143 is stacked on the gate oxide films 1029, 1329, 229, and 329, and a mask 67 is formed only on portions of the polysilicon layer 143 that serve as NMOS and PMOS gate electrodes. (FIG. 166). Using this mask 67, anisotropic etching of the polysilicon layer 143 is performed by, for example, RIE. Thereby, the gate electrode 1026 of the first TLPM and the gate electrode of the second TLPM are formed by self-alignment inside the first and second trenches 1030 and 1330 simultaneously with the formation of the gate electrodes 226 and 326 of the NMOS and PMOS. 1326 is formed. Therefore, the cost is reduced by simplifying the process. Then, the mask 67 is removed (FIG. 167).
[0127]
Subsequently, a shadow oxide film 68 is formed to cover the gate electrodes 1026 and 1326 of the first and second TLPM and the gate electrodes 226 and 326 of the NMOS and PMOS (FIG. 168). Thereafter, a mask 69 having an opening in the source region and drain region of the first TLPM and the NMOS formation region is formed on the substrate surface, and arsenic (As ₇₅ ) Or the like is ion-implanted (FIG. 169). Thereafter, the implanted impurities are diffused, and the first TLPM source region 1025 is formed at the bottom of the first trench 1030, the first TLPM drain region 1023 is formed outside the first trench 1030, and the NMOS channel region 233. A source region 225 and a drain region 223 are simultaneously formed.
[0128]
Next, a mask 2006 in which the source region and the drain region of the second TLPM and the PMOS formation region are opened is formed, and boron (B ₁₁ ) Or the like is ion-implanted (FIG. 170). Thereafter, the implanted impurities are diffused, and the second TLPM source region 1325 is formed at the bottom of the second trench 1330, the second TLPM drain region 1323 is formed outside the second trench 1330, and the PMOS channel region 333. A source region 325 and a drain region 323 are formed simultaneously. Then, the mask 2006 is removed (FIG. 171). Note that the order of the process in FIG. 169 and the process in FIG. 170 may be reversed.
[0129]
Subsequently, an interlayer insulating film 131 is stacked on the entire surface of the substrate, and the inner portions of the interlayer insulating film 131 inside the first and second trenches 1030 and 1330 are etched by self-alignment to open contact holes. Further, the inside of the first trench 1030 is filled with the source polysilicon 1046, and the inside of the second trench 1330 is filled with the source polysilicon 1346 (FIG. 172). Then, a passivation film 71 is formed on the entire surface of the substrate (FIG. 173). Further, contact holes are opened in the passivation film 71 and the interlayer insulating film 131.
[0130]
Then, a metal is patterned thereon to form a source electrode 1028 in contact with the first TLPM source polysilicon 1046, a drain electrode 1027 in contact with the first TLPM drain region 1023, and a second TLPM source polysilicon. Source electrode 1328 in contact with 1346, drain electrode 1327 in contact with drain region 1323 of the second TLPM, drain electrode 227 in contact with NMOS drain region 223, source electrode 228 in contact with NMOS source region 225, drain of PMOS A drain electrode 327 in contact with the region 323 and a source electrode 328 in contact with the PMOS source region 325 are simultaneously formed. In this manner, a semiconductor device in which the first TLPM 1101, the second TLPM 1300, the NMOS 200, and the PMOS 300 are integrated on the same semiconductor substrate 51 as shown in FIG. 149 is completed.
[0131]
According to the above-described eighth embodiment, it is possible to obtain a one-chip power IC that is small in size, low in on-resistance, and low in cost while suppressing an increase in cost due to an increase in manufacturing steps. Further, a p-channel TLPM and an n-channel TLPM can be integrated on the same semiconductor substrate, and a power IC chip in which a power MOSFET made of these TLPM and a control circuit using planar type PMOS and NMOS are integrated. Then, the size can be reduced to about half the area of the conventional power IC chip.
[0132]
Embodiment 9 FIG.
FIG. 174 is a longitudinal sectional view showing the configuration of the semiconductor device according to the ninth embodiment of the present invention. As shown in FIG. 174, in the semiconductor device of the ninth embodiment, a P-type body region 1024 is added to the TLPM 1100 instead of the TLPM 1100 in the first P well region 52 in the sixth embodiment shown in FIG. A TLPM 1102 having a configuration is formed. The body region 1024 is provided so as to surround the P-type base region 1045 along the bottom surface of the trench 1030 of the TLPM 1102. Since other configurations are the same as those of the sixth embodiment, the same configurations as those of the sixth embodiment are denoted by the same reference numerals and description thereof is omitted.
[0133]
A manufacturing process of the semiconductor device illustrated in FIG. 174 will be described. 175 to 177 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. 174. First, as shown in FIGS. 2 and 3, an N well region 54, a first P well region 52, and a second P well region 53 are formed in the surface layer of the semiconductor substrate 51. Next, as shown in FIGS. 99 and 100, an extended drain region 1022 is formed. Thereafter, as shown in FIG. 101, a mask 58 having a trench formation region opened is provided on the mask oxide film 57.
[0134]
The mask oxide film 57 is patterned using the mask 58, and after removing the mask 58, trench etching is performed by RIE to form a trench 1030 in the first P well region 52. Thereafter, a buffer oxide film 59 is formed inside the trench 1030 (FIG. 175). Subsequently, boron (B ₁₁ ) Or the like is ion-implanted (FIG. 176). The implanted impurity is diffused to form a body region 1024 at the bottom of the trench (FIG. 177). The subsequent steps are the same as those shown in FIG. In this manner, a semiconductor device in which the TLPM 1102, the NMOS 200, and the PMOS 300 having the P-type body region 1024 are integrated on the same semiconductor substrate 51 as shown in FIG. 174 is completed.
[0135]
Here, when the trench 1030 is formed after the selective oxide film 63 for element isolation is formed, the following may be performed. That is, N well region 54, first P well region 52, and second P well region 53 are formed in the surface layer of semiconductor substrate 51 in the order shown in FIGS. An extended drain region 1022 is formed.
[0136]
Subsequently, in the order shown in FIGS. 119 to 125, a selective oxide film 63 for element isolation is formed, and a trench 1030 is formed. Next, the inside of the trench 1030 is sacrificial oxidized, and boron (B ₁₁ ) Or the like is ion-implanted (FIG. 178). The implanted impurity is diffused to form a body region 1024 at the bottom of the trench (FIG. 179). Then, the mask oxide film 57, the silicon nitride film 76, and the sacrificial oxide film inside the trench are removed (FIG. 180). The subsequent steps are the same as those shown in FIG.
[0137]
According to the ninth embodiment described above, it is possible to obtain a one-chip power IC that is small in size, low in on-resistance, and low in cost while suppressing an increase in cost due to an increase in manufacturing steps. In the sixth embodiment, the extended drain region 1022 having a relatively deep diffusion is formed deeper than the P base region 1045 and is connected under the trench 1030, so that the substrate 51 and the P base region 1045 are not separated. When the substrate 51 and the P base region 1045 are separated by the extended drain region 1022, the potential of the substrate 51 is in a floating state, and there is a possibility that a potential difference is generated between the P base region 1045 and the substrate 51. In a state where a potential difference has occurred, there is a possibility that the P base region is depleted and punch-through occurs at the time of OFF. Further, a parasitic PNP bipolar transistor composed of the P base region 1045, the extended drain region 1022 and the substrate 51 or a parasitic thyristor composed of the drain region, the P base region, the extended drain region and the substrate 51 is formed, and these parasitic elements are latched up. there's a possibility that. However, by forming the body region 1024, it is possible to prevent the substrate 51 and the P base region 1045 from being separated and the extended drain region 1022 from being connected under the trench, thereby preventing punch-through and formation of parasitic elements. The TLPM 1102 having a high breakdown voltage and a low on-resistance can be obtained.
[0138]
Embodiment 10 FIG.
FIG. 181 is a longitudinal sectional view showing the configuration of the semiconductor device according to the tenth embodiment of the present invention. As shown in FIG. 181, in the semiconductor device of the tenth embodiment, in the seventh embodiment shown in FIG. 128, a P-type body region 1024 is added to the TLPM 1101 instead of the TLPM 1101 in the first P well region 52. A TLPM 1103 having a configuration is formed, and a TLPM 1301 having a configuration in which an N-type body region 1324 is added to the TLPM 1300 instead of the TLPM 1300 is formed in the N well region 54.
[0139]
The P-type body region 1024 is provided so as to surround the P-type base region 1045 along the bottom surface of the trench 1030 of the TLPM 1103. The N-type body region 1324 is provided so as to surround the N-type base region 1345 along the bottom surface of the trench 1330 of the TLPM 1301. Since other configurations are the same as those of the seventh embodiment, the same configurations as those of the seventh embodiment are denoted by the same reference numerals and description thereof is omitted.
[0140]
A manufacturing process of the semiconductor device illustrated in FIG. 181 will be described. 182 to 186 are longitudinal sectional views of the semiconductor device shown in FIG. First, as shown in FIGS. 2 and 3, an N well region 54, a first P well region 52, and a second P well region 53 are formed in the surface layer of the semiconductor substrate 51. Next, as shown in FIGS. 99 and 129 to 131, an N-type extended drain region 1022 and a P-type extended drain region 1322 are formed, a mask oxide film 57 is laminated, and a trench formation region is opened thereon. The masks 58 are stacked.
[0141]
The mask oxide film 57 is patterned using the mask 58, and after removing the mask 58, trench etching is performed by RIE to form a first trench 1030 and a second trench 1330. Thereafter, a buffer oxide film 2007 is formed inside the first and second trenches 1030 and 1330 (FIG. 182). Subsequently, the second trench 1330 is covered with a mask 2008, and boron (B ₁₁ ) And the like are ion-implanted (FIG. 183). After the mask 2008 is removed, the first trench 1030 is covered with the mask 2009, and phosphorus (P ₃₁ ) And the like are ion-implanted (FIG. 184). Note that the order of the process in FIG. 183 and the process in FIG. 184 may be reversed.
[0142]
After removing the mask 2009, the implanted impurity is diffused to form a P-type body region 1024 and an N-type body region 1324 simultaneously (FIG. 185). Then, all the oxide film on the substrate surface including the mask oxide film 57 is removed (FIG. 186). The subsequent steps are the same as those shown in FIG. In this way, a semiconductor device in which the TLPM 1103 having the P-type body region 1024, the TLPM 1301 having the N-type body region 1324, and the NMOS 200 are integrated on the same semiconductor substrate 51 as shown in FIG.
[0143]
Here, as shown in FIG. 187, in the semiconductor device of the eighth embodiment (FIG. 149), instead of the first TLPM 1101, the TLPM 1103 having the P-type body region 1024 is formed, and instead of the second TLPM 1300. In addition, the TLPM 1301 having the N-type body region 1324 may be formed.
[0144]
According to the above-described tenth embodiment, not only can a one-chip power IC that is small in size, low in on-resistance, and low in cost can be obtained while suppressing an increase in cost due to an increase in manufacturing processes, and the following effects can be obtained. Is obtained. That is, the dose amount of the N-type extended drain region 1022 is 2 × 10, for example. ¹³ cm ^-2 When it becomes high enough, the diffusion length of the N-type extended drain region 1022 becomes larger than the sum of the depth of the first trench 1030 and the diffusion length of the P-type base region 1045, and the breakdown voltage is lowered and latch-up occurs due to punch-through. . Similarly, the dose amount of the P-type extended drain region 1322 is, for example, 2 × 10 ¹³ cm ^-2 When it becomes high enough, the diffusion length of the P-type extended drain region 1322 becomes larger than the sum of the depth of the second trench 1330 and the diffusion length of the N-type base region 1345, resulting in a decrease in breakdown voltage due to punch-through and latch-up. .
[0145]
For such inconvenience, by providing the P-type body region 1024 and the N-type body region 1324 as in the tenth embodiment, the N-type extended drain regions 1022 are connected to each other directly below the first trench 1030. Since this can prevent the P-type extended drain regions 1322 from being connected directly below the second trench 1330, it is possible to prevent punch-through and latch-up.
[0146]
As shown in FIG. 188, the TLPM 1103 having the P-type body region 1024 is formed in the first P-well region 52 instead of the first TLPM 1101, and the N-type body region is formed in the N-well region 54. A configuration in which the second TLPM 1300 without a gap is formed may be employed. As shown in FIG. 189, the first TLPM 1101 having no P-type body region is formed in the first P-well region 52, and the N-type region is formed in the N-well region 54 instead of the second TLPM 1300. The TLPM 1301 having the body region 1324 may be formed. In any configuration, punch-through and latch-up can be prevented.
[0147]
Embodiment 11 FIG.
FIG. 190 is a longitudinal sectional view showing the configuration of the semiconductor device according to the eleventh embodiment of the present invention. As shown in FIG. 190, in the semiconductor device of the eleventh embodiment, TLPM 1104 is formed in first P well region 75 having a substantially constant depth including the lower portion of trench 1030, and the first P N-type extended drain regions 1122 are formed on both sides of the trench 1030 in the well region 75 so as to surround the N-type drain region 1023. Other configurations of the TLPM 1104 are the same as those of the TLPM 1100 of the semiconductor device illustrated in FIG. In addition, about the structure similar to Embodiment 6, the same code | symbol is attached | subjected and description is abbreviate | omitted.
[0148]
A manufacturing process of the semiconductor device shown in FIG. 190 will be described. 191 to 195 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. First, in accordance with the order shown in FIGS. 37 to 43, the N well region 54 is formed in the surface layer of the semiconductor substrate 51, the trench 1030 is formed, and the first P well region 75 and the second P well region 53 are formed. At the same time, the oxide film inside the trench and on the substrate surface is removed.
[0149]
Next, after performing buffer oxidation, a mask 2010 is formed in which the outer region of the trench 1030 in the first P well region 75 is opened, and phosphorus (P ₃₁ ) And the like are ion-implanted (FIG. 191). At this time, as shown in FIG. 191, the mask 2010 is also covered in the trench 1030 in order to prevent the diffusion of N-type impurities at the bottom of the trench and prevent punch-through, and to prevent the parasitic element from being latched up. It is. In addition, by doing so, it is possible to achieve high breakdown voltage and low on-resistance for the extended drain region 1122 having a relatively dense N-type impurity dose.
[0150]
After removing the mask 2010, the implanted impurity is diffused to form an N-type extended drain region 1122 outside the sidewall of the trench 1030 (FIG. 192). Next, the oxide film inside the trench and the substrate surface is removed (FIG. 193), and then the buffer oxide film 60 is formed again on the substrate surface and inside the trench 1030 (FIG. 194). A silicon nitride film 61 is formed thereon, and a mask 62 having an element isolation region opened is provided thereon (FIG. 195). The subsequent steps are the same as those shown in FIG. In this way, the semiconductor device having the configuration shown in FIG. 190 is completed.
[0151]
It should be noted that the eleventh embodiment can be applied to the semiconductor device of the seventh embodiment (FIG. 128). That is, as shown in FIG. 196, instead of the TLPM 1101 of the seventh embodiment, the TLPM 1104 is formed in the first P well region 75 having a substantially constant depth including the lower portion of the trench 1030, and the first P An N-type extended drain region 1122 may be formed on both sides of the trench 1030 in the well region 75 so as to surround the N-type drain region 1023. Furthermore, the eleventh embodiment can be applied to the semiconductor device of the eighth embodiment (FIG. 149).
[0152]
According to the eleventh embodiment described above, a one-chip power IC that is small in size, low on-resistance, and low in cost can be obtained while suppressing an increase in cost due to an increase in manufacturing steps. Further, since the first P well region 75 is formed after the trench 1030 is formed, the diffusion length of the P well region 75 can be increased by the depth of the trench, and the ion is formed outside the trench 1030. Since the N-type extended drain region 1122 is formed by implantation, the diffusion length of the N-type extended drain region 1122 can be reduced. Therefore, there is an effect that punch-through and latch-up can be prevented without providing a P-type body region.
[0153]
Embodiment 12 FIG.
In the twelfth embodiment, in the semiconductor device of the sixth embodiment, a TLPM 1105 having a barrier metal layer is provided inside the trench 1030 instead of the TLPM 1100. The base region 1045 is grounded through the P-type plug region. In addition, about the same structure as Embodiment 6, the same code | symbol is attached | subjected and description is abbreviate | omitted.
[0154]
FIG. 197 is a planar layout diagram of the impurity profile of the semiconductor device according to Embodiment 12 of the present invention. As shown in FIG. 197, in the planar layout of the impurity profile, the source region 225, the gate electrode 226, and the drain region 223 of the NMOS 200 are arranged in this order adjacent to the selective oxide film 63 at the left end. Next to the drain region 223, the source region 325, the gate electrode 326, and the drain region 323 of the PMOS 300 are arranged in this order via the selective oxide film 63.
[0155]
Further, the first P well region 52 is arranged next to the drain region 323 via the selective oxide film 63, and next to the extended drain region 1022, the drain region 1023, the trench 1030, the drain region 1023, and the extended drain region of the TLPM 1105. 1022 are arranged in this order. In a part of the region of the trench 1030, a P-type plug region 1051 is formed between the gate electrode 1026 and the gate electrode 1026. In the remaining region of the trench 1030, a source region 1025 is formed between the gate electrode 1026 and the gate electrode 1026.
[0156]
A manufacturing process of the semiconductor device according to the twelfth embodiment will be described with reference to FIGS. 198 to 202. FIG. 201 is a longitudinal sectional view in the middle of manufacturing at AA ′ of FIG. 197, and FIGS. 200 and 202 are longitudinal sectional views in the middle of manufacture at BB ′ in FIG. 197. In FIG. 197, AA ′ passes through the source region 1025, and BB ′ passes through the plug region 1051. First, according to the order shown in FIGS. 2, 3, and 99 to 113, the N well region 54, the first P well region 52, the second P well region 53, the extended drain region 1022, the trench 1030, and the selective oxide film 63, base region 1045, NMOS channel region 233, PMOS channel region 333, gate oxide films 1029, 229 and 329, gate electrodes 1026, 226 and 326, and shadow oxide film 68 are formed.
[0157]
Thereafter, in a region corresponding to AA ′ in FIG. 197, as shown in FIG. 114, a mask 69 in which a source region and a drain region of TLPM and an NMOS formation region are opened is formed on the substrate surface. At this time, in the region corresponding to BB ′ in FIG. 197, as shown in FIG. 198, not only the PMOS formation region but also the source region of TLPM, that is, the inside of the trench 1030 is covered with the mask 69. And arsenic (As ₇₅ N-type impurities such as) are ion-implanted.
[0158]
Subsequently, the implanted impurities are diffused. As a result, in a region corresponding to AA ′ in FIG. 197, as shown in FIG. A source region 225 and a drain region 223 are simultaneously formed therein. In the region corresponding to BB ′ in FIG. 197, as shown in FIG. 199, the drain region 1023 of TLPM and the source region 225 and the drain region 223 are simultaneously formed in the channel region 233 of NMOS as shown in FIG. Is done.
[0159]
After removing the mask 69, in a region corresponding to AA ′ in FIG. 197, a mask 70 having a PMOS formation region opened is formed on the substrate surface as shown in FIG. At this time, in the region corresponding to BB ′ in FIG. 197, as shown in FIG. 199, the mask 70 has a pattern in which not only the PMOS formation region but also the inside of the trench 1030 is opened. And boron (B ₁₁ ) And the like are ion-implanted.
[0160]
Subsequently, the implanted impurities are diffused. As a result, in a region corresponding to AA ′ in FIG. 197, a source region 325 and a drain region 323 are formed in the PMOS channel region 333 as shown in FIG. Further, in a region corresponding to BB ′ in FIG. 197, as shown in FIG. Is done. Strictly speaking, the plane layout diagram of FIG. 197 shows the layout in the state shown in FIGS.
[0161]
After removing the mask 70, an interlayer insulating film 131 is laminated on the entire surface of the substrate, and the inner portion of the trench 1030 of the interlayer insulating film 131 is etched by self-alignment to open a contact hole. In the region corresponding to AA ′ in FIG. 197, as shown in FIG. 201, a barrier metal layer 86 is formed inside the trench 1030 so as to be in contact with the source region 1025 at the bottom of the trench, and the inside thereof is formed. Fill with source polysilicon 1046. At this time, in the region corresponding to BB ′ in FIG. 197, as shown in FIG. 202, the barrier metal layer 86 is in contact with the plug region 1051 at the bottom of the trench. The barrier metal layer 86 is insulated from the gate electrode 1026 by an insulating film.
[0162]
Next, as shown in FIG. 118, a passivation film 71 is formed on the entire surface of the substrate, contact holes are opened in the passivation film 71 and the interlayer insulating film 131, and metal is patterned to form a source electrode and a drain electrode.
[0163]
According to the above-described twelfth embodiment, not only can a one-chip power IC with a small size, a low on-resistance, and a low cost be suppressed while suppressing an increase in cost due to an increase in the manufacturing process, and the following effects can be obtained. Is obtained. That is, the source polysilicon 1046 is P-type or N-type having a high impurity concentration. However, in the case of the N-type, the N-type source polysilicon 1046 and the P-type plug region 1051 can be obtained without the barrier metal layer 86. As a result, a pn diode structure is formed and no ohmic contact is formed. Similarly, when the source polysilicon 1046 is P-type and there is no barrier metal layer 86, a pn diode structure is formed by contact between the P-type source polysilicon 1046 and the N-type source region 1025, resulting in an ohmic contact. Not.
[0164]
For such inconvenience, the barrier metal layer 86 is provided as in the twelfth embodiment, so that the source polysilicon 1046 is P-type regardless of whether the source polysilicon 1046 is N-type or P-type. Both plug region 1051 and N-type source region 1025 are electrically connected with low resistance. In this way, by grounding the source and the substrate, it is possible to prevent floating in the P-type base region 1045 serving as a channel and to prevent a decrease in breakdown voltage of the TLPM 1105.
[0165]
Embodiment 13 FIG.
FIG. 203 is a longitudinal sectional view showing the structure of the semiconductor device according to the thirteenth embodiment of the present invention. As shown in FIG. 203, in the thirteenth embodiment, in the semiconductor device of the seventh embodiment, a TLPM 1106 having a barrier metal layer 86 is provided inside the trench 1030 instead of the first TLPM 1101, and the first TLPM 1101 is provided. Instead of the second TLPM 1300, a TLPM 1302 having a barrier metal layer 87 is provided inside the trench 1330. In addition, about the same structure as Embodiment 7, it attaches the same code | symbol and abbreviate | omits description.
[0166]
A manufacturing process of the semiconductor device shown in FIG. 203 will be described. 204 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. First, according to the order shown in FIGS. 2, 3, 99 and 129 to 147, the N well region 54, the P well regions 52 and 53, the N type extended drain region 1022, the P type extended drain region 1322, the first Trench 1030, second trench 1330, selective oxide film 63, P-type base region 1045, N-type base region 1345, NMOS 200 channel region 233, gate oxide films 1029, 229 and 1329, gate electrodes 226, 1026 and 1326, An N-type source region 1025 and an N-type drain region 1023 of the first TLPM 1106, a P-type source region 1325 and a P-type drain region 1323 of the second TLPM 1302, and a source region 225 and a drain region 223 of the NMOS 200 are formed.
[0167]
Thereafter, an interlayer insulating film 131 is stacked on the entire surface of the substrate, and the inner portion of the first trench 1030 and the inner portion of the second trench 1330 of the interlayer insulating film 131 are etched by self-alignment to open a contact hole. . Then, a barrier metal layer 86 is formed inside the first trench 1030 so as to be in contact with the N-type source region 1025 at the bottom of the trench. Further, a barrier metal layer 87 is formed inside the second trench 1330 so as to be in contact with the P-type source region 1325 at the bottom of the trench. Then, the inside of the barrier metal layer 86 in the first trench 1030 and the inside of the barrier metal layer 87 in the second trench 1330 are filled with polysilicon, and the source polysilicon 1046 and the second TLPM 1302 of the first TLPM 1106 are filled. The source polysilicon 1346 is simultaneously formed (FIG. 204). The barrier metal layers 86 and 87 are insulated from the gate electrodes 1026 and 1326 by an insulating film.
[0168]
Next, a passivation film 71 is formed on the entire surface of the substrate, and contact holes are opened in the passivation film 71 and the interlayer insulating film 131. Then, by patterning the metal to form the source electrode and the drain electrode, the semiconductor device having the configuration shown in FIG. 203 is completed.
[0169]
205, in the semiconductor device of the eighth embodiment (FIG. 149), instead of the first TLPM 1101, the TLPM 1106 having the barrier metal layer 86 is formed inside the trench 1030, and the first TLPM 1101 is formed. Instead of the second TLPM 1300, the TLPM 1302 having the barrier metal layer 87 inside the trench 1330 may be formed.
[0170]
According to the above-described thirteenth embodiment, not only is a one-chip power IC that is small in size, low in on-resistance, and low in cost reduced while suppressing an increase in cost due to an increase in manufacturing processes, the following effects can be obtained. Is obtained. That is, the source polysilicons 1046 and 1346 are P-type or N-type with a high impurity concentration. However, in the case of the N-type, the N-type source polysilicon 1346 and the P-type source region are present without the barrier metal layer 87. The contact with 1325 forms a pn diode structure and does not become ohmic contact. Similarly, when the source polysilicons 1046 and 1346 are P-type, if there is no barrier metal layer 86, a pn diode structure is formed by the contact between the P-type source polysilicon 1046 and the N-type source region 1025. There is no ohmic contact.
[0171]
For such inconvenience, by providing the barrier metal layers 86 and 87 as in the thirteenth embodiment, the source polysilicon 1046 is formed regardless of whether the source polysilicon 1046 and 1346 is N-type or P-type. , 1346 are electrically connected to both the N-type source region 1025 and the P-type source region 1325 with low resistance. Further, since the number of masks is reduced as compared with the case where the source polysilicons 1046 and 1346 are formed separately, the cost is reduced.
[0172]
Embodiment 14 FIG.
In the fourteenth embodiment, in the semiconductor device of the seventh embodiment, a TLPM 1106 having a barrier metal layer 86 is provided inside the trench 1030 instead of the first TLPM 1101, and instead of the second TLPM 1300, A TLPM 1302 having a barrier metal layer 87 is provided inside the trench 1330. The P-type base region 1045 and the N-type base region 1345 are grounded through the P-type plug region and the N-type plug region, respectively. In addition, about the same structure as Embodiment 7, it attaches the same code | symbol and abbreviate | omits description.
[0173]
FIG. 206 is a planar layout diagram of the impurity profile of the semiconductor device according to Embodiment 14 of the present invention. As shown in FIG. 206, in the planar layout of the impurity profile, the source region 225, the gate electrode 226, and the drain region 223 of the NMOS 200 are arranged in this order adjacent to the selective oxide film 63 at the left end. An N well region 54 is arranged next to the drain region 223 with a selective oxide film 63 interposed therebetween, and a drain region 1323, a trench 1330, a drain region 1323, and an N well region 54 of the second TLPM 1302 are arranged next to the N well region 54 in this order. . In a part of the region of the trench 1330, an N-type plug region 1351 is formed between the gate electrode 1326 and the gate electrode 1326. In the remaining region of the trench 1330, a source region 1325 is formed between the gate electrode 1326 and the gate electrode 1326.
[0174]
Further, the first P well region 52 is arranged next to the N well region 54 through the selective oxide film 63, and next to the extended drain region 1022, the drain region 1023, the trench 1030, the drain region 1023 and the first TLPM 1106. Extended drain regions 1022 are arranged in this order. In a part of the region of the trench 1030, a P-type plug region 1051 is formed between the gate electrode 1026 and the gate electrode 1026. In the remaining region of the trench 1030, a source region 1025 is formed between the gate electrode 1026 and the gate electrode 1026.
[0175]
206 passes through the source regions 1025 and 1325, and the vertical cross-sectional configuration of the semiconductor device at CC ′ is as shown in FIG. That is, in the first TLPM 1106, the source polysilicon 1046 is electrically connected to the N-type source region 1025 through the barrier metal layer 86 in the trench 1030 with a low resistance. Similarly, in the second TLPM 1302, the source polysilicon 1346 is electrically connected to the P-type source region 1325 through the barrier metal layer 87 in the trench 1330 with a low resistance.
[0176]
In addition, DD ′ in FIG. 206 passes through the plug regions 1051 and 1351, and the vertical cross-sectional configuration of the semiconductor device at DD ′ is as shown in FIG. That is, in the first TLPM 1106, the source polysilicon 1046 is electrically connected to the P-type plug region 1051 through the barrier metal layer 86 in the trench 1030 with a low resistance. Similarly, in the second TLPM 1302, the source polysilicon 1346 is electrically connected to the N-type plug region 1351 through the barrier metal layer 87 in the trench 1330 with a low resistance.
[0177]
According to the above-described fourteenth embodiment, not only is a one-chip power IC that is small in size, low in on-resistance, and low in cost reduced while suppressing an increase in cost due to an increase in manufacturing processes, the following effects can be obtained. Is obtained. That is, the source polysilicons 1046 and 1346 are P-type or N-type with a high impurity concentration. However, in the case of the N-type, the N-type source polysilicon 1346 and the P-type source region are present without the barrier metal layer 87. The contact with 1325 forms a pn diode structure and does not become ohmic contact. If the barrier metal layer 86 is not provided, a pn diode structure is formed by the contact between the N-type source polysilicon 1046 and the P-type plug region 1051, and no ohmic contact is formed.
[0178]
Similarly, when the source polysilicons 1046 and 1346 are P-type, if there is no barrier metal layer 86, a pn diode structure is formed by the contact between the P-type source polysilicon 1046 and the N-type source region 1025. There is no ohmic contact. Without the barrier metal layer 87, the pn diode structure is formed by the contact between the P-type source polysilicon 1346 and the N-type plug region 1351, and no ohmic contact is formed.
[0179]
For such inconvenience, by providing the barrier metal layers 86 and 87 as in the fourteenth embodiment, the source polysilicon 1046 can be formed regardless of whether the source polysilicon 1046 and 1346 are N-type or P-type. , 1346 are electrically connected to all of the P-type source region 1325, the N-type source region 1025, the N-type plug region 1351 and the P-type plug region 1051 with low resistance. In this way, by grounding the source and the substrate, floating in the base regions 1045 and 1345 serving as channels can be prevented, and a reduction in the breakdown voltage of the TLPM 1106 and 1302 can be prevented. Further, since the source polysilicons 1046 and 1346 can be formed at the same time, the number of masks is reduced as compared with the case where the source polysilicons 1046 and 1346 are formed separately, so that the cost is reduced.
[0180]
Embodiment 15 FIG.
FIG. 208 is a longitudinal sectional view showing the configuration of the semiconductor device according to the fifteenth embodiment of the present invention. As shown in FIG. 208, in the semiconductor device of the fifteenth embodiment, the P-type body region 1024 is formed in the first P well region 52 in the trench bottom of the TLPM 1100 instead of the TLPM 1100 in the sixth embodiment shown in FIG. , And a TLPM 1107 having a structure in which a P-type body region 1061 and a second N-type extended drain region 1062 are added to the trench sidewall of the TLPM 1100 is formed. The second N-type extended drain region 1062 is formed in the P-type body region 1061 on the trench sidewall. Since other configurations are the same as those of the sixth embodiment, the same configurations as those of the sixth embodiment are denoted by the same reference numerals and description thereof is omitted.
[0181]
A manufacturing process of the semiconductor device shown in FIG. 208 will be described. 209 to 212 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. First, as shown in FIGS. 2, 3, 99, and 100, an N well region 54, a first P well region 52, a second P well region 53, and an extended drain region 1022 are formed. Thereafter, a trench 1030 is formed in the first P well region 52, a buffer oxide film 59 is formed therein, and then boron (B ₁₁ P-type impurities such as) are obliquely implanted (FIG. 209).
[0182]
Subsequently, boron (B ₁₁ ) And the like are ion-implanted (FIG. 210). The implanted impurity is diffused to simultaneously form a body region 1024 on the bottom surface of the trench and a body region 1061 on the side wall of the trench. Next, phosphorus (P ₃₁ N-type impurities such as) are obliquely implanted (FIG. 211). The implanted impurity is diffused to form a second N-type extended drain region 1062 on the trench sidewall (FIG. 212). The subsequent steps are the same as those shown in FIG.
[0183]
Here, as shown in FIG. 213, in the semiconductor device of the seventh embodiment (FIG. 128), a P-type body region 1024 is added to the trench bottom instead of the first TLPM 1101, and a P-type body is formed on the trench sidewall. The TLPM 1107 having a configuration in which a region 1061 and a second N-type extended drain region 1062 are added is formed, and instead of the second TLPM 1300, an N-type body region 1324 is added at the bottom of the trench, and an N-type body is formed on the trench sidewall. A TLPM 1303 having a configuration in which the region 1361 and the second P-type extended drain region 1362 are added may be formed. As shown in FIG. 214, the same applies to the semiconductor device of the eighth embodiment (FIG. 149).
[0184]
In the second TLPM 1303, the N-type body regions 1324 and 1361 and the second P-type extended drain region 1362 are formed in the same manner as the P-type body regions 1024 and 1061 and the second N-type extended drain of the first TLPM 1107. This is the same as the method for forming the region 1062. However, the conductivity type of the implanted impurity is reversed.
[0185]
According to the fifteenth embodiment described above, a one-chip power IC that is small in size, low on-resistance, and low in cost can be obtained while suppressing an increase in cost due to an increase in manufacturing steps. In addition, according to the fifteenth embodiment, the presence of the P-type body region 1061 and the second N-type extended drain region 1062 on the trench sidewall keeps the N-type impurity concentration on the trench sidewall constant and the on-resistance due to the concentration distribution. In addition, the charge balance between the P-type body region 1061 and the second N-type extended drain region 1062 can be maintained even if a relatively high concentration of N-type impurity is ion-implanted into the trench sidewall. The effect that the breakdown voltage can be achieved is obtained. The same effect can be obtained with the second TLPM 1303.
[0186]
Embodiment 16 FIG.
In the semiconductor device of the sixteenth embodiment, a resistance element and a TLPM are integrated on the same semiconductor substrate. FIG. 215 is a longitudinal sectional view showing the configuration of the semiconductor device according to the sixteenth embodiment of the present invention. As shown in FIG. 215, TLPM (TLPM 1101 described in the seventh embodiment as an example) is formed in first P well region 52. A PMOS 300 is formed in the N well region 54. Resistive element 1500 is formed in second P well region 53.
[0187]
An N well region 1501 is formed in the second P well region 53. In the N well region 1501, high concentration N type contact regions 1503 and 1504 separated by a P type offset region 1502 are formed. The electrodes 1505 and 1506 are in contact with the N-type contact regions 1503 and 1504.
[0188]
A manufacturing process of the semiconductor device shown in FIG. 215 will be described. 216 to 223 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. 215. First, N well region 54, first P well region 52, and second P well region 53 are formed in the order shown in FIGS. Next, a buffer oxide film 56 is formed on the substrate surface, a mask 2011 having a desired pattern is formed thereon, and phosphorus (P) is formed in the first P well region 52 and the second P well region 53. ₃₁ ) And the like are ion-implanted (FIG. 216).
[0189]
At this time, phosphorous (P) is separately used for the first P well region 52 and the second P well region 53 using two masks. ₃₁ N-type impurities such as) may be ion-implanted. In that case, by appropriately setting the concentration of the N well region 1501 in the N well region 54 and the second P well region 53, it becomes difficult for the N well region 54 and the N well region 1501 to be connected. And the resistance element 1500 can be prevented from interacting with each other.
[0190]
Next, the implanted impurities are diffused to form an extended drain region 1022 in the first P well region 52 and an N well region 1501 in the second P well region 53. After removing the mask 2011, a mask oxide film 57 is stacked on the buffer oxide film 56 (FIG. 217). Thereafter, the mask oxide film 57 is patterned to form a trench 1030 in the first P well region 52, and a selective oxide film 63 for element isolation is formed.
[0191]
Next, a mask 2012 is formed with openings above the trench 1030 and above the region serving as the offset region of the resistance element. And boron (B ₁₁ ) Or the like is ion-implanted (FIG. 218) and diffused to form a base region 1045 at the bottom of the trench in the first P well region 52, and at the same time, an N well region 1501 in the second P well region 53. An offset region 1502 is formed therein. Then, the mask 2012 is removed (FIG. 219).
[0192]
Subsequently, a PMOS channel region 333 and gate oxide films 1029 and 329 are formed, and a polysilicon layer 143 is stacked. A mask 2013 is formed only on a portion of the polysilicon layer 143 that becomes a PMOS gate electrode (FIG. 220), and a PMOS gate electrode 326 and a TLPM gate electrode 1026 are formed by anisotropic etching such as RIE. . Then, the mask 2013 is removed (FIG. 221). Next, a shadow oxide film 68 is formed. Then, a mask 2014 in which the source region and the drain region of the TLPM and the N-type contact region of the resistance element are opened is formed, and arsenic (As ₇₅ ) And the like are ion-implanted (FIG. 222).
[0193]
The implanted impurities are diffused to form a TLPM source region 1025 at the bottom of the trench 1030, a TLPM drain region 1023 outside the trench 1030, and N-type contact regions 1503 and 1504 for resistance elements. Then, after removing the mask 2014, boron (B ₁₁ ) Or the like is ion-implanted (FIG. 223).
[0194]
Thereafter, PMOS source and drain regions are formed by impurity diffusion. Next, an interlayer insulating film 131 is stacked, a contact hole is opened at the bottom of the trench, and the inside of the trench is filled with source polysilicon. Thereafter, a passivation film 71 is formed and a contact hole is opened. Finally, a source electrode and a drain electrode are formed, and electrodes 1505 and 1506 that are in contact with the N-type contact regions 1503 and 1504 of the resistance element 1500 are formed. Note that the order of the process of FIG. 222 and the process of FIG. 223 may be reversed.
[0195]
According to the above-described sixteenth embodiment, the resistance element 1500 and the TLPM 1101 can be integrated. Therefore, by integrating these with the bipolar transistor, the capacitance, etc., the TLPM can be integrated in the entire analog IC. Therefore, power consumption can be reduced as compared with a conventional analog IC using a planar power MOSFET.
[0196]
Embodiment 17. FIG.
In the semiconductor device of the seventeenth embodiment, a bipolar transistor and a TLPM are integrated on the same semiconductor substrate. FIG. 224 is a longitudinal sectional view showing the configuration of the semiconductor device according to the seventeenth embodiment of the present invention. As shown in FIG. 224, the TLPM (TLPM 1100 described in the sixth embodiment as an example) is formed in the first P well region 52. A PMOS 300 is formed in the first N well region 54. An NMOS 200 is formed in the second P well region 53. Bipolar transistor 1400 is formed in second N well region 85.
[0197]
A P-type offset region 1401 and an N-type collector region 1403 are formed in the second N well region 85. A P-type base region 1405 and an N-type emitter region 1406 are formed in the P-type offset region 1401. Collector electrode 1409, base electrode 1410, and emitter electrode 1411 are in contact with collector region 1403, base region 1405, and emitter region 1406, respectively.
[0198]
A manufacturing process of the semiconductor device illustrated in FIG. 224 will be described. 225 to 237 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. 224. First, in the order shown in FIGS. 150 to 152, the first P well region 52, the second P well region 53, the first N well region 54, and the second N well region 85 are formed, and the buffer oxide film is formed. 56 is formed, phosphorus (P ₃₁ N-type impurities such as) are ion-implanted.
[0199]
Next, the implanted impurity is diffused to form an extended drain region 1022 in the first P well region 52. Thereafter, a mask oxide film 57 is laminated on the buffer oxide film 56 (FIG. 225), and a mask 58 having an opening in the trench formation region is formed (FIG. 226). The mask oxide film 57 is patterned using the mask 58 to form a trench 1030 in the first P well region 52. Then, all the oxide film on the substrate surface including the mask oxide film 57 is removed (FIG. 227). Thereafter, a selective oxide film 63 for element isolation is formed using the patterned silicon nitride film 61 (FIG. 228).
[0200]
After removing the silicon nitride film 61 and performing sacrificial oxidation, a mask 2015 is formed with openings above the trench 1030, above the region serving as the NMOS channel region, and above the region serving as the offset region of the bipolar transistor. . Using this mask 2015, boron (B ₁₁ ) Or the like is ion-implanted (FIG. 229). Then, the implanted impurity is diffused to form a P-type base region 1045 on the bottom surface of the trench 1030, an NMOS channel region 233 is formed in the second P-well region 53, and a P-type offset region 1401 is formed. . Then, the mask 2015 is removed (FIG. 230).
[0201]
Subsequently, phosphorus (P) is formed using a mask 66 in which a region to be a channel region of the PMOS is opened. ₃₁ ) And the like are ion-implanted (FIG. 231). The implanted impurity is diffused to form a PMOS channel region 333 in the first N well region 54. After removing the mask 66 and the thin oxide film on the substrate surface and inside the trench, gate oxide films 1029, 229, and 329 are formed (FIG. 232). Next, a polysilicon layer 143 is stacked, and a mask 67 is formed only on the portion of the polysilicon layer 143 that becomes the gate electrodes of NMOS and PMOS (FIG. 233). Note that the order of the process in FIG. 229 and the process in FIG. 231 may be reversed.
[0202]
Subsequently, an NMOS gate electrode 226, a PMOS gate electrode 326, and a TLPM gate electrode 1026 are formed by anisotropic etching such as RIE. Then, the mask 67 is removed (FIG. 234). Thereafter, a shadow oxide film 68 is formed, and a mask 2016 is formed in which the source region and drain region of TLPM, the NMOS formation region, and the N-type collector region and N-type emitter region of the bipolar transistor are opened. And arsenic (As ₇₅ ) And the like are ion-implanted (FIG. 235).
[0203]
The implanted impurities are diffused, and a source region 1025 of TLPM is formed at the bottom of the trench 1030, a drain region 1023 of TLPM is formed outside the trench 1030, a source region 225 and a drain region 223 are formed in the NMOS channel region 233, A collector region 1403 and an N-type emitter region 1406 are formed. Then, after removing the mask 2016, boron (B) is used using a mask 2017 in which the PMOS formation region and the P-type base region of the bipolar transistor are opened. ₁₁ ) And the like are ion-implanted (FIG. 236). Note that the order of the process in FIG. 235 and the process in FIG. 236 may be reversed.
[0204]
Thereafter, the source region 325 and the drain region 323 of the PMOS and the P-type base region 1405 of the bipolar transistor are formed by impurity diffusion, and the mask 2017 is removed (FIG. 237). Next, an interlayer insulating film 131 is stacked, a contact hole is opened at the bottom of the trench, and the inside of the trench is filled with source polysilicon. Thereafter, a passivation film 71 is formed and a contact hole is opened. Finally, a source electrode and a drain electrode are formed, and a collector electrode 1409, a base electrode 1410, and an emitter electrode 1411 of the bipolar transistor 1400 are formed.
[0205]
According to the above-described seventeenth embodiment, the bipolar transistor 1400 and the TLPM 1100 can be integrated. Therefore, by integrating these with the resistance element, the capacitance, etc., the TLPM can be integrated in the analog IC as a whole. Therefore, power consumption can be reduced as compared with a conventional analog IC using a planar power MOSFET.
[0206]
Embodiment 18 FIG.
In the semiconductor device of the eighteenth embodiment, capacitance and TLPM are integrated on the same semiconductor substrate. FIG. 238 is a longitudinal sectional view showing the configuration of the semiconductor device according to Embodiment 18 of the present invention. As shown in FIG. 238, TLPM (TLPM 1100 described in the sixth embodiment as an example) is formed in the first P well region 52. A PMOS 300 is formed in the first N well region 54. An NMOS 200 is formed in the second P well region 53. A capacitance 1600 is formed in the second N well region 85.
[0207]
A P-type offset region 1601 is formed in the second N well region 85. A high concentration P-type region 1602 is formed in the P-type offset region 1601. A capacitance electrode 1603 is provided on the high-concentration P-type region 1602 with a capacitance insulating film 1604 interposed therebetween.
[0208]
A manufacturing process of the semiconductor device shown in FIG. 238 will be described. 239 to 244 are longitudinal sectional views in the course of manufacturing the semiconductor device shown in FIG. 238. First, in the order shown in FIGS. 150 to 152 and 225 to 232, the first P well region 52, the second P well region 53, the first N well region 54, the second N well region 85, Extended drain region 1022, trench 1030, selective oxide film 63, TLPM P-type base region 1045, NMOS channel region 233, P-type offset region 1601 of capacitance (reference numeral 1401 in FIG. 230), PMOS A channel region 333, gate oxide films 1029, 229, and 329, and a capacitance insulating film 1604 (not shown in FIG. 230) are formed.
[0209]
Next, using a mask 2018 in which a high-concentration P-type region having a capacitance is opened, boron (B ₁₁ ) And the like are ion-implanted (FIG. 239). The implanted impurity is diffused to form a high concentration P-type region 1602 in the P-type offset region 1601. After the mask 2018 is removed, a polysilicon layer 143 is stacked, and a mask 2019 is formed only on the portion of the polysilicon layer 143 that becomes the gate electrode of NMOS and PMOS and the portion that becomes the capacitance electrode (FIG. 240). ).
[0210]
Subsequently, a capacitance electrode 1603, an NMOS gate electrode 226, a PMOS gate electrode 326, and a TLPM gate electrode 1026 are formed by anisotropic etching such as RIE. Then, the mask 2019 is removed (FIG. 241). Thereafter, a shadow oxide film 68 is formed, and a mask 69 having an opening in the source region and drain region of TLPM and the NMOS formation region is formed. And arsenic (As ₇₅ ) And the like are ion-implanted (FIG. 242).
[0211]
The implanted impurities are diffused to form a TLPM source region 1025 at the bottom of the trench 1030, a TLPM drain region 1023 outside the trench 1030, and a source region 225 and a drain region 223 in the NMOS channel region 233. Then, after removing the mask 69, boron (B ₁₁ ) And the like are ion-implanted (FIG. 243). Thereafter, a PMOS source region 325 and drain region 323 are formed by impurity diffusion, and the mask 70 is removed (FIG. 244). Note that the order of the process in FIG. 242 and the process in FIG. 232 may be reversed.
[0212]
Next, an interlayer insulating film 131 is stacked, a contact hole is opened at the bottom of the trench, and the inside of the trench is filled with source polysilicon. Thereafter, a passivation film 71 is formed and a contact hole is opened. Finally, a source electrode and a drain electrode are formed.
[0213]
According to the eighteenth embodiment described above, the capacitance 1600 and the TLPM 1100 can be integrated. Therefore, by integrating these with a resistance element, a bipolar transistor, etc., the TLPM can be integrated in the analog IC as a whole. Therefore, power consumption can be reduced as compared with a conventional analog IC using a planar power MOSFET.
[0214]
Embodiment 19. FIG.
FIG. 245 is a longitudinal sectional view showing the configuration of the semiconductor device according to Embodiment 19 of the present invention. As shown in FIG. 245, in the nineteenth embodiment, in the semiconductor device of the sixth embodiment shown in FIG. 98, the second P well region 53 is replaced with the NMOS 200 in the same manner as the first P well region 52. A TLPM 1100 is formed.
[0215]
Thus, in Embodiments 6 to 18 described above, one TLPM may be formed in each of the plurality of P well regions. The same applies to the N well region, and one TLPM may be formed in each of the plurality of N well regions. A plurality of TLPMs may be formed in one well region. According to the nineteenth embodiment, since there are a plurality of TLPMs of the same conductivity type on the same semiconductor substrate, there is an effect that the TLPM can be made as a large current element.
[0216]
Embodiment 20. FIG.
FIG. 246 is a longitudinal sectional view showing the configuration of the semiconductor device according to the twentieth embodiment of the present invention. As shown in FIG. 246, in this semiconductor device, a first N well region 3001, a first P well region 3002, a second N well region 3003, and a second P well region 3004 are formed in a semiconductor substrate 3000. The first N-well region 3001, the first P-well region 3002, the second N-well region 3003, and the second P-well region 3004 have a P-channel first TLPM 3100 and an N-channel second TLPM 3100, respectively. A TLPM 3200, a PMOS 3300, and an NMOS 3400 are formed. The gate oxide films 3101 and 3201 of the TLPMs 3100 and 3200 are formed thicker than the gate oxide films 3301 and 3401 of the PMOS 3300 and the NMOS 3400.
[0217]
In FIG. 246, reference numerals 3102, 3202, 3302 and 3402 denote gate electrodes. Reference numerals 3103, 3203, 3303, and 3403 denote source regions. Reference numerals 3104, 3204, 3304, and 3404 denote drain regions. Reference numerals 3105, 3205, 3305, and 3405 denote source electrodes, respectively. Reference numerals 3106, 3206, 3306, and 3406 denote drain electrodes. Reference numerals 3107 and 3207 are interlayer insulating films, and reference numerals 3108 and 3208 are drain polysilicons. Reference numeral 3005 denotes a selective oxide film for element isolation. In FIG. 246, the interlayer insulating film and the passivation film on the substrate surface are omitted.
[0218]
The thicknesses of the gate oxide films 3101 and 3201 of the TLPMs 3100 and 3200 are not particularly limited, but are, for example, 600 angstroms. On the other hand, the thicknesses of the gate oxide films 3301 and 3401 of the PMOS 3300 and NMOS 3400 are not particularly limited, but are about 170 angstroms, for example. Here, a voltage of 20 V or more is normally applied to the drain portion of the TLPM which is a high breakdown voltage element. FIG. 247 is a diagram showing a simulation result of the relationship between the gate oxide film thickness and the drain breakdown voltage. As shown in FIG. 247, when the gate oxide film thickness is 600 angstroms, the drain breakdown voltage is 27V, which is sufficient. On the other hand, when the gate oxide film thickness is about 200 Å, which is the same as that of a normal CMOS portion, the drain breakdown voltage is about 18V, which is insufficient.
[0219]
Therefore, it is conceivable to increase the thickness of the gate oxide film in order to obtain a sufficient drain breakdown voltage of TLPM. However, in that case, the gate oxide film in the CMOS portion becomes thick, causing problems such as a rise in threshold voltage and a slow response, a difficulty in current flow, and a small noise margin. Occurs. Therefore, the gate oxide films 3101 and 3201 of the TLPMs 3100 and 3200 are formed thicker than the gate oxide films 3301 and 3401 of the PMOS 3300 and the NMOS 3400 by a manufacturing process described below as an example.
[0220]
248 to 256 are longitudinal sectional views of the semiconductor device having the same configuration as that of the semiconductor device shown in FIG. First, a first N well region 3001, a first P well region 3002, a second N well region 3003, and a second P well region 3004 are selectively formed in a P type semiconductor substrate 3000 (FIG. 248). Next, a first trench 3110 and a second trench 3210 are formed using the patterned mask oxide film 4001. Then, drain regions 3104 and 3204 of each TLPM are formed on the bottom surfaces of the first trench 3110 and the second trench 3210 (FIG. 249).
[0221]
After removing the mask oxide film 4001, a selective oxide film 3005 for element isolation is formed (FIG. 250). Next, a sacrificial oxide film 4002 is formed, and channel regions 3111, 3211, 3311, and 3411 of TLPM 3100, TLPM 3200, PMOS 3300, and NMOS 3400 are formed by ion implantation or the like (FIG. 251). After the sacrificial oxide film 4002 is removed, a first gate oxide film 4003 is formed on the substrate surface and inside the trenches 3110 and 3210. Then, the trenches 3110 and 3210 are covered with a mask 4004, and etching or the like is performed in that state to remove the first gate oxide film 4003 from the CMOS portion. As a result, the first gate oxide film 4003 remains only inside the trenches 3110 and 3210 (FIG. 252).
[0222]
After removing the mask 4004, a second gate oxide film 4005 is formed on the substrate surface and inside the trenches 3110 and 3210 (FIG. 253). Thus, the gate oxide film 3301 of the PMOS 3300 and the gate oxide film 3401 of the NMOS 3400 are constituted by the second gate oxide film 4005. On the other hand, the gate oxide film 3101 of the first TLPM 3100 and the gate oxide film 3201 of the second TLPM 3200 have a configuration in which the second gate oxide film 4005 is stacked on the first gate oxide film 4003, and The oxide film is thicker than the gate oxide films 3301 and 3401.
[0223]
Next, gate electrodes 3102, 3202, 3302, 3402 are formed (FIG. 254), and TLPM 3100, 3200, PMOS 3300 and NMOS 3400 source regions 3103, 3203, 3303, 3403, and PMOS 3300 and NMOS 3400 drain regions 3304, 3404 are formed ( FIG. 255). In the illustrated example, an LDD structure is used. Next, an interlayer insulating film is stacked, a contact hole is opened at the bottom of the trench of the interlayer insulating film, and the insides of the first trench 3110 and the second trench 3210 are filled with drain polysilicon 3108 and 3208 (FIG. 256). ). Then, a passivation film is formed on the entire surface of the substrate, contact holes are opened, and a source electrode and a drain electrode are formed, thereby completing a semiconductor device.
[0224]
According to the twentieth embodiment described above, the gate oxide films 3101 and 3201 of the TLPMs 3100 and 3200 can be formed thicker than the gate oxide films 3301 and 3401 of the CMOSFET section. Thus, a semiconductor device in which a high breakdown voltage power MOSFET is integrated on the same semiconductor substrate can be obtained.
[0225]
Embodiment 21. FIG.
The twenty-first embodiment relates to a structure of a buried electrode in a trench applicable to a TLPM integrated with a CMOS unit or the like as described above, or a single TLPM. Hereinafter, eight examples of the structure of the buried electrode will be shown.
[0226]
FIG. 257 is a longitudinal sectional view showing a first example of the semiconductor device according to the twenty-first embodiment. A TLPM 5100 shown in FIG. 257 is a second type element having a source contact at the bottom of the trench. A first-stage trench 5101 is formed in the semiconductor substrate 5000, and a thick oxide film 5102 is formed on the side wall thereof. A second-stage trench 5103 is formed from the bottom of the first-stage trench, and a source region 5104 and a base region 5105 are formed at the bottom of the second-stage trench 5103. Inside the first and second stage trenches, a gate electrode 5107 is formed via a gate oxide film 5106 along the side wall of the thick oxide film 5102 in the first stage trench and the second stage trench 5103. Yes.
[0227]
A barrier metal layer 5109 made of Ti, TiN, Ta, TaN, TiC, TaC, W 2 N or the like is provided inside the gate electrode 5107 with an interlayer insulating film 5108 interposed therebetween. The barrier metal layer 5109 is in contact with the source region 5104, and a tungsten plug 5110 is provided as an embedded electrode on the inside thereof. A drain region 5111 is provided on the surface of the substrate, and an extended drain region 5112 is provided between the drain region 5111 and the base region 5105. The substrate surface penetrates through the interlayer insulating film 5108 and the passivation film 5115 and is electrically connected to the source region 5104 through the tungsten plug 5110 and the barrier metal layer 5109 through the drain electrode 5113 in contact with the drain region 5111. A source electrode 5114 is provided.
[0228]
According to the first example, when the tungsten plug 5110 is embedded by the CVD method, the growth rate is 0.15 to 0.6 μm per minute, so the growth rate when the doped polysilicon is embedded is as follows. Compared to the rate of about 25 angstroms per minute, there is an advantage that it can grow two orders of magnitude faster. The barrier metal layer 5109 can prevent tungsten from diffusing into the silicon substrate or the oxide film.
[0229]
FIG. 258 is a longitudinal sectional view showing a second example of the semiconductor device according to the twenty-first embodiment. A TLPM 5200 shown in FIG. 258 is a first type element having a drain contact at the bottom of the trench, and is formed by digging a trench twice. A drain region 5211 is provided at the bottom of the trench, and an extended drain region 5212 is provided so as to surround the trench. A gate electrode 5207 is formed in the trench through a gate oxide film 5206. A barrier metal layer 5209 that is in contact with the drain region 5211 is provided inside the gate electrode 5207 with an interlayer insulating film 5208 interposed therebetween. The inside of the barrier metal layer 5209 is buried with a tungsten plug 5210.
[0230]
A source region 5204 and a plug region 5221 are provided on the substrate surface. A source electrode 5214 is in contact with the source region 5204 and the plug region 5221 through the interlayer insulating film 5208 and the passivation film 5215. The drain electrode 5213 is electrically connected to the drain region 5211 through the tungsten plug 5210 and the barrier metal layer 5209.
[0231]
According to the second example, similar to the first example described above, by embedding the tungsten plug 5210 by the CVD method, the growth can be performed two orders of magnitude faster than when the doped polysilicon is buried. There is an advantage that can be.
[0232]
FIG. 259 is a longitudinal sectional view showing a third example of the semiconductor device according to the twenty-first embodiment. A TLPM 5300 shown in FIG. 259 is a second type element having a source contact at the bottom of the trench, and is formed by digging the trench once. A source region 5304 and a base region 5305 are provided at the bottom of the trench 5303. In the trench, a barrier metal layer 5309 that contacts the gate oxide film 5306, the gate electrode 5307, the interlayer insulating film 5308, and the source region 5304 is provided in this order from the outside. The inside of the barrier metal layer 5309 is buried with a tungsten plug 5310.
[0233]
A drain region 5311 is provided on the substrate surface. The drain electrode 5313 passes through the interlayer insulating film 5308 and the passivation film 5315 and is in contact with the drain region 5311. Source electrode 5314 is electrically connected to source region 5304 through tungsten plug 5310 and barrier metal layer 5309.
[0234]
According to the third example, similar to the first example described above, by embedding the tungsten plug 5310 by the CVD method, the growth can be performed two orders of magnitude faster than the case where the doped polysilicon is buried. There is an advantage that can be. Further, the barrier metal layer 5309 can prevent tungsten from diffusing into the silicon substrate or the oxide film.
[0235]
FIG. 260 is a longitudinal sectional view showing a fourth example of the semiconductor device according to the twenty-first embodiment. A TLPM 5400 shown in FIG. 260 is a first type element having a drain contact at the bottom of the trench, and is formed by digging the trench once. The drain region 5411 is provided at the bottom of the trench. In the trench, a gate oxide film 5406, a gate electrode 5407, an interlayer insulating film 5408, and a barrier metal layer 5409 in contact with the drain region 5411 are provided in this order from the outside. The inside of the barrier metal layer 5409 is buried with a tungsten plug 5410.
[0236]
A source region 5404 and a plug region 5421 are provided on the substrate surface. A source electrode 5414 is in contact with the source region 5404 and the plug region 5421 through the interlayer insulating film 5408 and the passivation film 5415. The drain electrode 5413 is electrically connected to the drain region 5411 through the tungsten plug 5410 and the barrier metal layer 5409.
[0237]
According to the fourth example, similar to the first example described above, by embedding the tungsten plug 5410 by the CVD method, the growth can be performed two orders of magnitude faster than when the doped polysilicon is buried. There is an advantage that can be.
[0238]
FIG. 261 is a longitudinal sectional view showing a fifth example of the semiconductor device according to the twenty-first embodiment. A TLPM 5500 shown in FIG. 261 is a second type element having a source contact at the bottom of the trench, and is formed by digging a trench twice. A source region 5504 and a base region 5505 are provided at the bottom of the trench. Within the trench, a thick oxide film 5502, a gate oxide film 5506, a gate electrode 5507, and an interlayer insulating film 5508 are provided in this order from the outside. The inner side of the interlayer insulating film 5508 is buried with a WSi (tungsten silicide) electrode 5510 in contact with the source region 5504.
[0239]
A drain region 5511 is provided on the substrate surface. The drain electrode 5513 passes through the interlayer insulating film 5508 and the passivation film 5515 and is in contact with the drain region 5511. The source electrode 5514 is electrically connected to the source region 5504 through the WSi electrode 5510.
[0240]
According to the fifth example, when the WSi electrode 5510 is embedded by the CVD method, the growth rate is 0.15 to 0.6 μm / min. There is an advantage that it can be grown two orders of magnitude faster than when polysilicon is embedded. Further, since the barrier metal layer is unnecessary, there is an advantage that the throughput is improved as compared with the first example described above.
[0241]
FIG. 262 is a longitudinal sectional view showing a sixth example of the semiconductor device according to the twenty-first embodiment. A TLPM 5600 shown in FIG. 262 is a second type element having a source contact at the bottom of the trench, and is formed by digging a trench twice. A source region 5604 and a base region 5605 are provided at the bottom of the trench. Inside the trench, a thick oxide film 5602, a gate oxide film 5606, a gate electrode 5607, an interlayer insulating film 5608, and a barrier metal layer 5609 in contact with the source region 5604 are provided in this order from the outside. The inside of the barrier metal layer 5609 is buried with a P-doped polysilicon electrode 5610.
[0242]
A drain region 5611 is provided on the surface of the substrate. The drain electrode 5613 penetrates the interlayer insulating film 5608 and the passivation film 5615 and is in contact with the drain region 5611. The source electrode 5614 is electrically connected to the source region 5604 via the P-doped polysilicon electrode 5610 and the barrier metal layer 5609. According to the sixth example, the barrier metal layer 5609 can suppress the diffusion of the dopant from the P-doped polysilicon electrode 5610.
[0243]
FIG. 263 is a longitudinal sectional view showing a seventh example of the semiconductor device according to the twenty-first embodiment. A TLPM 5700 shown in FIG. 263 is a second type element having a source contact at the bottom of the trench, and is formed by digging a trench twice. A source region 5704 and a base region 5705 are provided at the bottom of the trench. In the trench, a thick oxide film 5702, a gate oxide film 5706, a gate electrode 5707, and an interlayer insulating film 5708 are provided in this order from the outside. The inner side of the interlayer insulating film 5708 is buried with a buried electrode 5710 that is in contact with the source region 5704. The buried electrode 5710 is formed by burying non-doped polysilicon in the trench and then doping P (phosphorus).
[0244]
A drain region 5711 is provided on the surface of the substrate. The drain electrode 5713 passes through the interlayer insulating film 5708 and the passivation film 5715 and is in contact with the drain region 5711. The source electrode 5714 is electrically connected to the source region 5704 through the embedded electrode 5710. According to the seventh example, the growth rate when the non-doped polysilicon is buried by the CVD method is 2 to 3 times faster than the growth rate of the doped polysilicon, so that there is an advantage that the throughput is improved. .
[0245]
FIG. 264 is a longitudinal sectional view showing an eighth example of the semiconductor device according to the twenty-first embodiment. A TLPM 5800 shown in FIG. 264 is a second type element having a source contact at the bottom of the trench, and is formed by digging a trench twice. A source region 5804 and a base region 5805 are provided at the bottom of the trench. Inside the trench, a thick oxide film 5802, a gate oxide film 5806, a gate electrode 5807, an interlayer insulating film 5808, and a barrier metal layer 5809 in contact with the source region 5804 are provided in this order from the outside. The inside of the barrier metal layer 5809 is buried with a buried electrode 5810. The buried electrode 5810 is formed by burying non-doped polysilicon in the trench and then doping phosphorus.
[0246]
A drain region 5811 is provided on the surface of the substrate. The drain electrode 5813 penetrates through the interlayer insulating film 5808 and the passivation film 5815 and is in contact with the drain region 5811. The source electrode 5814 is electrically connected to the source region 5804 through the buried electrode 5810 and the barrier metal layer 5809. According to the eighth example, the growth rate when the non-doped polysilicon is buried by the CVD method is 2 to 3 times faster than the growth rate of the doped polysilicon, so that the throughput is improved. . Further, the barrier metal layer 5809 can suppress diffusion of dopant from the embedded electrode 5810.
[0247]
In addition, regarding the fifth to eighth examples, the first type that takes a drain contact at the bottom of the trench, the TLPM formed by digging the trench twice, the second type that takes the source contact at the bottom of the trench, The same effect can be obtained when applied to a TLPM formed by digging a trench once and a TLPM formed by digging a trench once by a first type having a drain contact at the bottom of the trench.
[0248]
In Embodiment 21, the metal material of the embedded electrode is not limited to tungsten, but may be copper, aluminum, or the like. The dopant is not limited to phosphorus. Moreover, the trench may have a configuration of three or more stages. The gate insulating film is not limited to an oxide film, and may be an electrical insulating film or a high resistance film. Further, the present invention can be applied not only to silicon semiconductors but also to compound semiconductor elements such as SiC.
[0249]
In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, the P type and the N type may be reversed in the description of each embodiment described above. In the above-described embodiments, the case where there are two P well regions and one N well region has been described, but the number of each well region is not limited thereto. Further, the depth and width of each trench are selected as appropriate, thereby obtaining a TLPM of an arbitrary output stage.
[0250]
【The invention's effect】
According to the present invention, the gate electrode of the TLPM and the gate electrode of the planar device are formed by patterning the same polysilicon layer, the drain electrode and the source electrode of the TLPM, and the drain electrode and the source electrode of the planar device. Are formed by patterning the same metal wiring layer, it is possible to electrically connect the TLPM and the planar device to each other through this metal wiring layer or polysilicon layer. In addition, since it is not necessary to perform wire bonding to the printed circuit board, it is possible to obtain a one-chip power IC that is small in size, low on-resistance, and low in cost.
[Brief description of the drawings]
1 is a longitudinal sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;
2 is a longitudinal sectional view of the semiconductor device shown in FIG. 1 in the middle of its manufacture.
3 is a longitudinal sectional view of the semiconductor device shown in FIG. 1 in the middle of its manufacture.
4 is a longitudinal sectional view of the semiconductor device shown in FIG. 1 in the middle of its manufacture.
FIG. 5 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1;
6 is a longitudinal sectional view of the semiconductor device shown in FIG. 1 in the middle of its manufacture.
7 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
8 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
FIG. 9 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1;
10 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1. FIG.
11 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1. FIG.
12 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
13 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
14 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
15 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
16 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
17 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
18 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
19 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1. FIG.
20 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
21 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
22 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
23 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
24 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
25 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
26 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
27 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 1; FIG.
FIG. 28 is a longitudinal sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention;
FIG. 29 is a longitudinal sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention;
FIG. 30 is a longitudinal sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention;
FIG. 31 is a longitudinal sectional view showing a modification of the semiconductor device according to the first embodiment of the present invention;
32 is a longitudinal sectional view showing an example of integration with the bipolar transistor of the semiconductor device according to the first embodiment of the present invention; FIG.
FIG. 33 is a longitudinal sectional view showing an example of integration with the resistor element of the semiconductor device according to the first embodiment of the present invention;
FIG. 34 is a longitudinal sectional view showing an example of integration with the capacitance of the semiconductor device according to the first embodiment of the present invention;
FIG. 35 is a diagram schematically showing a size comparison between a power module to which a semiconductor device according to the present invention is applied and a power module using a conventional planar type power MOSFET.
FIG. 36 is a longitudinal sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention;
FIG. 37 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36;
38 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
FIG. 39 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36;
40 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
41 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
42 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
43 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
44 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
45 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
46 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
47 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 36; FIG.
FIG. 48 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 49 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 50 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 51 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
52 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention; FIG.
FIG. 53 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 54 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 55 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 56 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 57 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
58 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention; FIG.
FIG. 59 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 60 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 61 is a longitudinal sectional view in the middle of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 62 is a longitudinal sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention;
63 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
64 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
65 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
66 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
67 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
68 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
69 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
70 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 62; FIG.
FIG. 71 is a longitudinal sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention;
72 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
73 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
74 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
75 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
76 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
77 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
78 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
79 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
80 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
81 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
82 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
83 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
84 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
85 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
86 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
87 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
88 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
FIG. 89 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71;
90 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 71; FIG.
FIG. 91 is a longitudinal sectional view showing a modification of the semiconductor device according to the fifth embodiment of the present invention;
92 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
93 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
94 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
95 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
96 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
97 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 91; FIG.
FIG. 98 is a longitudinal sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention;
99 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
100 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
101 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
102 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
103 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
104 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
105 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
FIG. 106 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98;
107 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
108 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
109 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
110 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
111 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
112 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
113 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
114 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
115 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
116 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
117 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
118 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98; FIG.
119 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98 by another manufacturing method; FIG.
120 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98 by another manufacturing method; FIG.
FIG. 121 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98;
122 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98; FIG.
FIG. 123 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98;
124 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98; FIG.
125 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 98 by another manufacturing method; FIG.
126 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98; FIG.
127 is a longitudinal sectional view in the middle of manufacturing by another manufacturing method of the semiconductor device shown in FIG. 98; FIG.
128 is a longitudinal sectional view showing a configuration of a semiconductor device according to a seventh embodiment of the present invention; FIG.
129 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
130 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
131 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
132 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
133 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
134 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
135 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
136 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
137 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
138 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
139 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
140 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
141 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
142 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
143 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
144 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
145 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
146 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
147 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
148 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 128; FIG.
FIG. 149 is a longitudinal sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present invention;
150 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
151 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
152 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
153 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
154 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
155 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
156 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
157 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
158 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
159 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
160 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
161 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
162 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
163 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
164 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
165 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
166 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
167 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
168 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
169 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
170 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
171 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
172 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149; FIG.
173 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 149;
FIG. 174 is a longitudinal sectional view showing the configuration of the semiconductor device according to the ninth embodiment of the present invention;
175 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174; FIG.
176 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174; FIG.
177 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174; FIG.
178 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174 by another manufacturing method; FIG.
179 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174 by another manufacturing method; FIG.
180 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 174 by another manufacturing method; FIG.
181 is a longitudinal sectional view showing the structure of a semiconductor device according to a tenth embodiment of the present invention; FIG.
182 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 181; FIG.
183 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 181; FIG.
184 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 181; FIG.
185 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 181. FIG.
186 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 181; FIG.
187 is a longitudinal sectional view showing another configuration of the semiconductor device according to the tenth embodiment of the present invention; FIG.
188 is a longitudinal sectional view showing still another configuration of the semiconductor device according to the tenth embodiment of the present invention; FIG.
189 is a longitudinal sectional view showing still another configuration of the semiconductor device according to Embodiment 10 of the present invention; FIG.
190 is a longitudinal sectional view showing the structure of a semiconductor device according to an eleventh embodiment of the present invention; FIG.
191 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 190; FIG.
192 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 190; FIG.
193 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 190; FIG.
194 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 190. FIG.
195 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 190; FIG.
196 is a longitudinal sectional view showing another configuration of the semiconductor device according to Embodiment 11 of the present invention; FIG.
FIG. 197 is a planar layout diagram of the impurity profile of the semiconductor device according to Embodiment 12 of the present invention;
198 is a longitudinal sectional view in the middle of manufacturing the semiconductor device taken along line BB ′ of FIG. 197; FIG.
199 is a longitudinal sectional view in the middle of manufacturing the semiconductor device taken along line BB ′ of FIG. 197; FIG.
200 is a longitudinal sectional view of the semiconductor device in the middle of manufacturing along BB ′ of FIG. 197; FIG.
201 is a longitudinal cross-sectional view during the manufacture of the semiconductor device, taken along the line AA ′ in FIG. 197; FIG.
202 is a vertical cross-sectional view of the semiconductor device taken along the line BB ′ of FIG. 197 in the middle of manufacture. FIG.
203 is a longitudinal sectional view showing the structure of a semiconductor device according to a thirteenth embodiment of the present invention; FIG.
204 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 203; FIG.
205 is a longitudinal sectional view showing another configuration of the semiconductor device according to the thirteenth embodiment of the present invention; FIG.
FIG. 206 is a planar layout diagram of the impurity profile of the semiconductor device according to Embodiment 14 of the present invention;
207 is a longitudinal sectional view showing a configuration of a semiconductor device taken along line DD ′ in FIG. 206. FIG.
FIG. 208 is a longitudinal sectional view showing the structure of a semiconductor device according to a fifteenth embodiment of the present invention;
209 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 208. FIG.
210 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 208; FIG.
211 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 208; FIG.
FIG. 212 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 208;
FIG. 213 is a longitudinal sectional view showing another configuration of the semiconductor device according to the fifteenth embodiment of the present invention;
FIG. 214 is a longitudinal sectional view showing another configuration of the semiconductor device according to the fifteenth embodiment of the present invention;
FIG. 215 is a longitudinal sectional view showing the structure of the semiconductor device according to the sixteenth embodiment of the present invention;
216 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
217 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
218 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
219 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
220 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
221 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
222 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
223 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 215; FIG.
224 is a longitudinal section showing a configuration of a semiconductor device according to Embodiment 17 of the present invention; FIG.
225 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
226 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
227 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
228 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
229 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
230 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
231 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
232 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
233 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
234 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224;
235 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
236 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
237 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 224; FIG.
238 is a longitudinal section showing a configuration of a semiconductor device according to Embodiment 18 of the present invention; FIG.
239 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238;
240 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238; FIG.
241 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238; FIG.
242 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238; FIG.
243 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238;
244 is a longitudinal sectional view in the middle of manufacturing the semiconductor device shown in FIG. 238; FIG.
245 is a longitudinal sectional view showing the structure of a semiconductor device according to Embodiment 19 of the invention; FIG.
246 is a longitudinal section showing a configuration of a semiconductor device according to Embodiment 20 of the present invention; FIG.
247 is a diagram showing simulation results for the relationship between gate oxide film thickness and drain withstand voltage. FIG.
248 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as that of the semiconductor device shown in FIG. 246;
249 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246;
250 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246;
251 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246;
252 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246;
253 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246;
254 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as that of the semiconductor device shown in FIG. 246;
FIG. 255 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as that of the semiconductor device shown in FIG. 246;
256 is a longitudinal sectional view in the middle of manufacturing the semiconductor device having the same structure as the semiconductor device shown in FIG. 246; FIG.
257 is a longitudinal sectional view showing a first example of a semiconductor device according to a twenty-first embodiment of the present invention; FIG.
258 is a longitudinal sectional view showing a second example of the semiconductor device according to the twenty-first embodiment of the invention; FIG.
259 is a longitudinal section showing a third example of the semiconductor device according to Embodiment 21 of the present invention; FIG.
FIG. 260 is a longitudinal sectional view showing a fourth example of the semiconductor device according to the twenty-first embodiment of the present invention;
FIG. 261 is a longitudinal sectional view showing a fifth example of the semiconductor device according to the twenty-first embodiment of the present invention;
262 is a longitudinal sectional view showing a sixth example of the semiconductor device according to the twenty-first embodiment of the present invention; FIG.
263 is a longitudinal sectional view showing a seventh example of the semiconductor device according to the twenty-first embodiment of the present invention; FIG.
264 is a longitudinal sectional view showing an eighth example of the semiconductor device according to the twenty-first embodiment of the present invention; FIG.
FIG. 265 is a longitudinal sectional view showing the structure of a conventional planar type power MOSFET.
266 is a longitudinal sectional view showing the structure of a conventional TLPM having a drain contact at the bottom of a trench. FIG.
267 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266. FIG.
268 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266;
269 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266. FIG.
270 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266. FIG.
271 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266. FIG.
272 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266;
273 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266;
274 is a longitudinal sectional view in the middle of manufacturing the TLPM shown in FIG. 266;
275 is a longitudinal sectional view showing a structure of a conventional TLPM having a source contact at the bottom of a trench. FIG.
[Explanation of symbols]
51 Semiconductor substrate
52, 53, 54, 72, 73, 74, 75, 85 well region
63 Selective oxide film
71 Passivation film
86,87 Barrier metal layer 6
100, 101, 102, 103, 104, 301, 302 TLPM
122,352 Extended drain region
123, 353 first drain region
125, 355 first source region
126, 356 First gate electrode
127,357 first drain electrode
128, 358 First source electrode
129,359 First gate oxide film
130,330 trench
131 Interlayer insulation film
132,362 polysilicon
143 polysilicon layer
200,300 Planar MOSFET
223, 323 second drain region
225, 325 second source region
226, 326 second gate electrode
227, 327 Second drain electrode
228, 328 second source electrode
229, 329 Second gate oxide film
400 Bipolar Transistor
409 Collector electrode
410 Base electrode
411 Emitter electrode
500 resistance elements
505, 506 Resistance element electrode
600 capacitance
603 Capacitance electrode
1100, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1300, 1301, 1302, 1303 TLPM
1022, 1322 extended drain region
1023, 1323 drain region
1024, 1061, 1324, 1361 body region
1025, 1325 source region
1026, 1326 Gate electrode
1027, 1327 Drain electrode
1028, 1328 Source electrode
1029, 1329 Gate oxide film
1030, 1330 trench
1031,1331 Interlayer insulating film
1045, 1345 base region
1046, 1346 source polysilicon
1051,1351 Plug area

Claims (25)

A first gate oxide film and a first gate electrode in the trench; a first source region of a second conductivity type at the bottom of the trench; and a first first of the second conductivity type outside the trench. A first conductivity type base region serving as a second conductivity type extended drain region and a channel region between the first source region and the first drain region; A trench lateral power MOSFET comprising a first drain electrode electrically connected to one drain region and a first source electrode electrically connected to the first source region;
A second gate oxide film and a second gate electrode are provided on the substrate surface, and the first conductivity type second drain region and the first conductivity type first electrode are formed on the substrate surface layer with the second gate electrode interposed therebetween. And a first planar electrode having a second drain electrode electrically connected to the second drain region and a second source electrode electrically connected to the second source region. Type MOSFET,
A third gate oxide film and a third gate electrode are provided on the surface of the substrate, and a third drain region of the second conductivity type and a second conductivity type of the second conductivity type are formed on the substrate surface layer with the third gate electrode interposed therebetween. And a second planar electrode having a third drain electrode electrically connected to the third drain region and a third source electrode electrically connected to the third source region. Type MOSFET,
Is a semiconductor device formed on the same semiconductor substrate,
The first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are patterned on the same metal wiring layer. is formed by,
The first source electrode is in contact with a conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the trench, and the conductor is in contact with a barrier metal layer,
The semiconductor device according to claim 1, wherein the barrier metal layer is in contact with the first source region and a plug region of the same conductivity type as the base region provided at the bottom of the trench . The semiconductor device according to claim 1, wherein the first gate electrode, the second gate electrode, and the third gate electrode are formed by patterning the same polysilicon layer. 3. The semiconductor device according to claim 1, wherein a body region having the same conductivity type as that of the base region is provided at a bottom portion of the trench. The semiconductor device according to claim 3, further comprising a body region having the same conductivity type as the base region outside the trench. A first gate oxide film and a first gate electrode in the first trench; a first source region of a second conductivity type at the bottom of the first trench; A first drain region of a second conductivity type on the outside; a first extension drain region and a channel region of the second conductivity type between the first source region and the first drain region; A first drain electrode having a first base region of one conductivity type, electrically connected to the first drain region, and a first source electrode electrically connected to the first source region A first trench lateral power MOSFET that
A second gate oxide film and a second gate electrode in the second trench; a second source region of a first conductivity type at the bottom of the second trench; A second drain region of the first conductivity type is provided outside, and a second extension drain region and a channel region of the first conductivity type are provided between the second source region and the second drain region. A second drain electrode electrically connected to the second drain region; and a second source electrode electrically connected to the second source region. A second trench lateral power MOSFET that
A third gate oxide film and a third gate electrode are provided on the surface of the substrate, and a third drain region of the second conductivity type and a second conductivity type of the second conductivity type are formed on the substrate surface layer with the third gate electrode interposed therebetween. A planar MOSFET having a third source region and a third drain electrode electrically connected to the third drain region and a third source electrode electrically connected to the third source region; ,
Is a semiconductor device formed on the same semiconductor substrate,
The first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are patterned on the same metal wiring layer. Formed by
The first source electrode contacts a first conductor made of an N-type or P-type semiconductor that extends from the substrate surface to the bottom of the trench in the first trench, and the first conductor is a first conductor. In contact with the barrier metal layer,
The first barrier metal layer is in contact with the first source region and a first plug region provided at the bottom of the first trench and having the same conductivity type as the first base region,
The second source electrode is in contact with a second conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the second trench, and the second conductor is a second conductor. In contact with the barrier metal layer,
The second barrier metal layer is in contact with the second source region and a second plug region provided at the bottom of the second trench and having the same conductivity type as the second base region. A semiconductor device characterized by comprising: 6. The semiconductor device according to claim 5, wherein the first gate electrode, the second gate electrode, and the third gate electrode are formed by patterning the same polysilicon layer. 7. The semiconductor device according to claim 5, further comprising a first body region having the same conductivity type as that of the first base region at the bottom of the first trench. 8. The semiconductor device according to claim 7, further comprising: a second body region having the same conductivity type as that of the second base region at the bottom of the second trench. 9. The semiconductor device according to claim 7, further comprising a body region having the same conductivity type as the first base region outside the first trench. 9. The semiconductor device according to claim 8, further comprising a body region having the same conductivity type as that of the second base region outside the second trench. A first gate oxide film and a first gate electrode in the first trench; a first source region of a second conductivity type at the bottom of the first trench; A first drain region of a second conductivity type on the outside; a first extension drain region and a channel region of the second conductivity type between the first source region and the first drain region; A first drain electrode having a first base region of one conductivity type, electrically connected to the first drain region, and a first source electrode electrically connected to the first source region A first trench lateral power MOSFET that
A second gate oxide film and a second gate electrode in the second trench; a second source region of a first conductivity type at the bottom of the second trench; A second drain region of the first conductivity type is provided outside, and a second extension drain region and a channel region of the first conductivity type are provided between the second source region and the second drain region. A second drain electrode electrically connected to the second drain region; and a second source electrode electrically connected to the second source region. A second trench lateral power MOSFET that
A third gate oxide film and a third gate electrode are provided on the surface of the substrate, and a third drain region of the second conductivity type and a second conductivity type of the second conductivity type are formed on the substrate surface layer with the third gate electrode interposed therebetween. And a first planar electrode comprising a third drain electrode electrically connected to the third drain region and a third source electrode electrically connected to the third source region. Type MOSFET,
A fourth gate oxide film and a fourth gate electrode are provided on the surface of the substrate, and a fourth drain region of the first conductivity type and a first conductivity type of the first conductivity type are formed on the substrate surface layer with the fourth gate electrode interposed therebetween. And a second planar electrode having a fourth drain electrode electrically connected to the fourth drain region and a fourth source electrode electrically connected to the fourth source region. Type MOSFET,
Is a semiconductor device formed on the same semiconductor substrate,
The first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the The fourth source electrode is formed by patterning the same metal wiring layer, The first source electrode contacts a first conductor made of an N-type or P-type semiconductor that extends from the substrate surface to the bottom of the trench in the first trench, and the first conductor is a first conductor. In contact with the barrier metal layer,
The first barrier metal layer is in contact with the first source region and a first plug region provided at the bottom of the first trench and having the same conductivity type as the first base region,
The second source electrode is in contact with a second conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the second trench, and the second conductor is a second conductor. In contact with the barrier metal layer,
The second barrier metal layer is in contact with the second source region and a second plug region provided at the bottom of the second trench and having the same conductivity type as the first base region. A semiconductor device. 12. The first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are formed by patterning the same polysilicon layer. The semiconductor device described. 13. The semiconductor device according to claim 11, further comprising a first body region having the same conductivity type as that of the first base region at the bottom of the first trench. The semiconductor device according to claim 13, further comprising a second body region having the same conductivity type as that of the second base region at a bottom portion of the second trench. 15. The semiconductor device according to claim 13, further comprising a body region having the same conductivity type as that of the first base region outside the first trench. The semiconductor device according to claim 14, further comprising a body region having the same conductivity type as the second base region outside the second trench. The semiconductor device according to claim 1, wherein a gate oxide film of the trench lateral power MOSFET is thicker than a gate oxide film of the planar MOSFET. A first gate oxide film and a first gate electrode in the trench; a first source region of a second conductivity type at the bottom of the trench; and a first first of the second conductivity type outside the trench. A first conductivity type base region serving as a second conductivity type extended drain region and a channel region between the first source region and the first drain region; A trench lateral power MOSFET having a first drain electrode electrically connected to one drain region and a first source electrode electrically connected to the first source region; and a second gate on the substrate surface An oxide film and a second gate electrode, and a substrate surface layer sandwiching the second gate electrode, the first conductivity type second drain region and the first conductivity type second source region; Electrical to the second drain region A first planar MOSFET having a second drain electrode to be connected and a second source electrode electrically connected to the second source region; a third gate oxide film and a third gate electrode on the substrate surface; A third drain region of the second conductivity type and a third source region of the second conductivity type on the substrate surface layer across the third gate electrode, and the third drain region A third drain electrode electrically connected to the second source MOSFET and a second planar MOSFET having a third source electrode electrically connected to the third source region are formed on the same semiconductor substrate; The first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the third drain electrode, and the third source electrode are patterned on the same metal wiring layer. By The first source electrode is in contact with a conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the trench, and the conductor is in contact with the barrier metal layer; In manufacturing the semiconductor device in which the barrier metal layer is in contact with the first source region and the plug region of the same conductivity type as the base region, which is provided at the bottom of the trench,
An extended drain forming step of forming the extended drain region in the semiconductor substrate;
A trench forming step for forming the trench after the extended drain forming step;
A base channel forming step for simultaneously forming the base region and the channel region of the second planar MOSFET after the trench forming step;
A first channel forming step for forming a channel region of the first planar MOSFET after the base channel forming step;
A gate oxide film forming step of forming the first gate oxide film, the second gate oxide film, and the third gate oxide film after the first channel forming process;
After the gate oxide film forming step, a gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode;
A first drain / source formation step for simultaneously forming the first drain region, the first source region, the third drain region, and the third source region after the gate electrode formation step;
After the first drain / source formation step, a second drain / source formation step of simultaneously forming the second drain region, the second source region, and the plug region;
After the formation of the second drain / source, an interlayer insulating film is stacked on the entire surface of the substrate, and the interlayer insulating film is etched to expose the first source region and the plug region at the bottom of the trench. When,
A barrier metal forming step of forming a barrier metal layer in contact with the first source region and the plug region inside the trench after the first exposing step;
After the barrier metal forming step, a filling step of filling the trench with polysilicon in contact with the barrier metal layer;
After the filling step, a passivation film is stacked on the entire surface of the substrate, and the passivation film and the interlayer insulating film are etched to form the first drain region, the polysilicon, the second drain region, and the second source. A second exposing step of exposing the region, the third drain region and the third source region;
After the second exposure step, a metal wiring layer is stacked on the passivation film, and the metal wiring layer is patterned to form the first drain region, the polysilicon, the second drain region, the first Two source regions, the third drain region and the first source electrode in contact with the third source region, the first source electrode, the second drain electrode, the second source electrode, An electrode forming step of simultaneously forming the third drain electrode and the third source electrode;
A method for manufacturing a semiconductor device, comprising: After the trench formation step and before the base channel formation step, a body region having the same conductivity type as the base region and an extended drain region having a conductivity type different from the base region are formed outside the trench. The method of manufacturing a semiconductor device according to claim 18, wherein the semiconductor device is formed by double diffusion in order. A first gate oxide film and a first gate electrode in the first trench; a first source region of a second conductivity type at the bottom of the first trench; A first drain region of a second conductivity type on the outside; a first extension drain region and a channel region of the second conductivity type between the first source region and the first drain region; A first drain electrode having a first base region of one conductivity type, electrically connected to the first drain region, and a first source electrode electrically connected to the first source region A first trench lateral power MOSFET, a second gate oxide film and a second gate electrode in the second trench, and a second source region of the first conductivity type at the bottom of the second trench A first conductivity type outside the second trench. A second drain region, and a second conductivity type second that becomes a first conductivity type second extended drain region and a channel region between the second source region and the second drain region. A second trench lateral power having a base region and having a second drain electrode electrically connected to the second drain region and a second source electrode electrically connected to the second source region The MOSFET has a third gate oxide film and a third gate electrode on the substrate surface, and a second drain region and a second conductivity type of the second conductivity type are formed on the substrate surface layer with the third gate electrode interposed therebetween. A planar source having a third source region of a type and having a third drain electrode electrically connected to the third drain region and a third source electrode electrically connected to the third source region Type MOSFET and the same half The first source electrode is formed on a body substrate and is in contact with a first conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the first trench. The conductor contacts the first barrier metal layer, and the first barrier metal layer is the same as the first base region provided in the first source region and the bottom of the first trench. A second conductor made of an N-type or P-type semiconductor extending in the second trench from the substrate surface to the bottom of the trench. The second conductor is in contact with a second barrier metal layer, and the second barrier metal layer is provided at the second source region and at the bottom of the second trench, Second plug region having the same conductivity type as the second base region In manufacturing a semiconductor device in contact with
An extended drain forming step of forming the first extended drain region and the second extended drain region in the semiconductor substrate;
A trench forming step of forming the first trench and the second trench after the extended drain forming step;
A first implantation step of simultaneously implanting a first conductivity type impurity into the region serving as the first base region and the channel region of the planar MOSFET after the trench formation step;
After the first implantation step, a second implantation step of implanting a second conductivity type impurity into a region to be the second base region;
After the second implantation step, the implanted impurity is diffused to simultaneously form the first base region, the second base region, and the channel region of the planar MOSFET, and
A gate oxide film forming step of forming the first gate oxide film, the second gate oxide film, and the third gate oxide film after the base channel forming step;
After the gate oxide film forming step, a gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode;
After the gate oxide film forming step, the region serving as the first drain region, the region serving as the first source region, the region serving as the third drain region, and the region serving as the third source region are simultaneously performed. A third implantation step of implanting impurities of the second conductivity type;
After the third implantation step, a fourth implantation step of implanting a first conductivity type impurity into the region serving as the second drain region and the region serving as the second source region;
After the fourth implantation step, the implanted impurities are diffused to form the first drain region, the first source region, the second drain region, the second source region, and the third drain. A drain / source formation step of simultaneously forming a region, the third source region, the first plug region, and the second plug region;
After the drain / source formation step, an interlayer insulating film is stacked on the entire surface of the substrate, and the interlayer insulating film is etched to form the first source region and the second trench bottom at the first source region and the second trench bottom, respectively. A first exposing step of exposing the first plug region, the second source region, and the second plug region;
After the first exposure step, a first barrier metal layer in contact with the first source region and the first plug region, respectively, inside the first trench and inside the second trench, and A barrier metal forming step of forming a second barrier metal layer in contact with the second source region and the second plug region;
After the barrier metal forming step, the first polysilicon that contacts the first barrier metal layer and the second barrier metal layer in the first trench and the second trench respectively. Filling process of filling with polysilicon 2;
After the filling step, a passivation film is stacked on the entire surface of the substrate, and the passivation film and the interlayer insulating film are etched to form the first drain region, the first polysilicon, the second drain region, the first A second exposure step of exposing the second polysilicon, the third drain region, and the third source region;
After the second exposure step, a metal wiring layer is stacked on the passivation film, and the metal wiring layer is patterned to form the first drain region, the first polysilicon, and the second drain region. , The second polysilicon, the first drain electrode, the first source electrode, the second drain electrode, and the second drain electrode that are in contact with the third drain region and the third source region, respectively. An electrode forming step of simultaneously forming a source electrode, the third drain electrode, and the third source electrode;
A method for manufacturing a semiconductor device, comprising: After the trench formation step and before the first implantation step, the first conductivity type body region and the second conductivity type extended drain region are double diffused in this order outside the first trench. 21. The method of manufacturing a semiconductor device according to claim 20, wherein After the trench formation step and before the second implantation step, the second conductivity type body region and the first conductivity type extended drain region are double diffused in this order outside the second trench. The method of manufacturing a semiconductor device according to claim 21, wherein: A first gate oxide film and a first gate electrode in the first trench; a first source region of a second conductivity type at the bottom of the first trench; A first drain region of a second conductivity type on the outside; a first extension drain region and a channel region of the second conductivity type between the first source region and the first drain region; A first drain electrode having a first base region of one conductivity type, electrically connected to the first drain region, and a first source electrode electrically connected to the first source region A first trench lateral power MOSFET, a second gate oxide film and a second gate electrode in the second trench, and a second source region of the first conductivity type at the bottom of the second trench A first conductivity type outside the second trench. A second drain region, and a second conductivity type second that becomes a first conductivity type second extended drain region and a channel region between the second source region and the second drain region. A second trench lateral power having a base region and having a second drain electrode electrically connected to the second drain region and a second source electrode electrically connected to the second source region The MOSFET has a third gate oxide film and a third gate electrode on the substrate surface, and a second drain region and a second conductivity type of the second conductivity type are formed on the substrate surface layer with the third gate electrode interposed therebetween. A third drain electrode having a third source region of a type and having a third drain electrode electrically connected to the third drain region and a third source electrode electrically connected to the third source region; 1 planar MOSFET and base A fourth gate oxide film and a fourth gate electrode are provided on the surface, and a fourth drain region of the first conductivity type and a fourth drain of the first conductivity type are formed on the substrate surface layer with the fourth gate electrode interposed therebetween. A second planar type comprising a fourth drain electrode electrically connected to the fourth drain region and a fourth source electrode electrically connected to the fourth source region MOSFETs are formed on the same semiconductor substrate, and the first source electrode is in contact with a first conductor made of an N-type or P-type semiconductor that extends in the first trench from the substrate surface to the bottom of the trench. The first conductor is in contact with the first barrier metal layer, and the first barrier metal layer is provided at the first source region and at the bottom of the first trench. First plug region of the same conductivity type as the base region of The second source electrode is in contact with a second conductor made of an N-type or P-type semiconductor extending from the substrate surface to the bottom of the trench in the second trench, and the second source electrode The conductor contacts the second barrier metal layer, and the second barrier metal layer has the same conductivity as the second base region provided at the bottom of the second source region and the second trench. In manufacturing a semiconductor device in contact with the second plug region of the mold,
An extended drain forming step of forming the first extended drain region and the second extended drain region in the semiconductor substrate;
A trench forming step of forming the first trench and the second trench after the extended drain forming step;
A first base channel forming step for simultaneously forming the first base region and the channel region of the first planar MOSFET after the trench forming step;
A second base channel forming step of simultaneously forming the second base region and the channel region of the second planar MOSFET after the first base channel forming step;
A gate oxide film forming step of forming the first gate oxide film, the second gate oxide film, the third gate oxide film, and the fourth gate oxide film after forming the second base channel; ,
After the gate oxide film forming step, a gate electrode forming step of forming the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode;
After the gate electrode forming step, the first drain region, the first source region, the third drain region, the third source region, and the second plug region are formed simultaneously.・ Source formation process,
After the first drain / source formation step, the second drain region, the second source region, the fourth drain region, the fourth source region, and the second plug region are simultaneously formed. 2 drain / source formation steps;
After the second drain / source formation step, an interlayer insulating film is stacked on the entire surface of the substrate, and the interlayer insulating film is etched to form the first source region at the bottom of the first trench and the bottom of the second trench, respectively. A first exposing step of exposing the first plug region, the second source region, and the second plug region;
A first barrier metal layer in contact with the first source region and the first plug region, respectively, inside the first trench and inside the second trench after the first exposing step; A barrier metal formation step of forming a second barrier metal layer in contact with the second source region and the second plug region;
After the barrier metal forming step, the first polysilicon that contacts the first barrier metal layer and the second barrier metal layer in the first trench and the second trench respectively. Filling process of filling with polysilicon 2;
After the filling step, a passivation film is stacked on the entire surface of the substrate, and the passivation film and the interlayer insulating film are etched to form the first drain region, the first polysilicon, the second drain region, the first A second exposure step of exposing the second polysilicon, the third drain region, the third source region, the fourth drain region, and the fourth source region;
After the second exposure step, a metal wiring layer is stacked on the passivation film, and the metal wiring layer is patterned to form the first drain region, the first polysilicon, and the second drain region. , The second polysilicon, the third drain region, the third source region, the fourth drain region, and the first source electrode in contact with the fourth source region, the first drain electrode, Electrode formation for simultaneously forming a source electrode, the second drain electrode, the second source electrode, the third drain electrode, the third source electrode, the fourth drain electrode, and the fourth source electrode Process,
A method for manufacturing a semiconductor device, comprising: After the trench forming step and before the first base channel forming step, the body region of the first conductivity type and the first extended drain region are formed in this order on the outside of the first trench. The method of manufacturing a semiconductor device according to claim 23, wherein the semiconductor device is formed by heavy diffusion. After the trench formation step and before the second base channel formation step, the second conductivity type body region and the second extended drain region are formed in this order on the outside of the second trench. The method of manufacturing a semiconductor device according to claim 24, wherein the semiconductor device is formed by heavy diffusion.

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