JP4488293B2 - Plasma display panel drive device - Google Patents

Description

  The present invention relates to a plasma display panel driving apparatus.

As a display panel for a large screen, a plasma display panel (hereinafter abbreviated as PDP) is known. The PDP needs a drive circuit that can supply a high voltage and a large current.
The AC type PDP discharges a large number of address electrodes arranged in the column direction and a large number of scan electrodes and sustain electrodes arranged in parallel in the row direction so as to form a pair so as to be separated from and intersect the address electrodes. Opposing across the gas space, applying a voltage between the address electrode and the selection electrode of the scan electrode to perform addressing, and applying a sustain pulse voltage between the scan electrode and the sustain electrode to perform a sustain discharge It is configured.

A scan driver circuit is provided on the scan electrode side, and a scan electrode drive circuit is provided on the preceding stage. This scan electrode driving circuit is composed of a sustain circuit, a power recovery circuit, a separation circuit, a reset voltage generation circuit, a scan voltage generation circuit, a coil and a recovery capacitor, and the sustain circuit and the power recovery circuit are incorporated in one semiconductor power module. It is.
A sustain electrode drive circuit is provided on the sustain electrode side. This sustain electrode driving circuit is constituted by a sustain circuit, a power recovery circuit, a coil and a recovery capacitor, and the sustain circuit and the power recovery circuit are incorporated in one semiconductor power module.

  A period in which a sustain discharge is performed by applying a sustain pulse voltage VSUS that is alternately inverted between a sustain electrode (hereinafter referred to as an electrode X) and a scan electrode (hereinafter referred to as an electrode Y) by the two sustain circuits and the two power recovery circuits. Since the PDP is actually discharged, the power supplied to the panel is the largest, the peak current is about 200 A in the wiring through which the sustain pulse voltage VSUS flows, and the peak current is in the wiring of each power recovery circuit. A large current of about 50A flows. The voltage waveform of the sustain pulse voltage VSUS has a voltage of 170 V and a period of about 5 μs.

  In order to cope with the above-mentioned large peak current and at the same time suppress the power loss, both the sustain circuit, the power recovery circuit, and the switching element and the diode in the separation circuit are used by connecting a plurality of elements in parallel. When a power module is substituted, a plurality of modules are installed on each drive board according to the number of switch elements. These switch elements use power MOSFETs or fast recovery diodes suitable for high-speed operation.

Further, since the sustain pulse current has a large di / dt, radiation noise is generated due to induction caused by the pulse current. An example of a semiconductor power module used in such a sustain circuit through which a sustain pulse current flows is described in Japanese Patent Application Laid-Open No. 2000-89724.
In this publication, a pulse circuit through which a large current and a large voltage flow in a sustain circuit in a semiconductor power module, that is, the number of push-pull circuits in which two switch elements are connected in series is controlled to control on / off of the push-pull circuit. More than the number of circuits. As a result, the generation of noise is reduced by reducing the current flowing through each pulse circuit, and the control circuit is less likely to malfunction due to the influence of noise.

Another example of reducing the inductance and unnecessary radiation generated in the semiconductor power module and the drive board is described in Japanese Patent Application Laid-Open No. 2000-221938.
The semiconductor power module of this publication is composed of three metal plates with an insulating film provided between the wiring pattern and the metal plate, and is folded between the first and second metal plates and between the second and third metal plates. The large current switch element is arranged in the wiring pattern on the second metal plate. In addition, the drive board is configured to have an insulating plate, a metal plate on both sides of the insulating plate, an insulating film on the metal plate, and a wiring pattern on the insulating film. The wiring pattern is formed on both sides of the driving board. The wiring pattern on one side of the drive substrate and the wiring pattern on the semiconductor power module are connected, and the circuit component is mounted on the wiring pattern on the other side. A metal substrate is placed next to the wiring pattern, and an eddy current flows in the metal substrate due to the magnetic field generated by the current flowing in the wiring pattern. The eddy current generates a magnetic field in the opposite direction, which is generated by the current flowing in the wiring pattern. The magnetic field is canceled and the inductance is reduced.
JP 2000-89724 A JP 2000-221938 A

  In the example described in the above Japanese Patent Laid-Open No. 2000-89724, since a plurality of sustain circuits are arranged in a module, chip arrangement and wiring layout must be complicated. Although an example in which the sustain circuit and the reset circuit are arranged in the module is shown, the separation circuit is also a circuit through which a large current flows, and if these are taken into the module, the same number of separation circuits are provided for each pulse circuit. If they are not arranged, the effects of the circuit described in this publication cannot be obtained, and the circuit configuration of the module is further complicated. In addition, although this publication is effective for countermeasures against noise inside the module, it is not effective for noise generated by high-speed, high-current pulses on the drive board on which the module is installed.

Moreover, in the example described in the above Japanese Patent Laid-Open No. 2000-221938, it is necessary to cover the entire surface of the semiconductor power module with a metal substrate including a connection terminal for electrically connecting the driving substrate and the module. The structure becomes complicated. In order to form the metal substrate in a U-shape, a special assembly process is required.
Also, the drive board is usually used because it has a configuration in which an insulating plate is sandwiched between two metal plates, an insulating film is arranged so that the metal plates are sandwiched, and a wiring pattern is arranged on the insulating film. A four-layer board or the like cannot be used. Furthermore, although it is necessary to arrange components on both sides of the board, a through hole cannot be made because the metal board is inserted, and electrical connection between both sides cannot be made. When components are arranged on both sides of the substrate, a space corresponding to the height of the components is required when the substrate is connected to the plasma display device, and the thinness that is a feature of the plasma display device cannot be realized.

Further, even when all components are arranged on one side, it is necessary to increase the board area in order to mount all the components on one side. Furthermore, the wiring pattern on the substrate is complicated and the wiring resistance increases, which adversely affects the characteristics of the plasma display panel.
The object of the present invention is to solve the above-mentioned drawbacks, reduce the influence of high speed and large current flowing in the output circuit, and reduce the radiation noise generated in the wiring pattern on the drive substrate. Is to provide.

In order to achieve the above object, a plasma display panel driving apparatus according to the present invention includes a scan electrode driving circuit having a first sustain circuit, a first power recovery circuit, and a separation circuit on a scan electrode side of the plasma display panel, and a discharge sustaining electrode. A plasma display panel driving device comprising a discharge sustaining electrode driving circuit having a second sustain circuit and a second power recovery circuit on one side, and one end side of a first substrate constituting a part of the scanning electrode driving circuit The first sustain circuit is disposed on the other end, the separation circuit is disposed opposite the first sustain circuit, and the first power recovery circuit is disposed on the first substrate separated from the first sustain circuit and the separation circuit. In addition, a plurality of terminals of the first sustain circuit and the separation circuit are arranged close to the end of the first substrate to form a first semiconductor module, and the discharge sustaining electrode A second sustain circuit is arranged on one end side of the second substrate constituting a part of the dynamic circuit, and a second power recovery circuit is arranged on the other end side, and a plurality of second sustain circuits and second power recovery circuits are arranged. A terminal is arranged close to the end of the second substrate to form a second semiconductor module. In the first semiconductor module, the first, second, and third conductive lands are provided on one end side of the first substrate , and the other end side. fourth, fifth conductive lands formed, a first conductive land, with mounting the switching elements constituting the first sustain circuit respectively to the second conductive lands, the first conductive land is one of the terminals The sustain power supply terminal is provided, and the second conductive land is provided with an output terminal which is one of the terminals. The second conductive land is partly adjacent to the switching element of the first conductive land, and the second conductive land Switching element A ground terminal, which is one of the terminals, is provided in the third conductive land, the switching element of the first conductive land and the second conductive land are connected by a wire, and the second conductive land The switching element and the third conductive land are connected by a wire, the sustain power supply terminal, the output terminal and the ground terminal are arranged in a line along the end of the first substrate, and separated into the fourth conductive land. In the switching element, the switching element constituting the circuit is mounted, the reset voltage terminal is provided, and the current path of the reset voltage generation circuit for discharging the entire surface of the plasma display panel and the first sustain circuit is separated during the reset period. The first separation switching element is disposed close to the second conductive land, and the scan electrode is selected during the address period. Separating the-option electrode and the scan voltage generating circuit for supplying a scan voltage to the current path of said reset voltage generating circuit, and arranging the second separation switching elements in the switching element in proximity to the fifth conductive lands, the A scan voltage terminal is provided on the five conductive land , the second conductive land and the first separated switching element are connected by a wire, the fifth conductive land and the second separated switching element are connected by a wire, and the reset voltage terminal and the The scan voltage terminals are arranged in a row along the other end of the first substrate, and in the second semiconductor module, sixth, seventh, eighth, and ninth conductive lands are formed on one end side of the second substrate. In addition, the switching elements constituting the second sustain circuit are mounted on the sixth conductive land and the eighth conductive land, respectively, and the terminal of the terminal is provided on the sixth conductive land. A sustain power supply terminal which is one of the terminals, and an output terminal which is one of the terminals is provided in the eighth conductive land, and the seventh conductive land is disposed in the vicinity of the sixth conductive land, and is an output which is one of the terminals. A terminal is provided and connected to the switching element by a wire, the ninth conductive land is disposed close to the eighth conductive land , a ground terminal which is one of the terminals is provided, and the switching element and the wire The sustain power terminal, the two output terminals, and the ground terminal are arranged in a row along one end of the second substrate, and the second conductive land is partly adjacent to the switching element of the first conductive land. Therefore, the output terminal of the second conductive land is provided on the other end side of the first conductive land opposite to the one end side where the sustain power supply terminal is provided. The ground terminal of the third conductive land is arranged so that the portion bent and formed into an L-shape is closely opposed and the switching element of the second conductive land is close to the third conductive land. On the other end side opposite to the provided one end side, the portion where the output terminal of the second conductive land is provided is extended and the portion bent in the opposite direction to the portion bent in the L shape is the switching In order to make the element mounting portion close to each other, and to arrange the first separation switching element close to the second conductive land, the end of the second conductive land on the fourth conductive land side A scan voltage terminal of the fifth conductive land is provided in order to face the end of the four conductive lands close to the first separated switching element and to place the second separated switching element close to the fifth conductive land. Has been Since the end of the fourth conductive land on the second separation switching element side is closely opposed to the other end opposite to the one end, the seventh conductive land is disposed close to the sixth conductive land. A portion of the sixth conductive land where the sustain power supply terminal is provided is extended to the other end opposite to the one end where the output terminal of the conductive land is provided. In order to dispose the ninth conductive land close to the eighth conductive land, the eighth conductive land is disposed on the other end of the ninth conductive land opposite to the one end where the ground terminal is provided. The portion provided with the output terminal is extended and the portions bent in an L shape are made to face each other in close proximity, all the switching elements are composed of power MOSFETs, and the interval between each conductive land is 1 to 10 mm. The length of the wire Characterized in that is 6 to 10 mm.

In addition, a first drive board for mounting the first semiconductor module is provided, and a capacitor for stabilizing the power supply is provided on the first drive board in the vicinity of the sustain power supply terminal provided on the first board and provided on the first board. A connector for connecting to a scan driver circuit existing between the scan electrode and the scan electrode drive circuit is provided in the immediate vicinity of the output terminal, and a second drive board for mounting a second semiconductor module is provided. A capacitor for stabilizing the power supply is provided on the substrate in the vicinity of the sustain power supply terminal provided on the second substrate, and a connector for connecting to the discharge sustaining electrode is provided in the immediate vicinity of the output terminal provided on the second substrate. It is characterized by.

Further, the first drive substrate has a two-layer structure, and a ground pattern portion and a wiring pattern portion for supplying a large current pulse supplied from the power stabilization capacitor to the first substrate side are provided in the second layer. A wiring pattern part for supplying a large current pulse output from the first board side to the connection connector is provided as the second board mounting part.
The first drive substrate has a two-layer structure, and a ground pattern portion is provided in the second layer and a wiring pattern portion for supplying a large current pulse supplied from the power stabilization capacitor to the first substrate side is provided. In addition to the second substrate mounting portion, a wiring pattern portion for supplying a large current pulse output from the first substrate side to the connection connector is provided.

Also, ground terminals for electrical connection with the ground pattern portion of the first drive substrate are provided at the four ends of the first substrate, and ground terminals for electrical connection with the ground pattern portion of the second drive substrate are provided. It is provided at the four ends of two substrates.

Further, a heat sink is attached to the other main surface of the first substrate, the heat sink is electrically connected to the ground of the first substrate, and a heat sink is attached to the other main surface of the second substrate. It is electrically connected to the ground of the second substrate.

  According to the plasma display panel driving apparatus of the present invention, the path through which the sustain pulse current flows on the second substrate that supplies the large current pulse to the sustain electrode of the plasma display panel and the first substrate that supplies the large current pulse to the scan electrode. Are all formed in the substrate, the large current wiring pattern on the driving substrate can be made very simple, and the wiring layout and circuit configuration of the driving substrate can be simplified. In addition, since the sustain pulse current path in the first substrate and the second substrate is formed by the shortest path, it is possible to reduce the parasitic inductance in the wiring pattern and to reduce the voltage drop due to the wiring pattern routing.

  In addition, a first sustain circuit is disposed on one end side of the first substrate, a separation circuit is disposed on the other end side so as to face the first sustain circuit, and a plurality of terminals of the first sustain circuit and the separation circuit are connected to the first substrate. The second sustain circuit is arranged on one end side of the second substrate, the second power recovery circuit is arranged on the other end side, and a plurality of terminals of the second sustain circuit and the second power recovery circuit are arranged. Since it is arranged close to the end of the second substrate, radiation noise generated by a large current pulse can be reduced.

Also, the high-current wiring pattern on the driving substrate can be made very simple, the wiring layout and circuit configuration on the driving substrate can be simplified, and radiation generated by high-speed, high-current pulses on the driving substrate can be simplified. Noise can be reduced.
In addition, the drive substrate to which the substrate is attached can be configured with a two-layer structure, and the cost can be reduced.

  In addition, an earth current equivalent to the earth pattern portion of the substrate can be passed through the heat sink, and the earth current flowing on the substrate can be reduced, and radiation noise generated on the substrate can be reduced.

Hereinafter, embodiments of the present invention will be described using examples. Here, the module refers to a semiconductor power module.
(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a plasma display apparatus according to an embodiment of the present invention. In addition, in each figure, what has the same function is given the same reference number, and the detailed description is abbreviate | omitted.

  In the PDP 101, sustain electrodes X1 to Xn are arranged in parallel with the scan electrodes Y1 to Yn, respectively, and address electrodes A1 to Am are arranged so as to be spaced apart from each other, and m × n Pixels are formed in a matrix. The electrodes X1 to Xn are connected in common at one end. Hereinafter, the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn are collectively referred to as an electrode A, an electrode X, and an electrode Y, respectively.

The address driver circuit 102 is connected to the electrode A and applies a predetermined high voltage pulse based on a signal from the waveform control circuit 103.
An X-side electrode drive substrate 10 is connected to the electrode X. The X-side electrode drive substrate 10 mainly includes a sustain circuit 11, a power recovery circuit 12, a coil 21, and a recovery capacitor 22.

  The sustain circuit 11 includes switch elements 13 and 14 and a high-side driver IC 19. The switch elements 13 and 14 form a push-pull circuit, and the high-side driver IC 19 controls on / off of the switch elements 13 and 14. The common output portion of the push-pull circuit is connected to the electrode X, and the sustain pulse voltage VSUS for sustain discharge for causing the PDP to display and emit light is applied to the other output terminal of the upper arm side switch element 13, and the lower arm side switch element 14 The other output terminal is grounded. The high side driver IC 19 is driven based on the signal from the waveform control circuit 103 to apply the sustain pulse voltage VSUS to the electrode X.

  The power recovery circuit 12 includes switch elements 15 and 16, diodes 17 and 18, and a high side driver IC 20. One end of the recovery capacitor 22 is grounded, and the other end is connected to one end of the output of the switch element 15 of the power recovery circuit 12 and one end of the output of the switch element 16. The other end of the output of the switch element 15 is connected to the input end of the diode 17, and the other end of the output of the switch element 16 is connected to the output end of the diode 18. The output terminal of the diode 17 and the input terminal of the diode 18 are connected in common and connected to one end of the coil 21 to serve as an output unit of the power recovery circuit 12. The other end of the coil 21 is connected to the output part of the sustain circuit 11. The switch elements 15 and 16 are controlled to be turned on / off by the high side driver IC 20. The high-side driver IC 20 is driven based on the signal from the waveform control circuit 103, and charges accumulated in the recovery capacitor 22 are supplied to the electrode X via the coil 21 and the output part of the sustain circuit 11. Further, the charge from the electrode X is accumulated in the recovery capacitor 22.

The sustain circuit 11 and the power recovery circuit 12 on the X-side electrode drive substrate 10 are configured by a second semiconductor power module 23.
On the other hand, a scan driver circuit 117 is connected to the electrode Y. Based on the signal from the waveform control circuit 103, the scan driver circuit 117 selectively outputs the voltage applied from the Y-side electrode drive substrate 1 to the electrodes Y1 to Yn.

  The Y-side electrode drive substrate 1 mainly includes a scan voltage generation circuit 2, a reset voltage generation circuit 3, a separation circuit 4, a sustain circuit 11 of the X-side electrode substrate, a sustain circuit 5 having the same configuration as the power recovery circuit 12, and a power recovery circuit 6 , Coil 7 and recovery capacitor 8. The scan voltage generation circuit 2 sequentially selects and outputs the scan voltage VSCN to the electrodes Y1 to Yn via the scan driver circuit 117. The reset voltage generation circuit 3 outputs the reset voltage VSET to the electrodes Y1 to Yn via the separation circuit 4 and the scan driver circuit 117. The sustain circuit 5 outputs a sustain pulse voltage VSUS to the electrodes Y1 to Yn via the separation circuit 4 and the scan driver circuit 117 based on the signal from the waveform control circuit 103. The separation circuit 4 plays a role of separating the circuit so that a high voltage such as a voltage applied from the scan voltage generation circuit 2 and the reset voltage generation circuit 3 is not output to the sustain circuit 5 side during the sustain discharge period. The separation circuit 4, the sustain circuit 5, and the power recovery circuit 6 on the Y-side electrode drive substrate 1 are configured by a first semiconductor power module 9.

  Next, FIG. 2 shows an example of a timing chart of the driving circuit of the plasma display device according to the present invention. First, the reset voltage VSET generated by the reset voltage generating circuit 3 is applied to the electrode Y during the reset period, and the entire surface is discharged between the electrode X and the electrode Y. Next, the scan voltage VSCN generated by the scan voltage generation circuit 2 in the address period is applied to the selection electrode of the electrode Y via the scan driver circuit 117, and the address driver circuit 102 applies the address voltage VAD to the selection electrode of the electrode A. The discharge cell is selected by applying an address discharge between the electrode Y and the electrode A. Thereafter, during the sustain discharge period, the sustain circuits 11 and 5 apply the sustain pulse voltage VSUS that is alternately inverted between the electrodes X and Y to perform the sustain discharge, whereby the light emission display on the PDP 101 is performed. In the next erasing period, the erasing voltage Ve is applied to the electrode X to extinguish the sustain discharge.

A subfield consisting of the reset period, address period, sustain discharge period, and erase period as described above is combined multiple times to form one field, and the number of sustain discharges in each subfield is changed to weight the luminance. The key is displayed.
FIG. 3 is an equivalent circuit diagram of an embodiment of a pair of semiconductor power modules according to the present invention.
FIG. 3A shows the second semiconductor power module 23, and FIG. 3B shows the first semiconductor power module 9.

  In FIG. 3A, a portion surrounded by a broken line 11 is a sustain circuit, and a portion surrounded by a broken line 12 is a power recovery circuit. FIG. 3A shows only main components of each circuit. Reference numerals 13, 14, 15, and 16 denote switch elements. In this embodiment, an example using a power MOSFET is shown. Reference numerals 17 and 18 denote diodes. Each switch element and diode use a plurality of elements in parallel connection according to their current ratings, but the elements connected in parallel are not shown here because they are shown as equivalent circuits.

  The power MOSFETs 13 and 14 of the sustain circuit 11 form a push-pull circuit. The drain terminal of the upper arm switch element 13 is connected to the sustain power supply terminal SUS to which the sustain pulse voltage VSUS is applied, and the source terminal is connected to the terminal OUTH. . The source terminal of the lower arm switch element 14 is connected to the power ground terminal PGND to which the ground potential is applied, and the drain terminal is connected to the terminal OUTL. The terminal OUTH and the terminal OUTL are commonly connected outside the module and are connected to one terminal of the coil 21.

The gate terminals of the power MOSFETs 13 and 14 are respectively connected to two output terminals of the high side driver IC 19, and the on / off states of the power MOSFETs 13 and 14 are controlled by output signals from the high side driver IC 19. Signals from the waveform control circuit 103 are input to the two input terminals MH and ML of the high side driver IC 19.
The drain terminal of the power MOSFET 15 of the power recovery circuit 12 is connected to the terminal PC1, the source terminal of the power MOSFET 16 is connected to the terminal PC2, and the terminals PC1 and PC2 are commonly connected outside the module and connected to the recovery capacitor 22. The source terminal of power MOSFET 15 is connected to the anode terminal of diode 17, and the cathode terminal of diode 17 is connected to terminal PL1. The drain terminal of power MOSFET 16 is connected to the cathode terminal of diode 18, and the anode terminal of diode 18 is connected to terminal PL2. Terminals PL1 and PL2 are commonly connected outside the module and connected to the other terminal of the coil 21. The gate terminals of the power MOSFETs 15 and 16 are connected to the two output terminals of the high side driver IC 20, and on / off of the power MOSFETs 15 and 16 is controlled by the output signal from the high side driver IC 20. Signals from the waveform control circuit 103 are input to the two input terminals SH and SL of the high side driver IC02.

With the above configuration, the sustain pulse current applied from the terminal SUS during the sustain discharge period passes through the power MOSFET 13 and is output from the terminal OUTH and output to the electrode X. The sustain pulse current output from the electrode X is supplied from the terminal OUTL into the module, passes through the power MOSFET 14, and is output from the terminal PGND to the ground.
Since all the paths through which the sustain pulse current flows on the X-side electrode substrate are formed in the second semiconductor power module 23, the large current wiring pattern on the driving substrate can be made extremely simple, and the wiring layout and circuit of the driving substrate can be achieved. It is possible to simplify the configuration. In the present embodiment, an example is shown in which all the high-side driver ICs for controlling on / off of each switch element are arranged in the module. However, the high-side driver ICs are arranged on a driving board outside the module, and each high-side driver IC is arranged. Even if the terminal for applying the output control signal from the side driver IC is provided in the module to drive each switch element, the effect of the present invention is not impaired.

  On the other hand, in FIG. 3B, the part surrounded by the broken line 4 is the separation circuit, the part surrounded by the broken line 5 is the sustain circuit, and the part surrounded by the broken line 6 is the power recovery circuit. FIG. 3B shows only the main components of each circuit. Reference numerals 24, 25, 26, 27, 30, and 31 are switch elements. In this embodiment, an example using a power MOSFET is shown. 28 and 29 are diodes. Each switch element and diode use a plurality of elements in parallel connection according to their current ratings, but the elements connected in parallel are not shown here because they are shown as equivalent circuits.

  The power MOSFETs 24 and 25 of the sustain circuit 5 form a push-pull circuit, the drain terminal of the upper arm switch element 24 is connected to the sustain power supply terminal SUS to which the sustain pulse voltage VSUS is applied, and the source terminal of the lower arm switch element 25 is Connected to a power ground terminal PGND to which a ground potential is applied, the source terminal of the upper arm switch element 24 and the drain terminal of the lower arm switch element 25 are connected in common, and a terminal OUT connected to one terminal of the coil 7 outside the module. Connected to.

The gate terminals of the power MOSFETs 24 and 25 are connected to the two output terminals of the high side driver IC 32, respectively, and on / off of the power MOSFETs 24 and 25 is controlled by the output signal from the high side driver IC 32. Signals from the waveform control circuit 103 are input to the two input terminals MH and ML of the high side driver IC 32.
The drain terminals of the power MOSFETs 30 and 31 of the separation circuit 4 are connected in common, and are connected to a terminal SET that serves as a sub output terminal when the reset voltage VSET from the reset voltage generation circuit 3 is applied. The source terminal of the power MOSFET 30 is connected to the terminal OUT. The source terminal of the power MOSFET 31 is connected to the terminal SCN that is commonly connected to the scan voltage generation circuit and the scan driver circuit 117 outside the module and serves as a main output terminal. The gate terminals of the power MOSFETs 30 and 31 are connected to the output terminals of the high side driver ICs 33 and 34, respectively, and on / off of the power MOSFETs 30 and 31 is controlled by output signals from the high side driver ICs 33 and 34. Signals from the waveform control circuit 103 are input to the input terminals PH and EL of the high-side driver ICs 33 and 34, respectively.

  The drain terminal of the power MOSFET 26 of the power recovery circuit 6 is connected to the terminal PC1, the source terminal of the power MOSFET 27 is connected to the terminal PC2, and the terminals PC1 and PC2 are commonly connected outside the module and connected to the recovery capacitor 8. The source terminal of power MOSFET 26 is connected to the anode terminal of diode 28, and the cathode terminal of diode 28 is connected to terminal PL1. The drain terminal of power MOSFET 27 is connected to the cathode terminal of diode 29, and the anode terminal of diode 29 is connected to terminal PL2. Terminals PL1 and PL2 are commonly connected outside the module and connected to the other terminal of the coil 7. The gate terminals of the power MOSFETs 26 and 27 are connected to the two output terminals of the high side driver IC 35, and the on / off states of the power MOSFETs 26 and 27 are controlled by output signals from the high side driver IC 35. Signals from the waveform control circuit 103 are input to the two input terminals SH and SL of the high side driver IC 35.

  With the above configuration, the sustain pulse current applied from the terminal SUS during the sustain discharge period is output from the terminal SCN through the power MOSFETs 24, 30, and 31, and is output to the scan driver circuit. Conversely, the sustain pulse current output from the scan driver circuit is supplied from the terminal SCN to the module, passes through the power MOSFETs 31, 30, 25, and is output from the terminal PGND to the drive substrate ground.

  Since all the paths through which the sustain pulse current flows on the Y-side electrode substrate are formed in the first semiconductor power module 9, a large current wiring pattern on the driving substrate can be extremely simplified, and the wiring layout and circuit of the driving substrate can be achieved. It is possible to simplify the configuration. In this embodiment, an example is shown in which all the high-side driver ICs for controlling on / off of each switch element are arranged in the module. However, the high-side driver ICs are arranged on a driving board outside the module, and Even if the terminal for applying the output control signal from the side driver IC is provided in the module to drive each switch element, the effect of the present invention is not impaired.

FIG. 4 is a plan transparent view of an embodiment of a pair of semiconductor power modules according to the present invention. 4A shows the second semiconductor power module 23, and FIG. 4B shows the first semiconductor power module 9.
In FIG. 4, 47a and 47b are metal base printed boards, and a circuit pattern (conductive land) made of a copper material is arranged on an electrically insulating layer arranged on one main surface of the metal board, and circuit components are arranged. The configuration is implemented. The power MOSFETs 13-16, 24-27, 30, 31 and the diodes 17, 18, 28, 29 are conductive lands (sixth conductive land 36, seventh conductive land 37, eighth conductive land 38, ninth conductive land 39, 1 conductive land 42, 2nd conductive land 43, 3rd conductive land 46, 4th conductive land 44, 5th conductive land 45, and other conductive lands) fixed at predetermined positions with solder or the like and electrically connected. . Although omitted in the figure, a heat spreader (heat dissipating metal base) may be inserted between the power MOSFET and the conductive land for the purpose of improving heat dissipation. Further, the surface electrodes of the power MOSFET and the diode are electrically connected to the conductive land by a plurality of source wires, respectively.

  In the second semiconductor power module of FIG. 4A, the external connection terminals are arranged in a row on the long side of the module that hits the left and right sides. Sustain circuit terminals SUS, OUTH, OUTL and PGND are arranged in order from the top on the left long side of the drawing, and a plurality of input / output terminals PC2, PL2, PL1, A terminal OUT electrically connected to the PC1 and OUTL, and a plurality of control terminals (not shown) for performing on / off control of the switch elements of the sustain circuit and the power recovery circuit are arranged in a line.

  First, the arrangement of the left long side will be described. A plurality of power MOSFETs 13 are arranged in a row on a conductive land 36 electrically connected to the terminal SUS, and source wires 40 of the plurality of power MOSFETs 13 are electrically connected on a conductive land 37. The conductive land 37 is electrically connected to the terminal OUTH. A plurality of power MOSFETs 14 are arranged in a row on the conductive lands 38 electrically connected to the terminal OUTL, and the source wires 41 of the plurality of power MOSFETs 14 are electrically connected on the conductive lands 39. The conductive land 39 is electrically connected to the terminal PGND.

  The conductive lands 36 to 39 are arranged close to the electrically connected terminals SUS, OUTH, OUTL, and PGND, respectively, and the insulating distance between the conductive lands 36 and the conductive lands 37 where the plurality of power MOSFETs 13 are arranged is 1 mm. In other words, the conductive lands 38 on which the plurality of power MOSFETs 14 are arranged and the circuit pattern 39 are arranged in a straight line or in a rectangle with a short distance so that the insulation distance is 1 mm to 10 mm. In addition, 1 mm is preferable.

  Further, the plurality of power MOSFETs 13 are disposed on the conductive land 36 at positions where the wiring length of the source wire 40 for electrically connecting the surface electrodes and the conductive land 37 is 6 to 10 mm. The MOSFET 14 is installed on the conductive land 38 at a position where the wiring length of the source wire 41 for electrically connecting each surface electrode and the conductive land 39 is 6 to 10 mm. The number of source wires 40 and 41 is more than the number calculated from the rated current of each power MOSFET. For example, if the rated current of the power MOSFET is 50 A and the fusing current per source wire is 25 A, three wires are sufficient, but by hitting 5 to 10 wires, the parasitic inductance in the metal thin wire is reduced.

  On the other hand, a plurality of input / output terminals PC2, PL2, PL1, and PC1 of the power recovery circuit are arranged on the right long side as shown in FIG. 4A, and the power MOSFETs 15 and 16 and the diodes 17 and 17 are disposed on the conductive lands. 18 is arranged, and each conductive land and the semiconductor element are electrically connected by a source wire. A terminal OUT electrically connected to the terminal OUTL is also disposed. Further, a plurality of control terminals of a control circuit that performs on / off control of the switch elements of the sustain circuit and the power recovery circuit are arranged. Since a large current such as a sustain pulse current does not flow through each terminal on the right long side and the conductive land, and the parasitic inductance does not adversely affect the plasma display panel, a detailed description is omitted.

Since the seventh conductive land 37 is disposed close to the sixth conductive land 36, the sixth conductive land 36 is disposed on the other end side of the seventh conductive land 37 opposite to the one end side where the output terminal OUTH is provided. The portion provided with the sustain power supply terminal SUS is extended so that the portions bent in an L shape are opposed to each other.
Since the ninth conductive land 39 is disposed close to the eighth conductive land 38, the eighth conductive land 38 is disposed on the other end side of the ninth conductive land 39 opposite to the one end side where the ground terminal is provided. The portion where the output terminal OUTL is provided is extended so that the portion bent in an L-shape is placed close to each other.
With the above configuration, the current path I1 from the sustain power supply terminal SUS to the output terminal OUTH in which the sustain pulse current flows in the second semiconductor power module 23 and the current path I2 from the output terminal OUTL to the power ground terminal PGND are the shortest distances. Therefore, the parasitic inductance in the module can be reduced, and the voltage drop caused by the conductive land can be reduced.

  Next, in the first semiconductor power module shown in FIG. 4B, external connection terminals are arranged on the long side of the module that hits the left and right sides. A plurality of input / output terminals PC1, PL1, PL2, PC2, a terminal SUS, a terminal OUT, and a terminal PGND of the power recovery circuit are arranged in order from the top on the left long side of the drawing. On the right long side of the drawing, a plurality of control terminals (not shown) for performing on / off control of the switch elements of the sustain circuit, the separation circuit, and the power recovery circuit are arranged in order from the top, and further, a terminal SET and a terminal SCN are arranged. .

  First, the arrangement of the sustain circuit and the separation circuit will be described. A plurality of power MOSFETs 24 are arranged in a row on the conductive land 42 electrically connected to the terminal SUS, and the source wires of the plurality of power MOSFETs 24 and 30 are electrically connected on the wide circuit pattern 43, The power MOSFETs 30 (first separation switching elements) are arranged in a line on the left side on the conductive land 44 electrically connected to the terminal SET, and the plurality of power MOSFETs 31 (second separation switching elements) are the conductive lands 44. It is arranged in a row on the right side facing up. The wide conductive land 43 is electrically connected to a terminal OUT disposed between the terminal SUS and the terminal PGND. The source wires of the plurality of power MOSFETs 31 are connected to a conductive land 45 that is electrically connected to the terminal SCN. The power MOSFETs 24, 30, and 31 are arranged substantially in parallel on the conductive land.

  The first isolation switching element (MOSFET 30) isolates the current paths of the reset voltage generation circuit 3 and the first sustain circuit 5 for discharging the entire surface of the plasma display panel during the reset period. The second separation switching element (MOSFET 31) separates the current paths of the scan voltage generation circuit 2 and the reset voltage generation circuit 3 for supplying a scan voltage to the selection electrode of the scan electrode during an address period.

  In FIG. 4B, the plurality of power MOSFETs 25 are arranged in a line immediately below the position where the source wire of the power MOSFET 30 is connected on the conductive land 43 below the position where the source wire of the power MOSFET 24 is connected. Be placed. The source wires of the plurality of power MOSFETs 25 are connected to a conductive land 46 that is electrically connected to the terminal PGND. The power MOSFETs 25, 30, and 31 are arranged substantially in parallel on the conductive land.

  The conductive lands 42 to 46 to which a high voltage is applied have an insulation distance between the conductive lands of 1 mm to 10 mm. In order to reduce inductance, the terminals SUS, PGND, SET, and SCN are provided with a plurality of terminals, and the conductive lands 42 to 46 have the shortest lateral distance while ensuring the minimum space in which each power MOSFET and source wire can be placed. Thus, the conductive lands 42, 45, 46 are arranged in the vicinity of the terminals to be electrically connected. Further, the number of source wires of the power MOSFETs 24, 25, 30, 31 is more than the number calculated from the rated current of each power MOSFET. For example, if the rated current of the power MOSFET is 50 A and the fusing current per source wire is 25 A, three wires are sufficient, but by hitting 5 to 10 wires, the parasitic inductance in the metal thin wire is reduced.

Next, the arrangement of the power recovery circuit will be described. A plurality of input / output terminals PC1, PL1, PL2 and PC2 of the power recovery circuit are arranged on the upper side of the left long side as shown in FIG. 4B, and power MOSFETs 26 and 27 and diodes 28 and 29 are arranged on the conductive land. Each conductive land and the switch element are electrically connected by a source wire.
A plurality of control terminals of the control circuit that performs on / off control of the switch elements of the sustain circuit, the separation circuit, and the power recovery circuit are arranged on the upper side of the right long side. A large current such as a sustain pulse current does not flow through each terminal of the power recovery circuit and the control circuit and the conductive land, and the plasma display panel is not adversely affected by the parasitic inductance.

In order to make the second conductive land 43 partly close to the switching element 24 of the first conductive land 42, the other end side of the first conductive land 42 facing the one end side where the sustain power supply terminal SUS is provided. In addition, a portion of the second conductive land 43 where the output terminal OUT is provided is extended so that a portion bent in an L shape is placed close to each other.
Further, in order to bring the switching element 25 of the second conductive land 43 close to the third conductive land 46, the second conductive land 46 has a second end facing the one end where the ground terminal PGND is provided. A portion where the output terminal OUT of the two conductive lands 43 is provided is extended to be bent in the opposite direction to the portion bent in the L-shape, and the switching element mounting portion is made to face this portion close to each other. .
Further, in order to dispose the first separation switching element 30 close to the second conductive land 43, the end of the second conductive land 43 on the fourth conductive land 44 side is the first separation of the fourth conductive land 44. It is made to oppose in the vicinity of the end on the switching element 30 side.
Further, in order to dispose the second isolation switching element 31 close to the fifth conductive land 45, the fourth conductive land 45 has a fourth end on the other end facing the one end where the scan voltage terminal SCN is provided. The ends of the conductive lands 44 on the second separation switching element 31 side are close to each other and face each other.
With the above configuration, the current path I3 from the sustain power supply terminal SUS to the main output terminal SCN through which the sustain pulse current flows in the first semiconductor power module 9 and the current path I4 from the main output terminal SCN to the power ground terminal PGND are Since it is formed at the shortest distance in a straight line, it is possible to reduce the parasitic inductance in the module and to reduce the voltage drop due to the conductive land routing.

Next, an embodiment of the drive substrate according to the present invention will be described with reference to FIGS.
FIG. 5 is a view showing the structure of the X-side electrode drive substrate 10. FIG. 5A shows the wiring pattern of the first layer and FIG. 5B shows the wiring pattern of the second layer, and the arrangement of the first semiconductor power module 23, other main electronic components, and connection connectors can be seen. As shown in the transmission diagram. In FIG. 5, 10a represents the first layer of the X-side electrode drive substrate, and 10b represents the second layer. Modules and electronic components are arranged on the first-layer surface of FIG. 5A, and the second-layer surface of FIG. 5B is installed on the chassis.

  Reference numeral 48 denotes a sustain power stabilization capacitor for supplying a sustain pulse voltage. Reference numeral 49 denotes a connection connector for supplying a sustain pulse voltage to the X electrode. A plurality of connectors are arranged to reduce wiring resistance. 21 is a coil, 22 is a recovery capacitor, and 50 is a ground terminal for electrically connecting the ground pattern 51 of the X-side electrode drive substrate 10 and the chassis of the plasma display panel device. Reference numeral 52 denotes a connection connector for supplying a sustain pulse voltage to the X-side electrode drive board 10, and 53 denotes a connection connector for supplying other control signals and the like to the X-side electrode drive board 10.

  In FIG. 5A, reference numeral 54 denotes an output wiring pattern for electrically connecting the sustain pulse voltage VSUS to the connection connector 49 from the output terminals OUTH and OUTL of the first semiconductor power module 23. Usually, a substrate having a plurality of wiring layers is used as the driving substrate of the plasma display device. In this embodiment, the output wiring pattern 54 is arranged in the first layer. The second semiconductor power module 23 is arranged close to each other so that the linear distance t1 between the output terminals OUTH and OUTL and the connection connector 49 is the shortest.

  Reference numeral 55 denotes a power supply wiring pattern for electrically connecting the positive terminal of the sustain power stabilization capacitor 48 and the sustain power supply terminal SUS. In this embodiment, the power supply wiring pattern 55 is arranged on the first layer in the same manner as the output wiring pattern. The sustain power stabilization capacitor 48 is disposed close to the sustain power supply terminal SUS in order to minimize the inductance of the wiring pattern.

  56 is a wiring pattern for electrically connecting the positive terminal of the recovery capacitor 22 and the terminals PC1 and PC2 of the power recovery circuit, and 57 is a wiring pattern for electrically connecting one end of the coil 21 and the output terminal OUT. 58 is a wiring pattern for electrically connecting the other end of the coil 21 and the terminals PL1 and PL2 of the power recovery circuit, and 59 is a connection for supplying a control signal or the like to the X-side electrode drive substrate 10. This is a wiring pattern for electrically connecting the connector 53 and the control terminal (not shown) of the module. In this embodiment, all of these are arranged on the first layer in the same manner as the output wiring pattern. In the blank portion on the lower side in FIG. 5A, other electronic components of the X-side drive board are arranged.

  5B, the power ground terminal PGND of the second semiconductor power module 23, the negative terminal of the sustain power stabilization capacitor 48, the negative terminal of the recovery capacitor 22, and the ground for electrical connection with the chassis. All the terminals 50 are electrically connected by a ground pattern 51 disposed on almost the entire surface of the second layer of the X-side electrode drive substrate.

  With the above configuration, the large current path is almost formed in the module, and the large current path in the module is formed with the shortest distance. Further, by appropriately disposing each terminal of the second semiconductor power module, the large current wiring pattern on the drive substrate can be extremely simplified, and the ground current wiring pattern can be formed in a large area. Therefore, voltage drop fluctuations caused by high-speed, high-current pulses in the module and on the driving substrate can be suppressed, and radiation noise can be reduced.

  Also, when the conventional module configuration, the sustain circuit and the recovery circuit are configured with discrete components, the layout of components on the drive board is complicated, so the large current wiring pattern of each circuit is formed wide to reduce inductance. In the present embodiment, a large current pattern other than the ground current can be easily wired on the first layer, and the drive substrate can be configured with a two-layer substrate. Cost reduction can be achieved.

  FIG. 6 is a plan view of the Y-side electrode drive substrate 1. 6A shows the wiring pattern of the first layer and FIG. 6B shows the wiring pattern of the second layer, and the arrangement of the first semiconductor power module 9, other main electronic components, and connection connectors can be seen. As shown in the transmission diagram. In FIG. 6, 1a represents the first layer of the Y-side electrode drive substrate, and 1b represents the second layer. Modules and electronic components are arranged on the first layer side surface of FIG. 6A, and the second layer side surface of FIG. 6B is installed on the chassis.

  Reference numeral 60 denotes a sustain power stabilization capacitor for supplying a sustain pulse voltage. Reference numeral 61 denotes a reset voltage, a sustain pulse voltage, a scan voltage, etc. generated by the Y-side electrode drive substrate for supplying to the scan driver circuit 117. A plurality of connecting connectors are arranged to reduce wiring resistance. 7 is a coil, 8 is a recovery capacitor, and 62 is a ground terminal for electrically connecting the ground pattern 63 of the Y-side electrode drive substrate 1 and the chassis of the plasma display panel device. Reference numeral 64 is a connection connector for supplying a sustain pulse voltage to the Y-side electrode drive substrate 1, and 65 is a connection connector for supplying other control signals and the like to the Y-side electrode drive substrate 1.

  In FIG. 6A, reference numeral 66 denotes an output wiring pattern for electrically connecting the sustain pulse voltage VSUS from the main output terminal SCN of the first semiconductor power module 9 to the connection connector 61. Usually, a substrate having a plurality of wiring layers is used as the driving substrate of the plasma display device. In this embodiment, the output wiring pattern 66 is arranged in the first layer. The first semiconductor power module 9 is arranged close to each other so that the linear distance t2 between the main output terminal SCN and the connection connector 61 is the shortest.

  67 is a wiring pattern for electrically connecting the positive terminal of the recovery capacitor 8 and the terminals PC1 and PC2 of the power recovery circuit, and 68 is a wiring pattern for electrically connecting one end of the coil 7 and the output terminal OUT. 69 is a wiring pattern for electrically connecting the other end of the coil 7 and the terminals PL1 and PL2 of the power recovery circuit, and 70 is a connection for supplying a control signal and the like to the X-side electrode driving substrate 1. This is a wiring pattern for electrically connecting the connector 65 and a control terminal (not shown) of the module. In this embodiment, all of these are arranged on the first layer in the same manner as the output wiring pattern. In the blank portion on the lower side in FIG. 6A, other electronic components of the Y side drive board are arranged.

  In FIG. 6B, reference numeral 71 denotes a power supply wiring pattern for electrically connecting the positive terminal of the sustain power stabilization capacitor 60 and the sustain power supply terminal SUS, which is arranged in the second layer in this embodiment. Yes. The sustain power stabilization capacitor 60 is disposed close to the sustain power supply terminal SUS in order to minimize the inductance of the wiring pattern. Furthermore, the power ground terminal PGND of the first semiconductor power module 9, the negative terminal of the sustain power stabilization capacitor 60, the negative terminal of the recovery capacitor 8, and the ground terminal 62 for electrical connection to the chassis are all Y-side electrodes. They are electrically connected by a ground pattern 63 disposed on almost the entire surface of the second layer of the drive substrate.

  With the above configuration, the large current path is almost formed in the module, and the large current path in the module is formed with the shortest distance. Further, by appropriately disposing each terminal of the first semiconductor power module, the large current wiring pattern on the driving substrate can be extremely simplified, and the ground current wiring pattern can be formed in a large area. Therefore, voltage drop fluctuations caused by high-speed, high-current pulses in the module and on the driving substrate can be suppressed, and radiation noise can be reduced.

  In addition, when the conventional module configuration, sustain circuit, separation circuit, and recovery circuit are configured with discrete components, the layout of components on the drive board is complicated, so the large current wiring pattern of each circuit is wide to reduce inductance. However, in this embodiment, wiring other than the sustain pulse current path and the ground current from the sustain power stabilization capacitor to the module is easily wired in the first layer. As a result, the drive substrate can be constituted by a two-layer substrate, and the cost can be reduced.

As described above, since both the X-side electrode drive substrate and the Y-side electrode drive substrate are formed of a two-layer substrate, a significant cost reduction can be achieved as compared with a conventional four-layer substrate.
However, this embodiment is not limited to the two-layer substrate, and it is obvious that a conventional four-layer substrate can be used.
(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional transparent view of a semiconductor power module 72 showing an embodiment according to the present invention. In the second embodiment, in the second semiconductor power module 23 and the first semiconductor power module 9 in the first embodiment, only the configuration of the four ends of these modules is different.

  In FIG. 7, 73 is a metal substrate, 74 is an electrical insulating layer, 75 is a circuit pattern, and 73 to 75 form a metal base printed board 76. Reference numeral 77 denotes a power MOSFET, and 78 denotes a high-side driver IC for driving the power MOSFET. The high-side driver IC is disposed at a desired position of the circuit pattern 75 and is electrically connected to the circuit pattern by a source wire 79.

  Reference numeral 80 denotes a power ground terminal connected to the ground pattern layer 81b of the drive board 81 among a plurality of terminals for electrically connecting the module and the drive board 81, and 84 denotes the ground pattern layer 81b of the drive board 81. Ground terminals located at the four ends of the module for connection. (Other terminals are not shown.) 82 is a heat radiating plate that efficiently releases heat generated by the module, and is electrically connected to the metal substrate 73 of the metal printed circuit board 76. Reference numeral 83 denotes a bolt for bonding and fixing the metal base printed board 76 and the heat sink 82. The bolt 83 fixes the metal base printed board 76 and the heat sink 82 at the four ends of the module, and is electrically connected to the ground terminal 84 arranged at the four ends of the module through a circuit pattern. In this embodiment, the ground terminal 84 and the metal substrate 73 are electrically connected by the bolt 83, but a part of the electrical insulating layer 74 is opened and a desired circuit pattern and the metal substrate 73 are connected by a metal wire. Also good.

With the above configuration, since the metal substrate 73 and the heat radiating plate 82 are electrically connected to the ground pattern layer 81b of the drive substrate 81 via the ground terminal 84, a ground current can flow. As a result, the ground current flowing on the drive substrate 81 can be reduced, and the radiation noise generated on the drive substrate can be reduced.
Further, in the X electrode driving substrate 10 and the Y-side electrode driving substrate 1 described with reference to FIGS. 5 and 6, the ground terminals and the ground patterns of the second semiconductor power module 23 and the first semiconductor power module 9 are electrically connected. As a result, the ground current flowing on the drive substrate can be reduced, so that the radiation noise generated on the drive substrate can be reduced.

Although the substrates 47a and 47b in FIG. 4 have been described as separate substrates, they may be configured as a single substrate. Therefore, in this case, the first semiconductor power module and the second semiconductor power module are integrated.
Moreover, although the drive board | substrate (1a, 1b) and the drive board | substrate (10a, 10b) shown in FIG.5, 6 were demonstrated as an independent board | substrate, these can also be integrated and comprised as one drive board | substrate.

Further, the high side driver ICs 19, 20, 32, 33, 34, and 35 are not shown in FIG. 4 because they are not directly related to the present invention.
Furthermore, the switching elements used are not limited to MOSFETs but may be other semiconductor switching elements.

  As described above, the present invention is particularly useful as a driving device for a plasma display panel that requires high frequency and high current driving.

It is a block diagram which shows schematic structure of the plasma display apparatus in one Example of this invention. It is an example of the timing chart of the drive circuit of the plasma display apparatus which concerns on this invention. 1 is an equivalent circuit diagram of an embodiment of a pair of semiconductor power modules according to the present invention. It is a plane permeation | transmission figure of one Example of a pair of semiconductor power module which concerns on this invention. It is a figure which shows one Example of the X side electrode drive substrate which concerns on this invention. It is a figure which shows one Example of the Y side electrode drive substrate which concerns on this invention. It is a cross-sectional transparent view of the semiconductor power module which shows one Example which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

1: Y-side electrode drive board
2: Scan voltage generation circuit
3: Reset voltage generation circuit
4: Separation circuit
5, 11: Sustain circuit
6, 12: Power recovery circuit
7, 21: Coil
8, 22: Recovery capacitor
9, 23: Semiconductor power module
10: X-side electrode drive board
13,14,15,16, 24,25,26,27,30,31: Switching element
17,18,28,29: Diode
19, 20, 32, 33, 34, 35: High-side driver IC
36,37,38,39,42,43,44,45,46: Conductive land
40, 41, 79: Source wire
47,76: Metal base printed circuit board
48, 60: Sustain power stabilization capacitors
49,61: Connector
50,62: Earth terminal
51, 63: Earth pattern
52, 64: Sustain power connector
53, 65: Control signal connector
54,55,56,57,58,59,66,67,68,69,70,71: Wiring pattern
72: Semiconductor power module
73: Metal substrate
74: Electrical insulation layer
75: Circuit pattern
77: Power MOSFET
80: Power ground terminal
81: Driving board
82: Heat sink
83: Bolt
84: Ground terminal
101: PDP
102: Address driver circuit
103: Waveform control circuit
117: Scan driver circuit

Claims (5)

A discharge having a first sustain circuit, a first power recovery circuit and a separation circuit on the scan electrode side of the plasma display panel, and a second sustain circuit and a second power recovery circuit on the discharge sustaining electrode side A plasma display panel driving device including a sustain electrode driving circuit,
A first sustain circuit is disposed on one end side of the first substrate constituting a part of the scan electrode driving circuit, and a separation circuit is disposed on the other end side so as to face the first sustain circuit. The first sustain circuit and the separation circuit are arranged at a position of the first substrate separated from the first sustain circuit and the separation circuit, and a plurality of terminals of the first sustain circuit and the separation circuit are arranged near the end of the first substrate to form a first semiconductor module,
A second sustain circuit is arranged on one end side of the second substrate constituting a part of the discharge sustaining electrode driving circuit, and a second power recovery circuit is arranged on the other end side, and the second sustain circuit and the second power recovery are arranged. A plurality of terminals of the circuit are arranged close to the end of the second substrate to form a second semiconductor module,
In the first semiconductor module, the first, second and third conductive lands are formed on one end side of the first substrate, and the fourth and fifth conductive lands are formed on the other end side. The first conductive land and the second conductive land are formed. A switching element constituting a first sustain circuit is mounted on each land, and a sustain power supply terminal which is one of the terminals is provided on the first conductive land,
The second conductive land is provided with an output terminal which is one of the terminals,
Part of the second conductive land is close to the switching element of the first conductive land, the switching element of the second conductive land is close to the third conductive land, and the third conductive land has 1 of the terminal. A grounding terminal is provided,
The switching element of the first conductive land and the second conductive land are connected by a wire, the switching element of the second conductive land and the third conductive land are connected by a wire, and the sustain power supply terminal, the output terminal, and the ground terminal are connected to each other. Arranged in a row along the edge of the first substrate,
The fourth conductive land is equipped with a switching element that constitutes a separation circuit, and is provided with a reset voltage terminal to provide a current path for the reset voltage generation circuit and the first sustain circuit for discharging the entire plasma display panel during the reset period. A first separation switching element in the switching element to be separated is disposed adjacent to the second conductive land;
A second isolation switching element in the switching element for separating a current path of the scan voltage generation circuit for supplying a scan voltage to the selection electrode of the scan electrode and the reset voltage generation circuit during an address period is a fifth conductive land. Are arranged close to each other, provided with a scan voltage terminal on the fifth conductive land,
The second conductive land and the first separation switching element are connected by a wire, the fifth conductive land and the second separation switching element are connected by a wire, and the reset voltage terminal and the scan voltage terminal are connected to the other of the first substrate. Arranged in a row along the edge,
In the second semiconductor module, sixth, seventh, eighth, and ninth conductive lands are formed on one end side of the second substrate, and a second sustain circuit is formed in each of the sixth conductive land and the eighth conductive land. A switching element is mounted, the sixth conductive land is provided with a sustain power supply terminal that is one of the terminals, and the eighth conductive land is provided with an output terminal that is one of the terminals.
The seventh conductive land is disposed in the vicinity of the sixth conductive land, provided with an output terminal that is one of the terminals, and connected to the switching element by a wire,
The ninth conductive land is disposed adjacent to the eighth conductive land, and is provided with a ground terminal which is one of the terminals, and is connected to the switching element by a wire,
The sustain power terminal, the two output terminals, and the ground terminal are arranged in a line along one end of the second substrate,
In order to make the second conductive land partly close to the switching element of the first conductive land, the second conductive land is provided on the other end side of the first conductive land opposite to the one end side where the sustain power supply terminal is provided. Extending the portion of the land where the output terminal is provided and making the portion bent in an L shape close to each other,
In order to make the switching element of the second conductive land close to the third conductive land, the output terminal of the second conductive land is connected to the other end of the third conductive land opposite to the one end where the ground terminal is provided. The portion provided with a portion that is bent in the opposite direction to the portion bent into the L-shape is the switching element mounting portion, and this portion is closely opposed,
In order to dispose the first separation switching element close to the second conductive land,
The end of the second conductive land on the side of the fourth conductive land is opposed to the end of the fourth conductive land on the side of the first separation switching element,
In order to dispose the second isolation switching element close to the fifth conductive land,
The second conductive switching element side end of the fourth conductive land is opposed to the other end side opposite to the one end side where the scan voltage terminal of the fifth conductive land is provided,
In order to dispose the seventh conductive land close to the sixth conductive land, the sustain power terminal of the sixth conductive land is disposed on the other end side of the seventh conductive land opposite to the one end side where the output terminal is provided. Extending the part where is provided and making the part bent in the L-shape close to each other,
In order to dispose the ninth conductive land close to the eighth conductive land, the output terminal of the eighth conductive land is connected to the other end of the ninth conductive land opposite to the one end where the ground terminal is provided. Extend the provided part and make the L-shaped bent part close to each other,
A plasma display panel driving apparatus according to claim 1, wherein all the switching elements are composed of power MOSFETs, the interval between each conductive land is 1 to 10 mm, and the length of the wire is 6 to 10 mm. A first drive board for mounting the first semiconductor module is provided, and a capacitor for stabilizing the power supply is provided on the first drive board in the vicinity of the sustain power supply terminal provided on the first board, and the first board is provided on the first board. Providing a connector for connecting to the scan driver circuit existing between the scan electrode and the scan electrode drive circuit in the immediate vicinity of the output terminal,
A second drive board for mounting the second semiconductor module is provided, and a capacitor for stabilizing the power supply is provided on the second drive board in the vicinity of the sustain power supply terminal provided on the second board, and the second board is provided on the second board. 2. A plasma display panel driving apparatus according to claim 1, wherein a connector for connecting to the discharge sustaining electrode is provided in the immediate vicinity of the output terminal. The first driving board and a two-layer structure, and the ground pattern portion to the second layer, the power supply wiring pattern portion is provided for supplying a large current pulses supplied from the stabilizing capacitor to the first substrate side, the first layer A wiring pattern portion for supplying a large current pulse output from the first substrate side to the connection connector is provided as the first substrate mounting portion.
The second drive substrate has a two-layer structure, and a ground pattern portion is provided in the second layer, and a wiring pattern portion for supplying a large current pulse supplied from the power stabilization capacitor to the second substrate side in the first layer , 3. The plasma display panel according to claim 2, wherein the first layer is a second substrate mounting portion, and a wiring pattern portion is provided for supplying a large current pulse output from the second substrate side to the connection connector. Drive device. Provide ground terminals at the four ends of the first substrate for electrical connection with the ground pattern portion of the first drive substrate;
4. The plasma display panel driving device according to claim 3, wherein a ground terminal for making an electrical connection with the ground pattern portion of the second driving substrate is provided at four ends of the second substrate. A heat sink is attached to the other main surface of the first substrate, and the heat sink is electrically connected to the ground of the first substrate.
4. The plasma display panel driving device according to claim 3, wherein a heat sink is attached to the other main surface of the second substrate, and the heat sink is electrically connected to the ground of the second substrate.

Images