JP4488668B2 - Power semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device for controlling high power.
[0002]
[Prior art]
There is an IGBT (Insulated Gate Bipolar Transistor) as a semiconductor circuit element for power control. The IGBT is a new high voltage circuit element that combines the high-speed switching characteristics of a power MOSFET and the high output characteristics of a bipolar transistor, and has been widely used in recent years in the field of power electronics such as inverters and switching power supplies.
[0003]
FIG. 18 is a cross-sectional view showing a conventional IGBT. In FIG. 18, a P-type base layer 83 is selectively formed in the surface of a high-resistance N-type base layer 81. A low-resistance N-type source layer 84 is selectively formed in the surface of the P-type base layer 83. A gate electrode 86 is disposed on the P-type base layer 83 sandwiched between the N-type source layer 84 and the N-type base layer 81 with a gate insulating film 85 interposed therebetween. The gate electrode 86 is obtained by integrating the gate electrodes of two adjacent IGBTs. A source electrode 88 is disposed so as to contact both the N-type source layer 84 and the P-type base layer 83. On the other hand, a P-type emitter layer 82 is formed on the back surface of the N-type base layer 81. A drain electrode 87 is disposed on the P-type emitter layer 82.
[0004]
The operation of the IGBT configured as described above is as follows. That is, at the turn-on time, a positive voltage (positive bias voltage) is applied to the gate electrode 86 with respect to the source electrode 88. When a positive bias voltage is applied to the gate electrode 86, an N-type channel is formed in the surface of the P-type base layer 83 below the gate electrode 86. Thereby, the N-type source layer 84 and the N-type base layer 81 are short-circuited.
[0005]
As a result, electrons are injected from the N-type source layer 84 into the N-type base layer 81 and an electron current flows, and an amount of holes corresponding to the electron current flows from the P-type emitter layer 82 to the N-type base layer 81. Injected. As a result, the N-type base layer 81 undergoes conductive modulation and becomes low resistance, and a main current flows between the source and drain.
[0006]
On the other hand, at the time of turn-off, a zero or negative voltage (negative bias voltage) is applied to the gate electrode 85 with respect to the source electrode 88. As a result, the N-type channel disappears and electrons are no longer injected from the N-type emitter layer 84 into the N-type base layer 81. As a result, the N-type base layer 81 does not cause the conduction modulation, and the IGBT becomes non-conductive in due course.
[0007]
By the way, this type of IGBT has the following problems. That is, compared with a thyristor or the like, an IGBT has a higher on-voltage because carriers (electrons) are less injected from the cathode (source) side. The higher the withstand voltage, the thicker the substrate, so the on-voltage becomes higher. When the thickness exceeds a certain level, the on-voltage becomes extremely high and the power loss increases. For this reason, the breakdown voltage of the conventional IGBT is at most about 2 kV. Furthermore, since the distance between the gate electrodes is about the same as the gate electrode width and the saturation current is large, there is a problem that the IGBT is likely to latch up and become uncontrollable.
[0008]
[Problems to be solved by the invention]
As described above, the conventional IGBT has a high on-voltage because there is little carrier injection from the source side. Further, since the distance between the gate electrodes is about the same as the width of the gate electrode, the latch-up resistance (current at which latch-up starts) decreases.
[0009]
An object of the present invention is to provide a power semiconductor device in which any one of an on-voltage, a safe operation region, and a latch-up resistance is improved as compared with the prior art.
[0010]
[Means for Solving the Problems]
A first aspect of the present invention is a power semiconductor device having a plurality of circuit elements arranged in parallel,
Each of the circuit elements is
A first semiconductor layer;
A second conductivity type base layer disposed on the first semiconductor layer;
A first conductivity type base layer formed in a surface of the second conductivity type base layer;
A second conductivity type source layer formed in the surface of the first conductivity type base layer;
A gate electrode portion disposed on the first conductivity type base layer sandwiched between the second conductivity type source layer and the second conductivity type base layer via a gate insulating film;
A source electrode portion in contact with the second conductivity type source layer and the first conductivity type base layer;
A drain electrode portion in contact with the first semiconductor layer;
Comprising
The gate electrode portion is integrated for every two circuit elements of the circuit element to form a gate electrode, and the width of the gate electrode is set to L_G, D is the depth of the first conductivity type base layer_BThe thickness of the second conductivity type base layer at the portion sandwiched between the first conductivity type base layer and the first conductivity type emitter layer is W_B1 ≦ L_G ²/ (D_B・ W_B) ≦ 9 is satisfied.
[0011]
According to a second aspect of the present invention, in the power semiconductor device according to the first aspect, the distance between the gate electrodes is L._S60 μm ≦ L_GAnd 5 ≦ L_G/ L_SIt satisfies the following conditions.
[0012]
The peak value of the impurity concentration of the low-resistance second conductivity type semiconductor layer is 3 × 10.¹⁴cm^-31 × 10¹⁵cm^-3More preferably. The depth (thickness) of the low-resistance second conductive semiconductor layer may be ½ or more of the depth (thickness) of the first conductive base layer, but the first conductive More preferably, it is the same as the depth (thickness) of the mold base layer.
[0013]
According to the inventor's research, 60 μm ≦ L_G1 ≦ L_G ²/ (D_B・ W_B) It was found that the ON voltage can be lowered by setting ≦ 9. In addition, by using recent microfabrication technology, L_GL against_SCan be made sufficiently small (5 ≦ L_G/ L_SThus, it has been found that the saturation current can be suppressed to the latch-up current or less without increasing the on-voltage, and the safe operation area can be expanded. Therefore, according to the first and second viewpoints of the present invention based on the above knowledge, the on-voltage is lowered and the safe operation area is expanded as compared with the prior art.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type.
[0015]
FIG. 1 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to an embodiment of the present invention. The power semiconductor device according to the present embodiment includes a plurality of IGBTs (circuit elements) arranged side by side. These gate electrodes 6 and source electrodes 8 of the IGBTs are alternately arranged. As shown in FIG. 1, when attention is paid to one IGBT 102, the gate electrode portion 6b is integrated with the gate electrode portion 6a of another IGBT 101 adjacent on one side to constitute the gate electrode 6, and the source electrode portion 8b. Constitutes the source electrode 8 together with the source electrode portion 8c of another IGBT 103 adjacent to the other side. Therefore, in the two adjacent IGBTs 101 and 102, the gate electrode 6 is positioned between the source electrodes 8 and 8 of the IGBTs 101 and 102, and in the next two adjacent IGBTs 102 and 103, the source electrode 8 is the IGBTs 102 and 103. It is located between the gate electrodes 6 and 6.
[0016]
In FIG. 1, a P-type emitter layer 2 is selectively formed in the back surface of a high-resistance N-type base layer 1. A low-resistance N-type diffusion layer 9 is formed in the surface of the N-type base layer 1. A P-type base layer 3 is selectively formed in the surface of the N-type diffusion layer 9. In other words, a low-resistance N-type diffusion layer 9 is formed in the surface of the N-type base layer 1 immediately below the gate electrode 6 between the adjacent P-type base layers 3.
[0017]
The depth of the low resistance N-type diffusion layer 9 is suitably the same as that of the P-type base layer 3 as shown in FIG. However, this should be at least deeper than ½ of the depth of the P-type base layer 3.
[0018]
A low-resistance N-type source layer 4 is selectively formed in the surface of the P-type base layer 3. On the P-type base layer 3 sandwiched between the N-type source layer 4 and the N-type base layer 1 (N-type diffusion layer 9), a gate electrode 6 is disposed via a gate insulating film 5. A source electrode 8 is disposed so as to contact both the N-type source layer 4 and the P-type base layer 3.
[0019]
Here, one gate electrode 6 shown in the center of FIG. 1 functions as the gate electrode of two adjacent IGBTs 101 and 102. That is, the gate electrodes 6a and 6b of the IGBTs 101 and 102 extend from the P-type base layer 3 to the N-type base layer 1 (N-type diffusion layer 9) and are integrated.
[0020]
On the other hand, a drain electrode 7 is disposed so as to contact the P-type emitter layer 2.
[0021]
According to the power semiconductor device configured as described above, the N-type diffusion layer 9 promotes the injection of electrons, so that the on-voltage can be lowered.
[0022]
Here, the peak value of the impurity concentration of the N-type diffusion layer 9 is 3 × 10.¹⁴cm^-3The above is desirable. In particular, in the case of an N-type channel IGBT as in the present embodiment, 1 × 10¹⁵cm^-3The above is desirable. Further, the impurity concentration must not exceed the peak value of the impurity concentration of the P-type base layer 3 immediately below the N-type source layer 4.
[0023]
Above value (1 × 10¹⁵cm^-3) Is obtained from the following equation.
[0024]
Hole density n inside the N-type base layer 1_hIs expressed by the following equation.
[0025]
n_h= N_p・ Exp (W_B/ (D_h・ Τ)^1/2)
Where N_pIs the peak value of the impurity concentration of the P-type emitter layer 2, W_BIs the thickness of the N-type base layer 1 between the P-type base layer 3 and the P-type emitter layer 2, D_hRepresents a hole diffusion coefficient, and τ represents a carrier lifetime in a high injection state.
[0026]
Hole density n_hIf the peak value of the impurity concentration of the N-type diffusion layer 9 is not higher than that, the N-type diffusion layer 9 will be filled with holes. Therefore, the peak value of the impurity concentration of the N-type diffusion layer 9 is the hole density n_hIf it is smaller than that, carrier injection cannot be sufficiently performed, and the conduction characteristics of the IGBT cannot be improved.
[0027]
On the other hand, the peak value of the impurity concentration of the N-type diffusion layer 9 is the hole density n_hIf higher, the N-type diffusion layer 9 acts as an emitter for holes, and the electron injection efficiency increases. Each parameter is almost uniquely determined by the device structure and usage conditions, but the value is about 1 × 10.¹⁵cm^-3And the above value is obtained.
[0028]
In the case of a P-type channel IGBT, the low-resistance N-type diffusion layer 9 becomes a low-resistance P-type diffusion layer, and the peak value of the impurity concentration is 3 × 10.¹⁴cm^-3The above is desirable.
[0029]
Further, the width L of the gate electrode 6_GIs an important parameter in determining the conduction characteristics of the IGBT. Width L of gate electrode 6_GIf the length is too long, not only the channel density of the IGBT is lowered and the conduction characteristics are deteriorated, but also problems such as an increase in gate capacitance, an increase in cost, and a deterioration in controllability may occur.
[0030]
On the other hand, the width L of the gate electrode 6_GIs too short, holes injected from the P-type drain layer 2 are bypassed to the P-type base layer 3 and are not accumulated in the high-resistance N-type base layer 1, thereby deteriorating the conduction characteristics.
[0031]
According to the study of the present inventor, in order to improve the channel density and carrier accumulation and to lower the on-voltage, the width L of the gate electrode 6 regardless of the presence or absence of the N-type diffusion layer 9._GHas been designed to satisfy the following inequality.
[0032]
1 ≦ L_G ²/ (D_B・ W_B)
Where D_BIndicates the depth of the P-type base layer 3.
[0033]
This inequality is obtained as follows.
[0034]
The current density i of the IGBT in the state where the conduction modulation has occurred is
i = q · n · V_F・ (Μ_e+ Μ_h) / W_B                      ... (1)
It is represented by
[0035]
Where q is the elementary charge amount, n is the electron and hole carrier density, and V_FIs the on-state voltage, μ_eIs the electron mobility, μ_hIndicates the mobility of holes.
[0036]
The effective sheet resistance R of the P-type base layer 3 during conduction is
R = 1 / (q · μ_h・ N ・ D_B(2)
It is represented by
[0037]
  Since the voltage drop of the hole current due to the sheet resistance R may be equal to or higher than the junction voltage Vj,
  i ・ R ・ L_G ²/16≧ Vj (3)
It becomes.
[0038]
  Using equations (1)-(3)
  L_G ²/ (D_B・ W_B) ≧16V_j・ Μ_h/ (V_F・ (Μ_e+ Μ_h))
It is expressed. (4)
  Here, when silicon is used as the device material,
  μ_h/ (Μ_e+ Μ_h) About 0.25, V_jIs about 0.6 V, and V is within the range where power semiconductor devices are normally used._FIs about 4V, equation (4) becomes
  1 ≦ L_G ²/ (D_B・ W_B)
[0039]
L_G ²/ (D_B・ W_BIf the value of) is too large, the number of channels decreases as shown in FIG. According to the current knowledge obtained according to FIG. 10, to prevent channel loss, L_G ²/ (D_B・ W_B) Should not be set to exceed 9. Therefore, 1 ≦ L_G ²/ (D_B・ W_B) ≦ 9 is preferable.
[0040]
L_GIf it is too short, holes are easily bypassed and carriers are less likely to accumulate. In particular, in the case of a device whose breakdown voltage exceeds 3 kV, this is a fatal defect for the current-carrying characteristics. According to the inventor's experiment, L_GIt has been found that when the length is approximately 60 μm or more, carrier accumulation occurs in combination with the above conditions. Furthermore, according to the experiments of the present inventors, 2 ≦ L_G/ L_S, Preferably 5 ≦ L_G/ L_SIt was found that latch-up is less likely to occur when set to. Where L_SRepresents the distance between adjacent gate electrodes 6. This means that the semiconductor device is resistant to destruction and the safe operation area can be expanded, so that the protection circuit can be simplified.
[0041]
In the present embodiment, unlike the conventional case, L_GIs L_SSince it is much larger, the saturation current can be easily kept lower than the latch-up current. This is impossible with the process technology of IGBT and other elements that are frequently used in the past, but such a design is possible by a microfabrication technology using a step device or the like that has been developed in recent years.
[0042]
In the present embodiment, since the on-voltage and the safe operation area are improved by optimizing parameters, it is not necessary to introduce a new structure. Therefore, the number of steps is not increased and the process is not complicated, and the manufacturing cost is not increased.
[0043]
FIG. 2 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to another embodiment of the present invention. In the following drawings, the same reference numerals as those in FIG. 1 denote the same parts, and detailed descriptions thereof are omitted.
[0044]
The feature of this embodiment is that the thickness of the central portion 10 of the gate insulating film 5 is thicker than other portions. As a result, the gate capacitance can be reduced, and the gate drive circuit can be simplified and operated at high speed.
[0045]
The N-type diffusion layer 9 is desirably provided uniformly below the gate electrode 6 as in the embodiment shown in FIG. However, if this is difficult due to restrictions such as process, it can be changed as in the embodiment shown in FIG. Here, the N-type diffusion layer 9 is not formed under the center of the gate electrode 6 away from the N-type channel region, but only in the vicinity of the N-type channel region. Even in this case, the effect of reducing the ON voltage can be obtained.
[0046]
FIG. 3 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0047]
The present embodiment is different from the embodiment shown in FIG. 2 in that the N-type diffusion layer 9 is formed under the gate electrode 6. However, the N-type diffusion layer 9 is not uniformly arranged unlike the embodiment shown in FIG. That is, the thickness of the central portion of the N-type diffusion layer 9 is thinner than other portions.
[0048]
Such a structure is obtained as follows, for example. That is, the width of the central portion 10 of the gate insulating film 5 is narrowed, N-type impurities are ion-implanted using the gate insulating film 5 as a mask, and then heat treatment (annealing) is performed. In this way, the N-type impurity diffuses down to the bottom of the central portion 10 of the gate insulating film 5, so that the N-type diffusion layer 9 can be formed under the gate electrode 6.
[0049]
In the case of the embodiment shown in FIG. 3, the gate capacitance is slightly increased by the narrow width of the central portion 10 of the gate insulating film 5 compared to the embodiment shown in FIG. However, according to the study by the present inventor, even in this case, it is found that the conduction characteristics are improved if the N-type diffusion layer 9 is disposed under the gate electrode 6.
[0050]
FIG. 4 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0051]
When securing a high breakdown voltage, for example, a breakdown voltage of 2 kV or more, the width L of the gate electrode 6_GWhen the withstand voltage of 3 kV or more is secured to 30 μm or more, the width L of the gate electrode 6_GIs set to 60 μm or more. Thus, when the area of the gate electrode 6 is increased, it becomes easy to form the metal electrode 12 such as an Al electrode on the gate electrode 6 as shown in FIG.
[0052]
Therefore, normally, the gate electrode 6 is formed only of polysilicon. However, by providing the metal electrode 12 on the gate electrode 6, the gate resistance is reduced and high speed operation is possible. In addition, the gate drive circuit can be simplified.
[0053]
FIG. 5 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0054]
This embodiment is different from the embodiment shown in FIG. 1 in that a part of the N-type base layer 1 is selectively connected to the drain electrode 7. That is, in this embodiment, an anode short structure is adopted.
[0055]
According to the present embodiment, since the injection of holes from the drain side can be suppressed by the anode short structure, the tail current at turn-off can be particularly reduced, and the turn-off loss can be reduced. As a result, even if the switching frequency is increased, the power loss can be kept small, and an apparatus such as an inverter can be operated efficiently. In addition, noise can be reduced by increasing the switching frequency.
[0056]
Even if the carrier injection efficiency from the drain side is lowered due to the anode short structure, the carrier injection efficiency from the source side is higher than before due to optimization of parameters and the N-type diffusion layer 9, so that The voltage is kept low.
[0057]
FIG. 6 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0058]
This embodiment is different from the embodiment shown in FIG. 1 in that a lifetime reduction layer 13 is formed. The lifetime reduction layer 13 can be formed by, for example, diffusion of heavy metals such as Au and Pt, or irradiation with radiation such as H and He. Moreover, lifetime reduction using electron beam irradiation may be used in combination with this. As shown in FIG. 6, if the lifetime reducing layer 13 is formed in the N-type base layer 1 particularly in the vicinity of the boundary between the P-type emitter layer 2 and the N-type base layer 1, holes are injected from the drain side. This can be effectively suppressed, and the same effect as that of the embodiment shown in FIG. 5 employing the anode short structure can be obtained.
[0059]
FIG. 7 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0060]
This embodiment differs from the embodiment shown in FIG. 6 in that a low resistance N-type buffer layer 14 is disposed between the P-type emitter layer 2 and the high resistance N-type base layer 1. By providing the N-type buffer layer 14, the N-type base layer 1 can be thinned. Thereby, discharge of the carrier at the time of switching can be accelerated, and switching can be performed at high speed. The total amount of impurities in the N-type buffer layer 14 is 1 × 10¹⁴cm^-2The following is desirable. If there is an impurity amount larger than this, injection of holes from the drain is remarkably suppressed, and the current-carrying characteristics deteriorate.
[0061]
Further, a lifetime reduction layer 13 is formed in the N-type base layer 1 near the boundary between the N-type buffer layer 14 and the N-type base layer 1. As a result, injection of holes from the drain side is suppressed, switching loss can be reduced and switching can be performed at high speed without deteriorating the energization characteristics.
[0062]
FIG. 8 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0063]
This embodiment is different from the embodiment shown in FIG. 1 in that the low resistance N-type diffusion layer 9 is not formed under the gate electrode 6. Even when the N-type diffusion layer 9 is not provided, the above-mentioned 1 ≦ L_G ²/ (D_B・ W_B) ≦ 9 and 2 ≦ L_G/ L_S, Preferably 5 ≦ L_G/ L_SBy designing so as to satisfy the above condition, it is possible to improve the on-voltage, the safe operation region, and the latch-up tolerance of the device.
[0064]
FIG. 9 is a cross-sectional view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0065]
This embodiment differs from the embodiment shown in FIGS. 1 to 8 in that the optimization of parameters and the use of the high mobility semiconductor layer 11 instead of the low resistance N-type diffusion layer 9 makes it possible to This is because the on-voltage is lowered by increasing the injection.
[0066]
The high mobility semiconductor layer 11 is formed in advance on the surface of the N-type base layer 1 by a film forming method such as an epitaxial growth method before forming the P-type base layer 3 and the N-type source layer 4. deep.
[0067]
Examples of the material of the high mobility semiconductor layer 11 include SiGe, amorphous Si, and SiC when Si is used as the material of the N-type base layer 1.
[0068]
According to the present embodiment, since the high mobility semiconductor layer 11 exists in the N-type channel region, electrons on the source side are injected into the N-type base layer 1 through the high mobility semiconductor layer 11. .
[0069]
Therefore, electrons are injected into the N-type base layer 1 at a higher speed than before, and the amount of electrons injected into the N-type base layer 1 per unit time is increased, so that the electron injection efficiency is increased and the on-voltage is Go down.
[0070]
In the present embodiment, the high mobility semiconductor layer 11 is formed on the entire surface of the N-type base layer 1, but it is not necessary. The high mobility semiconductor layer 11 includes at least the N-type source layer 4 and N It suffices to exist in the surface of the P-type base layer 3 sandwiched between the mold-type base layers 1, that is, in the N-type channel region. Further, the impurity concentration of the high mobility semiconductor layer 11 at this time is 1 × 10 5 for channel formation.¹⁸cm^-3Is preferably smaller. Furthermore, the film thickness of the high mobility semiconductor layer 11 is preferably 0.05 μm or less in consideration of problems such as lattice mismatch.
[0071]
In addition, after using the high mobility semiconductor layer 11, the above-mentioned 1 ≦ L_G ²/ (D_B・ W_B) ≦ 9 and 2 ≦ L_G/ L_S, Preferably 5 ≦ L_G/ L_SBy designing so as to satisfy the above condition, the on-voltage can be further reduced, and the IGBT does not latch up and the safe operation area can be expanded.
[0072]
Next, a planar layout of the power semiconductor device according to the present invention will be described with reference to FIGS. The layout illustrated in FIGS. 11 to 16 can be combined with any of the cross sections illustrated in FIGS. Therefore, when the low resistance N-type diffusion layer 9 does not exist as in the embodiment shown in FIGS. 8 and 9, the portion indicated by reference numeral 9 in FIGS. 11 to 16 is the high resistance N-type base layer 1. Should be understood as.
[0073]
FIG. 11 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0074]
The feature of this embodiment is that the N-type source layer 4 is formed in a comb shape. A thin portion corresponding to the teeth of the comb in the N-type source layer 4 is in contact with the source electrode 8, and a portion corresponding to the spine of the comb forms a MOSFET region together with the gate electrode 6.
[0075]
According to the present embodiment, the portion corresponding to the comb teeth of the N-type source layer 4 acts as a resistor, so that a resistor is disposed between the source electrode 8 and the MOSFET. Operation is stable.
[0076]
Further, by using a comb shape as the pattern of the N-type source layer 4, the area of the N-type source layer 4 can be reduced and the latch-up resistance can be increased as compared with the case of using a stripe pattern having a normal size. .
[0077]
FIG. 12 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0078]
The present embodiment is different from the embodiment shown in FIG. 11 in that the N-type source layer 4 is formed in a ladder shape. Thus, even if the pattern of the N-type source layer 4 is formed in a ladder shape, the latch-up resistance can be increased as in the embodiment shown in FIG. Further, since the N-type source layer 4 crosses the source electrode 8, the contact between the N-type source layer 4 and the source electrode 8 is more reliable than in the embodiment shown in FIG.
[0079]
Furthermore, in the present embodiment, the width of the source electrode 8 is reduced and the distance L between the gate electrodes is reduced._STherefore, the element region can be used effectively.
[0080]
FIG. 13 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0081]
This embodiment is different from the embodiment shown in FIG. 12 in that a plurality of N-type source layers 4 formed as independent islands are arranged so as to correspond to the steps of the ladder. Even if the N-type source layer 4 is formed in this manner, the latch-up resistance can be increased as in the embodiment shown in FIG. Also, the distance L between adjacent gate electrodes 6_STherefore, the element region can be used effectively.
[0082]
FIG. 14 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0083]
This embodiment is different from the embodiment shown in FIG. 11 in that the N-type source layer 4 is formed in a stripe shape having a very narrow width by using a recent fine processing technique (fine dry etching technique). . According to the present embodiment, since the width of the N-type source layer 4 is narrow, a high latch-up resistance can be realized even in a stripe shape.
[0084]
FIG. 15 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0085]
The feature of this embodiment is that a plurality of P-type base layers 3 formed as independent rectangular islands are arranged periodically and in a matrix. The N-type source layer 4 is formed in a cross shape so as not to easily cause latch-up, and an opening is provided in the center thereof, and the source electrode 8 contacts the P-type base layer 3 through this opening. is doing. With such a layout, the device can be highly integrated and the energization characteristics can be improved.
[0086]
FIG. 16 is a plan view showing a main part (IGBT part) of a power semiconductor device according to still another embodiment of the present invention.
[0087]
A feature of this embodiment is that a plurality of P-type base layers 3 formed as independent hexagonal islands are arranged periodically and in a matrix. The N-type source layer 4 is formed in a star shape so as not to easily cause latch-up, and an opening is provided in the center thereof, and the source electrode 8 contacts the P-type base layer 3 through this opening. is doing. With such a layout, the device can be highly integrated and the energization characteristics can be improved.
[0088]
FIG. 17 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
[0089]
The present embodiment includes an IGBT 105 according to the present invention, a free wheel diode 106 and a junction termination portion 107 disposed adjacent to the IGBT 105. By simultaneously forming the switching element 105 and the diode 106 on the same substrate, inductance and capacitance due to wiring can be reduced, and switching can be performed at high speed and stably.
[0090]
The diode 106 has a P-type anode layer 16 and an N-type cathode layer 18 connected to the source electrode 8 and the drain electrode 7 of the IGBT 105, respectively. The P-type anode layer 16 and the N-type cathode layer 18 are connected via the high-resistance N-type layer 1 and the low-resistance N-type buffer layer 14.
[0091]
An N-type stopper layer 19 is diffused in the surface of the N-type layer 1 at the end of the junction termination portion 107. An insulating film 20 is formed on the surface of the junction termination portion 107 from the P-type anode layer 16 to the N-type stopper layer 19.
[0092]
The IGBT 105 and the diode 106 need to have a sufficient distance (a length longer than the carrier diffusion length). For this reason, the electric field concentrates on the surface of the region between the IGBT 105 and the diode 106, and the breakdown voltage may deteriorate. In order to cope with this problem, a high-resistance P-type diffusion layer 17 is disposed between the P-type base layer 3 of the IGBT 105 and the P-type anode layer 16 of the diode 106. The P-type diffusion layer 17 can be formed at the same time as the P-type diffusion layer 17 of the junction termination portion 107, and therefore there is no need to add an extra forming step.
[0093]
The total amount of impurities in the P-type diffusion layer 17 is 1 × 10¹⁴cm^-2The following is desirable. As a result, the breakdown voltage at the junction termination portion 107 can be maintained well, and the IGBT 105 and the diode 106 can be sufficiently separated.
[0094]
As described above, in the present invention, a power semiconductor device having excellent current-carrying characteristics can be provided by an optimum design of structure and concentration. In particular, it is possible to provide a device that can be controlled by MOS driving at a breakdown voltage of 3 kV or higher, which currently uses GTO (Gate Turn-off Thyristor).
[0095]
Although this device has a parasitic thyristor structure, it does not latch up and is resistant to destruction, so that the protection circuit can be simplified as compared with the GTO. Since the gate circuit and the protection circuit can be simplified as compared with the GTO, the system size is also reduced. For example, when an inverter device is manufactured, the size can be reduced to half of the conventional size. Furthermore, since the device structure is a planar (planar) type, it is easy to form a current extraction portion, and the device structure can be incorporated into various packages.
[0096]
【The invention's effect】
According to the present invention, it is possible to reduce the on-voltage of the device, expand the safe operation area, and increase the latch-up resistance.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of a power semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a main part of a power semiconductor device according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 10 {L_G ²/ (D_B・ W_B)}^1/2And on-voltage V_FThe characteristic view which shows the relationship.
FIG. 11 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 12 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 13 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 14 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 15 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 16 is a plan view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 17 is a cross-sectional view showing a main part of a power semiconductor device according to still another embodiment of the present invention.
FIG. 18 is a cross-sectional view showing a conventional IGBT.
[Explanation of symbols]
1 ... N-type base layer (second conductivity type base layer)
2. P-type emitter layer (first semiconductor layer: first conductivity type emitter layer)
3. P-type base layer (first conductivity type base layer)
4. N-type source layer (second conductivity type source layer)
5 ... Gate insulation film
6 ... Gate electrode
7 ... Drain electrode
8 ... Source electrode
9: N-type diffusion layer (second conductivity type semiconductor layer)
10. Thick film part
11 ... High mobility semiconductor layer

Claims (1)

A power semiconductor device having circuit elements constituting a plurality of IGBTs arranged in parallel,
Each of the circuit elements is
A first conductivity type emitter layer;
A second conductivity type base layer disposed on the first conductivity type emitter layer;
A first conductivity type base layer formed in a surface of the second conductivity type base layer;
A second conductivity type source layer formed in the surface of the first conductivity type base layer;
A gate electrode portion disposed on the first conductivity type base layer sandwiched between the second conductivity type source layer and the second conductivity type base layer via a gate insulating film;
A source electrode portion in contact with the second conductivity type source layer and the first conductivity type base layer;
A drain electrode portion in contact with the first conductivity type emitter layer;
A low-resistance second conductive semiconductor layer formed in the surface of the second conductive base layer and below the gate electrode;
Comprising
In each circuit element of the circuit element, the gate electrode portion is integrated with the gate electrode portion of another circuit element adjacent to one side to form a gate electrode, and the source electrode portion is another circuit element adjacent to the other side. A source electrode is formed integrally with the source electrode portion, and the gate electrode and the source electrode are alternately set;
Using silicon as the device material, the on-voltage of the device is about 4 V, the width of the gate electrode is L _G , the depth of the first conductivity type base layer is D _B , the first conductivity type base layer and the first When the thickness of the second conductive type base layer sandwiched between the conductive type emitter layers is W _B and the distance between the gate electrodes is L _S , 1 ≦ L _G ² / (D _B · W _B ) ≦ 9, satisfying the condition and 60 [mu] m ≦ _{L G} and 5 ≦ _L G / _{L S,}
A power semiconductor device characterized by the above.

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