JP4488935B2 - High voltage semiconductor device - Google Patents

Description

The present invention relates to a high-voltage semiconductor device.

  As a high voltage semiconductor device for performing power conversion in a power supply field that handles high voltage and large current, a structure for high voltage and large current using silicon as an element material has been conventionally used. However, there is a limit in using silicon for further miniaturization and low loss of the high voltage semiconductor device. Therefore, it has been desired to develop a semiconductor device using a new material whose various physical properties exceed the physical properties of silicon. Examples of materials that far exceed the physical property limits of silicon include silicon carbide (hereinafter referred to as SiC) and diamond. The critical electric field of these materials, for example, is 10 times or more that of silicon and very high, and is also called a high critical electric field material. For this reason, the thickness of the drift layer of the semiconductor device can be reduced to about 1/10 or less, and the carrier concentration can be increased 10 times or more. As a result, the electrical resistance can be reduced to about 1/100 or less, and semiconductor devices using these materials are expected to realize a significant reduction in loss. However, in a semiconductor device formed of a high critical electric field material such as SiC, an electric field that is ten times higher than that of a silicon semiconductor device is generated inside the semiconductor device in an off state, so that breakdown due to electric field concentration is likely to occur. Therefore, the structure of the termination portion provided for effectively relaxing the electric field is important. “Termination portion” refers to various semiconductor layers provided around the main junction portion to alleviate electric field concentration near the main junction portion of the semiconductor device.

In general, a silicon semiconductor device uses a termination technique that provides a termination portion such as JTE (Junction Termination Extension), FLR (Field Limiting Ring), FMR (Floating Metal Rings), etc., in order to obtain a high breakdown voltage. These termination portions are formed in the peripheral portion of the semiconductor chip so as to surround the main junction portion, and relieve the electric field at the main junction end portion.
Japanese Patent Laid-Open No. 07-142713 Japanese Patent Laid-Open No. 02-142186 Japanese Patent Application Laid-Open No. 08-078661

  When manufacturing a high voltage semiconductor device with a high critical electric field material such as SiC, the conventional termination technique for relaxing the electric field at the main junction end is not suitable. The reason is that the above-described termination technique has a small width of the depletion layer extending in the drift layer and cannot sufficiently relax the electric field.

FIG. 13 is a cross-sectional view of a semiconductor device having a JTE termination. In the case of this semiconductor device, the JTE region 18 is formed around the end portion of the main junction 5, and the depletion layer 19 is expanded throughout the JTE region 18 when a high voltage is applied, so that also in the outer peripheral direction of the main junction 5. The depletion layer 19 is expanded in the depth direction of the n ⁻ drift layer 6 to relax the electric field at the end of the main junction 5. When the JTE region 18 is highly concentrated, the depletion layer 19 extends into the n ⁻ drift layer 6, but the width of the depletion layer 19 at the end of the JTE region 18 is reduced. If the JTE region 18 is too low in concentration, the depletion layer 19 does not expand, the electric field at the end of the main junction 5 increases, and the breakdown voltage decreases. For this reason, when trying to achieve a high breakdown voltage by expanding the width of the depletion layer 19 to the JTE region 18, the concentration-dependent characteristics of the JTE region 18 become steep, and the width of the optimum allowable concentration that can achieve a high breakdown voltage is extremely narrow. It cannot be manufactured using high-precision concentration control technology such as driving.

  FIG. 14 is a cross-sectional view of a semiconductor device having a FLR termination. In this semiconductor device, the depletion layer 21 is extended in the drift layer 6 between the FLR layers 20 by using a plurality of FLR layers 20 as termination portions. Since the depletion layer 21 does not need to be fully expanded in the FLR layer 20, the FLR layer 20 may be set to a high concentration of a certain concentration or more, which is easy to realize. However, since a plurality of termination FLR layers 20 are used in parallel, the exclusive area becomes large. That is, since the plurality of FLR layers 20 are formed so as to surround the outer periphery of the active region 5, even if the width is small, a large area is occupied. Therefore, there is a problem in that the area of the active region 5 must be reduced by an amount corresponding to the area of the FLR layer 20 in a limited area of the semiconductor device, leading to a decrease in current capacity and an increase in on-resistance.

  In order to realize a high-voltage semiconductor device as described above, a termination structure that effectively relaxes the electric field is necessary. However, in a semiconductor device made of a high critical electric field material such as SiC, it is necessary to form a termination portion. A highly precise concentration control technique was necessary. Moreover, a large occupied area is required for the termination part.

  An object of the present invention is to provide a high voltage semiconductor device having a termination structure that does not require an ultra-high precision concentration control technique and has a small occupation area.

The high voltage semiconductor device of the present invention is
A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of each of the second semiconductor layers other than the connection portion located in part and on an inner surface of each of the grooves; and
Wherein the surface of the insulating layer at the bottom of each groove, said second semiconductor layer and the connection portion conductive layer provided continuously over the surface of which is located on the outer peripheral side than the groove,
It is characterized by having.

In another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove; and
A conductive layer provided continuously from the bottom surface of each groove over the surface of the insulator layer of the second semiconductor layer located on the outer peripheral side of the groove;
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of grooves each having a bottom at a position away from the first main surface of the semiconductor layer of the first conductivity type in a depth direction so as to surround one semiconductor layer;
Of the plurality of grooves, the innermost groove is between the first semiconductor layer and the first main surface of the first conductivity type semiconductor layer outside the first semiconductor layer. A groove outside the innermost groove is divided into a plurality of first main surfaces of the semiconductor layer of the first conductivity type;
The bottom of each groove, the first main surface of the semiconductor layer of the first conductivity type between two adjacent grooves, and the first conductivity type located outside the outermost groove. A conductive layer for forming a Schottky junction provided on each of the first main surfaces of the semiconductor layer;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

In one embodiment of the high breakdown voltage semiconductor device, an inner periphery of the outermost conductive layer is formed on a surface portion of the first conductive type semiconductor layer provided with an outermost conductive layer among the plurality of conductive layers. And a semiconductor layer of another first conductivity type having an impurity concentration higher than the impurity concentration of the semiconductor layer of the first conductivity type is provided in an outer peripheral region separated by a predetermined distance from the end of the first conductivity type. .

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove;
A conductive layer provided on a bottom surface of each groove and in Schottky contact with the semiconductor layer of the first conductivity type;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

In the high voltage semiconductor device of one embodiment,
Another conductive layer formed on the outer peripheral portion of the first main surface of the first conductive type semiconductor layer outside the outermost second semiconductor layer; and
In the surface portion of the first conductive type semiconductor layer on which the other conductive layer is formed, the first conductive layer is formed in an outer peripheral region that is a predetermined distance away from an inner peripheral end of the other conductive layer. Another semiconductor region of the first conductivity type having a concentration higher than the impurity concentration of the conductivity type semiconductor layer is provided.

In the high breakdown voltage semiconductor device of one embodiment, the conductive layer is formed in a portion sandwiched between the insulator layers on both sides at the bottom of each groove.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A conductive layer formed on a bottom surface of each of the grooves and in Schottky contact with the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each second semiconductor layer and a side surface of the groove on each conductive layer;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each of the second semiconductor layers other than the connection portion located in part and on the inner surfaces of the first and second grooves, and
Wherein the surface of the insulating layer at the bottom of each groove, said second semiconductor layer and the connection portion conductive layer provided continuously over the surface of which is located on the outer peripheral side than the groove,
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove; and
A conductive layer provided continuously from the bottom surface of each groove over the surface of the insulator layer of the second semiconductor layer located on the outer peripheral side of the groove;
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of grooves provided in an annular shape so as to surround the first semiconductor layer, each having a bottom at a position away from the bottom surface of the first semiconductor layer in the depth direction;
Of the plurality of grooves, the innermost groove is between the first semiconductor layer and the first main surface of the first conductivity type semiconductor layer outside the first semiconductor layer. A groove outside the innermost groove is divided into a plurality of first main surfaces of the semiconductor layer of the first conductivity type;
The bottom of each groove, the first main surface of the semiconductor layer of the first conductivity type between two adjacent grooves, and the first conductivity type located outside the outermost groove. A conductive layer for forming a Schottky junction provided on each of the first main surfaces of the semiconductor layer;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove;
A conductive layer provided on a bottom surface of each groove and in Schottky contact with the semiconductor layer of the first conductivity type;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

In yet another aspect, the high breakdown voltage semiconductor device of the present invention includes:
A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A conductive layer formed on a bottom surface of each of the grooves and in Schottky contact with the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each second semiconductor layer and a side surface of the groove on each conductive layer;
A first electrode provided in the first semiconductor layer; and
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
It is characterized by having.

According to the present invention, it is possible to provide a high voltage semiconductor device having a termination structure that does not require an ultra-high precision concentration control technique and has a small occupation area.

  Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to FIGS.

<< First Reference Example >>
A first reference example as the basis of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of a trench MOSFET provided with equally spaced trench termination portions according to a first reference example of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1 and 2, the trench type termination portion 39 is formed in an annular shape so as to surround the main junction 1 of the active region 1A. The dimensions of each part in the specific example of this semiconductor device are as follows. The thickness of the n ⁻ drift layer 6 is 50 μm, and the thickness of the n ⁺ drain layer 7 is 300 μm. The thickness of the p ⁺ body layer 5 is 2.5 μm, and the junction depth of the n ⁺ source layer provided in the p ⁺ body layer 5 is 0.5 μm. The depth and width of each trench 9 is 4 μm. The thickness of the gate insulator layer 35 that insulates the trench gate 10 is 1 μm at the bottom of the trench and 0.1 μm at the side of the trench.

The thickness of the insulator layer 36 on the bottom and side surfaces of the trench 9 of the termination portion 39 is 1 μm. The interval between adjacent trenches 9 in the termination portion 39 is 4 μm. Note that the thickness of the insulator layer 35 on the bottom and side surfaces of the trench for the trench gate 10 may be about 0.4 μm. The distance between the surface of the main junction 1 and the bottom surface of the trench 9 may be 4 μm or less, and preferably 1.5 μm or less. In this reference example , the gate electrode 13 has a stripe shape, but the shape may be, for example, a circle or a rectangle. The gate electrode 13 may be, for example, 10 or more stripes.

The manufacturing process of the semiconductor device of this reference example is as follows. First, an n ^{+ -type} SiC (silicon carbide) substrate having an impurity concentration of 10 ¹⁸ to 10 ²⁰ atm / cm ^{3 that} functions as the drain layer 7 is prepared, and 10 ¹⁴ to 10 ¹⁶ atm / cm ³ is formed on one surface thereof. An n ^- drift layer 6 (first conductivity type semiconductor layer) of SiC having an impurity concentration is formed by a vapor deposition method or the like. Next, p ⁺ body layer 5 (first semiconductor layer) and inter-trench p ⁺ layer 3 (with an impurity concentration of about 10 ¹⁶ to 10 ¹⁸ atm / cm ³ are formed on n ⁻ drift layer 6 through a later step. A SiC p ⁺ layer to be a second semiconductor layer) is formed by vapor phase epitaxy (epitaxial method) or the like. In a later step, an n ⁺ region having an impurity concentration of about 10 ¹⁸ atm / cm ³ , which becomes a region indicated by n ⁺ in FIG. 1, is selectively formed into a desired region by an ion implantation method such as nitrogen or phosphorus. Form. Next, the substrate subjected to the above steps is anisotropically etched to penetrate the p ⁺ layer and the bottom portion enters the n ⁻ drift layer 6 by a predetermined distance into the trench for the trench gate 10 and the termination portion 39 ( the first trench 39) . And the second groove) 9 are formed. Next, the trench bottom p ⁺ layer 2 (second conductivity type semiconductor region) having an impurity concentration of about 10 ¹⁶ to 10 ¹⁸ atm / cm ^{3 is formed in} a range of 0.5 μm from the bottom of the trench 9 to boron, aluminum. It is formed by ion implantation or the like. Subsequently, insulating layers 35 and 36 of SiO ₂ are formed on the inner wall of the trench for the trench gate 10 and the inner wall of the trench 9 for the termination portion 39. The insulating layer 35 on the inner wall of the trench gate 10 has a thickness of about 0.1 μm. However, the insulating layer on the inner wall of the trench 9 for the termination portion 39 may be as thick as 0.5 to 1 μm. Thereafter, polysilicon containing phosphorus at a high concentration is deposited and buried in the trench for the trench portion 9 and the trench gate 10. Next, the polysilicon in the trench for the trench gate 10 is left, and the polysilicon in the other part is removed to form a polysilicon gate electrode 13. Finally, a source electrode 12 (first electrode) is formed on the surface of the p ⁺ layer 5 with aluminum, nickel or the like. Further, the drain electrode 11 (second electrode) is formed on the surface of the drain layer 7 of the substrate to complete the substrate. The p ⁺ layer 3 between trenches and the p ⁺ body layer 5 are formed by an epitaxial method, but can also be formed by using an ion implantation method.

The structure and operation principle of the features of the present invention will be described in detail below.
As the first feature of the structure, the trench bottom p ⁺ layer 2, which is a semiconductor region used as FLR (Field Limiting Ring), is located at the bottom of the trench 9, and the inter-trench p ⁺ layer 3 is between adjacent trenches 9. It is in.
Second, there is a certain distance between the trench bottom p ⁺ layer 2 at the bottom of the trench 9 and the p ⁺ layer 3 between the trenches 9 between the adjacent trenches 9, and the upper layer portion of the n ⁻ drift layer 6 therebetween. There is an n ^- layer 4 between the trenches. The inter-trench n ⁻ layer 4 is interposed between the surface of the main junction 1 and the trench bottom p ⁺ layer 2, thereby obtaining the following effects.

When a voltage higher than that of the source electrode 12 is applied to the drain electrode 11 of the semiconductor device having the above structure, the depletion layer 30 indicated by a dotted line is removed from the main junction 1 between the p ⁺ body layer 5 and the n ⁻ drift layer 6. Spreads in the direction of the drain electrode 11 and the source electrode 12 to block the voltage. Around the active region 1A, the depletion layer 30 mainly extends to the n ^- layer 4 between the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 between the trenches, and the electric field of the main junction 1 at the end of the active region 1A. To ease. At this time, since the depletion layer 30 need not almost spread on the trench bottom ^{p +} layer 2 and the trenches between ^{p +} layer 3, ^{10 16} atm impurity concentration of the trench bottom ^{p +} layer 2 and the trenches between ^{p +} layer 3 It is only necessary to make the concentration higher than / cm ^{3 and} it is not necessary to precisely control the concentration. As described above, since the accuracy of the density control technique may be low, manufacturing is easy and easy to realize. Further, the inter-trench n ⁻ layer 4 is located along the wall surface of the trench 9 in the depth direction of the drift layer 6 (direction perpendicular to the surface of the semiconductor device) and between the trench p ⁺ layer 3 and the trench bottom p ⁺ layer 2. Therefore, the increase in surface area is not affected. Therefore, in the limited surface area of the semiconductor device, the area of the active region 1A can be increased by an amount corresponding to the dimension in the depth direction of the n ⁻ layer 4 between the trenches. Since the area of the active region 1A is increased, an increase in current capacity and a reduction in on-resistance can be achieved. Further, when the trench for the trench gate 10 is formed in the active region 1A of the MOSFET, the trench 9 for the termination portion 39 can be formed at the same time, so that the process can be simplified. Furthermore, by filling the trenches for the trench 9 and the trench gate 10 with polysilicon, SiO ₂ or the like, contamination of the surface of the semiconductor device can be prevented and high reliability can be realized.

An example of the dimensions of each part of the trench type termination part 39 of this reference example is shown in FIG. FIG. 3B shows the dimensions of the termination portion of the MOSFET with FLR of a conventional semiconductor device having a breakdown voltage comparable to that of the semiconductor device. In FIG. 3A, the horizontal dimension of the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 is 2 μm, respectively, and the total dimension is 4 μm. The distance between the p ⁺ layer 3 between the trenches and the bottom p ⁺ layer 2 of the trench, that is, the dimension in the depth direction of the n ⁻ layer 4 between the trenches is 1 μm. On the other hand, in FIG. 3B, the horizontal dimension of the two p ⁺ layers 2A and 2B is 2 μm and the total dimension is 4 μm. The distance of the n ⁻ layer 4B between the two p ⁺ layers 2A and 2B is 1 μm, and the distance of the n ⁻ layer 4A between the p ⁺ layer 2A and the p ⁺ body layer 5 is 1 μm. The total dimension is therefore 6 μm. In the termination portion 39 of this reference example, the n ⁻ layer 4 between trenches corresponding to the n ⁻ layers 4A and 4B in FIG. 3B is formed by the p ⁺ layer 3 between the trenches in the depth direction of the drift layer 6 and the bottom of the trench. It will be formed between the p ⁺ layers. As a result, the inter-trench n ⁻ layer 4 becomes irrelevant to the increase in the area of the termination portion 39, and the presence of the inter-trench n ⁻ layer 4 does not lead to an increase in the surface area of the termination portion 39. Ie, the surface area is reduced as compared with the correspondingly conventional. The area of the termination portion 39 of this reference example is two-thirds the area of the conventional FLR, and in the same size semiconductor device, the area of the active region 1A can be increased accordingly, so that the current capacity is increased. And reduction of on-resistance can be achieved.

In this reference example , as shown in FIG. 1, the semiconductor device having the termination portion 39 including the three trenches 9 is taken as an example. However, the provision of the termination portion 39 having a larger number of trenches 9 further increases the breakdown voltage. Can be realized. For example, the breakdown voltage of 4800 V when the termination portion 39 having three trenches 9 is provided is increased to 5300 V when the termination portion 39 having five trenches 9 is provided. In this reference example , the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 have almost the same impurity concentration to simplify the process. However, by changing these impurity concentrations individually, the MOSFET on-state characteristics and breakdown voltage can be reduced. Since it can be improved independently, further performance improvement can be achieved. Further, by setting the impurity concentration of the plurality of trench bottom p ⁺ layers 2 to a predetermined value and setting the impurity concentration of the plurality of p ⁺ layers 3 between the trenches to predetermined values, the on-characteristics and breakdown voltage are further improved. Can do. For example, when the impurity concentration of the trench bottom p ⁺ layer 2 is 3 × 10 ¹⁷ atm / cm ³ and the impurity concentration of the p ⁺ layer 3 between trenches is 10 ¹⁸ atm / cm ³ , the breakdown voltage is not changed to 4800V. The on-resistance can be reduced from 35 mΩcm ² to 28 mΩcm ² . Further, with respect to the impurity concentrations of the plurality of trench bottom p ⁺ layers 2 and inter-trench p ⁺ layers 3, the impurity concentration of the innermost periphery is the highest, and the impurity concentration at the outer periphery is higher toward the outer periphery. You may form so that it may reduce gradually. For example, when ten trenches 9 are provided in the termination portion 39, the impurity concentration of the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 of the innermost trench 9 is 10 ¹⁹ atm / cm ³ , The trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 of the nine outer peripheral trenches 9 were formed so that the impurity concentration gradually decreased from 5 × 10 ¹⁸ to 10 ¹⁶ atm / cm ³ . In addition, when the thickness of the n ⁻ drift layer 6 was 150 μm and the impurity concentration was 10 ¹⁴ atm / cm ³ , the breakdown voltage could be increased to 20 KV.

<< Second Reference Example >>
FIG. 4 is a cross-sectional view of a semiconductor device of a second reference example serving as a basis of the present invention. The semiconductor device of this reference example is a trench MOSFET having a termination portion 39 having unequally spaced trenches 9A and 9B. In FIG. 4, the width of the trench 9A of the first-stage trench type termination portion 39A adjacent to the active region 1A is made larger than the widths of the other trenches 9B. A p ⁺ electric field relaxation layer 40 is formed at the bottom of the trench gate 10. Since other configurations are the same as those of the first reference example , description thereof is omitted.
In the semiconductor device of this reference example , when the voltage is blocked, the depletion layer is further away from the main junction 1 by the trench bottom p ⁺ layer 2A formed at the bottom of the first-stage wide trench 9A. Can be expanded. Therefore, the electric field at the end of the main junction 1 is further relaxed, and a high breakdown voltage semiconductor device can be realized. For example, when the width of the first-stage trench 9A is 30 μm, the breakdown voltage can be 5800V. As a result, the breakdown voltage could be increased by about 25% compared to the semiconductor device of the first reference example having the trench type termination portion in which the trenches 9 having a width of 4 μm were formed at equal intervals. By further widening the width of the first-stage trench 9A, it is possible to further increase the breakdown voltage. For example, when the thickness is 60 μm, the breakdown voltage can be further increased to 6000 V. In this case, the on-resistance was 35 mΩ / cm ^2, which was the same value as that of the first reference example .

<< First Example >>
FIG. 5 is a sectional view of the semiconductor device according to the first embodiment of the present invention. The semiconductor device of the present embodiment is a trench MOSFET having equidistant trench termination portions having auxiliary electrodes (field plates) 14. First, similarly to the semiconductor device of the first reference example shown in FIG. 1, insulating layers 15A and 15 such as SiO ₂ are formed on the bottom and side surfaces of the trench 9 of the termination portion 39, respectively. Next, the auxiliary electrode 14 whose one end is in contact with the insulator layer 15A on the bottom surface of the trench 9 is formed. The other end of the auxiliary electrode 14 is brought into contact with the connecting portion 3A at the top of the p ⁺ layer 3 between the trenches. As a result of providing the auxiliary electrode 14, the depletion layer 30 in the vicinity of the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 was further expanded in the direction of the drain electrode 11. As a result, the depletion layer further spreads on the outer periphery of the active region 1A, and the electric field near the main junction 1 is further relaxed. As a result, the withstand voltage was higher by 35% or more than that of the first reference example . Further, as in the first reference example , the exclusive area of the termination part was reduced to about two thirds compared to the conventional termination part.

<< Second Embodiment >>
FIG. 6 is a cross-sectional view of a trench MOSFET having an auxiliary electrode 14 (field plate) and an equally spaced trench termination 39 in the semiconductor device according to the second embodiment of the present invention. In the second embodiment , an insulating layer 15 such as SiO ₂ is formed on the side surface of the trench 9 of the termination portion 39 and the upper surface of the p ⁺ layer 3 between the trenches. The second embodiment is different from the first embodiment in that an auxiliary electrode 14A having one end in contact with the insulating layer 15 on the upper surface of the p ⁺ layer 3 between the trenches and the other end in contact with the trench bottom p ⁺ layer 2 is formed. By bringing auxiliary electrode 14A into contact with the bottom p ⁺ layer of the trench, the electric field of insulator layer 15 in trench 9 is relaxed. As a result, as in the case of the first example , the electric field in the vicinity of the main junction 1 was relaxed, and the breakdown voltage was higher by 35% or more than that of the first reference example . Further, as in the first reference example , the exclusive area of the termination part 39 could be reduced to about two-thirds compared to the conventional termination part.

<< Third Reference Example >>
FIG. 7 is a cross-sectional view of a trench MOSFET including a termination portion 39 having shallow equidistant trenches 9 in a semiconductor device according to a third reference example of the present invention. In the figure, the distance from the main surface 46 of the active region 1A of the surface of the junction portion 43 of the inter-trench n ⁻ layer 4 and the inter-trench p ⁺ layer 3 of the termination portion 39 is larger than that of the first reference example. It is closer to the drain electrode 11 side than the position of the portion 1. Moreover, the point that the thickness of the p ⁺ layer 3 between the trenches is thinner than the trench bottom p ⁺ layer 2 is also different from the first reference example . When the inter-trench p ⁺ layer 3 approaches the drain electrode 11, the depletion layer 30 tends to expand toward the drain electrode 11, and as a result, a high breakdown voltage semiconductor device can be realized. Moreover, the exclusive area of the termination part 39 can also be reduced to 2/3 compared with the conventional one like the first reference example .

<< Third embodiment >>
FIG. 8 is a cross-sectional view of a trench MOSFET including a trench termination 39 having a Schottky junction (hereinafter referred to as a Schottky contact) in the semiconductor device according to the third embodiment of the present invention. In this embodiment, the trench bottom p ⁺ layer 2 and the inter-trench p ⁺ layer 3 provided in the termination portion 39 of each of the above embodiments are not formed. In this embodiment, Schottky contacts 17A, 17B, 17C, 17D, 17E, and 17F are formed of a thin film such as gold or platinum on the bottom of each trench 9 and the surface of the n ⁻ drift layer 6 between each trench 9. Adjacent Schottky contacts, for example, Schottky contacts 17A and 17B, are provided on the n ^- drift layer 6 having a step, and each Schottky contact 17A to 17F is formed in an annular shape so as to surround the active region 1A. A Schottky contact 17G is formed of gold, platinum or the like on the surface of the outermost field limiter n ⁺ layer 16 of the termination portion 39, and the inner edge of the Schottky contact 17G is further inside than the inner edge of the field limiter n ⁺ layer 16. It is made to come to. The depletion layer 30 extends in the direction of the drain electrode 11 by the Schottky contacts 17A, 17C, 17E at the bottom of the trench 9 and the Schottky contacts 17B, 17D, 17F, 17G between the trenches 9. As a result, the electric field in the vicinity of the main junction 1 is relaxed, and a withstand voltage characteristic similar to that of the first reference example is obtained. Even when the surface of the semiconductor device is contaminated, the field limiter n ⁺ layer 16 prevents the depletion layer 30 from extending to the end along the surface of the n ⁻ drift layer 6 and prevents a decrease in breakdown voltage.

With respect to the Schottky contact 17G inside the field limiter n ⁺ layer 16, the extension of the depletion layer 30 extending along the surface is suppressed not only by the field limiter n ⁺ layer 16 but also by the electric field effect of the Schottky contact 17G. This can prevent the field limiter n ⁺ layer 16 from increasing the electric field strength and decreasing the breakdown voltage.

For example, in the semiconductor device having the same structural specifications as the first reference example , when surface contamination exists, the breakdown voltage is 4500 V, but in the semiconductor device of the third embodiment , it can be kept at 4800 V. Needless to say, if surface contamination can be prevented by means of packaging, etc., the desired effect can be achieved without providing the Schottky contact 17G of the field limiter n ⁺ layer 16.

<< 4th Example >>
FIG. 9 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention. In the fourth embodiment, inter-trench Schottky contact 17B in the semiconductor device of the third embodiment, 17D, instead of 17F, the point of forming a trench between the p ⁺ layer 53 by an ion implantation method, different from the third embodiment . An insulating layer 15 is formed on the side surface of each trench 9 of the termination portion 39 and the surface of the p ⁺ layer 53 between the trenches. Schottky contacts 17A, 17C, and 17E are provided at portions sandwiched between the insulating layers 15 on the bottom surface of the trench 9, respectively. Similar to the third embodiment , the semiconductor device of the fourth embodiment also exhibits high withstand voltage, and the area occupied by the termination portion 39 is small.

<< 5th Example >>
FIG. 10 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. The fifth embodiment is different from the fourth embodiment in that Schottky contacts 17A, 17C, and 17E are formed on the entire bottom surface of the trench 9 of the termination portion 39, respectively. By forming Schottky contacts 17A, 17C, and 17E on the entire bottom surface of the trench 9, a depletion layer also extends from the bottom surface end portion of the trench 9 of the termination portion 39 when the semiconductor device is turned off. The electric field of the n ⁻ layer 4 between adjacent trenches is further relaxed, and a high breakdown voltage can be achieved.

In the semiconductor device of each embodiment described above, by connecting the gate G to the source S, can function as a two-pole semiconductor device or diode source S and drain Lee emissions D. Even in the diode configured as described above, a high breakdown voltage can be achieved as in the MOSFET described in each of the above embodiments, and a diode having a low loss and a large current capacity can be obtained.

《Inverter device》
FIG. 11 is a circuit diagram showing an example of a three-phase inverter, which is a power conversion device configured using a MOSFET and a diode to which the present invention is applied. Six MOSFETs SW11, SW12, SW21, SW22, SW31, and SW32 as switching elements are connected by a connection method well known in the art. Diodes D11, D12, D21, D22, D31, and D32 are connected in reverse parallel to the MOSFETs SW11, SW12, SW21, SW22, SW31, and SW32, respectively. The MOSFETs SW11 to SW32 are subjected to switching control by a control circuit (not shown), and an input DC voltage is converted into a three-phase AC voltage to obtain an AC output 60. The MOSFETs SW11... SW32 are the MOSFETs according to any one of the embodiments described above , and are switching elements that have a high breakdown voltage and a high switching speed. By applying the present invention to the MOSFET and the diode, the inverter can have a high breakdown voltage. In a conventional MOSFET using SiC, a high withstand voltage of 500 V or higher increases the on-resistance, and it is difficult to improve the performance of the high withstand voltage inverter. When the semiconductor device according to each embodiment of the present invention is applied, high performance of the high voltage inverter device, that is, compactness, low loss, and low noise can be achieved. As a result, it is possible to reduce the cost and increase the efficiency of the system using the inverter device.

《Rectifier device》
FIG. 12 is a circuit diagram showing an example of a rectifier configured using a MOSFET and a diode to which the present invention is applied. The four MOSFETs SW11, SW12, SW21, and SW22 connected in a bridge and the diodes D11, D12, D21, and D22 connected in reverse parallel to the MOSFETs SW11, SW12, SW21, and SW22, respectively, are connected to the semiconductor device of any of the above embodiments. Use. By this rectifier circuit, the AC voltage of the AC power supply 61 is converted into a DC voltage. The MOSFET of the present invention is an element having a high withstand voltage and a large switching speed. By applying the present invention to this element and a diode, the high withstand voltage rectifier can be made compact, low loss, low noise, etc. An effect is obtained. Therefore, low cost and high efficiency of the system using the rectifier can be achieved.

Although the embodiments of the present invention have been described above, the present invention covers more application ranges or derived structures.
In the first, second, fourth, and fifth embodiments , the impurity concentration of the innermost periphery of each of the plurality of trench bottom p ⁺ layers 2 and inter-trench p ⁺ layers 3 is the highest. However, the outer periphery may be formed so that the impurity concentration gradually decreases toward the outer periphery. Further, both impurity concentrations may be arbitrarily set.
In each of the above embodiments, only the case of the SiC element has been described, but the present invention can be applied to other semiconductor materials such as silicon and gallium arsenide. In particular, it is effective for wide gap semiconductor materials such as diamond and gallium nitride.

  In the description of each of the above embodiments, only the case where the drift layer 6 is an n-type element has been described. However, even when the drift layer 6 is a p-type element, each n-type layer is changed to a p-type layer, The structure of the present invention can be applied by changing the layer to an n-type layer. Further, applicable elements are not limited to MOSFETs, and can be widely applied to IGBTs, GTOs, SI transistors, SI thyristors, diodes, thyristors, and the like. The structure of the active region or the main junction of each semiconductor device can be applied to any of a planar type, a trench type, a buried type, and the like.

  The present invention is applicable to a power semiconductor device having a high withstand voltage.

The top view of the trench type MOSFET which has the equidistant trench type termination part which is a semiconductor device of the 1st reference example used as the foundation of the present invention II-II sectional view of FIG. (A) is principal part sectional drawing of the semiconductor device of a 1st reference example , (b) is principal part sectional drawing of the semiconductor device which has the conventional FLR (Field Limiting Ring). Sectional drawing of the trench type | mold MOSFET which has the trench type | mold termination part of an unequal interval which is a semiconductor device of the 2nd reference example used as the foundation of this invention Sectional drawing of trench type MOSFET which has an auxiliary electrode (field plate) which is a semiconductor device of 1st Example of this invention, and equidistant trench type termination part Sectional drawing of trench type MOSFET which has an auxiliary electrode (field plate) which is a semiconductor device of 2nd Example of this invention, and equidistant trench type termination part Sectional drawing of the trench type | mold MOSFET which has a shallow equidistant trench type | mold termination part which is a semiconductor device of the 3rd reference example of this invention Sectional drawing of MOSFET which has a trench type termination type part which has a Schottky contact which is a semiconductor device of 3rd Example of this invention Sectional drawing of MOSFET which has a trench type termination type part which has a Schottky contact which is a semiconductor device of 4th Example of this invention Sectional drawing of MOSFET which has a trench type termination type part which has a Schottky contact which is a semiconductor device of 5th Example of this invention Circuit diagram of inverter device using semiconductor device of the present invention Circuit diagram of rectifier using semiconductor device of the present invention Sectional view of a semiconductor device having a conventional JTE (Junction Termination Extension) Sectional view of a semiconductor device having a conventional FLR (Field Limiting Ring)

DESCRIPTION OF SYMBOLS 1 Main junction part 1A Active region 2, 2A, 2B Trench bottom p ⁺ layer 3, 3A Inter-trench p ⁺ layer 4 Inter-trench n ^- layer 4A, 4B n ^- layer 5p ⁺ body layer 6 n ^- drift layer 7 Drain region 9, 9A, 9B Termination trench 10 Trench gate 11 Drain electrode 12 Source electrode 13 Gate electrode 14, 14A Auxiliary electrode 15 Termination trench insulator layer 16 Field limiter 17, 17A, 17B, 17C, 17D, 17E, 17F, 17G Schottky contact 18 JTE region 19 depletion layer 20 FLR layer 21 depletion layer 30 depletion layer 35, 36 insulator layer 39, 39A termination portion 40 p ⁺ electric field relaxation layer 43 junction portion 46 main surface 53 p ⁺ layer between trenches MOSFET SW11, SW12, SW21 , SW22, SW31, SW32
Diode D11, D12, D21, D22, D31, D32

Claims (13)

A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of each of the second semiconductor layers other than the connection portion located in part and on an inner surface of each of the grooves; and
Wherein the surface of the insulating layer at the bottom of each groove, said second semiconductor layer and the connection portion conductive layer provided continuously over the surface of which is located on the outer peripheral side than the groove,
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove; and an insulator layer of the second semiconductor layer located on the outer peripheral side of the groove from the bottom surface of each groove. A conductive layer provided continuously over the surface,
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of grooves each having a bottom at a position away from the first main surface of the semiconductor layer of the first conductivity type in a depth direction so as to surround one semiconductor layer;
Of the plurality of grooves, the innermost groove is between the first semiconductor layer and the first main surface of the first conductivity type semiconductor layer outside the first semiconductor layer. A groove outside the innermost groove is divided into a plurality of first main surfaces of the semiconductor layer of the first conductivity type;
The bottom of each groove, the first main surface of the semiconductor layer of the first conductivity type between two adjacent grooves, and the first conductivity type located outside the outermost groove. A conductive layer for forming a Schottky junction provided on each of the first main surfaces of the semiconductor layer;
A first electrode provided on the first semiconductor layer, and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising:   An outer peripheral region at a predetermined distance from an inner peripheral end of the outermost conductive layer in a surface portion of the first conductive type semiconductor layer provided with an outermost conductive layer among the plurality of conductive layers 4. The high withstand voltage semiconductor device according to claim 3, wherein another semiconductor layer of the first conductivity type having an impurity concentration higher than that of the first conductivity type semiconductor layer is provided. A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove;
A conductive layer provided on a bottom surface of each groove and in Schottky contact with the semiconductor layer of the first conductivity type;
A first electrode provided on the first semiconductor layer, and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising: Another conductive layer formed on the outer peripheral portion of the first main surface of the first conductivity type semiconductor layer outside the outermost second semiconductor layer, and the other conductive layer, In the surface portion of the formed first conductive type semiconductor layer, the first conductive type semiconductor layer formed in the outer peripheral region at a predetermined distance from the inner peripheral end of the other conductive layer. 6. The high breakdown voltage semiconductor device according to claim 5, further comprising another semiconductor region of the first conductivity type having a concentration higher than the impurity concentration.   6. The high withstand voltage semiconductor device according to claim 5, wherein the conductive layer is formed in a portion sandwiched between the insulator layers on both sides of the bottom surface of each groove. A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A conductive layer formed on a bottom surface of each of the grooves and in Schottky contact with the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each second semiconductor layer and a side surface of the groove on each conductive layer;
A first electrode provided on the first semiconductor layer; and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each of the second semiconductor layers other than the connection portion located in part and on the inner surfaces of the first and second grooves, and
Wherein the surface of the insulating layer at the bottom of each groove, said second semiconductor layer and the connection portion conductive layer provided continuously over the surface of which is located on the outer peripheral side than the groove,
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of annular second conductivity type second semiconductor layers formed inside the first conductivity type semiconductor layer so as to surround the first semiconductor layer;
Each of the first and second semiconductor layers has a bottom at a position away from the bottom surface in the depth direction, and the innermost second semiconductor layer of the plurality of second semiconductor layers and the first semiconductor layer A first groove separating the semiconductor layer and a second groove separating the two adjacent second semiconductor layers;
A second conductive type semiconductor region formed in each of the first conductive type semiconductor layers from the bottom of each groove;
A first electrode provided in the first semiconductor layer;
A second electrode provided on a second main surface of the semiconductor layer of the first conductivity type;
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove; and an insulator layer of the second semiconductor layer located on the outer peripheral side of the groove from the bottom surface of each groove. A conductive layer provided continuously over the surface,
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first conductivity type first semiconductor layer formed inside the first conductivity type semiconductor layer in a depth direction from a portion of the first main surface of the first conductivity type semiconductor layer;
A predetermined gap is maintained between the first main surface of the first conductivity type semiconductor layer and the first semiconductor layer in a depth direction from a region having no first semiconductor layer in the first main surface. A plurality of grooves provided in an annular shape so as to surround the first semiconductor layer, each having a bottom at a position away from the bottom surface of the first semiconductor layer in the depth direction;
Of the plurality of grooves, the innermost groove is between the first semiconductor layer and the first main surface of the first conductivity type semiconductor layer outside the first semiconductor layer. A groove outside the innermost groove is divided into a plurality of first main surfaces of the semiconductor layer of the first conductivity type;
The bottom of each groove, the first main surface of the semiconductor layer of the first conductivity type between two adjacent grooves, and the first conductivity type located outside the outermost groove. A conductive layer for forming a Schottky junction provided on each of the first main surfaces of the semiconductor layer;
A first electrode provided on the first semiconductor layer, and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
An insulator layer formed on a surface of the second semiconductor layer and a side surface of each groove;
A conductive layer provided on a bottom surface of each groove and in Schottky contact with the semiconductor layer of the first conductivity type;
A first electrode provided on the first semiconductor layer, and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising: A semiconductor layer of a first conductivity type;
A first semiconductor layer of a second conductivity type formed on a portion of the first main surface of the semiconductor layer of the first conductivity type;
The first conductive surface of the first conductivity type semiconductor layer has a predetermined distance between the first main surface and a region not having the first semiconductor layer, with a predetermined interval between the first semiconductor layer and the first main surface. A plurality of annular second conductivity type second semiconductor layers provided so as to surround one semiconductor layer;
The innermost second semiconductor layer of the plurality of second semiconductor layers having a bottom at a position away from the first main surface in the depth direction of the first conductivity type semiconductor layer. And a first groove separating the first semiconductor layer and a second groove separating the two adjacent second semiconductor layers,
A conductive layer formed on a bottom surface of each of the grooves and in Schottky contact with the semiconductor layer of the first conductivity type;
An insulating layer formed on a surface of each second semiconductor layer and a side surface of the groove on each conductive layer;
A first electrode provided on the first semiconductor layer; and a second electrode provided on a second main surface of the first conductivity type semiconductor layer;
A high voltage semiconductor device characterized by comprising:

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