JP4489575B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a shield material and a manufacturing method thereof.

  Some conventional semiconductor devices include a shield case for protecting a plurality of electronic components (individual components, semiconductor chips, etc.) mounted on a substrate from electromagnetic waves. 1 and 2 are cross-sectional views of a conventional semiconductor device provided with a shield case. 1 and 2, H1 is the height of the potting resin 35 (hereinafter referred to as “height H1”), H2 is the height of the semiconductor device 10 (hereinafter referred to as “height H2”), and H3. Denotes the height of the semiconductor device 40 (hereinafter referred to as “height H3”), and A denotes the gap between the potting resin 35 and the shield case 36 (hereinafter referred to as “gap A”). In FIG. 2, the same components as those in FIG.

  As shown in FIG. 1, the semiconductor device 10 generally includes a substrate 11, individual components 26, a semiconductor chip 31, solder balls 25, and a shield case 36. The substrate 11 is roughly configured to include a base material 12, a through via 13, connection portions 14 and 15, a ground terminal 16, solder resists 17 and 23, and wiring 21. The through via 13 is disposed so as to penetrate the base material 12. The through via 13 is for electrically connecting the connection portions 14 and 15 and the wiring 21.

  The connection parts 14 and 15 are provided on the upper surface of the base material 12 and are electrically connected to the through via 13. The connection portion 14 is electrically connected to the semiconductor chip 31 via the gold wire 34. The connection unit 15 is electrically connected to the individual component 26. The ground terminal 16 is a conductor having a ground potential, and is provided on the base material 12 positioned outside the region where the individual component 26 and the semiconductor chip 31 are provided. The solder resist 17 is formed on the base material 12 so as to separate the connection portion 14 and the connection portion 15.

  The wiring 21 has a connection pad 22 to which the solder ball 25 is connected. The wiring 21 is provided on the lower surface of the substrate 12 so as to be connected to the through via 13. The solder resist 23 is provided on the lower surface side of the substrate 12 so as to expose the connection pads 22 and cover the wirings 21 other than the connection pads 22.

  The individual component 26 is a basic electrical element such as a transistor, a diode, a resistor, or a capacitor, and has one function as one component. The individual component 26 is electrically connected to the connection portion 15 by a solder paste 27.

  The semiconductor chip 31 is configured to include a semiconductor chip body 32 and electrode pads 33. The semiconductor chip body 32 is bonded onto the substrate 12 with an adhesive 24. The semiconductor chip 31 is electrically connected to the substrate 11 by a gold wire 34 that connects between the electrode pad 33 and the connection portion 14. The semiconductor chip 31 is covered with a potting resin 35 (resin formed by a potting method) for protecting the gold wire 34 (see, for example, Patent Document 1).

  The solder ball 25 is electrically connected to the connection pad 22. The solder ball 25 is an external connection terminal for connecting the semiconductor device 10 to another substrate such as a mother board.

  The shield case 36 covers the individual component 26 and the semiconductor chip 31 and is electrically connected to the ground terminal 16 by the solder paste 37 with a gap A provided between the shield case 36 and the potting resin 35. By providing such a shield case 36 in the semiconductor device 10, the individual component 26 and the semiconductor chip 31 can be protected from electromagnetic waves.

As shown in FIG. 2, in the semiconductor device 40, the ground terminal 42 is provided by the solder paste 37 in a state where the ground terminal 42 is provided on the side surface of the base material 41 and the gap A is provided between the potting resin 35 and the shield case 44. And the shield case 44 are electrically connected. As described above, the ground terminal 42 is provided on the side surface of the base material 41, and the ground terminal 42 and the shield case 44 are connected to each other as compared with the semiconductor device 10 provided with the ground terminal 16 on the top surface of the base material 12. The semiconductor device 40 can be downsized. Although not shown in FIGS. 1 and 2, the semiconductor devices 10 and 40 are provided with other semiconductor chips that are flip-chip connected. The potting resin 35 may be covered.
JP 2001-267628 A

  However, the potting resin 35 formed by the potting method has a problem that it is difficult to control the height H1, and since it takes time to form the resin, there is a problem that productivity of the semiconductor devices 10 and 40 is lowered. . In addition, in order to prevent the convex shape of the potting resin 35 from being transferred to the shield cases 36 and 44, it is necessary to provide a gap A between the potting resin 35 and the shield cases 36 and 44. Thus, the semiconductor device The heights H2 and H3 of 10 and 40 become high, and there is a problem that it is difficult to downsize the semiconductor devices 10 and 40.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor device that can be reduced in size and improved in productivity and a method for manufacturing the same.

  In order to solve the above-mentioned problems, the present invention is characterized by the following measures.

In the invention of claim 1, wherein a plate-shaped substrate, a semiconductor chip mounted on the substrate, provided on a side surface of said substrate, a conductor having a predetermined potential, so as to cover the semiconductor chip comprising a transfer molding resin provided on said substrate, the contact with the upper surface of the transfer molding resin, and the shield member being connected to said conductor, and a solder resist layer provided on the lower surface of the substrate In the semiconductor device, the conductor has a columnar shape in which a conductive member is disposed so as to fill a space of the notch portion in a semicircular notch portion formed on a side surface of the base material. The side surface of the conductor can be solved by a semiconductor device characterized by forming the same plane as the side surfaces of the transfer mold resin, the base material, and the solder resist layer.

According to the above invention, the transfer mold resin is provided so as to cover the semiconductor chip, and the shield material is disposed so as to be in contact with the upper surface of the transfer mold resin, thereby comparing with a conventional semiconductor device using a potting resin, The size of the semiconductor device in the height direction can be reduced. Further, by using a transfer mold resin formed by a transfer mold method, productivity of the semiconductor device can be improved as compared with a conventional semiconductor device using a potting method. Here, the predetermined potential is, for example, a ground potential or a potential such as a power supply potential of the semiconductor chip. Furthermore, by providing the conductor on the side surface of the substrate, the size in the surface direction of the base material of the semiconductor device can be reduced.

  The invention according to claim 2 can be solved by the semiconductor device according to claim 1, wherein the upper surface of the transfer mold resin is a flat surface.

  According to the above invention, by forming the upper surface of the transfer mold resin as a flat surface, it is possible to prevent a gap from being formed between the shield material in contact with the transfer mold resin and the transfer mold resin. The size in the height direction can be reduced. In addition, handling properties when the semiconductor device is mounted on another substrate (for example, a mother board) can be improved.

In the invention of claim 3, wherein a plate-shaped substrate, a semiconductor chip mounted on the substrate, provided on a side surface of said substrate, a conductor having a predetermined potential, so as to cover the semiconductor chip comprising a transfer molding resin provided on said substrate, the contact with the upper surface of the transfer molding resin, and the shield member being connected to said conductor, and a solder resist layer provided on the lower surface of the substrate and the method of manufacturing a semiconductor device, before Kimoto material before division has a plurality of substrate forming areas arranged to suit Ri next, on the boundary of the substrate forming region, a through-hole in the substrate A conductive member forming step in which a conductive member is provided in the through-hole so as to fill the through-hole to form a conductor having the predetermined potential; and each of the substrates the group definitive formation region Above, and the semiconductor chip mounting step of mounting the semiconductor chip, each of said substrate forming region definitive the substrate on the transfer molded resin forming step of forming a transfer molding resin so as to cover the semiconductor chip, the transfer After the molding resin forming step, a solder resist layer forming step for forming a solder resist layer that covers regions other than the connection pads on the lower surface of the conductor and the lower surface of the base material, and the transfer along the boundary line of the substrate forming region By cutting the mold resin, the base material, the solder resist layer and the conductive member to form a semi-cylindrical conductor, the cut surface of the conductor, the cut surface of the transfer mold resin, the cut surface of the base material And a conductor forming step in which the cut surface of the solder resist layer forms the same plane; This can be solved by a method for manufacturing a semiconductor device, comprising: a shield material disposing step of contacting a top surface of the transfer mold resin and disposing a shield material so as to be electrically connected to the conductor. .

  According to the above invention, a plurality of substrate forming regions are arranged adjacent to one base material, and a conductive member that penetrates the base material and has a predetermined potential is provided on the boundary line of the substrate forming region, After mounting the semiconductor chip, form a transfer mold resin to cover the semiconductor chip, cut the base material along the boundary line of the substrate forming area to form a conductor, and electrically connect the conductor and the shield material Thus, more semiconductor devices can be manufactured on one base material than before, and the productivity of the semiconductor devices can be improved. Here, the predetermined potential is, for example, a ground potential or a potential such as a power supply potential of the semiconductor chip.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to reduce in size, the semiconductor device which can improve productivity, and its manufacturing method can be provided.

Next, embodiments of the present invention will be described with reference to the drawings.
(Example)
First, the configuration of the semiconductor device 50 according to the embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. In FIG. 4, the X and X directions indicate the surface direction of the base material 52, and the Y and Y directions indicate the height direction of the semiconductor device 50 orthogonal to the X and X directions. 4 is the height of the transfer mold resin 90 (hereinafter referred to as “height H4”) when the upper surface 52A of the base material 52 is used as a reference, and H5 is the height of the semiconductor device 50 (hereinafter referred to as “height H4”). , “Height H5”).

  The semiconductor device 50 roughly includes a substrate 51, individual components 71, a first semiconductor chip 75, a second semiconductor chip 81, a transfer mold resin 90, a shield material 91, and solder balls 94. It is configured. The substrate 51 is roughly configured to include a base material 52, a through via 53, a ground terminal 54, first to third connection portions 56 to 58, solder resists 61 and 64, and wiring 62. ing. The outer shape of the substrate 51 can be 9 mm □, for example. The through via 53 is provided so as to penetrate the base material 52. The through via 53 is for electrically connecting the first to third connection portions 56 to 58 and the wiring 62.

  FIG. 5 is a perspective view of the ground terminal of the present embodiment. The ground terminal 54 is a conductor having a ground potential (“predetermined potential” described in claims). The ground terminal 54 is disposed in a notch 95 formed on each of the four side surfaces of the substrate 52. The notch 95 has a columnar shape whose upper and lower bottom surfaces are semicircular. The notch 95 is one of the two through holes 102 (see FIG. 9 and FIG. 18), which will be described later, divided into two equal parts along the boundary line of the substrate formation region E. The ground terminal 54 is electrically connected to the shield material 91 by the solder paste 93. For example, Cu can be used as the material of the ground terminal 54.

  Thus, by providing the ground terminal 54 on the side surface of the base material 52, the semiconductor in the surface direction (X, X direction) of the base material 52 is compared with the case where the ground terminal is provided on the upper surface 52A of the base material 52. The size of the device 50 can be reduced.

  The first to third connection portions 56 to 58 are provided on the upper surface 52 </ b> A of the base material 52, and are electrically connected to the through vias 53, respectively. The first connection portion 56 is electrically connected to the electrode 72 of the individual component 71. The second connection portion 57 is provided with a wire 79 electrically connected to the first semiconductor chip 75. The third connection portion 58 is for electrically connecting the second semiconductor chip 81 via the stud bump 83.

  The solder resist 61 is provided on the upper surface 52A of the base member 52 so as to separate the first to third connection portions 56 to 58. The wiring 62 has a connection pad 63 and is disposed on the lower surface 52 </ b> B of the base material 52 so as to be electrically connected to the through via 53. The connection pad 63 is electrically connected to the solder ball 94. The solder resist 64 is provided on the lower surface 52 </ b> B side of the base material 52 so as to expose the connection pads 63 and cover the wirings 62 other than the connection pads 63. The solder balls 94 are external connection terminals for connecting the semiconductor device 50 to another substrate such as a mother board, and are disposed on the connection pads 62.

  The individual component 71 is configured to have an electrode 72. The electrode 72 is for electrically connecting the individual component 71 and the first connection portion 56. The electrode 72 is connected to the first connection portion 56 by a solder paste 73. The individual component 71 is a basic electrical element such as a transistor, a diode, a resistor, or a capacitor, and has one function as one component (also referred to as “discrete component”).

  The first semiconductor chip 75 has an electrode pad 76 and is connected to the substrate 51 by wire bonding. The first semiconductor chip 75 on the side where the electrode pad 76 is not provided is bonded to the base material 52 with an adhesive 78. The electrode pad 76 is connected to the wire 79 and is electrically connected to the second connecting portion 57 via the wire 79.

  The second semiconductor chip 81 has an electrode pad 82 and is flip-chip connected to the substrate 51. A stud bump 83 is provided on the electrode pad 82, and the stud bump 83 is electrically connected to the third connection portion 58 by a solder paste 85 provided on the third connection portion 58. In addition, an underfill resin 87 is provided between the second semiconductor chip 81 and the substrate 51 in order to prevent a mismatch in thermal expansion coefficient between the second semiconductor chip 85 and the substrate 51.

  The transfer mold resin 90 is a resin formed by a transfer mold method, and is provided on the upper surface 52A side of the substrate 51 so as to cover the individual components 71, the first and second semiconductor chips 75 and 81, and the wires 79. Yes. In the transfer molding method, a member to be sealed (in the case of this embodiment, a substrate 51 on which the individual component 71, the first semiconductor chip 75, and the second semiconductor chip 81 are mounted) is set in a mold molding machine. In this method, pressure is applied to the resin that has been made fluid by raising the temperature, and the resin is poured into the mold (pressure feeding) to mold the resin into the mold.

  By using such a transfer mold resin 90, the controllability of the height H4 (the thickness of the transfer mold resin 90) can be improved as compared with the case where the potting resin 35 is used. Further, the time required for resin sealing can be shortened, and the productivity of the semiconductor device 50 can be improved. The height H4 of the transfer mold resin 90 can be set to 0.3 mm to 1.2 mm, for example.

  The upper surface 90A of the transfer mold resin 90 is a flat surface. Thus, when the upper surface 90A of the transfer mold resin 90 is brought into contact with the shield material 91 by making the upper surface 90A of the transfer mold resin 90 flat, the transfer mold resin 90 is interposed between the shield material 91 and the shield material 91. The gap is not formed, and the height H5 of the semiconductor device 50 is made smaller than the heights H2 and H3 of the conventional semiconductor devices 10 and 40 using the potting resin 35, thereby reducing the size of the semiconductor device 50. Can do.

Further, by making the upper surface 90A of the transfer mold resin 90 flat, and by bringing the upper surface 90A of the transfer mold resin 90 and the shield material 91 into contact with each other, the handling property of the semiconductor device 50 is improved and another substrate (for example, When the semiconductor device 50 is mounted on the mother board), it can be easily mounted.
For example, an epoxy resin can be used for the transfer mold resin 90.

  The shield material 91 has a shape that covers the upper surface 90 </ b> A and the side surface 90 </ b> B of the transfer mold resin 90. The shield material 91 is electrically connected to the ground terminal 54 by the solder paste 93 while being in contact with the upper surface 90A of the transfer mold resin 90.

  Thus, by bringing the shield material 91 into contact with the upper surface 90A of the transfer mold resin 90, not only the semiconductor device 50 can be miniaturized, but also the shield material 91 has a heat dissipation function, and the heat of the transfer mold resin 90 is transferred to the semiconductor. Heat can be dissipated outside the device 50. As a material of the shield material 91, for example, nickel silver can be used. Yohaku is a Cu—Ni—Zn alloy with excellent spreadability and corrosion resistance. As a mixing ratio of the Cu—Ni—Zn alloy, for example, Cu may be 62 wt%, Ni may be 14 wt%, and Zn may be 24 wt%.

  The solder ball 94 is an external connection terminal for connecting the semiconductor device 50 to another board such as a mother board. The solder ball 94 is disposed on the connection pad 63 and is electrically connected to the connection pad 63.

  As described above, the transfer terminal in which the ground terminal 54 is provided on the side surface of the base material 52 to cover the individual component 71, the first and second semiconductor chips 75 and 81, and the wire 79, and the upper surface 90A is flat. By providing the resin 90 and electrically connecting the shield material 91 and the ground terminal 54 in a state where the shield material 91 is in contact with the upper surface 90A of the transfer mold resin 90, the conventional semiconductor devices 10 and 40 are provided. Thus, the semiconductor device 50 can be reduced in size. Further, the productivity of the semiconductor device 50 can be improved as compared with the conventional semiconductor devices 10 and 40 using the potting resin 35. The position where the notch 95 is formed is not limited to this embodiment as long as it is on the side surface of the substrate 52. For example, you may provide the notch part 95 in the corner | angular part of the base material 52 side surface. Moreover, the shape of the notch part 95 is not limited to a present Example. Furthermore, a conductor having a predetermined potential, for example, a power supply potential (eg, 3.3 V, 1.8 V) of a semiconductor chip, may be provided on the side surface of the substrate 52 instead of the ground terminal 54.

  FIG. 6 is a plan view showing the positional relationship between the conventional base material and the substrate forming region, and FIG. 7 is a plan view showing the positional relationship between the base material and the substrate forming region of this example, FIG. 8 is an enlarged plan view of the base material shown in FIG. In FIG. 6, C indicates a region where a conventional substrate is formed (hereinafter referred to as “substrate forming region C”), and in FIG. 7, E indicates a region where the substrate 51 of this embodiment is formed. (Hereinafter referred to as “substrate forming region E”). Further, FIG. 8 shows a boundary line (hereinafter referred to as “boundary line D”) of the substrate formation region E cut by the dicer.

  As shown in FIG. 6, conventionally, since one substrate forming region C corresponds to one base material 98, there are many base material 98 portions that do not contribute to the formation of the substrate, and the base material 98 is effectively used. I couldn't. In the semiconductor device 50 of the present embodiment, as shown in FIG. 7, a plurality of substrate formation regions E (nine in FIG. 7) are provided for one base material 52 and the plurality of substrate formation regions E are adjacent to each other. In order to manufacture the semiconductor device 50 by providing the transfer mold resin 90 collectively in a plurality of substrate formation regions E, the base material 52 is effectively used to improve the productivity of the semiconductor device 50. Can do. The size of the substrate formation region E can be set to 9 mm □, for example.

  Next, a method for manufacturing the semiconductor device 50 will be described with reference to FIGS. 9 to 17 are views showing a manufacturing process of the semiconductor device of this embodiment. 9 to 17, the same components as those of the semiconductor device 50 shown in FIG. 4 are denoted by the same reference numerals.

  First, as shown in FIG. 9, the first through hole 101 is formed in the base material 52 corresponding to the substrate forming region E, and the second through hole 102 is formed in the base material 52 on the boundary line D of the substrate forming region E. Form. The first through hole 101 is for arranging the through via 53. FIG. 18 is a plan view of a substrate on which a second through hole is formed. The second through hole 102 is for arranging a ground terminal base material 104 (see FIG. 10) that is a base material of the ground terminal 54. As shown in FIG. 18, the second through hole 102 is formed on the boundary line D of the substrate formation region E. The first and second through holes 101 and 102 can be formed by, for example, any one of drilling using a drill, laser processing, and anisotropic etching. When the size of the substrate formation region E is 9 mm □, the size of the diameter R1 of the second through hole 102 can be set to 0.5 mm to 1.0 mm, for example.

  Next, as shown in FIG. 10, conductive members are provided in the first and second through holes 101, 102, a through via 53 is provided in the first through hole 101, and a ground terminal base material is provided in the second through hole 102. 104 (conductive member forming step). The ground terminal base material 104 is a conductive member having a ground potential, and is divided into two equal parts by a dicer described later to become two ground terminals 54. For example, Cu can be used as the material of the conductive member. FIG. 19 is a plan view showing another example of the ground terminal base material. In FIG. 10, the ground terminal base material 104 is formed by providing a conductive member so as to fill the second through-hole 102. However, as shown in FIG. 19, in the central portion of the second through-hole 102. The ground terminal base material 105 may be formed by providing a conductive member so that the through hole G is formed.

  Next, as illustrated in FIG. 11, first to third connection portions 56 to 58 that are electrically connected to the through via 53 and the solder resist 61 are formed on the upper surface 52 </ b> A of the base material 52. Subsequently, the wiring 62 including the connection pads 63 and the solder resist 64 that covers the wirings 62 other than the connection pads 63 are formed on the lower surface 52 </ b> B of the base material 52. In addition, F shown in FIG. 11 indicates a region on the base material 52 where the first semiconductor chip 75 is disposed (hereinafter referred to as “first semiconductor chip disposition region F”).

  Next, as shown in FIG. 12, the individual component 71 and the first and second semiconductor chips 75 and 81 are mounted on the structure shown in FIG. 11 (semiconductor chip mounting step). Specifically, the electrode 72 of the individual component 71 is electrically connected to the first connection portion 56 by the solder paste 73. Subsequently, the first semiconductor chip 75 is bonded to the first semiconductor chip arrangement region F on the base member 52 with an adhesive 78, and the electrode pad 76 and the second connection pad 57 are connected by the wire 79. Then, the first semiconductor chip 75 is mounted. Next, the stud bump 83 provided on the electrode pad 82 is connected to the third connection 58 by the solder paste 85 to mount the second semiconductor chip 81, and then the second semiconductor chip 81 and the base are mounted. An underfill resin 87 is disposed between the material 52.

  Next, as shown in FIG. 13, the mold 106 having a flat surface 106 </ b> A facing the base material 52 is disposed on the upper surface 52 </ b> A side of the base material 52. In the meantime, the transfer mold resin 90 is filled so as to cover the individual parts 71, the first and second semiconductor chips 75, 81, and the wires 79, and then, as shown in FIG. The transfer mold resin 90 is formed so that the upper surface 90A is a flat surface that is removed from the surface 52 (transfer mold resin forming step). In the case of the present embodiment, the transfer mold resin 90 is formed collectively on the nine substrate formation regions E. As described above, by providing the transfer mold resin 90 collectively for the plurality of substrate formation regions E, the time required for resin sealing is shortened as compared with the case where the potting resin 35 is used. The productivity of 50 can be improved. The height H4 of the transfer mold resin 90 can be set to 0.3 mm to 1.2 mm, for example.

  Next, as illustrated in FIG. 15, the structure illustrated in FIG. 14 is separated into pieces by a dicer along the boundary line D of the substrate formation region E. Thereby, the ground terminal base material 104 is divided into two equal parts, and the ground terminal 54 is formed (conductor forming step). Subsequently, as shown in FIG. 16, the shield material 91 is disposed so as to be in contact with the upper surface 90 </ b> A of the transfer mold resin 90, and the shield material 91 and the ground terminal 54 facing the ground terminal 54 are electrically connected by the solder paste 93. Connect (shield material placement step). Thereafter, as shown in FIG. 17, the semiconductor device 50 is manufactured by disposing the solder balls 94 on the connection pads 63.

  As described above, a plurality of substrate formation regions E are provided adjacent to each other on the base material 52, and a transfer mold resin 90 is collectively provided on the plurality of substrate formation regions E, whereby one base material 52 is provided. It is possible to increase the productivity of the semiconductor device 50 by increasing the number of the substrates 51 per hit and reducing the time required for resin sealing.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible. FIG. 20 is a plan view of a base material on which a ground terminal base material is formed. The position where the ground terminal base material is provided may be on the boundary line D of the substrate formation region E, and is not limited to the position of this embodiment. For example, as shown in FIG. 20, the ground terminal base material 110 may be provided in the second through hole 109 formed in the corner portion of the substrate formation region E. The ground terminal 54 may be provided on the upper surface 52 </ b> A of the base material 52.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to reduce in size, the semiconductor device which can improve productivity, and its manufacturing method can be provided.

It is sectional drawing (the 1) of the conventional semiconductor device provided with the shield case. It is sectional drawing (the 2) of the conventional semiconductor device provided with the shield case. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a sectional view of the semiconductor device shown in FIG. 3 in the BB line direction. It is a perspective view of the ground terminal of a present Example. It is the top view which showed the positional relationship of the conventional base material and a board | substrate formation area. It is the top view which showed the positional relationship of the base material and board | substrate formation area of a present Example. It is the top view to which the base material shown in FIG. 7 was expanded. It is FIG. (The 1) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 2) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 3) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 4) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 5) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 6) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 7) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 8) which showed the manufacturing process of the semiconductor device of a present Example. It is FIG. (The 9) which showed the manufacturing process of the semiconductor device of a present Example. It is a top view (the 1) of a substrate in which the 2nd penetration hole was formed. It is the top view which showed the other example of the ground terminal base material. It is a top view (the 2) of the base material in which the ground terminal base material was formed.

Explanation of symbols

10, 40, 50 Semiconductor device 11, 51 Substrate 12, 41, 52, 98 Base material 13, 53 Through-via 14, 15 Connection portion 16, 42, 54 Ground terminal 17, 23, 61, 64 Solder resist 21, 62 Wiring 22, 63 Connection pads 24, 78 Adhesives 25, 94 Solder balls 26, 71 Individual parts 27, 37, 73, 85, 93 Solder paste 31 Semiconductor chip 32 Semiconductor chip body 33, 76, 82 Electrode pads 34 Gold wires 35 Potting Resin 36, 44 Shield case 52A, 90A Upper surface 52B Lower surface 56 First connection portion 57 Second connection portion 58 Third connection portion 72 Electrode 75 First semiconductor chip 79 Wire 81 Second semiconductor chip 83 Stud bump 87 Underfill resin 90 Transfer mold resin 90B Side surface 91 Shield material 95 Notch portion 101 First through hole 102, 109 Second through hole 104, 105, 110 Ground terminal base material 106 Mold 106A Surface A Clearance C, E Substrate formation region F First semiconductor Tip placement area G Through hole H1 to H5 Height R1 Diameter

Claims (3)

A plate-shaped substrate, a semiconductor chip mounted on the substrate, provided on a side surface of said substrate, a conductor having a predetermined potential, provided on the semiconductor chip on said substrate so as to cover In the semiconductor device comprising the transfer mold resin, a shield material that is in contact with the upper surface of the transfer mold resin and connected to the conductor, and a solder resist layer provided on the lower surface of the base material,
The conductor has a columnar shape in which a conductive member is disposed so as to fill a space of the notch in a semicircular notch having a cross section formed on the side surface of the base material,
The side surface of the conductor forms the same plane as each side surface of the transfer mold resin, the base material, and the solder resist layer.   The semiconductor device according to claim 1, wherein an upper surface of the transfer mold resin is a flat surface. A plate-shaped substrate, a semiconductor chip mounted on the substrate, provided on a side surface of said substrate, a conductor having a predetermined potential, provided on the semiconductor chip on said substrate so as to cover In the method of manufacturing a semiconductor device comprising: the transfer mold resin, a shield material that is in contact with the upper surface of the transfer mold resin and connected to the conductor, and a solder resist layer provided on the lower surface of the base material.
Before division before Kimoto member has a plurality of substrate forming areas arranged to suit Ri next,
In order to form a conductor having the predetermined potential by providing a through hole in the base material on a boundary line of the substrate forming region and disposing a conductive member in the through hole so as to fill the through hole. A conductive member forming step of forming a conductive member of
Each of said substrate forming definitive in the region the substrate on a semiconductor chip mounting step of mounting the semiconductor chip,
On definitive on the substrate formation region of each said substrate, a transfer molding resin forming step of forming a transfer molding resin so as to cover the semiconductor chip,
After the transfer mold resin forming step, a solder resist layer forming step of forming a solder resist layer that covers a region other than the connection pads on the lower surface of the conductor and the lower surface of the base material;
By cutting the transfer mold resin, the base material, the solder resist layer, and the conductive member along a boundary line of the substrate forming region to form a semi-cylindrical conductor, the cut surface of the conductor, A conductor forming step in which the cut surface of the transfer mold resin, the cut surface of the base material, and the cut surface of the solder resist layer form the same plane;
A method of manufacturing a semiconductor device, comprising: a shield material disposing step of contacting a top surface of the transfer mold resin and disposing a shield material so as to be electrically connected to the conductor.

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