JP4492009B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a self-aligned contact (SAC) structure and a manufacturing method thereof.
[0002]
[Prior art]
Recent highly integrated semiconductor devices such as Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) employ a multilayer wiring structure and require advanced miniaturization technology. It has become. In particular, in a semiconductor device such as a memory or a gate array, an interval between wirings is becoming narrower due to miniaturization. For this reason, when the interlayer insulating film is opened in the space between two adjacent first wirings formed on the semiconductor substrate and the contact hole for connection between the second wiring and the semiconductor substrate is formed, the first wiring and the contact are formed. A self-aligned contact (also referred to as a self-aligned contact) that eliminates the alignment margin with the hole is used.
[0003]
A semiconductor device having a conventional self-aligned contact (hereinafter referred to as SAC) structure is manufactured by the steps shown in FIGS. 5A to 5F, 101 is a semiconductor substrate, 102 is a polysilicon film, 103 is a tungsten silicide (hereinafter referred to as WSi) film, and 102 and 103 constitute a first wiring layer. 104 is an offset insulating film (also referred to as an offset oxide film) formed only on the first wiring layer, 105 is a sidewall insulating film (also referred to as a sidewall film), and 106 is a silicon nitride (hereinafter referred to as SiN) film. The formed etching stopper film 107 is an interlayer insulating film formed of a boron phosphorus silicate glass (hereinafter referred to as BPSG) film. 108 is a polysilicon film, 109 is a WSi film, and 108 and 109 constitute a second wiring layer. Reference numeral 110 denotes a contact hole for electrically connecting the semiconductor substrate and the second wiring layer provided in a space between the two first wiring layers.
[0004]
First, a polysilicon film, a WSi film, and a tetraethylorthosilicate (hereinafter referred to as TEOS) film to be an offset insulating film are deposited on the semiconductor substrate 101 by a low pressure CVD (Chemical Vapor Deposition) method. After forming the wiring layer pattern, the first wiring layers 102 and 103 and the offset insulating film 104 are formed by anisotropic dry etching of the TEOS film, the WSi film, and the polysilicon film (FIG. 5A). Next, a TEOS film to be a sidewall insulating film is deposited by a low pressure CVD method (FIG. 5B), and a sidewall insulating film 105 is formed by the entire surface etch back (FIG. 5C).
[0005]
Thereafter, an etching stopper film 106 made of a SiN film is formed by a low pressure CVD method, a BPSG film is deposited by a normal pressure CVD method, and an interlayer insulating film 107 is formed (FIG. 5D). A resist hole contact pattern is formed by photolithography, and the interlayer insulating film 107 and the etching stopper film 106 are anisotropically dry etched to form a contact hole 110 (FIG. 5E). Next, as a second wiring layer, a polysilicon film 108 and a WSi film 109 are formed on the contact hole 110 and the planarized interlayer insulating film 107 by low pressure CVD (FIG. 5F).
[0006]
However, in the above-described conventional configuration, the interlayer insulating film must be formed thick in order to absorb a step on the semiconductor substrate caused by forming the first wiring layer on the semiconductor substrate. This increases the aspect ratio (length / diameter) of the contact hole for connecting the second wiring layer and the semiconductor substrate, resulting in an increase in contact resistance.
[0007]
The interlayer insulating film uses a BPSG film having excellent planarization characteristics and absorbs the above-described steps on the semiconductor substrate to play a role of forming a flat surface. Therefore, the film thickness of the interlayer insulating film is thin on the first wiring layer and thick on the semiconductor substrate on which the first wiring layer is not provided. In order to form a contact hole by etching the interlayer insulating film having such a local film thickness variation, overetching is required. Therefore, in order to avoid excessive over-etching, an etching stopper film made of a SiN film is provided on the top and side surfaces of the first wiring layer. However, it is difficult for such a SiN film to be completely selectively etched with a silicon oxide film such as a BPSG film constituting an interlayer insulating film. Therefore, when the overetching time becomes long, the etching stopper film is removed, and further, the etching of the offset insulating film and the sidewall insulating film on the first wiring layer proceeds, and the insulating film between the first wiring layer and the second wiring layer becomes thin. Therefore, there is also a problem that the withstand voltage between the wiring layers is lowered.
[0008]
Furthermore, in order to suppress a decrease in the withstand voltage between the first wiring layer and the second wiring layer as described above, it is conceivable to increase the thickness of the offset insulating film provided on the first wiring layer. However, when the offset insulating film is made thicker, the step between the first wiring layer and the semiconductor substrate becomes larger, and the flatness of the interlayer insulating film becomes worse.
[0009]
[Problems to be solved by the invention]
The present invention provides a semiconductor device and a method for manufacturing the same that can secure a dielectric breakdown voltage between the first wiring layer and the second wiring layer in the SAC portion, reduce the contact resistance, and further improve the flatness of the interlayer insulating film. The purpose is to do.
[0010]
[Means for Solving the Problems]
As a result of intensive investigations to achieve the above object, the present inventors have provided a concave groove in a semiconductor substrate and started forming the first wiring layer from a position lower than the main surface of the semiconductor substrate. It was found that can be solved at once.
That is, by starting to form the first wiring layer from a position lower than the main surface of the semiconductor substrate, the level difference on the semiconductor substrate caused by forming the first wiring layer is reduced, so that when the interlayer insulating film is deposited Flatness is improved. In addition, since the step on the semiconductor substrate is reduced, the thickness of the interlayer insulating film for absorbing the step is reduced. As a result, the depth of the contact hole provided for connection between the second wiring layer and the semiconductor substrate is reduced, so that the aspect ratio is reduced and the contact resistance is reduced. Furthermore, since the depth of the contact hole is reduced, the anisotropic etching time of the interlayer insulating film is shortened, so that the offset insulating film and the side wall insulation are less scraped. As a result, a sufficient thickness of the insulating film between the first wiring layer and the second wiring layer is ensured, and the withstand voltage between the first wiring layer and the second wiring layer is improved.
The present inventors have further studied and completed the present invention.
[0011]
  That is, the present inventionThe first side surface of the semiconductor device includes: (a) a semiconductor substrate; (b) a plurality of concave grooves provided in the main surface of the semiconductor substrate; and (c) a conductive layer provided in each of the concave grooves. A first wiring layer having a layer; (d) an offset insulating film provided on the first wiring layer; and (e) a side of the first wiring layer and the offset insulating film in each of the concave grooves. A sidewall insulating film provided on a wall surface; and (f) the offset insulating film, the sidewall insulating film, and the semiconductor substrate provided between the sidewall insulating films, the offset insulating film and the sidewall An etching stopper film having a low etching rate compared to the insulating film and having an etching selectivity; and (g) an etching stopper film provided on the etching stopper film and having a high etching rate compared to the etching stopper film. (H) a contact hole provided in the interlayer insulating film and reaching the surface of the convex portion of the semiconductor substrate; (i) provided along at least an inner surface of the contact hole; A second wiring layer electrically connected to the semiconductor substrate, and (j) the first wiring layer, the offset insulating film, and the sidewall insulating film are respectively provided in the concave grooves, Compared with the case where the first wiring layer, the offset insulating film, and the sidewall insulating film are provided on the main surface of the semiconductor substrate, the step between the main surface of the semiconductor substrate and the upper surface of the offset insulating film is small, The contact hole has a small aspect ratio.
[0012]
  In addition, the present inventionThe second side surface of the semiconductor device includes: (a) a semiconductor substrate; (b) a plurality of concave grooves provided in the main surface of the semiconductor substrate; and (c) a conductive layer provided in each of the concave grooves. A first wiring layer having a layer; (d) an offset insulating film provided on the first wiring layer; and (e) a sidewall surface of the first wiring layer and the offset insulating film in each of the concave grooves. (F) the offset insulating film, the sidewall insulating film, and the sidewall insulating film provided between the sidewall insulating films, and the offset insulating film and the sidewall insulating film. An interlayer insulating film having a higher etching rate than the film and having an etching selectivity; (g) a contact hole provided in the interlayer insulating film and reaching a convex surface of the semiconductor substrate; and (h) at least the contact hole. On the inside And (i) the first wiring layer, the offset insulating film, and the sidewall insulating film are respectively in the concave grooves. By providing, the main surface of the semiconductor substrate and the top surface of the offset insulating film are compared with the case where the first wiring layer, the offset insulating film, and the sidewall insulating film are provided on the main surface of the semiconductor substrate. And the contact hole has a small aspect ratio.
[0013]
  In addition, the present inventionA first aspect of the method for manufacturing a semiconductor device is as follows:Semiconductor substrateThe main surface of(B) a first wiring layer having a conductive layer by sequentially depositing a conductor layer and an insulating film on the semiconductor substrate and forming a pattern by a combination of photoresist and etching; And an offset insulating film laminated on the first wiring layer in each of the concave grooves, and (c) depositing an insulating film;In each of the concave groovesThe first wiring layer;SaidOn the side wall of the offset insulation filmBy etchingA step of providing a sidewall insulating film; (d) on the semiconductor substrate, on the offset insulating film and on the sidewall insulating film;Compared with the offset insulating film and the sidewall insulating film, the etching rate is low and the etching resistance is high.Etching stopper filmCompostA process of stacking,(E)On the semiconductor substrate;The etching stopper film has a higher etching rate and etching selectivity than the etching stopper film.Interlayer insulation filmCompostA process of stacking,(F)Etching and removing the interlayer insulating film and at least a part of the etching stopper film, and providing a contact hole vertically extending through the interlayer insulating film between the two first wiring layers to reach the convex surface of the semiconductor substrate When,(G)Forming a second wiring layer along at least the contact hole, and electrically connecting the second wiring layer and the semiconductor substrate.(H) providing the first wiring layer, the offset insulating film, and the sidewall insulating film in each of the concave grooves, thereby providing the first wiring layer, the offset insulating film, and the sidewall insulating film; Compared to the case where the semiconductor substrate is provided on the main surface of the semiconductor substrate, a step between the main surface of the semiconductor substrate and the top surface of the offset insulating film is formed to be small, and the contact hole having a small aspect ratio is formed. .
[0014]
  In addition, the present inventionThe second aspect of the method for manufacturing a semiconductor device is as follows:Semiconductor substrateThe main surface of(B) a first wiring layer having a conductive layer by sequentially depositing a conductor layer and an insulating film on the semiconductor substrate and forming a pattern by a combination of photoresist and etching; And an offset insulating film laminated on the first wiring layer in each of the concave grooves, and (c) depositing an insulating film;In each of the concave groovesThe first wiring layer;SaidOn the side wall of the offset insulation filmBy etchingA step of providing a sidewall insulating film; (d) on the semiconductor substrate, on the offset insulating film and on the sidewall insulating film;Compared with the offset insulating film and the sidewall insulating film, the etching rate is high and the etching selectivity is obtained.Interlayer insulation filmCompostAnd (e) the interlayer insulationMembrane(F) at least a part of the interlayer insulating film between the two first wiring layers, and a contact hole reaching the convex surface of the semiconductor substrate; and (f) at least the contact hole. Forming a second wiring layer along the line and electrically connecting the second wiring layer and the semiconductor substrate.(G) providing the first wiring layer, the offset insulating film, and the sidewall insulating film in each of the concave grooves, thereby providing the first wiring layer, the offset insulating film, and the sidewall insulating film; Compared to the case where the semiconductor substrate is provided on the main surface of the semiconductor substrate, a step between the main surface of the semiconductor substrate and the top surface of the offset insulating film is formed to be small, and the contact hole having a small aspect ratio is formed. .
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate, and 2 denotes a concave groove formed in the main surface of the semiconductor substrate 1. 3 is a polysilicon film, 4 is a WSi film, and 3 and 4 constitute a first wiring layer. Reference numeral 5 denotes an offset insulating film formed only on the first wiring layers 3, 4, 6 denotes a sidewall insulating film, 7 denotes an etching stopper film made of a SiN film, and 8 denotes an interlayer insulating film made of a BPSG film. 9 is a polysilicon film, 10 is a WSi film, and 9 and 10 constitute a second wiring layer. 11 is provided in a space between the first wiring layers, a contact hole for connecting the semiconductor substrate and the second wiring layer, and 12 is a convex surface of the semiconductor substrate exposed at the bottom of the contact hole 11 It is.
[0016]
The present invention is characterized in that the first wiring layer composed of the polysilicon film 3 and the WSi film 4 is formed in a concave groove provided in the main surface of the semiconductor substrate. That is, the bottom surface of the first wiring layer is formed lower than the main surface of the semiconductor substrate.
[0017]
In the present embodiment, the polysilicon film 3 is used as the lower layer of the first wiring layer, but the polysilicon film 3 may contain impurities such as phosphorus (P) and boron (B). Further, the lower layer of the first wiring layer is not limited to the polysilicon film, and any film may be used as long as it is a conductive material.
In this embodiment, the WSi film 4 is used as the upper layer of the first wiring layer. However, the present invention is not limited to this, and a silicide film of a refractory metal such as tantalum (Ta) or molybdenum (Mo) may be used. .
Further, in the present embodiment, the first wiring layer has a two-layer structure composed of the polysilicon film 3 and the WSi film 4, but may have a one-layer structure composed of only the polysilicon film 3, A single-layer film of a conductor different from the silicon film or a multi-layer structure of a multi-layered film made of different conductors may be used.
[0018]
The offset insulating film 5 is an insulating film formed only on the first wiring layers 3 and 4 and is composed of a TEOS film in this embodiment. The offset insulating film 5 has a function as an etching mask when forming the pattern of the first wiring layers 3 and 4, and further, the sidewall insulating film is etched back by the insulating film deposited on the first wiring layers 3 and 4. 6 also has a function of preventing the surfaces of the first wiring layers 3 and 4 from being exposed. The offset insulating film 5 may be a silicon oxide film other than the TEOS film. The same effect can be obtained even if the offset insulating film 5 is composed of a SiN film. Further, the offset insulating film 5 may be a laminated film in which a silicon oxide film typified by a TEOS film and an SiN film are arbitrarily combined.
[0019]
In this embodiment, the sidewall insulating film 6 is composed of a TEOS film. The sidewall insulating film 6 has a function of preventing the side surfaces of the first wiring layers 3 and 4 from being exposed when the SAC is formed. Note that the sidewall insulating film 6 may be formed of a silicon oxide film other than the TEOS film. The sidewall insulating film 6 may be a laminated film of a silicon oxide film such as a SiN film or a TEOS film and a SiN film.
[0020]
In this embodiment, the etching stopper film 7 is composed of a SiN film. The etching stopper film 7 is formed on the entire surface including the semiconductor substrate, the offset insulating film 5 and the sidewall insulating film 6. At the time of forming the SAC, only an interlayer insulating film 8 described later is selectively etched, and an etching stopper film 7 is formed so that the offset insulating film 5 and the sidewall insulating film 6 are not etched as much as possible. The reason why the SiN film is used for the etching stopper film 7 is that the etching rate is different from that of the BPSG film constituting the interlayer insulating film 8. By utilizing such a difference in etching rate, the BPSG film can be removed by etching under conditions where the etching rate is sufficiently higher than that of the SiN film during SAC formation.
Note that when the interlayer insulating film 8 and an SiN film having etching selectivity are used as the offset insulating film 5 and the sidewall insulating film 6, the etching stopper film 7 may be omitted.
[0021]
In this embodiment, the interlayer insulating film 8 is composed of a BPSG film. The BPSG film is an insulating film having excellent planarization characteristics when there is a step on the semiconductor substrate. The interlayer insulating film 8 may be composed of a PSG film (phosphorus silicate glass) or other silicon oxide film. The interlayer insulating film 8 may be flattened by a known flattening technique such as CMP (Chemical Mechanical Polishing) after film deposition.
[0022]
The contact hole 11 is for connecting the second wiring layer made of the polysilicon film 9 and the WSi film 10 to the semiconductor substrate. The contact hole 11 is provided in a space sandwiched between the first wiring layers, and extends vertically through the interlayer insulating film 8 to reach the convex surface 12 of the semiconductor substrate. When the first wiring layer is a gate electrode of a MOS transistor, the protruding surface 12 of the semiconductor substrate exposed at the bottom of the contact hole 11 is made of P or B depending on the type of P-MOS or N-MOS. Impurities are implanted.
[0023]
In the present embodiment, the polysilicon film 9 is used as the lower layer of the second wiring layer, but the polysilicon film 9 may contain impurities such as phosphorus (P) and boron (B). The lower layer of the second wiring layer is not limited to the polysilicon film, and any film may be used as long as it is a conductive material such as W or Al.
In the present embodiment, the WSi film 10 is used as the upper layer of the second wiring layer. However, the present invention is not limited to this, and a refractory metal silicide film such as tantalum (Ta) or molybdenum (Mo) may be used. Good.
Furthermore, in the present embodiment, the second wiring layer has a two-layer structure of the polysilicon film 9 and the WSi film 10, but it may have a single-layer structure consisting of only the polysilicon film 9, or a polysilicon film. It may be a multi-layer structure composed of a single layer film of a different conductor or a multi-layered film composed of different conductors.
[0024]
As shown in FIG. 1, in the semiconductor device according to the present embodiment, since the first wiring layer is formed in the concave groove 2 at a position lower than the main surface of the semiconductor substrate 1, the main surface of the semiconductor substrate 1 and the first wiring are formed. The step 13 between the layers 3 and 4 and the offset insulating film 5 is reduced, and the flatness when the interlayer insulating film is deposited is improved. Further, since the step 13 is reduced, the thickness of the interlayer insulating film 8 for absorbing the step 13, particularly the thickness 15 of the interlayer insulating film 8 in the SAC formation portion is reduced. As a result, since the depth of the contact hole 11 is reduced, the aspect ratio is reduced and the contact resistance is reduced. Further, when the depth of the contact hole 11 is reduced, the etching amount of the interlayer insulating film 8 is reduced when the contact hole 11 is formed, so that the etching time is shortened, and the offset insulating film 5 and the side wall insulating 6 are less scraped. Become. That is, damage to the offset insulating film 5 and the side wall insulation 6 when the contact hole 11 is formed can be reduced. As a result, a sufficient thickness 14 of the insulating film between the first wiring layers 3 and 4 and the second wiring layers 9 and 10 is secured, and the first wiring layers 3 and 4 and the second wiring layers 9 and 10 The withstand voltage between is improved.
[0025]
The semiconductor device according to the present invention can be manufactured by a known method. As a preferred embodiment of a method for manufacturing a semiconductor device according to the present invention, one embodiment of a method for manufacturing a semiconductor device shown in FIG. 1 will be described with reference to the drawings. 2A to 2I are process sectional views showing the manufacturing method. In such drawings, a cross section of a semiconductor device is shown. 2 and 3, 21 is a semiconductor substrate, 22 is a resist mask, 23 is a region where a first wiring layer is to be formed (hereinafter referred to as “first wiring layer formation scheduled region”), and 24 is a contact. A region in which holes are to be formed (hereinafter referred to as “contact hole formation planned region”), 25 is a concave groove formed in the main surface of the semiconductor substrate 21, 26 is a polysilicon film, 27 is a WSi film, and 28 is a polycrystal. An offset insulating film formed only on the first wiring layer formed of the silicon film 26 and the WSi film 27, 29 is a sidewall insulating film, 30 is an etching stopper film made of a SiN film, and 31 is an interlayer insulating film made of a BPSG film. A film 32 is provided in a space between the two first wiring layers, a contact hole for connecting the semiconductor substrate and the second wiring layers 34 and 35, and 33 is a contact. The surface of the protrusion of the semiconductor substrate exposed at the bottom of the hole 32, 34 a polysilicon film and 35 is a WSi film. A second wiring layer is formed from the polysilicon film 34 and the WSi film 35.
[0026]
First, a resist pattern having no resist film is formed in the first wiring layer formation planned region 23 on the semiconductor substrate 21 and a resist pattern having a resist film is formed in the contact hole formation planned region 24 by photolithography (FIG. 2A). )). The semiconductor substrate 21 is etched by anisotropic dry etching using the patterned resist film as a mask (FIG. 2B). The etching depth of the semiconductor substrate 21 is preferably about the same as the thickness of the first wiring layer formed in a later step, but the thickness is not limited to this and is selected to be an arbitrary thickness. Can do. After removing the resist mask, a groove 25 is formed in the first wiring layer formation planned region 23, and the contact hole formation planned region 24 is not etched and remains at the same height as the main surface of the semiconductor substrate 21 (FIG. 2). (C)).
[0027]
Next, a polysilicon film 26 containing an impurity such as phosphorus or boron is deposited to a thickness of about 110 nm by low pressure CVD. A WSi film 27 is deposited to a thickness of about 100 nm on the polysilicon film 26 by plasma CVD or sputtering, and then a TEOS film to be the offset insulating film 28 is laminated to a thickness of about 190 nm by low pressure CVD. After forming a first wiring layer forming resist pattern (not shown) by photolithography, the offset insulating film 28, the WSi film 27, and the polysilicon film 26 are sequentially subjected to anisotropic dry etching to form the polysilicon layer 26, WSi. A first wiring layer made of the layer 27 and an offset oxide film 28 formed only on the first wiring layer are formed in the respective concave grooves 25 (FIG. 2D).
[0028]
Next, a TEOS film having a thickness of about 180 nm is deposited on the entire surface by low pressure CVD (FIG. 2E). Next, a sidewall insulating film 29 is formed on the side surfaces of the first wiring layers 26 and 27 and the offset insulating film 28 by performing etch back on the entire surface (FIG. 2F). An etching stopper film 30 made of a SiN film is deposited to a thickness of about 80 nm on the entire surface, that is, on the semiconductor substrate 21, the offset insulating film 28, and the side wall insulating film 29 by a low pressure CVD method. Next, a BPSG film is deposited on the entire surface to a thickness of about 600 nm by atmospheric pressure CVD, and is heated and reflowed to form an interlayer insulating film 31 (FIG. 3G).
[0029]
A resist pattern (not shown) for contact hole formation is formed by photolithography, and the contact hole 32 is formed by anisotropic dry etching the interlayer insulating film 31 and at least a part of the etching stopper film 30 (FIG. 3 (h) )). More specifically, anisotropic dry etching is performed under the condition that the etching rate is high for the BPSG film 31 and the etching rate is low for the SiN film 30 that is the etching stopper film, and the BPSG film 31 is first formed. Then, etching is performed under the condition that at least a part of the SiN film 30 is removed, and the interlayer insulating film 31 is vertically cut between the two first wiring layers to reach the convex surface of the semiconductor substrate. 32 is formed.
[0030]
Next, as the second wiring layer, a polysilicon film 34 doped with an impurity such as phosphorus or boron by low pressure CVD is used, then a WSi film 35 is formed by low pressure CVD or plasma CVD, and the contact hole 32 and the planarized interlayer are formed. The layers are sequentially stacked on the insulating film 31 (FIG. 3I).
[0031]
Another embodiment of the method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. The present embodiment is characterized in that a concave groove is formed in the first wiring layer formation scheduled region on the semiconductor substrate simultaneously with the step of forming the element isolation insulating film on the semiconductor substrate. This embodiment is different in the steps shown in FIGS. 2A to 2C in the method for manufacturing a semiconductor device according to the above-described embodiment, and the subsequent steps, that is, FIGS. ) Is the same as the above embodiment.
In FIG. 4, 41 is a semiconductor substrate, 42 is an oxidation resistant film, 43 is a first wiring layer formation region, 44 is a contact hole formation region, and 45 is a region where an element isolation insulating film is to be formed (hereinafter referred to as “element”). 46) is a thermal oxide film, 47 is a resist mask, 48 is a concave groove formed in the main surface of the semiconductor substrate 41, and 49 is an element isolation insulating film.
[0032]
The surface of the semiconductor substrate 41 is thermally oxidized to form a pad thermal oxide film (not shown), and an SiN film having a thickness of about 150 nm is formed on the pad thermal oxide film as an oxidation resistant film 42 by using a low pressure CVD method. A film is formed. The oxidation resistant film 42 is patterned by photolithography and anisotropic etching so as not to mask not only the element isolation insulating film formation region 45 but also the first wiring layer formation region 43. At this time, the contact hole formation planned region 44 is masked (FIG. 4A).
[0033]
By performing thermal oxidation using the patterned oxidation resistant film 42 as a mask, a portion of the semiconductor substrate that is not covered with the oxidation resistant film 42 is oxidized, and an element isolation insulating film formation region 45 and a first wiring layer formation scheduled region are oxidized. A thermal oxide film 46 is formed on the substrate 43 (FIG. 4B). Next, the oxidation-resistant film 42 patterned in the process of FIG. 4A and the pad oxide film (not shown) thereunder are removed (FIG. 4C).
[0034]
A resist pattern 47 is formed by photolithography so as not to mask the first wiring layer formation region 43 (FIG. 4D). At this time, the element isolation insulating film formation scheduled region 45 is masked. The thermal oxide film 46 is removed by wet etching (isotropic etching) using the resist pattern 47 as a mask. When the resist pattern is removed, a concave groove 48 is formed in the first wiring layer formation scheduled region 43 on the semiconductor substrate 41, and an element isolation insulating film 49 is formed in the element isolation insulating film formation scheduled region 45. On the other hand, the contact hole formation scheduled region 44 is not wet-etched and remains at the same height as the main surface of the semiconductor substrate 41 (FIG. 4E).
[0035]
The steps from the formation of the groove 48 on the semiconductor substrate 41 to the formation of the semiconductor device having the SAC structure according to the present invention are the steps (d) to (f) shown in FIGS. Since it is the same, the description about this process is abbreviate | omitted.
[0036]
In the above method, the concave groove of the semiconductor substrate in the region where the first wiring layer is to be formed is formed by forming and removing the thermal oxide film. The removal of the thermal oxide film is performed by wet etching having good etching selectivity with the silicon substrate. As a result, as shown in FIGS. 2A to 2C, compared with the case where the semiconductor substrate is provided with a concave groove by masking the resist pattern and anisotropically etching the contact hole formation scheduled region, There is an advantage that variation in etching can be easily suppressed.
[0037]
In addition, the manufacturing method of this embodiment has an increased number of steps until the concave grooves are provided in the semiconductor substrate as compared with the manufacturing method of the embodiment shown in FIGS. However, in view of the fact that the manufacturing method of the embodiment shown in FIGS. 2 and 3 requires a step of subsequently providing an element isolation insulating film, the manufacturing method of this embodiment is generally There is no change in the number of steps as compared with the manufacturing method of the embodiment shown in 2 and 3.
[0038]
In the above embodiment of the present invention, the SAC structure in which the interlayer insulating film in the space between two adjacent first wiring layers is opened by etching is exemplified. However, the SAC structure according to the present invention is not limited to these, and can be applied to the case of forming BLC (Border-less Contact) for eliminating the alignment margin between the field insulating film and the contact hole, and the gist of the present invention. Various modifications can be made without departing from the scope of the present invention.
[0039]
【The invention's effect】
According to the present invention, as a semiconductor device having a SAC structure, a first wiring layer is provided in a recessed groove formed in a main surface of a semiconductor substrate, and a bottom surface of the first wiring layer is lower than a main surface of the semiconductor substrate. Therefore, the insulation breakdown voltage between the first wiring layer and the second wiring layer in the SAC portion can be secured, the contact resistance can be lowered, and the flatness of the interlayer insulating film can be further improved.
[0040]
In the method for manufacturing a semiconductor device according to the present invention, the concave groove provided in the main surface of the semiconductor substrate can be formed by a combination of formation of a mask pattern and etching using the mask pattern. Further, the concave groove on the main surface of the semiconductor substrate can be performed simultaneously with the step of forming the element isolation insulating film on the semiconductor substrate. As a result, the semiconductor device according to the present invention can be easily manufactured without adding a complicated process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a preferred embodiment of a semiconductor device according to the present invention.
2 is a process diagram showing a preferred embodiment of a method for manufacturing the semiconductor device shown in FIG. 1; FIG.
FIG. 3 is a flowchart subsequent to the manufacturing process shown in FIG. 2;
4 is a process diagram illustrating another preferred embodiment of the method for manufacturing the semiconductor device shown in FIG. 1; FIG.
FIG. 5 is a process diagram showing a manufacturing process of a semiconductor device having a conventional SAC structure.
[Explanation of symbols]
1, 21, 41, 101 Semiconductor substrate
2, 25,48  Grooves formed on the main surface of the semiconductor substrate
3,26,102 Polysilicon film
4,27,103 WSi film
5, 28, 104 Offset insulating film formed only on first wiring layer
6, 29, 105 Side wall insulating film
7, 30, 106 Etching stopper film made of SiN film
8, 31, 107 Interlayer insulating film made of BPSG film
9, 34, 108 Polysilicon film
10, 35, 109 WSi film
11, 32 Contact hole
12, 33 The convex surface of the semiconductor substrate exposed at the bottom of the contact hole
13 Step difference between offset insulating film and main surface of semiconductor substrate
14 Thickness of the insulating film between the first wiring layer and the second wiring layer
15 Thickness of interlayer insulation film of SAC formation part
22,47  Resist mask
23, 43 First wiring layer formation scheduled region
24,44 Contact hole formation area
45 Element isolation insulating filmPlanned formation area
46 Thermal oxide film
49 Element isolation insulating film

Claims (9)

(A) a semiconductor substrate;
(B) a plurality of grooves provided in the main surface of the semiconductor substrate;
(C) a first wiring layer having a conductive layer provided in each of the concave grooves;
(D) an offset insulating film provided on the first wiring layer;
(E) in each of the concave grooves, a sidewall insulating film provided on a sidewall surface of the first wiring layer and the offset insulating film;
(F) Provided on the semiconductor substrate existing between the offset insulating film, the sidewall insulating film, and each of the sidewall insulating films, and has a lower etching rate than the offset insulating film and the sidewall insulating film. An etching stopper film having etching resistance, and
(G) an interlayer insulating film provided on the etching stopper film, having an etching rate higher than that of the etching stopper film and having etching selectivity;
(H) a contact hole provided in the interlayer insulating film and reaching a convex surface of the semiconductor substrate;
(I) a second wiring layer provided at least along the inner surface of the contact hole and electrically connected to the semiconductor substrate;
With
(J) The first wiring layer, the offset insulating film, and the sidewall insulating film are provided in the concave groove, respectively, so that the first wiring layer, the offset insulating film, and the sidewall insulating film are the semiconductor. Compared to the case where the main surface of the substrate is provided, the step between the main surface of the semiconductor substrate and the top surface of the offset insulating film is small, and the aspect ratio of the contact hole is small.
Semiconductor device. (A) a semiconductor substrate;
(B) a plurality of grooves provided in the main surface of the semiconductor substrate;
(C) a first wiring layer having a conductive layer provided in each of the concave grooves;
(D) an offset insulating film provided on the first wiring layer;
(E) In each of the concave grooves, a sidewall insulating film provided on a sidewall surface of the first wiring layer and the offset insulating film;
(F) Provided on the semiconductor substrate existing between the offset insulating film, the sidewall insulating film, and each of the sidewall insulating films, and has a higher etching rate than the offset insulating film and the sidewall insulating film. An interlayer insulating film having etching selectivity;
(G) a contact hole provided in the interlayer insulating film and reaching the convex surface of the semiconductor substrate;
(H) a second wiring layer provided at least along the inner surface of the contact hole and electrically connected to the semiconductor substrate;
With
(I) The first wiring layer, the offset insulating film, and the sidewall insulating film are provided in the concave groove, respectively, so that the first wiring layer, the offset insulating film, and the sidewall insulating film are the semiconductor. Compared to the case where the main surface of the substrate is provided, the step between the main surface of the semiconductor substrate and the top surface of the offset insulating film is small, and the aspect ratio of the contact hole is small.
Semiconductor device. The offset insulating film and the sidewall insulating film are made of a silicon oxide film.
The semiconductor device according to claim 1. The offset insulating film and the sidewall insulating film are made of a silicon nitride film.
The semiconductor device according to claim 2. The interlayer insulating film is made of a silicon oxide film.
The semiconductor device according to claim 1 . (A) providing a plurality of concave grooves on the main surface of the semiconductor substrate;
(B) A conductive layer and an insulating film are sequentially deposited on the semiconductor substrate, and a first wiring layer having a conductive layer is laminated on the first wiring layer by pattern formation by a combination of photoresist and etching. Providing an offset insulating film in each of the concave grooves;
(C) an insulating film is deposited, providing a sidewall insulation film by etching on the side wall surface of the offset insulating film and the first wiring layer within said each of the groove step,
; (D) the semiconductor substrate, the offset insulating film and the sidewall insulating film, wherein the step of etching rate as compared with the offset insulating film and the sidewall insulating film is sedimentary etching stopper film having a low resistance to etching selectivity When,
On (e) the semiconductor substrate, on the etching stopper film, a step of sedimentary an interlayer insulating layer having an etch rate is high etch selectivity compared with the etching stopper film,
(F) Contact holes reaching the surface of the convex portion of the semiconductor substrate by etching away the interlayer insulating film and at least a part of the etching stopper film and longitudinally cutting the interlayer insulating film between the two first wiring layers. Providing a step;
(G) forming at least the second wiring layer along the contact holes, saw including a step of electrically connecting the semiconductor substrate and the second wiring layer,
(H) By providing the first wiring layer, the offset insulating film, and the sidewall insulating film in each of the concave grooves, the first wiring layer, the offset insulating film, and the sidewall insulating film are formed in the semiconductor. A method for manufacturing a semiconductor device, wherein a step between the main surface of the semiconductor substrate and the upper surface of the offset insulating film is formed smaller than that provided on the main surface of the substrate, and the contact hole is formed with a small aspect ratio . (A) providing a plurality of concave grooves on the main surface of the semiconductor substrate;
(B) A conductive layer and an insulating film are sequentially deposited on the semiconductor substrate, and a first wiring layer having a conductive layer is laminated on the first wiring layer by pattern formation by a combination of photoresist and etching. Providing an offset insulating film in each of the concave grooves;
(C) an insulating film is deposited, providing a sidewall insulation film by etching on the side wall surface of the offset insulating film and the first wiring layer within said each of the groove step,
; (D) the semiconductor substrate on the steps of the offset insulating film and the sidewall insulating film, as compared with the offset insulating film and the sidewall insulating film sedimentary an interlayer insulating layer having an etch rate is high etch selectivity ,
(E) and at least a portion of the interlayer insulating film is removed by etching, a step between the two said first wiring layer and vertically through the interlayer insulating film provided a contact hole reaching the surface of the protrusion of the semiconductor substrate ,
(F) forming at least the second wiring layer along the contact holes, saw including a step of electrically connecting the semiconductor substrate and the second wiring layer,
(G) By providing the first wiring layer, the offset insulating film, and the sidewall insulating film in the respective concave grooves, the first wiring layer, the offset insulating film, and the sidewall insulating film are formed in the semiconductor. A method for manufacturing a semiconductor device, wherein a step between the main surface of the semiconductor substrate and the upper surface of the offset insulating film is formed smaller than that provided on the main surface of the substrate, and the contact hole is formed with a small aspect ratio . Providing a plurality of concave grooves on the main surface of the semiconductor substrate,
(A) A mask pattern in which a mask is not formed in a region where a first wiring layer on the semiconductor substrate is to be formed is not masked and a region in which a contact hole is to be formed on the semiconductor substrate is formed. Process,
(B) etching a semiconductor substrate in a region where the first wiring layer is to be formed;
(C) The method of manufacturing a semiconductor device according to claim 6 or 7 and a step of removing the mask formed by the (a). Providing a plurality of concave grooves on the main surface of the semiconductor substrate,
(A) The region where the element isolation film on the semiconductor substrate is formed and the region where the first wiring layer is to be formed are not masked and the region where the contact hole is to be formed on the semiconductor substrate Forming a masked oxide-resistant film pattern,
(B) performing thermal oxidation to form a thermal oxide film in a region where the element isolation film and the first wiring layer are to be formed;
(C) removing the oxidation resistant film formed in the step (a);
(D) forming a resist mask pattern so as to mask a thermal oxide film in a region where the element insulation isolation film is formed and not mask a thermal oxide film in a region where the first wiring layer is to be formed; ,
(E) removing a thermal oxide film in a region where the first wiring layer is to be formed by etching;
(F) The method of manufacturing a semiconductor device according to claim 6 or 7 and a step of removing the resist mask formed by the (d).

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