JP4494613B2 - Semiconductor memory device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a dynamic RAM or a static RAM that performs internal synchronization using an ATD signal.
[0002]
[Prior art]
Generally, an internal synchronization signal is generated in response to an address change in a memory circuit such as an internal synchronous SRAM. Therefore, an address transition detection circuit (hereinafter referred to as an ATD circuit) is used as an address input circuit. Yes.
[0003]
A conventional address input circuit having an ATD circuit will be described with reference to FIG. Each address signal A0 to An is input to one of the NAND circuits 1. This NAND circuits 1 ... the other is reverse-polarity signal of the chip enable (CE) signal so as not to accept signals from the outside is given in the standby state. A signal from the NAND circuit 1... Is supplied to the address transition detection circuit 2 and from the inverter 3 to the decoder. The address transition detection circuit 2 detects a change in the address signal, and outputs an address transition (ATD) signal that is a reference pulse for internal operation timing control required in the internal circuit. The CE signal is given to the internal circuit via the inverters 4 and 5. The CE signal is supplied from the inverter 4 to the CE transition detection circuit 6. The CE transition detection circuit 6 outputs a transition detection signal CTD when CE changes. As described above, the internal synchronous memory circuit includes the ATD circuit 2 in the address input circuit, and the CE signal is input to the first stage.
[0004]
FIG. 8 shows an example of an address transition detection circuit, and FIG. 9 shows an example of a CE transition detection circuit.
[0005]
As the scale of the memory increases, the number of addresses increases accordingly. Therefore, a wired OR circuit 7 as shown in FIG. 10 is generally used as a circuit (SAT circuit) for synthesizing a plurality of ATD signals. This circuit 7 is for receiving an ATD signal generated in accordance with a change in each address and generating a similar synchronizing signal (SAT) as an output for a signal from any address. In consideration of access from the CE, the CE transition detection signal (CTD) may be input in the same manner as the ATD signal. The internal synchronization signal generated by these transition detection signals can be used as a precharge signal, an equalize signal, a sense amplifier control signal, a word line (decoder), a control signal, an output latch signal, etc. according to the application.
[0006]
However, when such a conventional SAT circuit is used, it reacts to any ATD signal, and in some cases, an unnecessary ATD signal may generate a useless synchronization signal internally. For example, as shown in FIG. 11, when CE is changed in a state other than address 0 (all address inputs are all “L”) and the standby state is entered, the address of CE is changed at the address where the address input is “H”. ATD signal is temporarily generated by the change. Therefore, although an internal synchronization signal (SAT) is generated, since the circuit itself is in a standby state, an internal synchronization signal is unnecessary and an unnecessary current is consumed.
[0007]
FIG. 13 shows a circuit in which the CE is synchronized with the output of the SAT circuit (SAT) in order to eliminate unnecessary output of the internal synchronization signal. As shown in FIG. 13 , the generation of an internal synchronization signal can be prevented by synchronizing CE with the output of the SAT circuit. That is, by putting the SAT signal into one of the NAND circuits, inputting the control signal into the other, inputting the output of the NAND circuit 8 into one of the NOR circuits 9, and inputting the CTD signal into the other, Generation of an internal synchronization signal can be prevented.
[0008]
[Problems to be solved by the invention]
However, when the above-described configuration, as shown in FIG. 13, so that occurs a delay of the internal synchronization signal for the number of gates is increased. Moreover, the through current due to the ATD pulse in the wired OR portion cannot be prevented. When the CE transition detection signal (CTD) is wired-or input as in FIG. 8, the gate to which the CE is input must be enabled before the CTD signal is generated, so unnecessary ATD signals at the time of CE access are removed. The purpose cannot be achieved.
[0009]
Further, as a method for preventing the generation of the internal synchronization signal during standby, in order to prevent the ATD signal itself from being generated, a circuit that latches an address using the CE signal may be provided in the address input circuit. However, in this case, since a plurality of address input circuits must be controlled, the load of the CE signal is large and the delay time of the control signal is long. Therefore, the address latch is not in time for an address change at the same time as or immediately after the transition to the standby state, and an ATD signal is generated. Of course, since the access time cannot be sacrificed, a delay circuit cannot be inserted on the address input side. Therefore, it is practically difficult to control on the ATD signal side in the circuit design taking the access time into consideration.
[0010]
Japanese Patent Publication No. 11-339475 discloses that a circuit for invalidating an ATD signal generated by a CE signal at the time of canceling standby is configured by using a plurality of circuits. However, this circuit has a problem that the normal address access time becomes slower than the conventional type because there are many control circuits as described above. Further, although it is unknown whether the SAT circuit of this publication is a simple multi-input NOR or a wired OR, there is a problem that a through current is consumed in any case.
[0011]
The present invention has been made to solve the above-described problems. The object of the present invention is to prevent the generation of an internal synchronization signal due to an ATD signal not involved in the internal operation, and to prevent an increase in current consumption. There is. Then, the control circuit for realizing it is not increased, and it is easily realized without deteriorating the performance of the memory circuit or increasing the chip area.
[0012]
[Means for Solving the Problems]
According to the present invention, an address transition detection signal (hereinafter referred to as an ATD signal) is generated in response to an address transition and a chip enable (CE) signal , and the plurality of ATD signals are received in a semiconductor memory device that performs internal synchronization. And a synchronization signal generation circuit that outputs the sum of all ATD signals as an internal synchronization signal, wherein the synchronization signal generation circuit inputs an ATD signal whose drain or source is connected to a common first node. Means, a second node for outputting the internal synchronization signal , a pull-up transistor provided at the second node, and a transition signal (CTD) of the chip enable (CE) signal for receiving the internal signal It means for generating a synchronizing signal, the first node and inserted the chip enable (CE) signal and the that is synchronized between the second node Comprising a MOS transistor which signal the control signal (CE_SAT) signal is input to the gate, and the MOS transistor, the signal by the synchronizing signal control signal (CE_SAT) signal, an internal synchronizing said second node of constant when not the potential, and controls to disconnect the connection of the first node and the second node.
[0013]
With the configuration described above, an unnecessary ATD signal generated when the CE changes is prevented from being generated as an output of the SAT circuit. Therefore, since no internal synchronization signal is generated, there is no extra operation, and it is possible to immediately shift to a standby state or an active state. Further, a through current due to an unnecessary ATD signal can be prevented.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram when the circuit of FIG. 1 is changed to a standby state, and FIG. 3 is a waveform when CE access is performed by the circuit of FIG. FIG. FIG. 4 shows an example of the SAT control signal generation circuit.
[0015]
As shown in FIG. 1, a wired OR circuit 7 is used as a circuit (SAT circuit) for synthesizing a plurality of ATD signals. The SAT circuit is commonly connected either drain or source, ATD signal is applied to the first node (gate), the sum of the ATD signal from the second node N2 to the internal circuit via the inverter 12 give. The drains shown in FIG. 1 are connected in common and the source is grounded.
[0016]
In the embodiment shown in FIG. 1, an N-channel MOS transistor 13 is inserted between a first node N1 and a second node N2 .
[0017]
The circuit 7 receives an ATD signal generated in response to a change in each address, and generates a similar synchronization signal (SAT) as an output for signals from any address. The N channel MOS transistor 13 is supplied with a SAT control signal (CE_SAT) synchronized with CE. The N-channel MOS transistor 13 keeps the second node at a constant potential when the internal synchronization is not performed by the SAT control signal. The CTD signal is given to the second node N2 via the N channel MOS transistor 11a.
[0018]
The SAT control signal (CE_SAT) is generated by, for example, the circuit shown in FIG. The CE signal is input to the inverter 41 of the SAT control signal generation circuit, and the output of the inverter 41 is applied to one of the delay circuit 43 and the NAND circuit 44. An input from the delay circuit 43 is given to the other input of the NAND circuit 44. Therefore, a signal synchronized with the CE signal delayed by the delay circuit 43 is output from the NAND circuit 44. The output from the NAND circuit 44 is applied to the gate of the N channel MOS transistor 13 through the inverter 45. The output of the inverter 41 is given to the internal circuit via the inverter 42.
[0019]
When normal address access is performed in the circuit of FIG. 1, when an ATD signal generated due to a change in address is received, an internal synchronization signal is generated because CE_SAT is “H”. Even when compared with the conventional circuit of FIG. 10, only one stage of the N-channel MOS transistor 13 is added, and the access time is equivalent to that of the conventional circuit.
[0020]
Next, the case where CE changes from the active state to the standby state will be described. As shown in FIG. 2, when the inverted signal of CE changes to “H” , a pseudo ATD signal is generated in the address circuit in order to indicate the address “0”. These signals are input to the SAT circuit 7, but CE_SAT is also changed from "H" to "L". Therefore, in the SAT circuit 40, the reception part of the ATD signal is disconnected from the output side, and the internal synchronization signal is Does not occur. At this time, since the ATD signal receiving section is also disconnected from the pull-up transistor, no through current flows in the SAT circuit 7 .
[0021]
Next, the case where CE changes from the standby state to the active state will be described. As shown in FIG. 3, the transition signal (CTD) due to the change of CE to enable generates an internal synchronization signal regardless of the state of CE_SAT. Except for the case where the address input is address 0, an ATD signal is generated due to a change in CE_ADD. If this ATD signal is not necessary in the circuit configuration, the delay circuit 43 in FIG. Good. As a result, the ATD signal does not affect the internal synchronization signal. When it is necessary to receive all the ATD signals due to the circuit configuration, the CE_SAT timing is changed by the end of the CTD signal and reflected in the internal synchronization signal.
[0022]
As described above, the present invention is characterized in that the SAT control signal (CE_SAT) is input between the ATD receiving circuit and the output of the SAT circuit. It is not generated as an output of the circuit. Therefore, since no internal synchronization signal is generated, there is no extra operation, and it is possible to immediately shift to a standby state or an active state. Further, a through current due to an unnecessary ATD signal can be prevented.
[0023]
FIG. 5 shows another embodiment of the present invention, which is realized by controlling the source side of the SAT circuit with a control signal. That is, the source side is grounded via the N-channel MOS transistor 13a. A SAT control signal (CE_SAT) synchronized with CE is applied to the gate of N channel MOS transistor 13a. The operation of this circuit is the same as in the embodiment of FIG.
[0024]
FIG. 6 is a circuit diagram showing another example of the SAT control signal generation circuit. In FIG. 6, a control signal is created for CW_SAT, which is a combination of signals from write enable (WE). If this control signal is input as the control signal for the circuits shown in FIGS. 1 and 4, the ATD signal in the write state can be invalidated. Therefore, in FIG. 6, a write enable (WE) signal is input to one of the NAND circuits 46 through the inverter 47. The other signal of the NAND circuit 46 is input with a signal synchronized with the CE described above. CW_SAT, which is a combination of signals from the write enable (WE), is output from the NAND circuit 46 as a control signal. A write enable (WE) signal is given from the inverter 48 to the internal circuit.
[0025]
By inputting CW_SAT, which is a combination of signals from write enable (WE), as a control signal, the write mode when the address setup time is shortened and the ATD signal unnecessary for the write mode during other use are canceled. I can do things. As a result, the read mode operation such as equalization and precharge does not overlap with the write mode write operation, and the current consumption is reduced.
[0026]
【The invention's effect】
As described above, according to the present invention, an unnecessary ATD signal generated when the CE changes is not generated as an output of the SAT circuit. Transition to state or active state. In addition, a through current due to an unnecessary ATD signal can be prevented.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram when the circuit of FIG. 1 is changed to a standby state.
FIG. 3 is a waveform diagram when CE access is performed in the circuit of FIG. 1;
FIG. 4 is a circuit diagram showing another embodiment of the present invention.
FIG. 5 is a circuit diagram showing an example of a SAT control signal generation circuit used in the present invention.
FIG. 6 is a circuit diagram showing another example of a SAT control signal generation circuit used in the present invention.
FIG. 7 is a circuit diagram showing a conventional address input circuit.
FIG. 8 is a circuit diagram showing an example of an address transition detection circuit.
FIG. 9 is a circuit diagram showing an example of a CE transition detection circuit.
FIG. 10 is a circuit diagram showing a conventional ATD signal synthesis (SAT) circuit.
11 is a waveform diagram when the circuit of FIG. 10 is changed to a standby state.
12 is a waveform diagram when CE access is performed in the circuit of FIG.
FIG. 13 is a circuit diagram showing a conventional ATD signal synthesis (SAT) circuit.
[Explanation of symbols]
7 SAT circuit 13 N-channel MOS transistor N1 First node N2 Second node

Claims (1)

In a semiconductor memory device that generates an address transition detection signal (hereinafter referred to as an ATD signal ) in response to an address transition and a chip enable (CE) signal , and performs internal synchronization.
A synchronization signal generating circuit that receives the plurality of ATD signals and outputs a sum of all the ATD signals as an internal synchronization signal, the synchronization signal generating circuit having a drain or a source at a common first node; Connected ATD signal input means;
A second node for outputting the internal synchronization signal;
Wherein provided on the second node, and the pull-up transistor, and means for generating an internal synchronization signal for receiving the chip enable (CE) signal transition signal (CTD),
And a MOS transistor inserted the chip enable (CE) signal and the synchronization signal control signal synchronized (CE_SAT) signal is input to the gate between the second node and the first node,
Said MOS transistor, by the synchronization signal control signal (CE_SAT) signal, as the second node at a constant potential when not performed internal synchronization, disconnecting the first node and the second node A semiconductor memory device which is controlled.

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