JP4495073B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, in a semiconductor device using a strained silicon layer as an active layer, by forming an insulating film in a strained silicon layer below a source / drain region, the operating characteristics of the semiconductor device The present invention relates to a semiconductor device and a manufacturing method thereof.

  In general, a semiconductor device is formed by placing a germanium (Ge) piece on a silicon (Si) substrate, growing a germanium layer on the silicon substrate under a constant temperature condition, and re-growing the silicon layer on the germanium layer. Then, a strained silicon layer having the same interstitial distance as the germanium layer can be grown. Therefore, the strained silicon layer has a lattice structure that is wider than the interval between the existing silicon lattices.

  Further, as the size of the semiconductor element is reduced, there is a problem that the mobility of generated electrons and holes decreases. Therefore, in order to solve the problem that the mobility of electrons and holes is reduced as described above, a strained silicon layer as described above is often used as a substrate of a semiconductor element.

  However, the conventional semiconductor device has the following problems.

  By using a strained silicon layer as a substrate, the mobility of electrons and holes has been increased to improve the operating characteristics of the semiconductor device. However, the leakage current generated when the semiconductor device is reduced to the nano-scale size, The generation of junction breakdown voltage due to DIBL (Drain Induced Barrier Lowing) due to the increase in leakage current cannot be solved.

  The present invention provides a semiconductor device and a method for manufacturing the same that can solve one or more problems caused by limitations and disadvantages in the prior art.

  An object of the present invention is to form an insulating film below the source / drain region of the strained silicon layer, reduce the leakage current, reduce the junction breakdown voltage due to the leakage current, and turn on the operating power even at a high voltage. It is to provide a semiconductor device and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to the present invention includes a strained silicon substrate in which an active region and a field region are partitioned, and a first silicon layer, a germanium layer, and a second silicon layer are sequentially grown; A gate electrode formed on an active region of the strained silicon substrate; a source / drain region formed on both sides of the gate electrode of the strained silicon substrate; and a lower portion of the source / drain region of the strained silicon substrate. And an insulating film to be formed.

  The insulating film is preferably formed to extend to a depletion portion of the source / drain region.

  The insulating film is preferably formed on a germanium layer of the strained silicon substrate.

  The thickness of the second silicon layer is preferably in the range of 50 to 250 mm.

  In order to achieve the above object, a semiconductor device according to the present invention includes a strained silicon substrate on which a first silicon layer, a germanium layer, and a second silicon layer are sequentially grown, and a first and a first formed on the strained silicon substrate. Two gate electrodes; first conductivity type source / drain regions formed on both sides of the first gate electrode of the strained silicon substrate; and second conductivity formed on both sides of the second gate electrode of the strained silicon substrate. And having an insulating film formed under the first and second source / drain regions of the strained silicon substrate.

  Meanwhile, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of growing a germanium layer on a first silicon layer, a step of forming at least two trenches in the germanium layer, Forming an insulating film on a germanium layer having a trench; and polishing at least two insulating film patterns by polishing the germanium layer and the insulating film so that the insulating film remains only on a bottom surface of the trench. A step of re-growing a germanium layer on the planarized germanium layer to planarize, a step of forming a second silicon layer on the germanium layer, and a second silicon layer between the at least two insulating films A step of forming a gate insulating film and a gate electrode; and implanting impurity ions on both sides of the gate electrode of the second silicon layer; And having and forming over scan and drain regions.

The composition ratio (X) of the first silicon layer (Si _x-1 ) and the germanium layer (Ge _x ) is preferably set to a ratio of 0.1 to 0.5.

  The semiconductor device and the manufacturing method thereof according to the present invention have the following effects.

  First, the present invention improves the reduction of mobility of electrons and holes due to the silicon lattice in a semiconductor element that is gradually miniaturized by forming an insulating film under the source / drain region inside the strained silicon substrate. At the same time, the size of the semiconductor element can be reduced, and leakage current due to channel reduction can be prevented. Therefore, the saturated drive current can be improved by 20 to 40%.

  Second, by solving the leakage current, the DIBL and the junction breakdown voltage are reduced, so that a nano-class semiconductor element and a high-voltage element can be obtained in a strained silicon substrate.

  Third, since the electron mobility is improved by 50% or more, the performance of the semiconductor element is remarkably improved.

  Fourth, even if a CMOS semiconductor device is manufactured, the number of steps for forming the n-type well and the p-type well can be reduced, so that the productivity can be improved and the unit price can be reduced.

  Fifth, since heat generated between the source and the drain can be easily released by the insulating film, it is possible to prevent the performance of the semiconductor element from being deteriorated due to heat.

  Sixth, when forming a CMOS semiconductor element, it is not necessary to form an element isolation film between the nMOS and the pMOS, so that the size of the semiconductor element can be reduced.

  Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Corresponding elements in the drawings have the same reference numerals.

  Preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a structural sectional view of a semiconductor device according to the present invention.
As shown in FIG. 1, a semiconductor device according to the present invention includes a strained silicon substrate 10 in which a germanium layer 5 is grown on a first silicon layer 3 and a second silicon layer 6 is regrown on the germanium layer 5. In order to partition the active region and the field region, an element isolation film 31 formed in the field region of the strained silicon substrate 10, a gate insulating film 41 and a gate sequentially stacked in a predetermined region on the strained silicon substrate 10 in the active region An electrode 42, source / drain regions 44a, 44b formed on both sides of the gate electrode 42 of the strained silicon substrate 10, and an insulating film 17a formed under the source / drain regions 44a, 44b in the strained silicon substrate 10. 17b.

The insulating films 17 a and 17 b are formed so as to be in contact with the element isolation film 31 and are formed on the germanium layer 3 in the strained silicon substrate 10.
A sidewall insulating film 43 is formed on the side surfaces of the gate electrode 42 and the gate insulating film 41.

A method for manufacturing a semiconductor device according to the present invention formed using such a principle will be described as follows.
2a to 2f are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.
As shown in FIG. 2 a, the germanium layer 5 is epitaxially grown on the first silicon layer 3, and the first insulating film 11 is deposited on the germanium layer 5. The distance between the lattices of the germanium layer 5 is larger than the distance between the lattices of the first silicon layer.

A substrate comprising silicon (Si _x-1 ) and germanium (Ge _x ) can be formed by a method other than the method of epitaxially growing the germanium layer 5 on the first silicon layer 3. At this time, the composition ratio (X) of silicon and germanium is set to a ratio of 0.1 to 0.5.
Next, a photosensitive film is applied on the first insulating film 11, and a first photosensitive film pattern 12 is formed by removing the photosensitive film in the source / drain regions formed thereafter in the exposure process and development process using a mask. .

As shown in FIG. 2B, the first insulating film 11 and the germanium layer 5 are removed to a predetermined depth using the first photosensitive film pattern 12 as a mask to form a trench 15.
Next, the first photosensitive film pattern 12 and the first insulating film 11 are all removed.
Thereafter, the second insulating film 17 is formed with a predetermined thickness on the entire surface of the germanium layer 5 including the inner wall of the trench 15.

As shown in FIG. 2c, the second insulating film 17 and a part of the germanium layer 5 are planarized so that the second insulating film 17 remains only on the lower surface of the trench 15 by a chemical mechanical polishing (CMP) process. , 17b pattern is formed.
The patterns of the insulating films 17a and 17b are extended to the depleted portions of the source / drain regions to be formed thereafter, so that the leakage path of the source / drain regions becomes longer and the junction capacitance is reduced. In addition, the insulating films 17a and 17b patterns have a function of easily releasing heat generated between the source and the drain.

  As shown in FIG. 2d, after the germanium layer 5 is epitaxially grown again on the substrate on which the insulating films 17a and 17b are formed, the germanium layer 5 is planarized using a CMP process. The reason for flattening is that when the germanium layer 5 is regrown, the germanium layer is relatively thinly formed on the upper side of the patterns of the insulating films 17a and 17b.

  As shown in FIG. 2e, a second silicon layer 6 is grown on the planarized germanium layer 5 to a thickness of 50 to 250 by an epitaxial process, and the first silicon layer 3, the germanium layer 5, and the second silicon layer are grown. A strained silicon substrate 10 in which 6 is sequentially stacked is formed. The distance between the lattices of the second silicon layer 6 formed on the germanium layer 5 is the same as the distance between the lattices of the germanium layer 5.

As shown in FIG. 2f, an active region and a field region are determined for the strained silicon substrate 10, and a trench is formed by etching the strained silicon substrate 10 at a predetermined depth in the field region, and an insulating film is formed in the trench. Thus, the element isolation film 31 is formed.
Further, an insulating film 41a for gate insulation and a conductive layer 42a are sequentially deposited on the entire surface of the strained silicon substrate 10 on which the element isolation film 31 is formed.

As shown in FIG. 2g, the gate insulating film 41a and the gate electrode 42 are formed by selectively removing the gate insulating film 41a and the conductive layer 42a.
At this time, the width of the gate insulating film 41 and the gate electrode 42 corresponds to the width of the channel of the transistor, and is formed longer than the distance between the patterns of the insulating films 17a and 17b. The depletion part is covered with the insulating film 17a, 17b pattern. That is, the gate electrode 42 is formed so as to overlap the patterns of the insulating films 17a and 17b. This serves to lengthen the leakage path of the leakage current.

Next, using the gate insulating film 41 and the gate electrode 42 as a mask, low concentration impurity ions are implanted to form LDD regions 23 a and 23 b on both sides of the gate electrode 42 of the strained silicon substrate 10.
Further, an insulating film is deposited on the entire surface, and anisotropic etching is performed to form spacers 43 on the side surfaces of the gate electrode 42 and the gate insulating film 41. Next, using the gate electrode 42 and the spacer 43 as a mask, impurity ions are implanted at a high concentration into the active region of the strained silicon substrate 10 to form source / drain regions 44a and 44b.

FIG. 3 is a sectional view in which such a semiconductor device of the present invention is applied to a CMOS.
That is, the n-MOS gate insulating film 141a and the gate electrode 142a are formed in a predetermined region of the strained silicon substrate 100 in which the germanium layer 15 is grown on the first silicon layer 13 and the second silicon layer 16 is regrown on the germanium layer 15. The p-MOS gate insulating film 141b and the gate electrode 142a are formed in other regions.

High-concentration n-type source / drain regions 144a and 144b are formed on the strained silicon substrate 100 on both sides of the n-MOS gate electrode 142a, and high-concentration p is formed on the strained silicon substrate 100 on both sides of the p-MOS gate electrode 142b. Type source / drain regions 145a and 145b are formed. Then, insulating films 117 a and 117 b are formed below the n-type and p-type source / drain regions 144 a, 144 b, 145 a and 145 b in the strained silicon substrate 100.
The insulating films 117a and 117b are formed on the germanium layer 13 of the strained silicon substrate 100, and are extended to the channel region side so as to cover the depletion portions of the source / drain regions 144a, 144b and 145a and 145b.

  Thus, even if a CMOS transistor is manufactured, since the electron mobility is excellent, it is not necessary to form a separate n-type well and p-type well, so that element isolation is provided between the n-MOS and the p-MOS. Does not require a membrane.

1 is a structural cross-sectional view of a semiconductor element according to the present invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. It is process sectional drawing of the semiconductor element which concerns on this invention. 1 is a structural cross-sectional view of a CMOS semiconductor device according to the present invention.

Explanation of symbols

  10, 100 substrate, 3, 13 first silicon layer, 5, 15 germanium layer, 6, 16 second silicon layer, 11 first insulating film, 12 first photosensitive film, 15 trench, 17 second insulating film, 17a, 17b, 117a, 117b Insulating film, 23a, 23b LDD region, 31 Device isolation film, 41, 141a, 141b Gate insulating film, 42, 142a, 142b Gate electrode, 44a, 44b, 144a, 144b, 145a, 145b Source / drain region

Claims (3)

Growing a germanium layer on the first silicon layer having a greater interstitial distance than the interstitial distance of the first silicon layer ;
Forming at least two trenches in the germanium layer;
Forming an insulating film on the germanium layer having the trench;
Polishing the germanium layer and the insulating film so as to leave the insulating film only on the bottom surface of the trench, and forming at least two insulating film patterns;
Re-growth and planarize the germanium layer on the planarized germanium layer;
Forming a second silicon layer on the germanium layer such that a distance between lattices is the same as a distance between lattices of the germanium layer ;
The second silicon layer between the at least two insulating pattern, forming a gate insulating film and the gate electrode,
The second silicon layer on both sides of the gate electrode, the impurity ions are implanted, possess and forming source and drain regions,
The method of manufacturing a semiconductor device, wherein the at least two insulating film patterns are formed under the source / drain regions so as to extend to a depletion portion of the source / drain regions . 2. The method of manufacturing a semiconductor device according to claim 1 , wherein a thickness of the second silicon layer is in a range of 50 to 250 mm. 3. The gate electrode, The method according to claim 1 or 2, characterized in that it is formed to the overlapping at least two of the insulating film pattern.

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