JP4497296B2 - Bullet ball machine - Google Patents

Description

  The present invention relates to a ball game machine having a random number generation device, and more specifically, a bullet equipped with a random number generation device that generates random numbers for symbol lottery or the like by a hardware composed of a random number clock generation circuit or the like during a game. It relates to a ball game machine.

  In a ball game machine equipped with such a random number generator, the counter counts a random number value based on the reference clock of the CPU that controls the game by causing the software to execute the program, and the game of the ball game machine The winning value is determined as a random number for the symbol lottery or the like by the winning of the winning prize provided on the board or the falling of the game ball to the symbol operating gate, and the winning determination is made. And the stop symbol in the symbol display apparatus on a game board is determined by this winning result. A random number obtained by such a method is referred to as a software random number. However, when generating random numbers by the method described above, the addition interval of the counter must be increased due to software processing, and the update cycle of the counter is relatively long. It was easy to discriminate, and it was easy to perform fraudulent acts such as intentionally winning a jackpot symbol that was advantageous to the player who forcibly played the game.

For this reason, as an alternative to a method for acquiring a random number for symbol lottery or the like by software as described above, for example, as described in Patent Document 1, a random number formed of an oscillator such as a crystal resonator or an oscillator Based on the clock generated by the clock generation circuit in a predetermined cycle, the clock count circuit counts a random number of a predetermined number of digits, and the CPU that controls the game extracts and reads the counted value. It is used as a random number for lottery. In this way, by counting the random number value by hardware, the software controlled by the CPU reduces the burden on the software compared to the case where the software executes the program and counts the random number value, and the random number clock generation circuit generates the clock. A random number generator capable of generating and updating random numbers at high speed according to the cycle is used.
JP 2003-190483 A

  By the way, when the random number is generated by hardware as described above, the oscillator constituting the random number clock generation circuit, the counter constituting the clock count circuit, and the count value counted by the clock count circuit are stored. The components constituting the random number generator, such as a register constituting the count value storage circuit, are required. Then, for example, a random number for a plurality of symbol lotteries is acquired in response to winning of a game ball to a plurality of starting prizes provided on the game board or falling of a game ball to a plurality of symbol operation gates. In the case of configuring a random number generator, hardware components such as the counter and the register are provided for each start winning tool or each symbol operation gate, so that the random number generator is increased in size with many hardware components. . For this reason, the cost of a random number generator having many expensive hardware parts is increased, or a large space for mounting many hardware parts on a substrate is required to configure the random number generator. There was a problem of becoming.

  In view of the above problems, in the present invention, the number of hardware parts constituting the random number generator is reduced, the portion related to the random number generator is reduced in size, and the low-cost random generator is provided. An object is to provide a ball game machine.

In order to solve the above problems, a ball game machine according to the present invention (for example, the pachinko machine PM in the embodiment) includes a game board and a first starter (for example, start in the embodiment) mounted on the game board. A winning tool 24) , a second starter (for example, the second symbol operation gate 25a in the embodiment) and a third starter (for example, the third symbol operation gate 25b in the embodiment) , the first , second, and Signal detecting means provided in the third starting portion for detecting winning or falling of hitting balls to each starting portion and outputting a detection signal (for example, first to third symbol operation sensors 51, 52, 53 in the embodiment) a), symbol display device (e.g., first to third symbol in the exemplary embodiment the display screen 28 that the symbol is displayed varies based on the detection of落入winning or hitting of a ball by provided signal detecting means to the game surface plate , 28b, and 28c), a random number clock generating means for generating a clock at a predetermined frequency (e.g., a random number clock generating circuit B51) in the embodiment, consists of a plurality of digits based on the clock generated by the random number clock generating means turbulent Random number counting means for counting numerical values (for example, first to fourth clock count circuits B81, B82, B83, B84 in the embodiment), and a latch signal for outputting a latch signal in response to input of a detection signal from the signal detection means An output means , a count value storage means for storing the count value counted by the random number counting means based on the latch signal output from the latch signal output means, and one of the count values stored in the count value storage means. Random number extracting means for extracting the count value (for example, the CPU 732 and the embodiment in the embodiment) And a symbol lottery means B35) for stopping the change display of the symbols on the symbol display device based on the extraction result by the random number extracting means, wherein the latch signal output means is a first starter The first latch signal output means (for example, the first latch signal output circuit B71 in the embodiment) that outputs a latch signal in response to the input of the detection signal from the signal detection means provided in the second detection section The second latch signal output means (for example, the second latch signal output circuit B72 in the embodiment) that outputs a latch signal in response to the input of the detection signal from the signal detection means , and the third starter and third latch signal output means for outputting a latch signal in response to the input of the detection signal from the signal detecting means (e.g., the third latch signal output circuit B73 in the embodiment) becomes from a, mosquitoes Cement value storage means, the first count value storing means for storing a count value using all the digits of the random number counting means on the basis of the latch signal outputted from the first latch signal output unit (e.g., first in the embodiment 1 count value storage circuit B91) and second count value storage means for storing a count value using some digits of the random number counting means based on the latch signal output from the second latch signal output means (for example, The count value using other digits of the random number counting means is stored based on the latch signal output from the higher order storage circuit B92a) of the second count value storage circuit and the third latch signal output means in the embodiment. third count value memory unit (e.g., the lower data storage circuit B92b of the second count value storing circuit in the embodiment) becomes from the same random number count hand to Composed of the count value to be counted, so that each different random value to the first, second and third count value storage means is stored by.

Further, in the ball game machine having the above configuration, the some digits are odd-numbered digits among all the digits consisting of a plurality of digits, and the other some digits are all digits consisting of a plurality of digits. It is preferable that it is an even-numbered digit. The random number counting means counts a random number value of a plurality of bytes based on the clock generated by the random number clock generating means, and the first count value storage means outputs a latch that is output in response to the detection signal from the signal detecting means. A count value of a plurality of bytes counted by the random number counting means based on the signal is stored, and the second count value storage means is a random number counting means based on a latch signal output in response to a detection signal from the signal detection means It is also preferable to store the count value of 1 byte or less among the plurality of bytes counted by the above.

According to the ball game machine related to the present invention, a plurality of random numbers are acquired in response to winning of a game ball to a plurality of starting prizes provided on the game board or dropping of a game ball to a plurality of symbol operation gates. The same clock count circuit in the random number generator provided in the ball game machine counts the random number value to be used for each start winning tool and each symbol operation gate from the count value counted by the same clock count circuit. The hardware configuration is such that the count value storage circuits (registers) provided in each store different random values . As described above, since the same clock count circuit is configured to count the count values to be stored in a plurality of registers, the configuration of the random number generator is as much as the arrangement of the clock count circuit provided for each conventional register. The space for doing so can be reduced, and downsizing is possible. Then, it is possible to reduce the manufacturing cost of the random number generation device while generating a random number having a short update cycle by hardware components such as a clock count circuit and preventing illegal acts.

  In addition, a register for storing a count value provided for each start winning tool or each symbol operating gate, for example, a register that can store a 1-byte count value provided for each symbol operating gate, and for the player It is also possible to use a register provided for each start winning tool for storing a multi-byte count value used as an opportunity to generate a game content (a jackpot game to be described later) that is more advantageous than the symbol operating gate. Is possible. As described above, if a register with a small storage capacity is used to store the count value acquired when the game ball enters the symbol operating gate, the components constituting the random number generator can be increased accordingly. It can be reduced. For this reason, it is possible to further reduce the size of the random number generator and reduce the cost of the random number generator.

  Hereinafter, a preferred embodiment of a ball game machine according to the present invention will be described in detail with reference to the accompanying drawings. 1 is an external front view of a pachinko machine PM described as an example of the above-described ball game machine, FIG. 2 is a rear view seen from the back side of the pachinko machine PM, and FIG. 3 is provided in the pachinko machine PM. FIG. 4 is a block diagram showing an outline of the control system. FIG. 4 is a block diagram showing a part related to the control of a gaming machine provided in the pachinko machine PM and a part related to generation of random numbers. FIG. FIG. 6 is a circuit diagram showing a random number generation unit, FIG. 6 is a diagram showing a main routine in the procedure for obtaining and using a random number for symbol lottery in the pachinko machine PM, and FIGS. 7 and 8 are diagrams of random numbers for symbol lottery in the pachinko machine PM. FIG. 9 is a diagram showing a part of a normal game processing subroutine in the procedure of acquisition and use, and FIG. 9 and FIG. 10 show how to acquire and use random numbers for symbol lottery in the pachinko machine PM. Are each diagram showing a part of a symbol variation processing subroutine in order.

  Here, first, a schematic configuration of a pachinko machine PM described as an example of the above-described ball game machine will be described with reference to FIG. 1 and FIG. This pachinko machine PM has a rectangular frame size and a front frame 2 that is configured to have a rectangular frame size corresponding to the front of the opening of the outer frame 1 that forms a vertical fixed holding frame. The hinge members 3a and 3b arranged on the left and upper sides are attached so as to be able to be opened and closed laterally and detachable, and normally in a closed state engaged with the outer frame 1 using a locking device 4 provided on the right side of the front. Retained.

  On the front side of the front frame 2, there is a glass door 5 that can be seen through the game board 20 through a transparent plate material such as a polycarbonate plate or a glass plate that has a rectangular shape matched to the front area of the front frame 2 and is attached to the center. Further, an upper ball tray 6 is arranged at the lower part of the glass door 5 to guide the game balls one by one to the hitting ball launching device 9 provided on the back surface of the front frame 2 by a hinge mechanism built in the left edge. 2 can be opened / closed and attached / detached sideways. Further, a lower ball tray 7 is provided at the lower part of the front frame 2, and an operation handle 8 for performing a game ball launching operation is attached along with the lower ball tray 7.

  The game board 20 is configured with a decorative board 21 having a substantially rectangular plate-like body and having a predetermined design cell attached to the surface thereof as a substrate. On the front side of the decorative plate 21, a belt-like outer rail 23a and an inner rail 23b are fixed in an arc shape, and a game area PA is defined on the inner side surrounded by the guide rails 23a and 23b. In the game area PA, the winning tools 22, 22, the starting winning tool 24, the second symbol operating gate 25a, the third symbol operating gate 25b, the attacker 26 with the big winning opening, the winning tool 29, and the progress of the game. A symbol display device 28 for displaying a predetermined symbol is attached, and the lower end of the game area PA falls without winning in any of the prize-winning tools 22, 22, 24, 29 and the big winning opening of the attacker 26. An out port 27 is provided for discharging the played game ball to the back side of the game board 20.

  The symbol display device 28 is located substantially at the center of the game board 20, and the symbol display device 28 displays a “special symbol” composed of a combination of three-digit symbols on the liquid crystal screen in a variable manner. 28a and a diagonally lower left and right portion of the first symbol display screen 28a, the display screen is smaller in size than the first symbol display screen 28a, and a “normal symbol” composed of a combination of two-digit symbols is used as a light emitting diode. It is comprised from a pair of 2nd and 3rd symbol display screens 28b and 28c which are variably displayed on the screen. Of the special symbols displayed on the first symbol display screen 28a, a symbol consisting of a combination of symbols of the same type in all three digits is particularly referred to as a “big hit symbol”. Of the symbols displayed on the second and third symbol display screens 28b and 28c, those in which two digits are composed of a combination of symbols of the same type are particularly referred to as “enlarged symbols”. Furthermore, the normal symbol displayed on the second symbol display screen 28b is referred to as "second symbol", and the normal symbol displayed on the third symbol display screen 28c is referred to as "third symbol".

  The starting prize-winning tool 24 is provided below the symbol display device 28, and has an enlargement device at the opening to expand the width of the opening. In the starting winning tool 24, a hitting ball flow path for detecting a hitting hit to the starting winning tool 24 is output and a detection signal is output, and the first symbol display screen 28a is used to start a variable display of symbols. One symbol operation sensor 51 is provided. The first symbol actuating sensor 51 uses a magnetic sensor and outputs a start winning signal that takes two states of a high signal and a low signal as a detection signal. The start winning signal is output as a low signal when no hit ball is detected, and is output as a high signal only while a hit ball is detected. An optical or mechanical sensor may be used as the first symbol operation sensor 51.

  The attacker 26 is attached below the start winning tool 24, and a part of the attacker 26 is opened by the operation of a solenoid (not shown) provided inside the attacker 26 in the case of a big hit game described later. It has become. In addition, on the diagonally upper left and right sides of the attacker 26, prize-winning tools 22, 22 are provided.

  The second symbol operating gate 25a and the third symbol operating gate 25b are provided diagonally below the symbol display device 28 at the same height as the start winning tool 24 so that the hit ball can be dropped. Yes. Similar to the first symbol operation sensor 51, a second symbol operation sensor 52 using a magnetic sensor is provided in the flow path of the hit ball in the second symbol operation gate 25a. The second symbol actuating sensor 52 outputs a hit ball falling signal that takes two states of a high signal and a low signal as a detection signal. The hit ball falling signal is output as a low signal when no hit ball is detected, and is output as a high signal only while a hit ball is detected. An optical or mechanical sensor may be used as the second symbol operation sensor 52.

  On the other hand, a third symbol activation sensor 53 using a magnetic sensor is provided in the hitting ball flow path in the third symbol activation gate 25 b, similarly to the first symbol activation sensor 51. The third symbol actuating sensor 53 outputs a hit ball falling signal that takes two states of a high signal and a low signal as a detection signal. The hit ball falling signal is output as a low signal when no hit ball is detected, and is output as a high signal only while a hit ball is detected. An optical or mechanical sensor may be used as the third symbol operation sensor 53.

  In addition, the winning tool 29 capable of winning a hit ball is provided above the symbol display device 28 in the game area PA, and has an enlargement device at the opening to increase the width of the opening. It has become. Also, four special symbol holding lamps 90, 90, 90, 90 are provided above the symbol display device 28, and two normal symbol holding lamps 91, 91 are provided on the left and right sides of the second symbol display screen 28b. 91, 91, and two normal symbol holding lamps 92, 92, 92, 92 are provided on the left and right sides of the third symbol display screen 28c.

  Further, a pair of right and left error display devices 93 (error LEDs) are provided above the game area PA to notify when an operation abnormality or the like of a circuit inside the pachinko machine PM occurs. When the error display device 93 is turned on, the player can recognize that the game operation of the pachinko machine PM is stopped due to an abnormality of the pachinko machine PM.

As shown in FIG. 2, the lower part of the rear surface of the front frame 2 has a hitting ball launching device 9 that launches a game ball toward the outer rail 23 a, and an operation of the hitting ball launching device 9 in response to the turning operation of the operation handle 8. A launcher control board 200 to be controlled is attached. Further, behind the upper ball tray 6 is formed an auxiliary mechanism portion called a game assisting board whose front side is normally covered with the upper ball tray 6 that is normally held closed, and a ball hitting device on the front side. Foul ball collection that discharges the game ball launched by 9 toward the outer rail 23a and the foul ball returned to the ball launcher 9 side without reaching the game area PA to the lower ball tray 7 A route member, a speaker for generating sound effects according to the game development status, and the like are attached.

  A back set board 30 is attached to the back of the front frame 2. This back set board 30 has a rectangular shape somewhat smaller than the inner size of the outer frame 1, and is configured based on a base frame body 31 integrally formed with a window 31w penetrating the front and back at the center. . Back set board swinging hinge members 32 and 33 are fixed to the side edge of the base frame body 31 at a predetermined interval in the vertical direction. The upper and lower back set panel swinging hinge members 32 and 33 are fixed to the front frame 2. The back set board 30 is mounted on the back side of the front frame 2 so that it can be opened and closed laterally and detachable by engaging with the upper and lower fixed hinge members 12 and 13 and swinging or disengaging. The closing lever 34 is used to close and hold the back of the front frame 2.

  The back set board 30 is provided with a prize ball path for paying out prize balls so as to surround the window 31w. That is, on the back side of the base frame 31, a tank member 35 for storing and supplying game balls, an alignment rod member 36 for aligning and flowing down game balls supplied from the tank member 35, and an alignment rod member 36 are supplied. A prize ball standby passage 37 for receiving and waiting for a predetermined number of game balls, a ball payout device 38 for paying out the game balls waiting in the prize ball standby passage 37 based on predetermined winning conditions, etc. A prize ball path such as a prize ball payout path 39 for guiding the game balls paid out from the payout device 38 to the upper and lower ball trays 6 and 7 is provided. In addition, on the front side of the base frame 31, an out ball and a safe ball that are positioned below the window 31 w and discharged to the back side of the game board 20, and a punch that is discharged from the middle of the winning ball path by the ball punching mechanism. A collecting path (not shown) for collecting balls and the like is formed, and a ball discharging path (not shown) is formed on the back surface side of the base frame 31 to discharge the game balls gathered connected to the collecting path to a collection bucket on the gaming facility side. ing.

  In each part of the back surface of the back set board 30, operation control of the game control device 700 as a main board for comprehensively controlling the operation of the pachinko machine PM and the ball payout device 38 based on a command signal from the game control device 700 is performed. A circuit board such as a ball payout board 300 to be performed, a lamp / voice control board 400 for controlling the operation of effect lighting and sound effects, and a power supply board 500 for supplying electric power to these control boards and various electronic devices is detachably attached. These circuit boards and electronic devices are connected by a wire harness (not shown) to constitute a pachinko machine PM.

  The pachinko machine PM is used in a game with the glass door 5, the upper ball tray 6, the back set board 30 and the like closed, and the front frame 2 closed and locked to the outer frame 1. The game is started by storing the game balls in the upper ball tray 6 and rotating the operation handle 8, and the game balls stored in the upper ball tray 6 are sent one by one to the hitting ball launcher 9 and are operated. The game is developed by being struck into the game area PA with the strength corresponding to the rotation operation angle.

  Next, an outline of the game in the pachinko machine PM will be described. First, when a player operates the operation handle 8, a hit ball is shot on the game board 20. The hit ball falls on the game board 20 while contacting a nail or the like (not shown). When a prize is won in any of the prize-winning tools 22, 22 in the process of falling, a prize ball provided on the upper left side of the backing plate 6 a that forms a horizontal rectangle in the upper ball tray 6 and can be opened and closed with respect to the front frame 2. Five prize balls are paid out to the player from the payout opening 6b.

  When the hit ball falls into the second symbol operation gate 25a and the second symbol operation sensor 52 provided in the second symbol operation gate 25a detects the hit ball (that is, when a high signal is output), the second symbol display screen In 28b, the variation of the normal symbol is started. Further, when the hit ball falls into the third symbol operation gate 25b and the third symbol operation sensor 53 provided in the third symbol operation gate 25b detects the hit ball (that is, when a high signal is output), the third symbol is operated. The change of the normal symbol is started on the display screen 28c. In a normal case, when a predetermined time (for example, 30 seconds) elapses after the fluctuation starts, a predetermined normal symbol already determined at the start of the fluctuation is stopped and displayed.

  When the normal symbol stopped and displayed on the second symbol display screen 28b is a combination of an enlarged symbol, for example, “77”, the magnifying device in the start winning tool 24 operates for a predetermined time, and the width of the opening of the start winning component 24 is increased. Is enlarged, it is easy to win a hit ball on the start winning tool 24. In addition, when the normal symbol that is stopped and displayed on the second symbol display screen 28b is a combination such as “13” that is not an enlarged symbol, the enlargement device of the start winning component 24 does not operate. Winning 24 is possible. If the hit ball enters the second symbol operation gate 25a during the variable display on the second symbol display screen 28b, up to four normal symbol holding lamps 91, 91, 91, 91 are lit. It has become. That is, the subsequent operation of the second symbol display screen 28b is assured by the number of times corresponding to the number of the normal symbol holding lamps 91, 91, 91, 91 being lit.

  When the normal symbol that is stopped and displayed on the third symbol display screen 28c is an enlarged symbol, for example, a combination of “77”, the magnifying device in the winning tool 29 operates for a predetermined time, and the width of the opening of the winning tool 29 is increased. By doing so, it becomes easy to win a hit ball on the winning tool 29. In addition, when the normal symbol that is stopped and displayed on the third symbol display screen 28c is a combination such as “13” that is not an enlarged symbol, the enlargement device of the winning tool 29 does not operate. Is possible. If the hit ball enters the third symbol operation gate 25b during the variable display on the third symbol display screen 28c, up to four normal symbol holding lamps 92, 92, 92, 92 are lit. It has become. That is, the subsequent operation of the third symbol display screen 28c is assured by the number of times corresponding to the number of the ordinary symbol holding lamps 92, 92, 92, 92 being lit.

  When there is a winning at the start winning opening 24, in addition to paying out five winning balls from the winning ball payout exit 6b, the first symbol display screen 28a is activated and the first symbol display screen 28a is operated. The design changes. As a result of this symbol variation, when the special symbol to be stopped and displayed is the jackpot symbol, a “jackpot game” is generated. In this jackpot game, the big prize opening in the normally closed attacker 26 is opened. When there is a hit of a hit ball at the open big winning opening, 15 prize balls are paid out from the prize ball payout exit 6b.

  The special winning opening is temporarily closed depending on whether a predetermined time (for example, 30 seconds) has elapsed since opening or ten balls have been won. And if there is a prize in a so-called V zone (specific area) (not shown) provided inside the big prize opening while the big prize opening is open, the big prize opening is once closed and then again It is supposed to be opened. Thereby, the opening of the special winning opening can be continued up to 16 times. In addition, when the big winning opening is finished 16 times, or when there is no winning in the V zone during the opening of the big winning opening, the jackpot game is ended. If the hit ball wins the start winning tool 24 during the variable display on the first symbol display screen 28a, up to four special symbol hold lamps 90, 90, 90, 90 are lit. Yes. That is, the subsequent operation of the first symbol display screen 28a is guaranteed by the number of times corresponding to the number of the special symbol holding lamps 90, 90, 90, 90 being lit.

  As described above, among the symbol display devices 28 including the first to third symbol display screens 28a, 28b, and 28c provided in the bullet ball game machine according to the present invention, the symbols are displayed on the first symbol display screen 28a. The symbol is displayed as an opportunity to generate a game content (a jackpot game) that is more advantageous to the player depending on the symbol to be stopped and displayed than the symbols displayed on the second and third symbol display screens 28b and 28c. Is.

  Next, an outline of a control system for controlling the pachinko machine PM will be described. As shown in FIG. 3, the present control system is a game control device 700 as a main board for comprehensively controlling the operation of the pachinko machine PM, a first symbol operation sensor 51, a second symbol operation sensor 52, and a third symbol operation. A sensor 53, a symbol display device 28, and the like are provided, and these are electrically connected by a cable or the like.

  The game control device 700 as a main board includes a system program for managing the entire operation of the pachinko machine PM, a storage unit formed by a semiconductor memory or the like in which a game execution program is stored in advance, and a micro that executes these programs. A main control unit 730 having a processor (hereinafter referred to as “CPU”), and generates a 16-bit random number (65536 random numbers from 0 to 65535) for symbol lottery regardless of the control by the main control unit 730 And a random number generator 750. In the present invention, the random number is not only a value that is randomly generated in a mathematical sense, but even if the generation is regular, the acquisition timing is random, so that the random number is substantially a random number. It also means a functional value. In the present invention, the random value counted by the clock count circuits B81 to B84, which will be described later, and stored in the first and second count value storage circuits B91 and B92 will be specifically referred to as “count value”.

  In addition to the CPU 732 described above, the control unit 740 in the main control unit 730 is provided with a ROM 733 and a RAM 734, and a control program to be executed by the CPU 732 and data necessary for the control process are described in the ROM 733. The main control unit 730 is provided with a reference clock generation circuit 731. The reference clock generation circuit 731 is a circuit that generates a reference clock that is an operation reference of the CPU 732 that plays a central role in the control of the pachinko machine PM. Pulses (clocks) at predetermined intervals using a crystal oscillator, a crystal resonator, or the like. Is generated. Further, the reference clock may be obtained by appropriately dividing the pulse by the frequency dividing unit 735 and converting the frequency.

  In addition, the CPU 732 has a symbol lottery means B35. When the game control device 700 detects a high signal from any one of the first symbol activation sensor 51, the second symbol activation sensor 52, and the third symbol activation sensor 53, 65536 random numbers generated sequentially from the random number generator 750. Among these, by obtaining one count value stored in a later-described count value storage circuit in the random number generator 750 by the symbol lottery means B35, the symbol display device 28 determines the stop symbol. The signal from the first symbol activation sensor 51 corresponds to the symbol variation control on the first symbol display screen 28a, and the signal from the second symbol activation sensor 52 corresponds to the symbol variation control on the second symbol display screen 28b. The signal from the third symbol operation sensor 53 corresponds to the symbol variation control on the third symbol display screen 28c.

  The symbol data table B36 on the ROM 733 contains a three-digit stop symbol on the first symbol display screen 28a in the symbol display device 28, a two-digit stop symbol on the second symbol display screen 28b, and a third symbol display screen. Symbol data for determining a 3-digit stop symbol in 28c is recorded. Each symbol data is given an address number, and one symbol data is specified from one address number. As described above, when a high signal is detected from any one of the first symbol operation sensor 51, the second symbol operation sensor 52, and the third symbol operation sensor 53, the symbols selected from the random numbers generated by the random number generator 750 are selected. The stop symbol is selected by comparing the lottery count value with the symbol data in the symbol data table B36. The predetermined stop symbols selected in this way are displayed on the first to third symbol display screens 28a to 28c of the symbol display device 28 on the game board 20, respectively.

  Here, with reference to FIG. 4 and FIG. 5, the structure of the part which concerns on generation | occurrence | production of the random number in the pachinko machine PM, and this extraction is demonstrated. FIG. 4 shows the main control unit 730 related to the control of the pachinko machine PM in the game control device 700, the random number generation unit 750 related to the generation of random numbers, etc., to the first to third symbol operation sensors 51 to 53 on the game board 20. Are also conceptually shown in a block diagram, and FIG. 5 is a circuit diagram of the random number generator 750. The input circuit unit B40 is a part to which input information from outside the game control device 700 as a main board and a random number generated by a random number generator 750 provided in the main board 700 are input, and is configured by a buffer IC or the like. Is done. Specifically, in the input circuit portion B40, an input signal from the first symbol operation sensor 51 that is output in response to the winning of the hit ball to the start winning tool 24, the second symbol operation gate 25a and the third symbol operation gate. 8b of the random number generated by the input signal from the second symbol activation sensor 52 and the third symbol activation sensor 53, which is output in response to the drop of the hit ball into any one of 25b, or the random number generator 750 Minutes are entered.

  The output circuit unit B45 is a part that outputs a signal such as a control signal to an electrical component (lamp, speakers) outside the game control device 700 and a read signal for reading a random number generated by the random number generator 750, such as a buffer. It is comprised by IC etc. Specifically, from the output circuit unit B45, when the game control device 700 determines that the start winning tool 24 has won a hit ball, a first read signal that triggers reading of a count value corresponding to this win Alternatively, when the game control device 700 determines that a hit ball has fallen into the second symbol operation gate 25a, a second read signal that triggers reading of the count value corresponding to this drop is output. Further, when the game control device 700 determines that a hit ball has dropped into the third symbol operation gate 25b, a third read signal is output as a trigger for reading the count value corresponding to this drop.

  The random number generation unit 750 generates and stores a count value used as a random number. Specifically, the random number generation unit B51, a random number clock inversion circuit B61, and first to third latch signal output circuits B71. , B72, B73, first to fourth clock count circuits B81, B82, B83, B84, a first count value storage circuit B91, and a second count value storage circuit B92 having upper and lower storage circuits B92a, B92b. .

  The random number clock generation circuit B51 (OSC1) is for generating a clock for counting random numbers and includes a clock output unit (OUT) for outputting the generated clock. The random number clock generation circuit B51 is constituted by, for example, a crystal oscillator that generates a 7.15909 MHz clock.

  The random number clock inversion circuit B61 (IC14a) inverts the clock output from the random number clock generation circuit B51, and uses the inverted clock as an inverted clock, which will be described later, a first latch signal output circuit B71 (IC13a) and a second latch signal output circuit. This is output to B72 (IC13b). Specifically, in the IC 14a, a signal obtained by inverting the clock output from the 1Q terminal is output as an inverted signal from the 1Q inverting terminal which is an inverted clock output unit, and the rising edge of the clock is the falling edge of the inverted clock. The falling edge of the clock corresponds to the rising edge of the inverted clock. The random number clock inverting circuit B61 may be configured using an IC such as a NOT gate.

  Each of the first to fourth clock count circuits B81, B82, B83, and B84 has a random number clock input unit (CK) for inputting a clock and a count output unit (QA to QD) for outputting the counted value. is doing. As shown in FIG. 5, the first to fourth clock count circuits B81, B82, B83, and B84 are constituted by a circuit in which four 4-bit increment counters (from IC1 to IC4) are cascade-connected to generate a random number clock. This is a circuit for adding at the rising edge of the clock generated by the circuit B51 and outputting the addition result.

  By inputting a clock from the random number clock generation circuit B51, first, a value for four digits (for example, “0001” and “0011”) is counted in the IC1. When "1111" is counted and the count of four digits ends, a carry signal is output from the CO terminal of IC1 to the ENT terminal of the second clock count circuit B82 (IC2) each time. In order for the second clock count circuit B82 to start counting, it is necessary to input the carry signal from the first clock count circuit B81. That is, in the IC2, the next four digits are started only after the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC2, a carry signal is sent from the CO terminal of IC2 to the third clock count circuit B83 each time. It is output to the ENT terminal of (IC3). In order for the third clock count circuit B83 to start counting, it is necessary to input the carry signal from the second clock count circuit B82. That is, in the IC 3, the next four digits are started only after the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B 51 are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC3, the carry signal is counted from the CO terminal of IC3 to the fourth clock each time. It is output to the ENT terminal of the circuit B84 (IC4). In order for the fourth clock count circuit B84 to start counting, it is necessary to input the carry signal from the third clock count circuit B83. In the IC4, this carry signal and the clock from the random number clock generation circuit B51 are required. (Input to the CK terminal) is input at the same time, and the next four digits are counted.

  As described above, a 16-bit binary number is generated by the clock count circuits B81 to B84. That is, among the 16-digit binary numbers, the first clock count circuit B81 (IC1) is the lowest four digits, the second clock count circuit B82 (IC2) is the upper four digits, and the third clock count circuit B83 (IC3 ) Is further in charge of the upper 4 digits and the fourth clock count circuit B84 (IC4) is in charge of the uppermost 4 digits.

  The counts added by the four clock count circuits B81 to B84 are sent to the first count value storage circuit B91 and the second count value storage circuit B92 via the respective count output sections (QA, QB, QC and QD terminals). Each is output and stored. In this embodiment, an addition type increment counter is used as the clock count circuit. However, in other embodiments, a subtraction type decrement counter may be used. In this embodiment, a 16-bit random number (4 bits × 4) is generated. However, in other embodiments, the number of bits is not limited to 16 bits and may be changed as appropriate. .

  The latch signal output circuit includes a first latch signal output circuit B71 (IC13a) related to acquisition of a random number associated with winning of a hit ball to the start winning tool 24, and a random number associated with dropping of a hit ball into the second symbol operating gate 25a. It is divided into a second latch signal output circuit B72 (IC13b) related to acquisition and a third latch signal output circuit B73 (IC14b) related to acquisition of random numbers associated with the drop of the hit ball into the third symbol operating gate 25b. .

  The inverted clock from the random number clock inverter circuit B61 (IC14a) is input to the first latch signal output circuit B71 (IC13a) via the first inverted clock input section (2CK). Further, the first symbol activation signal from the first symbol activation sensor 51 is input via the first symbol activation signal input unit (2D). When the first latch signal output circuit B71 receives the first symbol activation signal as the high signal via the first symbol activation signal input unit (2D), The first count value storage circuit B91 (IC5) is delayed as synchronized with the rising edge of the inverted clock input from the inverted clock input unit (2CK) and passed through the first latch signal output unit (2Q) as the first latch signal. And IC6).

  On the other hand, the inverted clock from the random number clock inverting circuit B61 is input to the second latch signal output circuit B72 (IC13b) via the second inverted clock input unit (1CK). Further, the second symbol operation signal from the second symbol operation sensor 52 is inputted through the second start signal input unit (1D). The second latch signal output circuit B72, when the second symbol operation signal as a high signal is input via the second start signal input section (1D), second rising edge of this signal is second inverted. Delayed in synchronization with the rising edge of the inverted clock input from the clock input unit (1CK), passed through the second latch signal output unit (1Q) as the second latch signal, The data is output to the upper memory circuit B92a (IC7).

Further, the third symbol activation signal from the third symbol activation sensor 53 is inputted to the third latch signal output circuit B73 (IC14b) via the third symbol activation signal input section (2D) . The third latch signal output circuit B73, when the third symbol actuation signal as a high signal through the third symbol actuating signal input section (2D) is input, the third latch signal output unit (2Q) The third latch signal is output to the lower-order storage circuit B92b (IC8) in the 2-count value storage circuit B92.

  The first to third symbol operation signals are also input to the main control unit 730 via the input circuit unit B40 and the like, as will be described later, and random number acquisition in a program described later executed for random number acquisition. It is also used as the timing for starting the process.

  The count value storage circuits B91 and B92 are used to temporarily store a random number derived from the winning of the hit ball to the start winning tool 24, and to drop the hit ball to the second symbol operating gate 25a. Of the second count value storage circuit B92 that temporarily stores the derived random number, the upper storage circuit B92a, and further, the random number derived from the drop of the hit ball into the third symbol operating gate 25b is temporarily stored. The second count value memory circuit B92 is divided into a lower memory circuit B92b.

  The first count value storage circuit B91 stores the count value counted by the clock count circuits B81 to B84 based on the first latch signal from the first latch signal output circuit B71. On the other hand, the upper storage circuit B92a of the second count value storage circuit B92 stores the count value counted by the clock count circuits B81 to B84 based on the second latch signal from the second latch signal output circuit B72. Is. Further, the low-order storage circuit B92b of the second count value storage circuit B92 stores the count value counted by the clock count circuits B81 to B84 based on the third latch signal from the third latch signal output circuit B73. Is.

  As shown in FIG. 5, the first count value storage circuit B91 includes a register unit (IC5 and IC6) including two 8-bit ICs and a buffer unit (IC9 and IC10) including two 8-bit ICs. The Further, the upper storage circuit B92a of the second count value storage circuit B92 includes a register unit (IC7) including one 8-bit IC and a buffer unit (IC11) including one 8-bit IC. Further, the low-order storage circuit B92b of the second count value storage circuit B92 includes a register unit (IC8) including one 8-bit IC and a buffer unit (IC12) including one 8-bit IC.

  Among the register units of the first count value storage circuit B91, the IC5 has a 4-digit count value from the first clock count circuit B81 (IC1) via the D1 terminal to the D4 terminal and the second clock count. The 4-digit count value from the circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, all the counts output from the count output unit (QA to QD terminals) of the first clock count circuit B81 are allocated as part of the random number stored in the first count value storage circuit B91, and the second clock All the counts output from the count output unit (QA to QD terminals) of the count circuit B82 are allocated as part of the random numbers stored in the first count value storage circuit B91. As described above, the D1 terminal to D8 terminal of the IC5 function as a count input unit, and the last 8 digits of the 16-bit binary count value derived from the first start winning tool 24a are input to the IC5 through them. The

  Among the register units of the first count value storage circuit B91, the IC6 has a 4-digit count value from the third clock count circuit B83 (IC3) via the D1 terminal to the D4 terminal and the fourth clock count. A 4-digit count value from the circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, all the counts output from the count output unit (QA to QD terminals) of the third clock count circuit B83 are allocated as part of the random number stored in the first count value storage circuit B91, and the fourth clock All the counts output from the count output unit (QA to QD terminals) of the count circuit B84 are assigned as part of the random number stored in the first count value storage circuit B91. As described above, the D1 terminal to D8 terminal of the IC 6 function as a count input unit, and the upper 8 digits of the 16-bit binary count value derived from the start winning tool 24 are input to the IC 6 through them.

  Of the counts output from the count output unit (QA to QD terminals) of the first clock count circuit B81, the register output (IC7) of the upper storage circuit B92a in the second count value storage circuit B92 is a count output unit. Counts output from the count output unit (QA to QD terminals) of the second clock count circuit B82 are assigned with the counts output from the QA and QC and input through the D1 terminal and the D2 terminal, respectively. Counts output from the parts QA and QC are allocated and input via the D3 terminal and the D4 terminal, respectively. Of the counts output from the count output units (QA to QD terminals) of the third clock count circuit B83, the counts output from the count output units QA and QC are assigned to the register unit (IC7). Of the counts input from the D5 terminal and D6 terminal and output from the count output unit (QA to QD terminals) of the fourth clock count circuit B84, the counts output from the count output units QA and QC are assigned. Are respectively input via the D7 terminal and the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 7 function as a count input unit, and an 8-bit binary count value derived from the second symbol operation gate 25a is input to the IC 7 through them.

  Of the counts output from the count output unit (QA to QD terminals) of the first clock count circuit B81, the register output (IC8) of the low-order storage circuit B92b of the second count value storage circuit B92 is the count output unit. Of the counts output from the count output unit (QA to QD terminals) of the second clock count circuit B82, the counts output from the QB and QD are assigned and input via the D1 terminal and the D2 terminal, respectively. Counts output from the parts QB and QD are allocated and input via the D3 terminal and the D4 terminal, respectively. The register unit (IC8) is assigned the counts output from the count output units QB and QD among the counts output from the count output unit (QA to QD terminals) of the third clock count circuit B83. Of the counts inputted from the D5 terminal and D6 terminal and outputted from the count output part (QA to QD terminals) of the fourth clock count circuit B84, the counts outputted from the count output parts QB and QD are assigned. Are respectively input via the D7 terminal and the D8 terminal. That is, the D1 terminal to D8 terminal of the IC8 function as a count input unit, and an 8-bit binary count value derived from the third symbol operation gate 25b is input to the IC8 through them.

  The first latch signal from the first latch signal output circuit B71 is input to the CLK terminal in the register unit (IC5 and IC6) of the first count value storage circuit B91. That is, these CLK terminals function as a first latch signal input unit. The count values input from the clock count circuits B81 to B84 at the time of the rising edge when the first latch signal input from the first latch signal input unit becomes a high signal are stored in the register units (IC5 and IC6). The Rukoto.

  The second latch signal from the second latch signal output circuit B72 is input to the CLK terminal in the register unit (IC7) of the higher-order memory circuit B92a in the second count value memory circuit B92. That is, the CLK terminal functions as a second latch signal input unit. The count value input from the clock count circuits B81 to B84 is stored in the register unit at the rising edge when the second latch signal input from the second latch signal input unit becomes a high signal.

  Further, the third latch signal from the third latch signal output circuit B73 is input to the CLK terminal of the lower-order storage circuit B92b register unit (IC8) in the second count value storage circuit B92. That is, the CLK terminal functions as a third latch signal input unit. The count value input from the clock count circuits B81 to B84 is stored in the register unit at the rising edge when the third latch signal input from the third latch signal input unit becomes a high signal.

  The G1 terminals in the buffer units (IC9 and IC10) of the first count value storage circuit B91 have read signals output from the output circuit unit B45 of the main control unit 730 based on a program executed for acquiring random numbers. In response to this read signal, one count value consisting of 16 digits stored in the first count value storage circuit B91 is output to the CPU 732. That is, at the time of the rising edge when the read signal input from the read signal input unit becomes a high signal, the count values stored in the register units (IC5 and IC6) at that time are respectively applied to the Y1 terminal to the Y8 terminal. Via the CPU data bus.

  Of the count values output from the first count value storage circuit B91, those that pass through the IC 9 are input to the CPU 732 via the input circuit unit B40, and are handled as the lower 8 digits of the 16-digit random number. It will be. On the other hand, among the count values output from the first count value storage circuit B91, those passing through the IC 10 are input to the CPU 732 via the input circuit unit B40 and are handled as the upper 8 digits of the 16-digit random number. It will be.

  The terminal G1 in the buffer unit (IC11) of the higher-order storage circuit B92a in the second count value storage circuit B92 is input from the read signal output from the output circuit unit B45 of the main control unit 730 based on the program, In response to this read signal, one count value consisting of 8 digits stored in the upper storage circuit B92a of the second count value storage circuit B92 is output to the CPU 732. That is, at the time of the rising edge when the read signal input from the read signal input unit becomes a high signal, the count value stored in the register unit (IC7) at that time is the CPU data via the Y1 terminal to Y8 terminal. Output to the bus.

  The terminal G1 in the buffer unit (IC12) of the lower-order storage circuit B92b of the second count value storage circuit B92 is input from a read signal output from the output circuit unit B45 of the main control unit 730 based on the program, In response to this read signal, one count value consisting of 8 digits stored in the low-order storage circuit B92b of the second count value storage circuit B92 is output to the CPU 732. That is, at the time of the rising edge when the read signal input from the read signal input unit becomes a high signal, the count value stored in the register unit (IC8) at that time is the CPU data via the Y1 terminal to Y8 terminal. Output to the bus.

  Next, the procedure for acquiring and using random numbers in an actual game will be described with reference to the flowcharts of FIGS. The flowcharts shown in FIG. 7 and FIG. 8 constitute a single flowchart by connecting the portions of the circle A, and the flowcharts shown in FIG. 9 and FIG. 10 are one flowchart in which the portions of the circle B are connected. Is configured.

  When the power of the pachinko machine PM is turned on, necessary parameters are initialized, and then the game process is executed according to the main routine shown in FIG. In this main routine, first, the normal game processing subroutine R1 is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1, in step S100, the hitting of the hit ball into the start winning tool 24 and the drop of the hit ball into the second symbol operating gate 25a and the third symbol operating gate 25b are checked.

  In step S <b> 110, it is determined whether or not there is a winning for the start winning tool 24. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S180 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S120.

  In step S120, a first read signal for the upper 8 bits of a 16-bit random number is output from the first read signal output unit of the output circuit unit B45. Then, the first read signal for the upper 8 bits is input to the first read signal input section (G1 terminal of the IC 10) of the first count value storage circuit B91. Then, the count value stored in the register unit (IC6) of the first count value storage circuit B91 is input to the first random number output from the buffer unit (IC10) by the input of the first latch signal based on the winning to the start winning tool 24. Part (Y1 terminal to Y8 terminal). Then, the process proceeds to step S130.

  In step S130, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S140. In step S140, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S150.

  In step S150, the first read signal for the lower 8 bits of the 16-bit random number is output from the first read signal output unit of the output circuit unit B45. Then, the first read signal for the lower 8 bits is input to the first read signal input unit (G1 terminal of IC9) of the first count value storage circuit B91. Then, the count value stored in the register unit (IC5) of the first count value storage circuit B91 by the input of the first latch signal based on the winning to the start winning tool 24 is the first random number output unit of the buffer unit (IC9). (Y1 terminal to Y8 terminal). Then, the process proceeds to step S160.

  In step S160, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S170. In step S170, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of a 16-bit random number. Then, together with the upper 8 bits stored in the previous step S140, it is handled as a 16-bit random number. Then, the process proceeds to step S180 in FIG.

In step S180 of FIG. 8, it is determined whether or not a hit ball has dropped into the second symbol operating gate 25a. Here, if it is determined that there is no drop, or if there is a drop but the number of reserved balls has already reached four, the process proceeds to step S220 . On the other hand, if it is determined that the number of reserved balls is less than 4 and there is a drop, the number of reserved balls is incremented by 1, and the process proceeds to step S190.

  In step S190, the second read signal is output from the second read signal output unit of the output circuit unit B45. Then, the 8-bit second read signal is input to the second read signal input unit (G1 terminal of the IC 11) of the higher-order storage circuit B92a in the second count value storage circuit B92. The count value stored in the register unit (IC7) of the upper memory circuit B92a of the second count value memory circuit B92 by the input of the second latch signal based on the drop of the hit ball into the second symbol operation gate 25a is obtained. , And output from the second random number output unit (Y1 terminal to Y8 terminal) of the buffer unit (IC11). Then, the process proceeds to step S200.

  In step S200, the count value output in the above stage is input from the random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S210. In step S210, the 8-bit count value input in the above-described stage is stored in the RAM 734. Then, the process proceeds to step S220.

  In step S220, it is determined whether or not a hit ball has entered the third symbol operating gate 25b. Here, if it is determined that there is no drop, or if there is a drop but the number of reserved balls has already reached four, the process proceeds to step S260. On the other hand, if it is determined that the number of reserved balls is less than four and there is a drop, the number of reserved balls is incremented by 1, and the process proceeds to step S230.

  In step S230, the third read signal is output from the third read signal output unit of the output circuit unit B45. The third read signal is input to the third read signal input unit (G1 terminal of the IC 12) of the second count value storage circuit B92. The count value stored in the register unit (IC8) of the second count value storage circuit B92 by the input of the third latch signal based on the drop of the hit ball into the third symbol operation gate 25b is the buffer unit (IC12). It is output from the third random number output unit (Y1 terminal to Y8 terminal). Then, the process proceeds to step S240.

  In step S240, the count value output in the above stage is input from the random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S250. In step S250, the 8-bit count value input in the above-described stage is stored in the RAM 734.

  In the subsequent step S260, various software random numbers for use in determining a special symbol are acquired and stored in the RAM 734 as well. Then, the process returns to the main routine shown in FIG. In the main routine shown in FIG. 9, the symbol variation processing subroutine R2 is executed according to the flowcharts shown in FIGS.

  In the symbol variation processing subroutine R2, first, in step S300 of FIG. 9, it is determined whether or not the number of reserved balls on the second symbol variation screen 28b is 1 or more. When the number of reserved balls is 0, the variation process on the second symbol variation screen 28b is not executed, and the process proceeds to step S340. On the other hand, if the number of reserved balls is 1 or more, the process proceeds to step S310. In step S310, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S320.

  In step S320, among the 8-bit random numbers (up to four) stored in the RAM 734 in step S210 in the previous normal game processing subroutine R1, the first stored one is stored in the ROM 733 from the storage area on the RAM 734. It is read into the upper storage area. The random number is deleted from the storage area on the RAM 734. Then, the process proceeds to step S330. In step S330, the random number read into the storage area on the ROM 733 in the above stage is compared with the symbol data in the symbol data table B36, so that the type of the normal symbol for the stop display is determined, and the symbol is finalized. The variable display that is displayed automatically is executed on the second symbol display screen 28b on the game board 20. Then, the process proceeds to step S340.

  In step S340, it is determined whether or not the number of reserved balls on the third symbol variation screen 28c is 1 or more. If the number of reserved balls is 0, the variation process on the third symbol variation screen 28c is not executed, and the process proceeds to step S380. On the other hand, when the number of reserved balls is 1 or more, the process proceeds to step S350. In step S350, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S360.

  In step S360, among the 8-bit random numbers (up to four) stored in the RAM 734 in step S250 in the previous normal game processing subroutine R1, the first stored one is stored in the ROM 733 from the storage area on the RAM 734. It is read into the upper storage area. The random number is deleted from the storage area on the RAM 734. Then, the process proceeds to step S370. In step S370, the random number read into the storage area on the ROM 733 in the above stage is compared with the symbol data in the symbol data table B36, thereby determining the type of the normal symbol to be stopped and displayed. The variable display is displayed on the third symbol display screen 28c on the game board 20. Then, the process proceeds to step S380.

  In step S380, it is determined whether or not the number of reserved balls on the first symbol variation screen 28a is 1 or more. When the number of held balls is 0, the variation process on the first symbol variation screen 28a is not executed, and the process returns to the main routine shown in FIG. On the other hand, when the number of reserved balls is 1 or more, the process proceeds to step S390. In step S390, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S400.

  In step S400, among the 16-bit random numbers (up to four) stored in the RAM 734 in steps S140 and S170 in the previous normal game processing subroutine R1, the first stored one is stored in the RAM 734. The data is read from the area to the storage area on the ROM 733. The random number is deleted from the storage area on the RAM 734. Then, the process proceeds to step S410. In step S410, the random number read into the storage area on the ROM 733 in the above-described stage is compared with the symbol data in the symbol data table B36 to determine whether or not the winning is made. If not, the process proceeds to step S430. On the other hand, in the case of winning, the process proceeds to step S420.

  In step S420, a special game flag is set. Then, the process proceeds to step S430. In step S430, after determining the type of special symbol according to the presence / absence of winning using the software random number acquired in step S260 of the previous normal game processing subroutine R1, the special symbol is finally displayed. Such variable display is executed on the first symbol display screen 28 a on the game board 20. Then, the process returns to the main routine shown in FIG.

  Next, in the main routine shown in FIG. 6, a special game processing subroutine R3 is executed. In the special game processing subroutine R3, when the special game flag is set in step S420 of the previous symbol variation processing subroutine R2, a special game, that is, a big hit game is executed. Then, after the jackpot game is over, the special game flag is cleared and then the process returns to the main routine. On the other hand, if the special game flag is not set, the process immediately returns to the main routine.

  In the main routine, the game is continued by repeating the subroutines R1 to R3 described above.

  Although the preferred embodiments of the present invention have been described so far, the scope of the present invention is not limited to the above-described embodiments. For example, the counts output from the count output units QA and QD of the first clock count circuit B81 to the register unit (IC7) of the higher-order storage circuit B92a in the second count value storage circuit B92, and the second clock count circuit B82 The count output unit QA outputs the count, the count output units QA and QD of the third clock count circuit B82 output, and the count output units QA, QB, and QD of the fourth clock count circuit B84. A count may be assigned and stored.

  In the register unit (IC8) of the low-order memory circuit B92b in the second count value memory circuit B92, for example, the count output from the count output parts QB and QC of the first clock count circuit B81 and the second clock The count output from the count output units QB, QC, QD of the count circuit B82, the count output from the count output units QB and QD of the third clock count circuit B82, and the count output unit QC of the fourth clock count circuit B84 And the count output from the program may be assigned and stored.

  That is, the counts assigned to and stored in the register unit (IC7) of the higher-order memory circuit B92a and the register unit (IC8) of the lower-order memory circuit B92b are used as the count output units of the first to fourth clock count circuits B81 to B84. It is possible to select at random from the counts output from QA to QD and assign them to each register unit.

1 is a front view of a game board of a ball game machine according to the present invention. It is a figure showing the internal structure of the ball game machine which concerns on this invention. It is a block diagram showing the outline of the control system provided in the said bullet ball game machine. It is a block diagram showing the part concerning control of the ball game machine provided in the said ball game machine, and the part concerning generation | occurrence | production of a random number. It is a circuit diagram showing the random number generation part in the said ball game machine. It is the figure which showed the main routine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said ball game machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said ball game machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said ball game machine. It is the figure which showed a part of symbol variation process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said ball game machine. It is the figure which showed a part of symbol variation process subroutine in the procedure of acquisition and utilization of the random numbers for symbol lottery in the said ball game machine.

Explanation of symbols

20 Game board 24 Start prize (first starter)
25a 2nd symbol operation gate (second starter)
25b 3rd symbol operation gate (second starter)
28 symbol display device 28a first symbol display screen (symbol display device)
28b 2nd symbol display screen (symbol display device)
28c 3rd symbol display screen (symbol display device)
51 1st pattern operation sensor (signal detection means)
52 2nd pattern operation sensor (signal detection means)
53 3rd pattern operation sensor (signal detection means)
732 CPU (Random number extraction means)
750 Random number generator B35 Symbol lottery means (random number extraction means)
B51 Random number clock generation circuit (random number clock generation means)
B71 First latch signal output circuit (first latch signal output means, latch signal output means)
B72 Second latch signal output circuit (second latch signal output means, latch signal output means)
B73 Third latch signal output circuit (second latch signal output means, latch signal output means)
B81 First clock count circuit (random number counting means)
B82 Second clock count circuit (random number counting means)
B83 Third clock count circuit (random number counting means)
B84 Fourth clock count circuit (random number counting means)
B91 First count value storage circuit (first count value storage means, count value storage means)
B92 Second count value storage circuit (second count value storage means, count value storage means)
B92a High-order storage circuit (second count value storage means, count value storage means)
B92b Lower storage circuit (second count value storage means, count value storage means)
PM Pachinko machine (ball game machine)

Claims (2)

A game board, a first starter , a second starter and a third starter mounted on the game board, and the first , second and third starters provided to each starter The signal detection means for detecting the winning or falling of the hit ball and outputting a detection signal, and the symbols are displayed in a variable manner based on the detection of the winning or hit of the hit ball by the signal detecting means provided on the game board A random number clock generating means for generating a clock at a predetermined frequency, a random number counting means for counting a random number consisting of a plurality of digits based on the clock generated by the random number clock generating means, and the signal detection Latch signal output means for outputting a latch signal in response to an input of a detection signal from the means, and counting by the random number counting means based on the latch signal output from the latch signal output means. A count value storage means for storing the counted count value, and a random number extraction means for extracting one count value from the count values stored in the count value storage means, and an extraction result by the random number extraction means A ball game machine for stopping the display of the variation of the symbol in the symbol display device,
The latch signal output means outputs a latch signal in response to an input of a detection signal from the signal detection means provided in the first starter, and the second starter A second latch signal output means for outputting a latch signal in response to an input of a detection signal from the signal detection means provided in the signal detector, and a detection signal from the signal detection means provided in the third starter. A third latch signal output means for outputting a latch signal in response to an input ;
The count value memory unit, the first count value storing means for storing a count value using all the digits of the first of said random number counting means based on the latch signal output from the latch signal output means, said first A second count value storage means for storing a count value using a part of digits of the random number counting means based on a latch signal output from the second latch signal output means; and a third latch signal output means. A third count value storage means for storing a count value using other digits of the random number counting means based on the output latch signal;
A ball game machine characterized in that different random numbers are stored in the first, second and third count value storage means from the count value counted by the same random number counting means. . The partial digit is an odd-numbered digit among all the digits consisting of a plurality of digits,
2. The ball game machine according to claim 1, wherein the other part of the digits is an even-numbered digit among all the digits composed of a plurality of digits.

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