JP4497462B2 - Wafer transfer controller applicable to equipment model - Google Patents

Description

The present invention relates to a wafer transfer controller that controls transfer of a silicon wafer in a semiconductor manufacturing apparatus, and more particularly to an apparatus model application type wafer transfer controller in which each control process is arranged around a shared memory and a transfer portion of a semiconductor manufacturing apparatus is modeled. About.

In a conventional wafer transfer controller, a control program is constructed according to the configuration of transfer equipment such as a transfer robot.
FIG. 6 is a block diagram showing a conventional wafer transfer controller.
In FIG. 6, 61 is a wafer transfer controller, 62 is a host processing device, 63 is an online host communication processing unit, 64 is a GUI (Graphical User Interface) processing unit, 65 is a transfer sequence processing unit, 66 is a transfer robot control processing unit, 67 is an I / O control processing unit, and 68 is a transport device group.
Hereinafter, the configuration of a conventional wafer transfer controller will be described with reference to FIG.
The wafer transfer controller 61 includes an online host communication processing unit 63, a GUI processing unit 64, a transfer sequence processing unit 65, a transfer robot control processing unit 66, and an I / O control processing unit 67. The transporting device group 68 is controlled based on the command from. Each processing unit 63, 64, 65, 66, 67 is constructed according to the transport specification of the semiconductor manufacturing apparatus.
Information is transferred between the processing units for transport control, and the information is transmitted via the shared memory so that the transport control can be performed efficiently. As for the method of handling the shared memory, it has been considered that exclusive processing is performed between processors to realize efficient sharing of the shared memory (for example, see Patent Document 1).
As described above, the conventional wafer transfer controller can perform information processing efficiently.
Japanese Examined Patent Publication No. 6-42231 (page 4-6, FIG. 1)

However, in a system such as a wafer transfer controller using a conventional shared memory, functional division, information flow, and exclusion are realized mainly for efficient control processing and information processing. However, there is a problem that it is difficult to divert and divert to a similar system because each control process and information structure must be reviewed.
The present invention has been made in view of such problems, and can be diverted to a similar system or diverted without revising each control process or changing the information structure even if a part of the control target is changed. An object of the present invention is to provide an apparatus model application type wafer transfer controller.

In order to solve the above problem, the invention according to claim 1 is directed to a carrier for inserting and transferring a wafer, a carrier controller for controlling the carrier, and a wafer from the carrier to a specified point in a process chamber. A wafer transfer robot for transferring the wafer, a robot controller for controlling the wafer transfer robot, I / O equipment related to wafer transfer, the carrier controller, the robot controller, and the I / O equipment. A wafer transfer controller comprising: a wafer transfer controller for controlling the wafer transfer controller, wherein the wafer transfer controller performs communication control with a shared memory for storing information related to wafer transfer control and a host device, and sends a transfer request to the shared memory. Online communication means for recording and the shared memory A transfer sequence processing means for writing a robot command and a carrier command in the shared memory and executing a specific sequence using the transfer request recorded in the memory as a trigger; and the wafer transfer controller recorded in the shared memory A carrier state display means for displaying the state of the carrier, a carrier for acquiring the carrier command from the shared memory, transmitting it to the carrier controller, and recording an event notification from the carrier controller in the shared memory From the control unit, a wafer transfer robot control unit for acquiring the robot command from the shared memory and transmitting it to the robot controller, and recording an event notification from the robot controller in the shared memory; Above I / O control means for reading I / O contact information of the / O device and reflecting the updated information of the I / O contact, the online host communication means, the transfer sequence processing means, the transfer The status display means, the carrier control means, the wafer transfer robot control means, and the I / O control means are characterized by being independent from each other and capable of accessing only the shared memory.
Further, in the invention described in claim 2, the shared memory defines a wafer transfer device model in which the features of the apparatus and the device for transferring the wafer are extracted, and transfer position information, robot commands and carriers assumed from this model. It is characterized by having, as virtual information, drive command information such as control commands, wafer state information, I / O equipment and wafer transfer equipment state information.
According to a third aspect of the present invention, the online host communication unit, the transfer sequence processing unit, the transfer state display unit, the carrier control unit, the wafer transfer robot control unit, and the I / O control unit The virtual information defined in the shared memory is used to perform sequence processing and information management for wafer transfer.
According to a fourth aspect of the present invention, the wafer transfer controller converts the virtual information of the robot command defined in the shared memory into a robot command for instructing an actual wafer transfer robot. It is characterized by having a robot command conversion table in which differences are set in advance.
The wafer transfer controller may convert the carrier control command virtual information defined in the shared memory into a carrier control command for instructing an actual carrier controller. The carrier command conversion table in which the difference is set in advance is provided.
According to a sixth aspect of the present invention, the wafer transfer controller converts the I / O information arrangement defined in the shared memory into an actual I / O information arrangement. An I / O map conversion table in which a difference in arrangement is set in advance is provided.
According to a seventh aspect of the present invention, the wafer transfer controller has a transfer position written to the shared memory for converting the teaching point to a transfer position that can be actually recognized by the wafer transfer robot. It is characterized by having a teaching point conversion table in which differences are set in advance.

According to the first aspect of the present invention, each control process is arranged around the shared memory, and each control process transfers information only to the shared memory. Independence of functions is improved, and functions can be easily added or changed without affecting other processes.
According to the second aspect of the invention, the structure of the wafer transfer device is modeled, and the information in the shared memory and the structure thereof are defined based on the model. Even when the position or order is changed, the transport specification can be realized without changing each control process and information structure.
According to the invention described in claim 3, since the virtual information defined in the shared memory is used to perform sequence processing and information management for wafer transfer, other transfer sequence additions and changes can be made. It can be easily realized without affecting the processing.
According to the invention of claim 4, since the difference between the virtual information defined on the shared memory and the information when actually communicating with the robot is absorbed, the model of the robot controller has been changed. Even in this case, it is possible to realize the transport specification without changing each control process and information structure.
Further, according to the invention of claim 5, since the difference between the virtual information defined on the shared memory and the information when actually communicating with the carrier controller is absorbed, the model of the carrier controller is changed. Even in this case, it is possible to realize the transport specification without changing each control process and information structure.
According to the invention of claim 6, since the difference between the I / O information arrangement defined on the shared memory and the actual I / O information arrangement is absorbed, the type or model of the I / O equipment Even when is changed, the transport specification can be realized without changing each control process and information structure.
According to the invention of claim 7, since the difference between the virtual transport position defined on the shared memory and the actual transport position is absorbed, each control can be performed even when the transport position is changed. Transport specifications can be realized without changing the processing and information structure.
As described above, according to the apparatus model-applied wafer transfer controller of the present invention, even if a part of the control target is changed, it is possible to divert or divert to a similar system without reviewing each control process or changing the information structure. Is possible.

  Hereinafter, specific examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an apparatus model application type wafer transfer controller of the present invention.
In FIG. 1, 1 is a wafer transfer controller, 2 is a shared memory, 3 is an online host communication processing unit, 4 is a transfer sequence processing unit, 5 is a GUI processing unit, 6 is a carrier control processing unit, and 7 is a transfer robot control processing unit. , 8 is an I / O control processing unit, 9 is a carrier command conversion table, 10 is a robot command conversion table, 11 is a teaching point conversion table, 12 is an I / O map conversion table, 13 is a carrier controller, 14 is a carrier, 15 Is a robot controller, 16 is a transfer robot, 17 is an I / O contact, and 18 is an I / O device.
The differences between the prior art and the present invention are as follows.
That is, in the conventional wafer transfer controller, transfer is performed between the online host communication processing unit 63, transfer sequence processing unit 65, GUI processing unit 64, transfer robot control processing unit 66, and I / O control processing unit 67. In contrast to the transfer of information for control, the apparatus model-applied wafer transfer controller 1 of the present invention has an online host communication processing unit 3, a transfer sequence processing unit 4, a GUI processing unit 5, a carrier control. A configuration in which the processing unit 6, the transfer robot control processing unit 7, and the I / O control processing unit 8 are arranged around the shared memory 2, and the processing units 3 to 8 are independent from each other and can exchange information only with the shared memory 2. Further, the apparatus model-applied wafer transfer controller 1 of the present invention is arranged outside and is provided with a FOUP (Front Openi). When communicating with the carrier controller 13, the robot controller 15, and the I / O contact 17 that controls the carrier 14, such as (ng Unifield Pod), the information name and position information defined in the shared memory 2 are actually transmitted and received. Comprising a carrier command conversion table 9, a robot command conversion table 10, a teaching point conversion table 11, and an I / O map conversion table 12 for absorbing the difference between the information name and the position information It is a point to be.

The functions of the processing units 3 to 8 of the apparatus model application type wafer transfer controller of the present invention will be described below with reference to FIG.
The online host communication processing unit 3 performs communication control with a computer (not shown) located above the wafer transfer controller 1 and records a transfer request in the shared memory 2 according to the contents of a command instructed by the upper computer. Further, the state of the wafer transfer controller 1 is read from the shared memory 2 and notified to the host computer.
The transport sequence processing unit 4 executes a specific sequence using the transport request recorded in the shared memory 2 as a trigger. When executing this specific sequence, for example, before sending a robot command to the robot controller 15, the state of the transfer robot 16 itself and the surrounding state of the transfer robot 16 are checked, and when all the conditions are satisfied. Write a command transmission request to the robot to the shared memory 2. Further, since the state of the transfer robot 16 itself and the surrounding state of the transfer robot 16 are recorded in the shared memory 2 by other processes in advance, the information is obtained from the shared memory 2.
The GUI processing unit 5 serves as a user interface for displaying the state of the wafer transfer controller 1 on a monitor or performing a manual operation.
The carrier control processing unit 6 is responsible for transmitting a carrier command to a carrier controller 13 that controls a device (for example, a load port) in which a carrier cassette or the like is installed. The carrier command written by the transport sequence processing unit 4 is acquired from the shared memory 2, converted into a carrier command to be actually transmitted using the carrier command conversion table 9, and then transmitted to the carrier controller 13. If there is an event notification from the carrier controller 13, the content is interpreted and recorded in the shared memory 2.
The transfer robot control processing unit 7 is responsible for transmitting robot commands to the robot controller 15. The robot command written by the transfer sequence processing unit 4 is acquired from the shared memory 2 and converted into a robot command to be actually transmitted using the robot command conversion table 10, and at the same time, the transfer position recorded in the shared memory 2 is actually Then, the command is transmitted to the robot controller 15 after conversion using the teaching point conversion table 11 to a position that the transfer robot 16 can recognize. If an event notification is received from the robot controller 15, the contents are interpreted and recorded in the shared memory 2.
The I / O control processing unit 8 updates the I / O contact 17 installed in the wafer transfer controller 1 or reflects the updated contents in the shared memory 2 when the I / O contact 17 is updated. Responsible for the role. Since the I / O arrangement defined in the shared memory 2 is fixed in the wafer transfer controller 1, the arrangement (address) is different from the actual I / O contact 17. Therefore, the difference is absorbed according to the contents of the predefined I / O map conversion table 12.

FIG. 2 is an explanatory view showing a semiconductor manufacturing apparatus model applied to the present invention.
In FIG. 2, 19 is an atmospheric chamber, 191, 192, 193, and 194 are carriers, and 195 is a wafer transfer robot. The atmospheric air that is taken out of the carrier in the atmospheric chamber 19 and is transferred to the trans chamber via the gate valve. A robot, 196 a buffer, 197 a position aligner, 198 a dummy cassette, 20 a transformer chamber, 201 a gate valve, and 202 a wafer transfer robot, a vacuum robot for transferring a wafer to a process chamber in the trans chamber 20, 203 , 204 is a buffer, 205 is a position aligner, 21, 22 and 23 are process chambers, 211, 221 and 231 are gate valves, and 212, 222 and 232 are points.
The details of the shared memory 2 will be described below with reference to FIG.
The information structure in the shared memory 2 is fixed in the wafer transfer controller 1, and the information type and information name are also general-purpose. In the model of the present embodiment, four carriers 191 to 194, an atmospheric chamber 19, a transformer chamber 20, and three process chambers 21 to 23 are included, and robots 195 and 202, position aligners 197 and 205, and a buffer 196 are included therein. , 203, 204, etc. are installed.
A general name is defined for each control device and position in the semiconductor manufacturing apparatus model shown in FIG. 2, and the defined name (hereinafter referred to as virtual information) is defined as it is in the shared memory 2.
Therefore, in the wafer transfer controller 1, each control process is performed using virtual information defined in the semiconductor manufacturing apparatus model shown in FIG. 2, and each information is directly transferred to and from the shared memory 2 defined by this model. The control processing unit is also constructed on the assumption of this virtual information.
FIG. 2 is an example for explaining the present invention. Needless to say, when an actual wafer transfer controller is constructed, a maximum model is defined in advance so that almost all cases can be covered. Yes.

FIG. 3 is an explanatory diagram showing a specific information structure example of the shared memory 2 of the present invention.
In FIG. 3, 2 is a shared memory, 301 is a system management information area, 302 is a transfer sequence processing request area, and 303 is a robot command information area.
As shown in FIG. 3, a system management information area 301, a transfer sequence information area 302, a robot command information area 303, etc. are recorded in the information structure, and virtual information defined by the model shown in FIG. 2 is used. Has been. Also, general-purpose name information (virtual information) such as “Carry” and “MOVE”, which is different from the command name for the actual transfer equipment, defined as the wafer transfer controller of the present invention is used.

FIG. 4 is a flowchart showing a processing example of the transport sequence processing unit 4 of the present invention.
Hereinafter, processing of the transport sequence processing unit 4 will be described with reference to FIG.
First, the presence / absence of a transport request in the shared memory 2 is checked (step ST41). If there is a transport request, the request content is read (step ST42). At this time, “Carry LP1 to P2” recorded in the transport sequence information area 302 is read. This is a command instructed to carry the wafer from the carrier 191 in FIG. 2 to the point 212 in the process chamber 21.
Next, the “Carry LP1 to P2” command is sequentially decomposed into robot commands “MOVE from LP1 to PA-1,” “MOVE from PA1 to GV1,” and the command can be transmitted to the robot. In this state, these robot commands “MOVE from LP1 to PA-1” and “MOVE from PA-1 to GV1” are written in the robot command information area 303 of the shared memory 2 (step ST43). Thereafter, steps ST41 to ST43 are repeated until the system ends (step ST44).

FIG. 5 is a flowchart showing a processing example of the transfer robot control processing unit 7 of the present invention.
In FIG. 5, 10 is a robot command conversion table, and 11 is a teaching point conversion table.
Hereinafter, processing of the transfer robot control processing unit 7 will be described with reference to FIG.
It is confirmed that the commands “MOVE from LP1 to PA-1” and “MOVE from PA-1 to GV1” have been written in the shared memory 2 (step ST51), and the command information is sequentially read by the robot command request reading process (step ST51). Step ST52).
From the read robot command “MOVE from LP1 to PA-1,” an actual robot command “WT TP1 TP6” is generated using the robot command conversion table 10 and teaching point conversion table 11 (step ST53).
Thereafter, the robot command “WT TP1 TP6” is transmitted to the robot controller 15 (step ST54). Thereafter, steps ST51 to ST54 are repeated until the system ends (step ST55).

As described above, the apparatus model application type wafer transfer controller according to the embodiment of the present invention includes the shared memory 2, the processing units 3 to 8, and the conversion tables 9 to 12, and the processing units 3 to 8 are mutually connected. Independently, the information can be exchanged only with the shared memory 2. Further, the shared memory 2 models the transport part of the semiconductor manufacturing apparatus, and general-purpose information and its information structure are stored on the shared memory 2 based on the model. Therefore, for example, even when the model of the robot controller 15 is changed and the teaching point is also changed at the same time, the wafer transfer controller 1 only includes the contents of the robot command conversion table 10 and the teaching point conversion table 11. The transfer sequence processing unit 4, the transfer robot control processing unit 7, and the shared memory 2 may be changed. It is possible to cope with without changing the information structure and information type.
Further, in the actual apparatus, even when the wafer is transferred to “PA-1”, even when the transfer specification is changed to a transfer specification in which a transit point is added on the way, the buffer 196 defined in the model of FIG. By changing a part of the processing of the transport sequence processing unit 4 and additionally newly defining an actual teaching number for the buffer 196 in the teaching point conversion table 11, it is possible to easily cope with the changed transport specifications. It is.

  In the present invention, the wafer transfer of the semiconductor manufacturing apparatus is described as an example. However, if the structure of the transfer apparatus and the transfer pattern are characteristic and the apparatus can be modeled as shown in FIG. The present invention can also be applied to other transfer devices.

The block diagram which shows the apparatus model application type wafer conveyance controller of this invention Explanatory drawing showing a semiconductor manufacturing apparatus model applied to the present invention Explanatory drawing which shows the specific information structure example of the shared memory 2 of this invention The flowchart which shows the process example of the conveyance sequence process part 4 of this invention. The flowchart which shows the process example of the conveyance robot control processing part 7 of this invention. Block diagram showing a prior art wafer transfer controller

Explanation of symbols

1, 61 Wafer transfer controller 2 Shared memory 3, 63 Online host communication processing unit 4, 65 Transfer sequence processing unit 5, 64 GUI processing unit 6, Carrier control processing unit 7, 66 Transfer robot control processing unit 8, 67 I / O control Processing unit 9 Carrier command conversion table 10 Robot command conversion table 11 Teaching point conversion table 12 I / O map conversion table 13 Carrier controller 14 Carrier 15 Robot controller 16 Transport robot 17 I / O contact 18 I / O device 19 Atmosphere chamber 191, 192, 193, 194 Carrier 195 Atmospheric robot 196 Buffer 197 Position aligner 198 Dummy cassette 20 Transformer chamber 201 Gate valve 202 Vacuum robot 203, 204 Buffer 205 Position aligner 21 22,23 process chamber 211, 221, 231 a gate valve 212, 222, 232 point 301 system management information area 302 transfer sequence processing request area 303 robot command information area 62 host processing apparatus 68 conveying apparatus group

Claims (7)

A carrier (14) for inserting and transferring a wafer;
A carrier controller (13) for controlling the carrier (14);
A wafer transfer robot (16) for transferring a wafer from the carrier (14) to a designated point in the process chamber (21, 22, 23);
A robot controller (15) for controlling the wafer transfer robot (16);
I / O equipment (18) related to wafer transfer;
A wafer transfer apparatus comprising: a carrier transfer controller (1) that performs overall control of the carrier controller (13), the robot controller (15), and the I / O device (18);
The wafer transfer controller (1)
A shared memory (2) for storing information relating to wafer transfer control;
Online communication means (3) for performing communication control with the host device and recording the transport request in the shared memory (2);
A transfer sequence processing means (4) for writing a robot command and a carrier command in the shared memory (2) and executing a specific sequence using the transfer request recorded in the shared memory (2) as a trigger; ,
A transfer state display means (5) for monitoring and displaying the state of the wafer transfer controller (1) recorded in the shared memory (2);
Carrier control means for acquiring the carrier command from the shared memory (2), transmitting the carrier command to the carrier controller (13), and recording an event notification from the carrier controller (13) in the shared memory (2) (6) and
A wafer transfer robot for acquiring the robot command from the shared memory (2) and transmitting it to the robot controller (15) and recording an event notification from the robot controller (15) in the shared memory (2) Control means (7);
I / O control means (8) for reading I / O contact (17) information of the I / O device (18) from the shared memory (2) and reflecting update information of the I / O contact (17) ) And
The online host communication means (3), the transfer sequence processing means (4), the transfer state display means (5), the carrier control means (6), the wafer transfer robot control means (7), and the I / O The apparatus model application type wafer transfer controller, wherein the control means (8) is independent from each other and can access only the shared memory (2). The shared memory (2)
Define a wafer transfer equipment model that extracts the features of the equipment and equipment to transfer the wafer, and transfer position information assumed from this model, drive command information such as robot commands and carrier control commands, wafer status information, I / O 2. The apparatus model-applied wafer transfer controller according to claim 1, wherein status information of the O device and the wafer transfer device is included as virtual information. The online host communication means (3), the transfer sequence processing means (4), the transfer state display means (5), the carrier control means (6), the wafer transfer robot control means (7), and the I / O The control means (8)
The apparatus model-applied wafer transfer controller according to claim 2, wherein the virtual information defined in the shared memory (2) is used to perform sequence processing and information management for wafer transfer. The wafer transfer controller (1)
A robot command conversion table (a robot command conversion table in which differences between the robot commands are set in advance to convert the virtual information of the robot commands defined in the shared memory (2) into robot commands to be instructed to the actual wafer transfer robot (16). 10. The apparatus model application type wafer transfer controller according to claim 2, further comprising: 10). The wafer transfer controller (1)
A carrier command conversion table in which the difference of the carrier control command is set in advance for converting the virtual information of the carrier control command defined in the shared memory (2) into a carrier control command for instructing the actual carrier controller (13). The apparatus model-applied wafer transfer controller according to claim 2, further comprising (9). The wafer transfer controller (1)
An I / O map conversion table in which a difference in the arrangement of the I / O information for converting the arrangement of the I / O information defined in the shared memory (2) into an actual arrangement of the I / O information is set in advance. The apparatus model-applied wafer transfer controller according to claim 2, further comprising (12). The wafer transfer controller (1)
A teaching point conversion table (in which the transfer position difference is set in advance for converting the transfer position written in the shared memory (2) into a transfer position that can be actually recognized by the wafer transfer robot (16)). 11. The apparatus model application type wafer transfer controller according to claim 2, further comprising: 11).

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