JP4500849B2 - Solid-state imaging device for AEAF - Google Patents

Description

  The present invention relates to an AEAF solid-state imaging device, and more particularly to an external measurement type autofocus sensor used in a compact camera in an autofocus solid-state imaging device having an AE function.

  2. Description of the Related Art Conventionally, as an AF (Auto Focus) sensor equipped with an AE (Auto Exposure) function, an automatic AE device for an imaging device (see, for example, Patent Document 1) is known. A circuit configuration diagram of this apparatus is shown in FIG.

  In FIG. 14, 30 is an AE circuit, 31 is a standard CCD, 32 is a reference CCD, 33 is a photoelectric conversion circuit, 34 is an integration time control circuit, 35 and 36 are comparison circuits, 37 is an AF counter circuit, and 38 is an AE. A counter circuit, 42 and 43 are output selection circuits, 44 and 45 are amplifiers, 46 is a correlation calculation circuit, 47 is an AD converter, 48 is a main control circuit, and 49 is a microcomputer.

  In this apparatus, a pair of linear sensors (a standard part CCD 31 and a reference part CCD 32) that are arranged on a single semiconductor chip at a predetermined distance and are suitable for performing AF, and electric charges accumulated in the pair of linear sensors. An integration time control means (integration time control circuit 34) for detecting an amount and generating an integration control signal for controlling charge accumulation due to light incidence, and a first for calculating the intensity of incident light from the integration control means. Exposure amount detection means (AF counter circuit 37, main control circuit 48, microcomputer 49) and photoelectric conversion elements arranged on the same semiconductor chip, and second exposure amount detection means (photoelectricity) for detecting the amount of incident light The exposure amount is determined using a conversion circuit 33, a comparison circuit 36, an AE counter circuit 38, a main control circuit 48, and a microcomputer 49).

According to the above apparatus, AF is performed by a pair of linear sensors (standard CCD 31 and reference CCD 32), exposure data for a main subject is obtained, and a photoelectric conversion element (photoelectric conversion circuit 33) formed on the same semiconductor chip is used. It is possible to obtain exposure data for the entire field of view including the background. By using both exposure data, fine exposure information can be obtained. For example, by combining exposure data for the main subject and exposure data for the entire field of view, it is possible to synchronize during the day and slow, and to select an appropriate exposure amount for the main subject during backlighting. Become.
JP-A-5-158107 JP 2000-180706 A

  Recently, microcomputers with built-in AD converters have become mainstream in compact cameras due to high performance, multi-functionality, and low price of microcomputers. For this reason, if there is an on-chip AD converter in the AF sensor and the AE sensor, problems such as the chip size cannot be reduced and the cost cannot be reduced occur.

  However, the above-described conventional example is an AEAF sensor suitable for a microcomputer that does not incorporate a previous AD converter, and is no longer suitable for a recent microcomputer that incorporates an AD converter. Further, since the counter circuits 37 and 38 and the correlation operation circuit 46 are also required, there is a great disadvantage that the chip size cannot be reduced.

  Further, in the above conventional example, since the integration control signal from the integration time control means is used, the exposure control time varies depending on the luminance of the subject. For this reason, when the amount of light is very weak, it takes time for the comparator of the integration control means to invert, so that the time until exposure is determined becomes very long. This greatly deteriorated the response of the camera, and as a result, the camera was very inconvenient for the photographer.

  In addition, since the CCD is used as the linear sensor for AF, the matching with the CMOS digital circuit is not good, so that the manufacturing process is complicated and the manufacturing cost is increased.

  The present invention has been made in consideration of the above problems, and a first object of the invention is to realize an AEAF solid-state imaging device equipped with a spot AE function suitable for a microcomputer incorporating an AD converter.

  The second object of the present invention is to improve the AE accuracy and the operation speed in the solid-state imaging device for AEAF.

  A third object of the present invention is to realize an AEAF solid-state imaging device having a small chip size and a low-cost spot AE function.

In order to achieve the above object, an AEAF solid-state imaging device according to the present invention includes an AF photoelectric conversion element array and a voltage monitoring unit that outputs a voltage signal corresponding to the amount of charge accumulated in the AF photoelectric conversion element array. And a first exposure amount detection means that includes a photoelectric conversion element for AE and outputs a signal photoelectrically converted by the photoelectric conversion element for AE as a first exposure amount detection signal, on the same semiconductor substrate. The formed AEAF solid-state imaging device includes second exposure amount detection means for outputting a monitor signal for auto gain control outputted from the AF photoelectric conversion element array as a second exposure amount detection signal. , the monitoring signal is output in real time by non-destructive readout, the second exposure amount detecting means, the second exposure amount detection after signal outputs of the photoelectric conversion element array for AF when focused The AF photoelectric conversion element and the AE photoelectric conversion element are PN junction photodiodes, and the P-type impurity layer and the N-type impurity layer forming the photodiode have the same impurity concentration and junction depth. It is characterized by being.

  Preferably, the AF photoelectric conversion element array, the voltage monitoring unit, and the second exposure amount detection unit are mounted on an AF sensor for AF, and the AE photoelectric conversion element and the first exposure amount are mounted. The detection means is mounted on an AE sensor (hereinafter referred to as “wide AE sensor” as necessary) for performing AE over almost the entire imaging region. In this case, the second exposure amount detection signal is a spot AE signal (exposure amount detection signal for the main subject) that also serves as an AGC (auto gain control) output of the AF sensor, and the first exposure amount detection. The use signal is preferably a wide AE signal of the wide AE sensor (exposure amount detection signal for the entire visual field including the main subject). In this configuration, for example, the following modes are possible.

  In the first aspect, an AF sensor for AF and a dedicated wide AE sensor for performing AE in almost the entire imaging region are provided on the same semiconductor substrate, and the photodiode of the photodiode during the accumulation period of the AF sensor is provided. The voltage monitor signal can be output to the AD converter of the microcomputer as an AE signal for spot AE. According to this, it is possible to realize an AEAF solid-state imaging device capable of performing spot AE suitable for a microcomputer with a built-in AD converter. In addition, since a dedicated spot AE sensor, which has been generally used in the past, is not required in a separate chip, it is possible to reduce the size and power consumption of the system.

  The second aspect is characterized in that real-time AGC and spot AE can be performed simultaneously by using an amplification type photoelectric conversion element capable of nondestructive readout as an AF sensor. According to this, since the accumulation time control and the spot AE output operation can be performed at the same time, an AEAF solid-state imaging device compatible with high-speed driving can be realized.

  The third aspect is characterized in that the spectral sensitivity characteristics of the AE sensor for wide AE and the AF sensor for performing spot AE are the same. Here, "same" means that the difference between the exposure value from the AE sensor and the exposure value from the AF sensor is within 0.3 EV (Exposure Value: exposure index). According to this, since the color temperature dependence of the spot AE and the wide AE can be reduced, the exposure accuracy can be improved.

  The fourth aspect is characterized in that the AE sensor for whole AE has a logarithmically compressed output of photocurrent, and the AGC signal for spot AE has a linear output. According to this, an AEAF solid-state imaging device with an expanded AE range can be realized by expanding a dynamic range by logarithmic compression of photocurrent.

  A fifth aspect is characterized by an AF sensor and an AE sensor that can be manufactured by a CMOS process. According to this, a low-cost AEAF solid-state imaging device can be realized by reducing the number of masks by the CMOS process and simplifying the manufacturing process.

  As described above, according to the present invention, the spot AE function suitable for the microcomputer with the built-in AD converter is mounted, the AE accuracy and the operation speed are improved, the chip size is small, and the low-cost spot AE function is provided. The mounted AEAF solid-state imaging device can be realized. That is, a solid-state imaging device having high-performance AE performance and AF performance can be realized with one chip. For this reason, in a lens shutter compact camera using the present invention, it is possible to realize a reduction in size, performance and price of the camera. Similar effects can be expected not only in compact analog (silver salt) cameras but also in imaging devices such as compact digital cameras.

  Embodiments of an AEAF solid-state imaging device according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic circuit block diagram of an AEAF solid-state imaging device according to the present embodiment, which best illustrates the features of the present invention. FIG. 2 is a schematic plan layout diagram for explaining the arrangement of AF sensor blocks, AE sensor blocks, analog circuits, and digital blocks, which will be described later, constituting this apparatus.

  1 and 2, 100 is a Si semiconductor substrate, 101 is an AF sensor block formed on the semiconductor substrate 100 (of the photoelectric conversion element array for AF, voltage monitoring means, and second exposure amount detection means of the present invention). Reference numeral 102 denotes an AE sensor block (which forms a main part of the first exposure amount detection means including the AE photoelectric conversion element of the present invention) formed on the same semiconductor substrate 100.

  Reference numeral 104 denotes a multiplexer (MPX), and 107 denotes a logic circuit, both of which form a digital block formed on the semiconductor substrate 100. Further, 103 is a thermometer circuit, 105 is an auto gain control (AGC) circuit, 106 is a power supply circuit, and 108 is a signal amplifier circuit, and these circuits constitute an analog circuit formed on the semiconductor substrate 100.

  Reference numeral 109 denotes a microcomputer (112 is an ADC) built in an AD converter (ADC), which exchanges digital signals such as various control signals bidirectionally with the logic circuit 107 on the Si semiconductor substrate 100, and also the Si semiconductor substrate. AF signal and AE signal described later sent via MPX 104 on 100 (wide AE signal corresponding to the first exposure amount detection signal of the present invention: exposure amount detection signal for the entire visual field including the main subject) , Analog signals such as a maximum value signal (voltage monitor signal used as the second exposure amount detection signal of the present invention (spot AE signal in this example: a spot exposure amount detection signal for the main subject)) are converted into digital signals by the ADC 112. It can be input after being converted to.

  Hereinafter, an AF sensor block 101 (hereinafter referred to as “AF sensor” as necessary), an AE sensor block 102 (hereinafter referred to as “AE sensor” or “wide AE sensor” as necessary), an analog circuit, The internal configuration will be described in the order of digital blocks.

(AF sensor block)
In the AF sensor block 101, a pair of linear sensor circuits forming a phase difference detection type AF sensor circuit 110, that is, a pair of reference units as shown in FIG. The AF circuit 110A and the reference unit AF circuit 110B are arranged on the semiconductor substrate 100 with a predetermined distance therebetween. The pair of reference portion AF circuit 110A and reference portion AF circuit 110B include a driving circuit that combines the photodiode forming the AF photoelectric converter array of the present invention and the voltage monitor means and second exposure amount detection means of the present invention. , A detection circuit, and a shift register. In the example of FIG. 1 and FIG. 2, the pairs of the linear sensor circuits are respectively arranged in three rows (in the example of FIG. 2, the rows 1A, 2A, and 3A of the reference portion AF circuit (the left side in the drawing), Reference section AF circuit columns 1B, 2B, and 2C (the right side in the figure form a pair).

  An AF imaging lens (see FIG. 13 to be described later) is provided on the photodiode of each linear sensor circuit (the reference unit AF circuit 110A and the reference unit AF circuit 110B). An image is formed on a photodiode of each linear sensor circuit through a lens. The distance to the subject is calculated from the imaging position on the photodiode of each linear sensor circuit, the focal length of the imaging lens, and the interval (baseline length) of the imaging lens.

  FIG. 3 shows an example of the linear sensor circuits 110A and 110B. In this example, a circuit of a CMOS linear AF sensor (for example, see Patent Document 2) previously proposed by the present applicant is applied.

  In FIG. 3, 1 is a pn junction photodiode that performs photoelectric conversion, 2 is a reset MOS transistor that resets the potential of the photodiode 1 to a reference potential (VRES) (φRES is a reset control signal), and 3 is a differential amplifier (Sensor amplifier) 1 to 3 constitute an amplifying photoelectric conversion element. A minimum value detection circuit and a maximum value detection circuit are connected in parallel to the output side of the differential amplifier 3 of the amplification type photoelectric conversion element.

  In the minimum value detection circuit and the maximum value detection circuit, 4 is a clamp capacitor, 5 is a MOS switch (φGR is an on / off control signal) for inputting a clamp potential (VGR), and 4 and 5 are clamp circuits (feedback type). Noise elimination circuit). Reference numerals 6 to 9 denote switching MOS transistors (φGR, φS1, φN1, φN2, and φS2 are on / off control signals), 10 is a differential amplifier for detecting a minimum value, and 11 is a differential amplifier for detecting a maximum value. The differential amplifiers 10 and 11 constitute a voltage follower circuit. Reference numeral 12 denotes a minimum value output MOS switch (φBTM is an on / off control signal), and 13 is a maximum value output MOS switch (φPEAK is an on / off control signal). A plurality of AF sensor units composed of the above 1 to 13 are arranged for each photodiode 1.

  Further, 14 is an OR circuit, 15 is a scanning circuit, 16 and 17 are constant current MOS transistors (φREF1 and φREF2 are on / off control signals). For the minimum value detection circuit, the final stage is an NMOS source follower circuit, and for the maximum value detection circuit, the final stage is a PMOS source follower circuit. Reference numeral 18 denotes a common output line for outputting a signal from the pixel.

  In this circuit configuration, by providing a feedback type noise clamp circuit (noise removal circuit) in front of the maximum value detection circuit and minimum value detection circuit, reset noise generated by the photodiode, sensor amplifier, maximum value detection circuit, FPN (Fixed Pattern Noise) generated in the minimum value detection circuit can be removed.

  In addition, a voltage follower circuit in which the final output stage is a source follower type is configured for each pixel, and at the time of minimum value output, the constant current source at the output stage of each voltage follower circuit is turned off, and the output connected to the constant current source By connecting the lines in common, the maximum value of the video signal can be obtained. Further, when outputting a video signal, a serial video signal can be obtained by turning on the constant current source at the output stage of each voltage follower circuit and sequentially connecting each voltage follower circuit to the output line. By this operation, the maximum value detection circuit and the signal output circuit can be used together, so that the chip can be miniaturized.

  The AF signal obtained by the signal output circuit also used as the maximum value detection circuit is amplified by the signal amplification circuit 108 and output to the ADC 112 of the microcomputer 109 via the MPX 104. The maximum value signal detected by the maximum value detection circuit is output to the AGC circuit 105 as an AGC voltage monitor signal, and is also output to the ADC 112 of the microcomputer 109 via the MPX 104 as a spot AE signal during AE. The

(AE circuit block)
As shown in FIG. 1, the AE circuit block 102 includes an AE circuit 121 (a PN junction photodiode forming an AE photoelectric conversion element of the present invention and a logarithmic compression forming the main part of the first exposure amount detecting means of the present invention. Type current-voltage conversion circuit), an Is compensation circuit 122, and a signal amplification circuit 123. 4 is a circuit diagram showing a PN junction photodiode and a logarithmic compression type current-voltage conversion circuit in the AE circuit 122.

In FIG. 4, 20 is a CMOS differential amplifier, 21 is a PN junction photodiode (PD), 22 is a PN junction diode, and 23 is an output MOS switch (φH _AE is an on / off control signal). As shown in FIG. 4, since the potential across the PN junction photodiode 21 becomes the reference potential (Vc), the potential across the PN junction photodiode 21 is in a zero bias state. Therefore, since the spread of the depletion layer is suppressed, generation of dark current from the depletion layer can be suppressed. The photocurrent generated in the photodiode 21 flows through the PN junction diode 22 to be converted into current and voltage. At this time, a logarithmic conversion output (V _out ) according to the following equation is performed according to the current-voltage characteristics of the diode.

ここで、ｋはボルツマン定数、Ｔは絶対温度、ｑは素電荷量、Ｉ_Ｐは光電流、Ｉｓはダイオードの逆方向飽和電流である。この式により、ＩｓがばらつくとＡＥ特性もばらつくことが理解できる。従って、ＡＥ特性のばらつきを抑えるためには、Ｉｓ補償回路１２２が必須となる。

Here, k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge quantity, I _P is the photocurrent, Is is the reverse saturation current of the diode. From this equation, it can be understood that AE characteristics also vary when Is varies. Therefore, the Is compensation circuit 122 is indispensable in order to suppress variations in AE characteristics.

The output (V _out ) of the AE circuit 121 is output at a predetermined timing via the output MOS switch 23, its Is is compensated by the Is compensation circuit 122, amplified by the signal amplification circuit 123, and the AE signal ( Wide AE signal) is sent to the ADC 112 of the external microcomputer 109 via the MPX 104.

(Analog circuit)
The analog circuit generates a reference potential and an auto gain control (AGC) circuit 105 for controlling the accumulation time of the AF sensor circuit 110 (the reference unit AF circuit 110A and the reference unit AF circuit 110B) of the AF circuit block 101. Power supply circuit 106 for generating an intermediate potential (reference potential VRES, Vc, clamp potential VGR, etc.) necessary for a band gap circuit and a sensor circuit, and an AF signal from the AF circuit block 101 to be output to the outside A signal amplifying circuit 108 for monitoring the temperature of the semiconductor substrate 100, and a thermometer circuit 103 for monitoring the temperature of the semiconductor substrate 100.

  Here, FIG. 5A shows a circuit diagram of the AGC circuit 105, and FIG. 5B shows an operation explanatory diagram thereof. In FIG. 5A, 25 is a buffer amplifier, and 26 is a comparator.

  The operation of the AGC circuit 105 will be described. First, as described above, when light is irradiated to the photodiode of the AF sensor circuit 110, electrons are accumulated in the photodiode. Accordingly, the signal input to the buffer amplifier 25 of the AGC circuit 105 has a smaller output voltage as a PEAK signal (monitor signal). When this PEAK signal becomes smaller than the comparator potential (VREF) of the comparator 26 as time elapses, as shown in FIG. 5B, the accumulation determination signal which is the comparator output to the logic circuit 107 changes from the logic low level to the high level. At this point, the accumulation operation of the AF sensor circuit 110 ends. Control relating to this series of accumulation operations is performed by an accumulation control pulse (φCH) output from the logic circuit 107 to the AF sensor circuit 110.

(Digital block)
The digital block includes driving pulses for driving the AF circuit block 102 (AF sensor circuit 110), the AE circuit block 102, the digital block, and the analog system circuit at a predetermined timing (shift register driving pulses φHs and φH in FIG. 1 and accumulation). A logic circuit 107 including a timing generation circuit (T / G) for generating a control pulse φCH and the like and a communication circuit (I / O) for communicating with the external microcomputer 109, and a microcomputer for selecting each signal. And a multiplexer (MPX) 104 for outputting to an AD converter 112 built in 109.

  According to the above configuration, based on the control signal from the logic circuit 107, the MPX 104 causes a plurality of analog signals, that is, a spot AE signal (maximum value signal), which is a voltage monitor signal for AGC from the AF circuit block 102, and AE. It is possible to read out the entire AE signal (wide AE signal) from the circuit block 102, the AF signal from the AF circuit block 102, and the temperature signal from the thermometer circuit 103 with one line output.

  Next, the operation of the AEAF solid-state imaging device of the present embodiment will be described with reference to the operation flowchart of FIG. This operation is controlled by processing of the logic circuit 107 based on a control signal (digital signal) related to operation control from the microcomputer 109.

  In FIG. 6, after the power is turned on and each circuit is initialized (steps St1 and St2), accumulation of photocharges by the AF sensor (AF circuit block 101) is started (step St3). Simultaneously with the start of photocharge accumulation by the AF sensor, the operation of the wide AE sensor (AE circuit block 102) (reading of the wide AE signal) is started (step St4).

  During the accumulation period of the AF sensor, the maximum potential of the photodiode is monitored in real time. After a predetermined accumulation time has elapsed, the MPX 104 sequentially outputs the maximum value signal, which is an AGC monitor signal of each AF sensor, to the AD converter 112 of the microcomputer 109 as a spot AE signal (step St5). Here, it is desirable that the predetermined accumulation time is set to a value that does not saturate the AF sensor with high brightness (about EV18).

  Even after reading out the spot AE signal, real-time monitoring by the AF sensor circuit 110 is continued. This is made possible by using a CMOS type amplification sensor capable of nondestructive readout in the present embodiment as an AF sensor. The accumulation operation is performed until the maximum value monitor signal of the AF sensor circuit 110 described above exceeds the reference potential of the AGC circuit 105 (the comparator signal (accumulation determination signal) from the comparator 26 in FIG. 5 is inverted). This is continued until the maximum accumulation time set in the system is reached (steps St6 and St7).

  Then, after the accumulation operation is completed, the AF signal is read out as in the conventional case (steps St8 and St9). After the reading of the AF sensor is completed, it is preferable that the bias of the AF sensor is cut to make the circuit non-operating in order to reduce power consumption.

  Thereafter, a logarithmic compression signal (wide AE signal) is output from the AE circuit block 102 (wide AE sensor). Finally, temperature signal output for dark current variation correction of the AF sensor signal and gain correction of the AE sensor signal is performed (step St10).

  After performing the above series of AE, AF, and temperature detection operations (steps St1 to St10), the power is turned off to end the sensor operation (step St11). Here, the temperature signal does not necessarily need to be read every time, and may be read at an arbitrary timing. The temperature signal may be read out before the AF signal is output.

  With the circuit format and operation sequence of this embodiment, spot AE and wide AE can be performed without the need for a multi-segment AE sensor. That is, according to the present embodiment, an AGC operation using nondestructive readout of a CMOS AF sensor is performed, and the AGC output is also used as a spot AE signal, and a logarithmic compression AE sensor for wide AE is provided on the same substrate. Since the backlight detection is performed by comparing the wide AE signal and the spot AE signal, it is possible to realize an AE-equipped AF sensor capable of detecting backlight without requiring multi-segment AE.

  In addition, by using the AGC monitor signal of the AF sensor as the spot AE signal, it is possible to prevent an increase in circuit scale and a decrease in operation speed, which are problems in the conventional example. That is, in addition to the above effects, it is possible to realize an AE function having a good response and a high dynamic range at the same time.

  FIG. 7 is a schematic cross-sectional structure diagram of the AEAF solid-state imaging device according to the present embodiment. In FIG. 7, 71 is an N-type Si substrate, 72 is an N− type epitaxial (Epi) layer, 73 is a PWL (P well), 74 is an NWL (N well), and 75 is an N + type impurity layer (N + diffusion layer). The PWL 73 and the N + impurity layer 75 form a PN junction photodiode.

  Further, 76 is a gate oxide film, 77 is a thick oxide film (LOCOS) which is an element isolation region, 78 is a POL wiring also serving as a gate of a MOS transistor, 79 is an interlayer insulating film (interlayer film), 80 is an AL wiring, and 82 is An AL film (light shielding layer) 83 serving as a light shielding film, and a SiON film (surface protective layer) 83 serving as a surface protective film.

Here, the impurity concentration of PWL73 is 1 × 10 ¹⁶ to 10 ¹⁷ cm ⁻³ , the junction depth is 1 to 2 μm, and the impurity concentration of the N + -type impurity layer 75 is 1 × 10 ¹⁸ to 10 ²⁰ cm ⁻³ . The junction depth is 0.2 to 0.3 μm.

  By making the photodiodes of the AE sensor and the AF sensor have the same structure as in the present embodiment, it is possible to achieve spectral sensitivity characteristics such that the difference in exposure value is within 0.3 EV.

  Since the spectral sensitivity characteristic of the sensor in this embodiment is substantially determined by the junction depth of the PWL, the PWL potential of the photodiode of the AE sensor and the PWL potential of the photodiode of the AF sensor do not necessarily have to be the same. In order to optimize this, another potential may be used. For example, in the solid-state imaging device of this embodiment, the PWL potential of the AF sensor is set to the GND level, and the PWL potential of the AE sensor is set to the reference potential Vc. This is effective in operating the operational amplifier in a good operating region by setting the input potential of the operational amplifier to Vc instead of GND.

  FIG. 8 shows spectral sensitivity characteristics of the AF sensor and the AE sensor in the present embodiment. Since both sensors have different well potentials, they have characteristics that can be sufficiently realized for an exposure error of 0.3 EV, although there is a slight difference in spectral sensitivity. Thus, exposure errors can be reduced by setting the AE sensor and the AF sensor to the same spectral sensitivity characteristic.

  In this embodiment, since each AE sensor and AF sensor are configured only by CMOS circuits, the compatibility with on-chip implementation of various CMOS circuits (analog and digital) is good, and intelligentization by various peripheral circuits on-chip. Is possible at the same time. Further, since the number of masks and the number of manufacturing steps are small, it is advantageous for cost reduction.

  As described above, according to the present embodiment, a solid-state imaging device for AEAF having high speed, high performance, and low cost can be realized. The present invention is applicable not only to a CMOS sensor but also to a CCD, a BASIS (Base Stored Image Sensor), a SIT (Static Induced Transistor), a CMD (Charge Modulation Device), an AMI (Amplified MOS Intelligent Imager), and the like. .

[Second Embodiment]
FIG. 9 shows a flowchart for explaining the operation of the AEAF solid-state imaging device of the present embodiment. In the first embodiment, as shown in FIG. 6, the AF signal is read after the spot AE signal is output (see steps St5 and St9 in FIG. 6). On the other hand, the present embodiment is characterized in that the spot AE signal is read after the AF signal is output as shown in FIG. 9 (see steps St5 and St9 in FIG. 9). Since the processing procedures and processing contents of the other steps St1 to St11 are the same as those in the first embodiment (FIG. 6), the description thereof is omitted.

  According to the present embodiment, since spot AE signals for all AF points are not read, spot AE signals for only the AF points that are focused based on the previously output AF signals can be read. The operation can be simplified and speeded up.

[Third Embodiment]
FIG. 10 is a schematic circuit block diagram of the AEAF solid-state imaging device of the present embodiment. The AEAF solid-state imaging device shown in FIG. 10 has the same configuration as that of the above-described embodiment (see FIG. 1), that is, an AF sensor block 101 formed on the Si semiconductor substrate 100 (a pair of phase difference detection type AF sensor circuits 110). Standard part AF circuit 110A and reference part AF circuit 110B), AE sensor block 102 (AE circuit 121, Is compensation circuit 122, signal amplification circuit 123), analog circuit (thermometer circuit 103, AGC circuit 105, power supply circuit) 106, a signal amplification circuit 108), and a digital block (MPX 104, logic circuit 107), and is connected to a microcomputer 109 having a built-in ADC 112.

  In the first and second embodiments, the maximum value signal of the photodiode of the AF sensor block 101 is used as the spot AE signal. In this embodiment, in addition to the maximum value signal, as shown in FIG. A value signal is also used. According to this, by using both the maximum value signal and the minimum value signal, finer exposure control becomes possible.

[Fourth Embodiment]
FIG. 11 is a schematic circuit block diagram of the AEAF solid-state imaging device of the present embodiment, and FIG. 12 is a schematic plan layout diagram thereof.

  The solid-state imaging device for AEAF shown in FIGS. 11 and 12 has the same configuration as that of the above embodiment (see FIG. 1), that is, an AF sensor block 101 (phase difference detection type AF sensor circuit 110) formed on the Si semiconductor substrate 100. A reference unit AF circuit 110A and a reference unit AF circuit 110B), an AE sensor block 102 (AE circuit 121, Is compensation circuit 122, signal amplification circuit 123), and analog circuits (thermometer circuit 103, AGC circuit 105). , A power supply circuit 106, a signal amplification circuit 108), and a digital block (MPX 104, logic circuit 107), and is connected to a microcomputer 109 with a built-in ADC 112.

  In FIG. 12, 91 is a wide-angle photodiode, and 92 is a telephoto photodiode. As shown in FIG. 11, the AE circuit block 102 is provided with two divided AE circuits 121 and 121 corresponding to the two-divided photodiode regions.

  That is, the present embodiment is characterized in that the AE circuit 121 (photodiode region) of the AE circuit block 102 constituting the wide AE sensor is divided into a plurality of parts. As described above, by dividing the photodiode area of the AE sensor into the wide-angle photodiode 91 and the telephoto photodiode 92, it becomes possible to use the AE sensor corresponding to the area of the zoom lens to be used. More accurate AE is possible. For example, all AE sensors may be used in the wide-angle zoom region, and only the central AE sensor may be used in the telephoto zoom region. Further, the same effect can be obtained even when the image is divided into two or more.

[Fifth Embodiment]
The present embodiment relates to an imaging device (camera) using the AEAF solid-state imaging device having the AF circuit block and the AE circuit block of the first to fourth embodiments.

  FIG. 13 is a schematic block diagram showing an embodiment when the AEAF solid-state imaging device is used in a lens shutter digital compact camera (imaging device). In FIG. 13, 201 is a barrier that serves as a lens switch and a main switch, 202 is a lens that forms an optical image of a subject on the solid-state imaging device 204, 203 is a diaphragm for changing the amount of light that has passed through the lens 202, and 204 is This is a solid-state imaging device for capturing the subject imaged by the lens 202 as an image signal.

  Reference numeral 205 denotes the AEAF solid-state imaging device described in the first to fourth embodiments. Here, for example, the same one as in the first embodiment (see FIG. 1 and the like) is used. Reference numeral 220 denotes an AEAF optical module on which the AEAF solid-state imaging device 205 is mounted. Reference numeral 221 denotes a pair of AF imaging lenses mounted on the AEAF optical module 220, and each of a pair of linear sensor circuits (a reference part AF circuit and a reference part AF circuit) of the AF circuit block of the AEAF solid-state imaging device 205. The incident light is condensed on the photodiode. Reference numeral 222 denotes an AE condensing lens mounted on the AEAF optical module 220 and condenses incident light on the photodiode of the AE circuit block of the AEAF solid-state imaging device 205.

  Reference numeral 206 denotes an A / D converter that performs analog-digital conversion on image signals, AE signals, and AF signals output from the solid-state imaging device 204 and the solid-state imaging device 205, and 208 denotes an image output from the A / D converter 207. A signal processing unit that performs various corrections and compression of data, a timing generation unit 209 that outputs various timing signals to the solid-state imaging device 204, the imaging signal processing circuit 206, the A / D converter 207, the signal processing unit 208, and the like. Reference numeral 210 denotes an overall control / arithmetic unit that controls various calculations and the entire camera, and 211 denotes a memory unit for temporarily storing image data.

  Further, 212 is an interface unit for recording or reading on a recording medium, 213 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 214 is an interface for communicating with an external computer or the like. Part.

  Next, an operation at the time of photographing with such a lens shutter digital compact camera will be described. When the barrier 201 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 207 is turned on.

  Based on the signal (AF signal) output from the AF circuit block of the solid-state imaging device 205, the overall control / calculation unit 210 calculates the distance to the subject by triangulation. Thereafter, the feeding amount of the lens 202 is calculated, and the lens 202 is driven to a predetermined position to be focused.

  Next, in order to control the exposure amount, a signal (wide AE signal) output from the AE circuit block of the solid-state imaging device 205 is converted by the A / D converter 207 and then input to the signal processing unit 208. At this time, the monitor signal (only the maximum value signal or only the maximum value signal or the maximum value signal and the minimum value signal) as the spot AE signal output from the above-described AF circuit block is used as necessary for the A / D converter 207. Then, the signal is input to the signal processing unit 208. Based on these data, the exposure calculation is performed by the overall control / calculation unit 210. The brightness is determined based on the result of the AE, and the overall control / calculation unit 210 adjusts the aperture 203 and the shutter speed according to the result.

  After that, after the exposure conditions are set, the main exposure with the solid-state image sensor 204 starts. When the exposure is completed, the image signal output from the solid-state imaging device 204 is A / D converted by the A / D converter 207, passes through the signal processing unit 208, and is written in the memory unit 211 by the overall control / calculation unit 210. Thereafter, the data stored in the memory unit 211 is recorded on the removable recording medium 213 through the recording medium control I / F unit 212 under the control of the overall control / arithmetic unit 210. Further, it may be directly input to a computer or the like through the external I / F unit 214.

  Note that the AEAF solid-state imaging device of the present embodiment can be used not only for a digital compact camera but also for a silver salt camera or the like. The same effect can be obtained even when used for a single-lens reflex camera.

Although each embodiment of the present invention has been described above, preferred embodiments of the present invention are listed as follows.
[Embodiment 1] AF photoelectric conversion element array for performing AF, voltage monitoring means for outputting a voltage signal corresponding to the amount of charge accumulated in the AF photoelectric conversion element array, and AE for performing AE A first exposure amount detecting means that includes a photoelectric conversion element and outputs a signal photoelectrically converted by the AE photoelectric conversion element as a first exposure amount detection signal, and is formed on the same semiconductor substrate. The AEAF solid-state imaging device includes a second exposure amount detection unit that outputs a monitor signal for auto gain control output from the photoelectric conversion element array for AF as a second exposure amount detection signal. A signal is output in real time by nondestructive readout, and an AEAF solid-state imaging device.
[Embodiment 2] The AEAF solid-state imaging device according to Embodiment 1, wherein there are a plurality of AF photoelectric conversion element arrays, each of which is arranged at a predetermined distance.
[Embodiment 3] The AEAF solid-state imaging device according to Embodiment 1, wherein the monitor signal is output in real time by nondestructive readout.
[Embodiment 4] The AEAF solid-state imaging device according to Embodiment 1, further comprising charge amplifying means for amplifying and reading photoelectric charges from the AF photoelectric conversion element.
[Embodiment 5] The voltage monitoring means outputs the maximum value signal of the AF photoelectric conversion element array as a real-time monitor signal, and the second exposure amount detection means outputs the maximum value signal to the second exposure signal. The solid-state imaging device for AEAF according to embodiment 1, wherein the solid-state imaging device is output as a quantity detection signal.
[Embodiment 6] The voltage monitoring means outputs two signals, a maximum value signal and a minimum value signal of the AF photoelectric conversion element array, as a real-time monitor signal, and the second exposure amount detection means is configured to output the maximum value. 2. The AEAF solid-state imaging device according to claim 1, wherein the signal and the minimum value signal are output as the second exposure amount detection signal.
[Embodiment 7] The AF photoelectric conversion element and the AE photoelectric conversion element are PN junction photodiodes, and the P-type impurity layer and the N-type impurity layer forming the photodiode have the same impurity concentration and junction depth. The solid-state imaging device for AEAF according to the first embodiment, characterized in that:
[Embodiment 8] The AEAF solid according to Embodiment 7, wherein the AF photoelectric conversion element and the AE photoelectric conversion element have an exposure index within 0.3 EV of an exposure index. Imaging device.
[Embodiment 9] In the solid-state imaging device in which a plurality of AF photoelectric conversion element arrays for performing multipoint AF and an AE photoelectric conversion element for performing AE with a wide field of view are formed on the same semiconductor substrate. First exposure amount detection means for outputting a signal photoelectrically converted by the AE photoelectric conversion element as a first exposure amount detection signal; and from the AF photoelectric conversion element array corresponding to the selected AF point. A solid-state image pickup device for AEAF, comprising: a second exposure amount detection means for selecting only a monitor signal and outputting it as a second exposure amount detection signal.
[Embodiment 10] The embodiment according to any one of embodiments 1 to 9, wherein a timing generation circuit and a multiplexer circuit for sequentially outputting a plurality of the signals are formed on the same semiconductor substrate. Solid-state imaging device for AEAF.
[Embodiment 11] The AEAF solid-state imaging device according to any one of Embodiments 1 to 10, the first exposure amount detection signal and the second exposure output from the AEAF solid-state imaging device. And a control means for controlling exposure conditions based on a signal for detecting the amount.

1 is a schematic circuit block diagram illustrating an AEAF solid-state imaging device according to a first embodiment of the present invention. 1 is a schematic plan layout diagram illustrating an AEAF solid-state imaging device according to a first embodiment of the present invention. 1 is a circuit diagram showing an AF circuit of a first embodiment of the present invention. 1 is a circuit diagram illustrating an AE circuit according to a first embodiment of the present invention. 1 is a circuit diagram illustrating an AGC circuit according to a first embodiment of the present invention. It is a flowchart explaining operation | movement of the solid-state imaging device for AEAF of 1st Embodiment of this invention. 1 is a cross-sectional structure diagram illustrating an AEAF solid-state imaging device according to a first embodiment of the present invention. It is a graph which shows the spectral sensitivity characteristic of AF sensor and AE sensor of 1st Embodiment of this invention. It is a flowchart explaining operation | movement of the solid-state imaging device for AEAF of 2nd Embodiment of this invention. It is a schematic circuit block diagram which shows the solid-state imaging device for AEAF of 3rd Embodiment of this invention. It is a schematic circuit block diagram which shows the solid-state imaging device for AEAF of 4th Embodiment of this invention. It is a schematic plane layout figure which shows the solid-state imaging device for AEAF of 4th Embodiment of this invention. It is a schematic block diagram which shows the camera system using the solid-state imaging device for AEAF of 5th Embodiment of this invention. It is a circuit block diagram which shows the automatic AE apparatus for imaging devices of a prior art example.

Explanation of symbols

1, 21 pn photodiode 2 Reset MOS transistor 3, 20 CMOS differential amplifier 4 Clamp capacitance 5-9 MOS switch 10 Minimum value detection differential amplifier 11 Maximum value detection differential amplifier 12, 13 MOS switch 14 OR circuit 15 Scan circuit 16, 17 Constant current MOS transistor 18 Common output line 22 pn diode 25 Buffer amplifier 26 Comparator 30 AE circuit 31, 32 CCD array 33 Photoelectric conversion circuit 34 Integration circuit 35, 36 Comparison circuit 37 AF counter circuit 38 AE counter Circuits 42, 43 Output selection circuit 44, 45 Buffer 46 Correlation calculation circuit 47 AD converter 48 Main control circuit 49 No-AD microcomputer 71, 100 N-type Si substrate 72 N-type epitaxial layer 73 PWL
74 NWL
75 N + impurity layer 76 Thin oxide film 77 LOCOS
78 POL wiring 79 Interlayer insulating film 80 AL wiring 82 Light shielding film 83 Protective film 91 Wide-angle photodiode 92 Telephoto photodiode 101 AF circuit block 102 AE circuit block 103 Thermometer circuit 104 Multiplexer 105 AGC circuit 106 Power supply circuit 107 Logic circuit 108 Signal amplification circuit 109 AD built-in microcomputer 110 Phase difference detection AF sensor circuit 110A Reference unit AF circuit 110B Reference unit AF circuit 112 ADC (AD converter)
121 AE circuit 122 Is compensation circuit 123 signal amplifier circuit

Claims (8)

An AF photoelectric conversion element array, a voltage monitoring unit that outputs a voltage signal corresponding to the amount of charge accumulated in the AF photoelectric conversion element array, and an AE photoelectric conversion element, the AE photoelectric conversion element In the AEAF solid-state imaging device in which the first exposure amount detection means for outputting the photoelectrically converted signal as the first exposure amount detection signal is formed on the same semiconductor substrate.
Second exposure amount detection means for outputting a monitor signal for auto gain control output from the photoelectric conversion element array for AF as a second exposure amount detection signal is provided, and the monitor signal is read in real time by nondestructive reading. Output,
It said second exposure amount detecting means read out said second exposure amount detection signal after the signal output of the AF photoelectric conversion element arrays when focused,
The AF photoelectric conversion element and the AE photoelectric conversion element are PN junction photodiodes, and the P-type impurity layer and the N-type impurity layer forming the photodiode have the same impurity concentration and junction depth. A solid-state imaging device for AEAF.   2. The AEAF solid-state imaging device according to claim 1, wherein the AF photoelectric conversion element array includes a plurality, and each is arranged with a predetermined distance.   2. The solid-state imaging device for AEAF according to claim 1, further comprising charge amplifying means for performing amplification reading of photoelectric charges from the AF photoelectric conversion element.   The voltage monitoring unit outputs a maximum value signal of the AF photoelectric conversion element array as a real-time monitor signal, and the second exposure amount detection unit uses the maximum value signal as the second exposure amount detection signal. The solid-state imaging device for AEAF according to claim 1, wherein the solid-state imaging device is output.   The voltage monitoring means outputs two signals, a maximum value signal and a minimum value signal of the AF photoelectric conversion element array, as a real-time monitor signal, and the second exposure amount detection means outputs the maximum value signal and the minimum value. 2. The AEAF solid-state imaging device according to claim 1, wherein a signal is output as the second exposure amount detection signal. 3. The AF photoelectric conversion element and the photoelectric conversion element for the AE, AEAF according to any one of claims 1 to 5 spectral sensitivity characteristic is characterized by comprising the exposure amount within 0.3EV in exposure index Solid-state imaging device. AEAF solid-state imaging device according to any one of claims 1 to 6 timing generator and the multiplexer circuit is characterized in that it is formed on the same semiconductor substrate for sequentially outputting a plurality of said respective signals . And AEAF solid-state imaging device according to any one of claims 1 to 7, the first exposure amount detection signal and the second exposure amount detection signal output by the AEAF solid-state imaging device And a control means for controlling exposure conditions.

Images