JP4501341B2 - Device inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a device inspection method for inspecting a device in which electrical elements such as transistors, liquid crystal elements, EL elements, and light receiving elements including photoelectric conversion elements are formed on a substrate, and a protective insulating film covers the electrical elements.
[0002]
[Prior art]
In recent years, devices using electric elements such as transistors, EL (Electro Luminescence) elements, liquid crystal elements, and photodiodes have become widespread. A device is manufactured by laminating layers of various substances on a substrate mainly using various methods such as plating, vapor deposition, photolithography, and etching to form an electric element on the substrate. In order to protect the electric element from dust, impact, outside air, etc., the electric element is covered with a protective insulating film.
[0003]
Patent Document 1 describes a photosensor as an electric element. In this photosensor, in order to detect the intensity of light incident on the semiconductor layer, the top gate electrode facing the semiconductor layer is formed of ITO, which is a transparent metal oxide. The photosensor is covered with the top gate electrode, and a transparent protective insulating film made of silicon nitride is formed. Further, this Patent Document 1 describes a solid-state imaging device in which a plurality of such photosensors are arranged in a matrix on a substrate, and the solid-state imaging device detects the intensity of light with each photosensor. Thus, an image of the subject is acquired.
[0004]
In general, a solid-state imaging device is used to acquire an image of a subject by entering reflected light of the subject through a lens away from the subject. Attempts have been made to use solid-state imaging devices so as to acquire an image of a subject by directly contacting the subject with an insulating film.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-94040
[0006]
[Problems to be solved by the invention]
By the way, when reading a fingerprint with such a solid-state imaging device, the fingertip that is a subject is brought into contact with the solid-state imaging device, so that the sweat of the fingertip adheres to the protective insulating film. If there is no defect in the protective insulating film, there is no particular problem. However, if there is a defect such as a pinhole due to minute particles in the protective insulating film, sweat permeates the photosensor through the defect, and the top of the photosensor particularly The gate electrode may be corroded by sodium ions or the like that are components of sweat. Such a problem is not limited to the solid-state imaging device, but also in other devices such as a liquid crystal display device and an EL display device in which a person may touch the protective insulating film. In addition to sweat, oxygen, moisture, and other harmful substances may permeate into the electrical element through defects in the protective insulating film. A device having a defect in the protective insulating film is a defective product, and needs to be selected from a device having no defective protective insulating film. However, defects such as pinholes in the protective insulating film are not so large as to be visually recognized, and a method for easily selecting a device having a defective protective insulating film and a device having no defective protective insulating film has been proposed. Not.
[0007]
Therefore, an object of the present invention is to provide a device inspection method capable of selecting a device having a defect in the protective film and a device having no defect in the protective film.
[0008]
[Means for Solving the Problems]
  In order to solve the above problems, for example, as shown in FIGS.
  Arranged in a matrix with a substrate,TransparentA plurality of light receiving elements (for example, double gate type transistor 3) having electrodes (for example, top gate electrode 30) and at least a part of the electrodes are covered.TransparentA protective film (for example, protective insulating film 4),
  Immerse the protective film of a solid-state imaging device that acquires an image of a subject by directly contacting the protective film with an electrolytic solution, immerse a counter electrode (for example, the anode rod 106) in the electrolytic solution, and the electrode and the counter electrode Apply voltage betweenAnd inspect the visual changes that make the transparent electrode opaqueIt is characterized by doing.
[0016]
  The light receiving element may have an electrode (for example, the bottom gate electrode 21, the drain electrode 27, and the source electrode 28) different from the electrode, and the other electrode and the electrode may be connected.
  Further, the electrode of the light receiving element and the other electrode may be insulated from each other after the inspection.
  Moreover, the other part of the electrode may be exposed from the protective film.
  In addition, a voltage may be applied between the electrode and the counter electrode so that the electrode functions as a cathode and the counter electrode functions as an anode.
  The device may include a plurality of light receiving elements, and the electrodes of the light receiving elements may be connected to each other by wiring.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. However, the scope of the invention is not limited to the illustrated examples.
[0018]
First, the solid-state imaging device 1 to be inspected will be described with reference to FIGS. FIG. 1 is a plan view showing the entire solid-state imaging device 1, FIG. 2 (a) is a plan view showing one pixel of the solid-state imaging device 1, and FIG. 2 (b) is a plan view showing FIG. ) Is a cross-sectional view showing the II cross section, FIG. 3A is a cross-sectional view showing the II-II cross section and the III-III cross section of FIG. 1, and FIG. FIG. 3C is a cross-sectional view showing the VV cross section of FIG. 1.
[0019]
The solid-state imaging device 1 at the inspection stage has a substantially flat transparent substrate 2 and a plurality of n rows and m columns (both n and m are integers) arranged in a matrix on one surface of the transparent substrate 2. , And a protective insulating film 4 that covers all the DG-Trs 3, 3,...
[0020]
The transparent substrate 2 is transparent to light (hereinafter simply referred to as “translucent”) and has an insulating property, and is a glass substrate such as quartz glass or a plastic substrate such as polycarbonate.
[0021]
Each DG-Tr3 is an electric element serving as a pixel. Each DG-Tr 3 includes a bottom gate electrode 21 formed on the transparent substrate 2, a semiconductor film 23 sandwiching the bottom gate electrode 21 and the interlayer insulating film 22 and facing the bottom gate electrode 21, and a center of the semiconductor film 23. A channel protective film 24 formed on the semiconductor film 23, impurity semiconductor films 25 and 26 formed on both ends of the semiconductor film 23 apart from each other, a drain electrode 27 formed on the impurity semiconductor film 25, an impurity A source electrode 28 formed on the semiconductor film 26 and a top which is a transparent electrode disposed above the interlayer insulating film 29 covering the drain electrode 27, the source electrode 28, and the channel protective film 24, facing the semiconductor film 23. Gate electrode 30.
[0022]
On the transparent substrate 2, bottom gate electrodes 21 are formed in a matrix for each DG-Tr3. Further, n bottom gate lines 41, 41,... Extending in the horizontal direction are formed on the transparent substrate 2, and the bottom gate electrode 21 of each DG-Tr 3 in the same row arranged in the horizontal direction is It is formed integrally with the common bottom gate line 41. The bottom gate electrode 21 and the bottom gate line 41 have conductivity and light shielding properties, and are made of, for example, chromium, a chromium alloy, aluminum, an aluminum alloy, or an alloy thereof.
[0023]
On the bottom gate electrode 21 and the bottom gate line 41, an interlayer insulating film 22 common to all the DG-Trs 3, 3,... Is formed. The interlayer insulating film 22 has insulating properties and translucency, and is made of, for example, silicon nitride or silicon oxide.
[0024]
On the interlayer insulating film 22, a semiconductor film 23 patterned in an island shape is formed for each DG-Tr3. The semiconductor film 23 has a substantially rectangular shape in plan view, and is a layer formed of amorphous silicon or polysilicon. A channel protective film 24 is formed on the semiconductor film 23. The channel protective film 24 has a function of protecting the surface of the semiconductor film 23 from an etchant used for patterning, has insulating properties and translucency, and is made of, for example, silicon nitride or silicon oxide. When light enters the semiconductor film 23, an amount of electron-hole pairs according to the amount of light is generated around the interface between the channel protective film 24 and the semiconductor film 23.
[0025]
An impurity semiconductor film 25 is formed on one end portion of the semiconductor film 23 so as to partially overlap the channel protective film 24, and an impurity semiconductor film 26 is partially channeled on the other end portion of the semiconductor film 23. It is formed so as to overlap the protective film 24. The impurity semiconductor films 25 and 26 are made of amorphous silicon containing n-type impurity ions (n⁺Silicon).
[0026]
On the impurity semiconductor film 25, a drain electrode 27 patterned for each DG-Tr3 is formed. On the impurity semiconductor film 26, a source electrode 28 patterned for each DG-Tr3 is formed. In addition, m drain lines 42, 42,... And source lines 43, 43,... Extending in the vertical direction are formed on the interlayer insulating film 22, and each DG− in the same column arranged in the vertical direction. The drain electrode 27 of Tr3 is formed integrally with the common drain line 42, and the source electrode 28 of each DG-Tr3 arranged in the vertical direction is formed integrally with the common source line 43. The drain electrode 27, the source electrode 28, the drain line 42, and the source line 43 have conductivity and light shielding properties, and are made of, for example, chromium, a chromium alloy, aluminum, an aluminum alloy, or an alloy thereof.
[0027]
All of the DG-Tr 3, 3,..., The channel protective film 24, the drain electrode 27 and the source electrode 28, and the drain lines 42, 42,. A common interlayer insulating film 29 is formed. The interlayer insulating film 29 has insulating properties and translucency, and is made of, for example, silicon nitride or silicon oxide.
[0028]
On the interlayer insulating film 29, a top gate electrode 30 patterned for each DG-Tr3 is formed. Further, n top gate lines 44 extending in the horizontal direction are formed on the interlayer insulating film 29, and the top gate electrodes 30 of the DG-Tr3 in the same row arranged in the horizontal direction are the common top. It is formed integrally with the gate line 44. The top gate electrode 30 and the top gate line 44 are transparent conductors such as a metal oxide having translucency, for example, indium oxide, zinc oxide, tin oxide, or a mixture containing at least one of these ( For example, it is made of tin-doped indium oxide (ITO) or zinc-doped indium oxide.
[0029]
A common protective insulating film 4 is formed on the top gate electrode 30 and the top gate line 44 of all the DG-Trs 3, 3,. The protective insulating film 4 has insulating properties and translucency, and is made of, for example, silicon nitride or silicon oxide.
The DG-Tr3 configured as described above is a photoelectric conversion element using the semiconductor film 23 as a light receiving portion.
[0030]
In the solid-state imaging device 1 described above, the interlayer insulating films 22 and 29 are formed on almost the entire surface of the transparent substrate 2, but the protective insulating film 4 is formed on the entire surface of the transparent substrate 2 as shown in FIG. Not. That is, the protective insulating film 4 is formed in the image input region where the DG-Trs 3, 3,... Are arranged in a matrix, and the protective insulating film 4 is not formed outside the image input region.
[0031]
Conductive wiring 50 is formed so as to surround an image input region in which DG-Tr3, 3,. The conductive wiring 50 is formed as an O-ring on the interlayer insulating film 29, most of the conductive wiring 50 is covered with the protective insulating film 4, and a part of the conductive wiring 50 is formed with the protective insulating film 4. It is exposed from the area.
[0032]
Also, the bottom gate lines 41, 41,..., The drain lines 42, 42,... And the source lines 43, 43,. The region extends from the region to a portion overlapping the conductive wiring 50. The drain lines 42, 42,... And the source lines 43, 43,... Are formed between the interlayer insulating film 22 and the interlayer insulating film 29 and are not exposed. The bottom gate line 41 is formed between the transparent substrate 2 and the interlayer insulating film 29 and is not exposed.
[0033]
As shown in FIG. 3 (a), contact holes 52, 52,... Are formed in the interlayer insulating film 29 where the conductive lines 50 overlap with the tips of the drain lines 42, 42,. Are partially embedded in the contact holes 52, 52,..., And the drain lines 42, 42,... Are connected to the conductive lines 50 through the respective contact holes 52. Similarly, in a plan view, contact holes 53, 53,... Are formed in the interlayer insulating film 29 where the tips of the source lines 43, 43,. .. Are partially embedded in the contact holes 53, 53,..., And the source lines 43, 43,... Are connected to the conductive wiring 50 through the respective contact holes 53. Further, as shown in FIG. 3B, contact holes 51, 51,... Are formed on the interlayer insulating film 22 and the interlayer insulating film 29 at positions overlapping the bottom gate lines 41, 41,. In each contact hole 51, a conductive first intermediate layer 46 is embedded in a portion of the interlayer insulating film 22 in each contact hole 51, and a conductive material is provided in a portion of each contact hole 51 in the interlayer insulating film 29. A part of the wiring 50 is buried. In each contact hole 51, the bottom gate line 41 is connected to the conductive wiring 50 through the first intermediate layer 46. The first intermediate layer 46, the drain electrode 27, the source electrode 28, the drain line 42, and the source line 43 are formed by processing a common conductor layer formed on the interlayer insulating film 22 by etching or the like. It has been done.
[0034]
In plan view, the top ends of the top gate lines 44, 44,... Extend from the region where the protective insulating film 4 is formed and are exposed, and intersect the routing portion of the conductive wiring 50. Here, as shown in FIG. 3C, the top gate line 44 and the conductive wiring 50 are formed by processing a common conductor layer formed on the interlayer insulating film 29 by etching or the like. Is.
[0035]
The conductive wiring 50 and the plurality of contact holes 51, 52, 53 are used for inspecting the solid-state imaging device 1, and the solid-state imaging device 1 is inspected in the state shown in FIG. 1 described above. It will be. After the inspection is completed, the routing portion of the conductive wiring 50 is removed, and the bottom gate lines 41, 41,..., The drain lines 42, 42,..., The source lines 43, 43,. Insulated.
[0036]
Next, a manufacturing method and an inspection method of the solid-state imaging device 1 will be described.
First, after a film forming process for forming a conductor layer on the transparent substrate 2 by PVD or CVD such as sputtering or vapor deposition, a mask process such as photolithography is performed, and the conductor layer is processed by etching or the like. By performing the shape processing step, the bottom gate electrode 21 and the bottom gate lines 41, 41,... Of each DG-Tr3 are patterned.
[0037]
Next, an interlayer insulating film 22 made of silicon nitride or silicon oxide is formed on almost the entire surface of the transparent substrate 2, a semiconductor layer is formed on the entire surface of the interlayer insulating film 22, and an insulating layer is formed on the entire surface of the semiconductor layer. Form a film. Next, the insulating layer is masked and the insulating layer is shaped to pattern the channel protective film 24 for each DG-Tr3, and then an amorphous silicon layer containing an n-type impurity is deposited. Then, by masking the amorphous silicon layer and processing the shape of the amorphous silicon layer, the impurity semiconductor films 25 and 26 are patterned for each DG-Tr3, and the underlying semiconductor film 23 is patterned for each DG-Tr3.
[0038]
Next, contact holes 51, 51,... Are formed in the interlayer insulating film 22 at portions overlapping the tips of the bottom gate lines 41, 41,. Next, a conductor layer is formed on the entire surface of the interlayer insulating film 22, and the conductor layer is masked, and the conductor layer is shaped, so that the drain electrode 27 and the source electrode 28 together with the DG-Tr3 are formed. .. And the source lines 43, 43,..., And the first intermediate layer 46 is patterned in each contact hole 51. The first intermediate layer 46 is in contact with the bottom gate line 41 in each contact hole 51.
[0039]
Next, an interlayer insulating film 29 is formed on the entire surface of the interlayer insulating film 22 on which the drain electrode 27 and the source electrode 28 are formed. Next, a contact hole 51 is formed in the interlayer insulating film 29 at a position overlapping with each first intermediate layer 46, and a contact hole 52 is formed in the interlayer insulating film 29 at a position overlapping with the tip of each drain line 42. Forms a contact hole 53 in the interlayer insulating film 29 at a location overlapping the tip of each source line 43.
[0040]
Next, a transparent conductor layer such as ITO is formed on the entire surface of the interlayer insulating film 29, a mask is formed on the transparent conductor layer, and the shape of the transparent conductor layer is processed, so that a top gate is formed for each DG-Tr3. The electrode 30 is patterned and the top gate lines 44, 44,... And the conductive wiring 50 are formed integrally with the top gate electrode 30. The conductive wiring 50 is on the tips of the bottom gate lines 41, 41,..., On the tips of the first intermediate layers 46, 46,... And the tips of the source lines 43, 43,. .., Drain lines 42, 42,..., Source lines 43, 43,... And top gate lines 44, 44,. They are conductive to each other.
[0041]
Then, as shown in FIG. 1, the conductive gates 50 are crossed over the top gate lines 44, 44,... So that the front ends of some of the top gate lines 44, 44,. The protective insulating film 4 is formed so that the intersections are exposed.
[0042]
Next, the solid-state imaging device 1 is inspected using the oxidation-reduction apparatus 100 shown in FIG. The oxidation-reduction apparatus 100 includes a DC power source 101 and a treatment tank 103 in which an electrolytic solution 102 such as an ammonium borate solution is stored. In FIG. 4, the solid-state imaging device 1 is shown in the VI-VI cross section of FIG. The anode rod 106, which is a counter electrode such as platinum, gold, silver, and indium, is sandwiched between conductive anode clips 104 connected to the anode of the DC power source 101, and the anode rod 106 is immersed in the electrolyte solution 102. On the other hand, the solid-state imaging device 1 is sandwiched between the cathode clip 105 so that the conductive cathode clip 105 connected to the cathode of the DC power supply 101 contacts the exposed portions of the top gate lines 44, 44,. To do. .., Drain lines 42, 42,..., Source lines 43, 43,... And top gate lines 44, 44,. Even when a potential is applied via the bottom gate electrode 21, the drain electrode 27, the source electrode 28, and the top gate electrode 30 of all the DG-Trs 3, 3,. Therefore, all bottom gate lines 41, all drain lines 42, all source lines 43, all top gate lines 44, all bottom gate electrodes 21, all drain electrodes 27, All the source electrodes 28 and all the top gate electrodes 30 function as cathodes in the electrolytic solution. Further, no potential difference occurs between the electrodes of each DG-Tr3, and it is possible to prevent the DG-Tr3 from being damaged.
[0043]
Then, the solid-state imaging device 1 is immersed in the electrolytic solution 102, but the protective insulating film 4 is coated so that the exposed portions of the top gate lines 44, 44,... And the conductive wiring 50 are not immersed in the electrolytic solution 102. The part is immersed in the electrolytic solution 102.
[0044]
When a predetermined time elapses after the DC power source 101 is turned on, when a minute pinhole exists in the protective insulating film 4, the electrolytic solution 102 penetrates the protective insulating film 4 and is reduced by the penetrated electrolytic solution 102. Reaction occurs in the top gate electrodes 30, 30,... And the top gate lines 44, 44,. On the other hand, when a minute pinhole is not formed in the protective insulating film 4, the electrolytic solution 102 does not reach the top gate electrodes 30, 30,... And the top gate lines 44, 44,. 30, and the top gate lines 44, 44, ... do not react.
[0045]
When the solid-state imaging device 1 is immersed for a predetermined time, the solid-state imaging device 1 is taken out from the electrolytic solution 102 and the electrolytic solution attached to the solid-state imaging device 1 is washed away. When the protective insulating film 4 has minute pinholes, the metal oxides of the top gate electrodes 30, 30,... And the top gate lines 44, 44,. On the other hand, when there is no pinhole in the protective insulating film 4, the top gate electrodes 30, 30,... And the top gate lines 44, 44,. When the solid-state imaging device 1 is visually observed from the protective insulating film 4 side and the top gate electrodes 30, 30,... And the top gate lines 44, 44, etc. are observed, the top gate electrodes 30, 30,. , 44,... Can be determined by transparency / opacity. .. Or the top gate lines 44, 44,..., Or pinholes in the protective insulating film 4 and the solid-state imaging device 1 in which the pinholes are formed in the protective insulating film 4. Can be sorted into solid-state imaging devices 1 in which are not formed.
[0046]
The top gate electrodes 30, 30,... And the top gate lines 44, 44,... Are opaque by the above method, which is defective, and the top gate electrodes 30, 30,. The solid-state imaging device 1 in which... Remains transparent is normal. A defective solid-state imaging device 1 cannot be used as a product, and a normal solid-state imaging device 1 can be used as a product.
[0047]
For the normal solid-state imaging device 1, a resist film is formed on the protective insulating film 4 in the image input region in which DG-Tr 3, 3,... Are arranged in a matrix. Then, by etching the protective insulating film 4 at a portion not covered with the resist film, the conductive wiring 50 is crossed over the drain lines 42, 42,... And the bottom gate lines 41, 41,. Expose between intersections. At this time, the conductive wiring 50 is not exposed between the intersections overlapping the source lines 43, 43,.
[0048]
Next, of the exposed portions of the conductive wiring 50, the intersections overlapping the drain lines 42, 42,... And the intersections overlapping the bottom lines 41, 41,. The tip of 44,... Is masked with a photoresist. Then, as shown in FIG. 5, the conductive wiring 50 is partially removed by etching. That is, the conductive wiring 50 is etched away between the drain lines 42, 42,..., Between the bottom gate lines 41, 41,. Thus, by processing the conductive wiring 50 by etching, the bottom gate lines 41, 41,..., The drain lines 42, 42,... And the top gate lines 44, 44,. Insulate. In the conductive wiring 50, since the protective insulating film 4 remains between the intersections overlapping the source lines 43, 43,..., The source lines 43, 43,. As shown in FIG. 2, the remaining conductive wirings 50 are connected to each other. Further, the source lines 43, 43,... Are insulated from the bottom gate lines 41, 41,..., The drain lines 42, 42,.
[0049]
6 (a), 6 (b), and 6 (c) are cross-sectional views showing the VII-VII cross section, the VIII-VIII cross section, and the IX-IX cross section of FIG. 5, respectively. As shown in FIG. 6 (a), intermediate layers 50A, 50A,... Are stacked at the tips of drain lines 42, 42,. A part of 50 remains. As shown in FIG. 6B, the second intermediate layers 50B, 50B,... Are separated from the first intermediate layers 46, 46,. Although the layers are independently stacked, the second intermediate layers 50B, 50B,. As shown in FIG. 6C, the first terminal layers 50C, 50C, which are part of the remaining conductive wiring 50, are provided at the tips of the top gate lines 44, 44,. , ... are formed so as to be integrated with each other.
[0050]
Thereafter, a transparent conductive layer is coated on one surface of the transparent substrate 2 (the side on which DG-Tr3, 3,... Are formed). The conductor layer is made of, for example, indium oxide, zinc oxide, tin oxide, or a mixture containing at least one of them (for example, tin-doped indium oxide (ITO), zinc-doped indium oxide).
[0051]
Next, among the transparent conductor layers, DG-Tr3, 3,... Are masked on the image input area arranged in a matrix, and further, the intermediate layers 50A, 50A,. The portions overlapping 50B... And the first terminal layers 50C, 50C. Then, by processing the shape of the transparent conductor layer, an electrostatic protection electrode 5 (shown in FIGS. 7 and 8) is formed in the image input region, and is shown broken in the XX section of FIG. A terminal layer 5A is formed on each intermediate layer 50A as shown in FIG. 8A, and a terminal is provided on each second intermediate layer 50B as shown in FIG. 8B viewed from the XI-XI cross section of FIG. The layer 5B is formed, and the second terminal layer 5C is formed on each of the first terminal layers 50C as shown in FIG. 8C viewed from the XII-XII cross section of FIG. The electrostatic protection electrode 5, the terminal layers 5A, 5A,..., The terminal layers 5B, 5B,... And the second terminal layers 5C, 5C,.
[0052]
.. Are connected to the terminal layer 5A, and the output terminal 7A of the top gate driver 7 as a shift register is connected to the second terminal layer 5C. Further, the output terminals 8A of the bottom gate driver 8 that is a shift register are connected to the terminal layer 5B.
[0053]
That is, the drain electrode 27 of each DG-Tr3 is appropriately operated by the data driver 6 connected via the drain line 42, and the top gate electrode 30 of each DG-Tr3 is connected via the top gate line 44. The bottom gate electrode 21 of each DG-Tr 3 is appropriately operated by the top gate driver 7 and appropriately operated by the bottom gate driver 8 connected via the bottom gate line 41.
[0054]
As shown in FIG. 9, the solid-state imaging device 1 that has been inspected and manufactured as described above has a subject place a fingertip on the electrostatic protection electrode 5, and the reflected light hν of the fingertip is converted into DG-Tr3, 3,. This is used to acquire a fingerprint image of the fingertip by receiving light with the semiconductor film 23. Even if the subject directly touches the fingertip with the electrostatic protection electrode 5, no pinhole is formed by particles in the electrostatic protection electrode 5 and the protective insulating film 4, so that the sweat of the fingertip is top gated through the pinhole. The electrodes 30, 30,... And the top gate lines 44, 44,. In the above embodiment, the electrostatic protection electrode 5 is provided on the protective insulating film 4. However, the present invention is not limited to this, and a fingerprint image is formed by placing a fingertip directly on the protective insulating film 4 without providing the electrostatic protective electrode 5. The solid-state imaging device 1 that obtains Alternatively, in the case of a solid-state imaging device in which an adverse effect such as rain that corrodes the electrode penetrates through a pinhole, the fingertip is not directly in contact with the protective insulating film 4 but through the lens facing the protective insulating film 4. Such a non-contact type solid-state imaging device may be used, and the solid-state imaging device 1 may be used as such an imaging device.
[0055]
A function and an operation example of the driver of the solid-state imaging device 1 will be described. Each source line 43 is maintained at a constant voltage via the conductive wiring 50, and is grounded, for example, and maintained at 0 [V]. The electrostatic protection electrode 5 is grounded via a wiring 5A. The wiring 5A may be connected to each source line 43, but a high voltage current due to static electricity at the fingertip flows through the electrostatic protection electrode 5 and the source line 43, so that the data driver 6, the top gate driver 7, or It is preferable that the bottom gate driver 8 is not connected on the upper surface of the transparent substrate 2 because the bottom gate driver 8 may be damaged and may cause a malfunction due to voltage displacement.
[0056]
The top gate driver 7 is a shift register, and is reset in the order from the top gate line 44 of the first row to the top gate line 44 of the nth row (when the nth row is reached, the first row is returned as necessary). A pulse is output. The reset pulse is generated by receiving light at the high-level reset potential for removing holes accumulated in the semiconductor film 23 and the channel protective film 24 during the reset period and the semiconductor film 23 during the carrier accumulation period. Among electron-hole pairs, it is composed of a low-level carrier storage potential that holds holes.
[0057]
The bottom gate driver 8 is a shift register, and outputs a high level read pulse in order from the bottom gate line 41 in the first row to the bottom gate line 41 in the nth row. The read pulse is composed of a read potential for forming an n-channel in the semiconductor film 23 in the read period and a depletion potential for forming a depletion layer in the semiconductor film 23 in the non-read period, and the semiconductor film in the read period. The n-channel region formed in 23 depends on the amount of light incident on the semiconductor film 23.
[0058]
First, in the reset operation, a pulse voltage (reset pulse; for example, high level of Vtg = + 15 V) φTi is applied to the reset period Treset of the top gate line 44 of the i-th row, and the semiconductor film 23 of each DG-Tr3 and Carriers (here, holes) accumulated near the interface between the channel protective film 24 and the semiconductor film 23 are emitted.
[0059]
Next, by applying a low level (for example, Vtg = −15 V) bias voltage φTi to the top gate line 44, the reset operation is terminated and a carrier accumulation period Ta by the carrier accumulation operation is started. In the carrier accumulation period Ta, the light that reaches the upper part of the electrostatic protection electrode 5 through the DG-Tr 3 from the light source below the transparent substrate 2 is a convex part along the fingerprint pattern in contact with the electrostatic protection electrode 5 The electron-hole pairs generated in the incident effective region of the semiconductor film 23, that is, the carrier generation region, are generated according to the amount of light reflected by the semiconductor film 23, and the semiconductor film 23 and the semiconductor film 23 in the channel protective film 24 Holes are accumulated near the interface, that is, around the channel region.
[0060]
In the precharge operation, in parallel with the carrier accumulation period Ta, a predetermined voltage (precharge voltage) Vpg is applied to the drain line 42 based on the precharge signal φpg, and the drain line 42 and the drain electrode 27 are charged. (Precharge period Tprch).
Next, in the read operation, after the precharge period Tprch has elapsed, a high level (for example, Vbg = + 10 V) bias voltage (read selection signal; hereinafter referred to as a read pulse) φBi is applied to the bottom gate line 41. DG-Tr3 is turned on (reading period Tread).
[0061]
Here, in the readout period Tread, carriers (holes) accumulated in the channel region according to the incidence of light work in a direction that relaxes Vtg (−15 V) applied to the top gate terminal TG having a reverse polarity. In addition, an n channel is formed by Vbg of the bottom gate terminal BG, and the drain line voltage VD of the drain line 42 tends to gradually decrease with time from the precharge voltage Vpg in accordance with the drain current.
[0062]
That is, when the carrier accumulation state in the carrier accumulation period Ta is a dark state and carriers (holes) are not accumulated in the channel region, a negative bias is applied to the top gate terminal TG, whereby the bottom gate terminal BG is positively charged. The bias is canceled, DG-Tr3 is turned off, and the drain voltage, that is, the voltage VD of the drain line 42 is held almost as it is.
[0063]
On the other hand, when the carrier accumulation state is a bright state, carriers (holes) corresponding to the amount of incident light are captured in the channel region, so that the negative bias of the top gate terminal TG is canceled and canceled. Due to the positive bias of the bottom gate terminal BG, the DG-Tr3 is turned on. Then, the voltage VD of the drain line 42 decreases according to the ON resistance corresponding to the amount of incident light.
[0064]
Therefore, the change tendency of the voltage VD of the drain line 42 is the time from the end of the reset operation by applying the reset pulse φTi to the top gate terminal TG until the read pulse φBi is applied to the bottom gate terminal BG (carrier accumulation). It is deeply related to the amount of light received during the period Ta), and shows a tendency to decrease slowly when the accumulated carriers are small, and to decrease sharply when there are many accumulated carriers. For this reason, the read period Tread starts and the data driver 6 detects the voltage VD of the drain line 42 after a predetermined time has elapsed or until the voltage reaches the voltage based on a predetermined threshold voltage. By detecting this time, the amount of irradiation light is converted.
[0065]
By sequentially performing the series of image reading operations described above on the DG-Tr3 in the 1st to nth rows, the DG-Tr3 can be operated as a two-dimensional sensor system.
Further, if the state in which a low level (for example, Vbg = 0 V) is applied to the bottom gate line 41 is continued after the precharge period Tprch has elapsed, the DG-Tr3 is maintained in the OFF state, and the voltage VD of the drain line 42 becomes Holds charge voltage Vpg. As described above, the selection function for selecting the reading state of the DG-Tr 3 is realized by the application state of the voltage to the bottom gate line 41.
[0066]
The present invention is not limited to the above embodiment, and various improvements and design changes may be made without departing from the spirit of the present invention.
In the above embodiment, in order to prevent damage to the solid-state imaging device 1 due to static electricity charged on the subject, the electrostatic protection electrode 5 for discharging static electricity is provided on the protective insulating film 4, but it is shown in FIG. As described above, imaging may be performed by bringing a subject such as a fingertip into contact without the electrostatic protection electrode 5.
[0067]
In the above description, the present invention is applied to the method for inspecting the solid-state imaging device 1, but the present invention may be applied to the case of inspecting other devices.
For example, a device to be inspected includes a liquid crystal display panel, an organic EL display panel, a CCD image sensor, a CMOS image sensor, and the like.
[0068]
In the case of a liquid crystal display panel, examples of the electric element include a liquid crystal element including a liquid crystal layer and a pair of counter electrodes sandwiching the liquid crystal layer (at least one is a transparent electrode made of a metal oxide). In addition, a MOS transistor having a source electrode, a drain electrode, and a gate electrode (at least one of which is a transparent electrode made of a metal oxide) may be used.
[0069]
In the case of an organic EL display panel, the electric element is sandwiched between a pair of counter electrodes (at least one is a transparent electrode made of a metal oxide) and the counter electrodes, and is applied between the counter electrodes. An EL element including an organic compound layer that emits light at a high voltage, and a MOS transistor is also included.
[0070]
In the case of a CCD image sensor and a CMOS image sensor that are solid-state imaging devices, as an electrical element, a semiconductor such as a PN junction structure that is a light receiving portion and a pair of electrodes that sandwich the semiconductor (at least one of which is made of a metal oxide is transparent And a photodiode provided for each pixel.
[0071]
Moreover, although the electrode of the electric element to be observed was transparent, it may not be transparent. In this case, it is determined whether or not the electrode has been reduced by observing whether or not the color of the electrode has changed. In other words, when the color of an electrode changes by immersing a device with an electric element to be observed in an electrolyte, the device is defective, and when the color of the electrode does not change, the device is normal. It is a product. Furthermore, instead of judging the quality of the protective insulating film 4 by visual change, a voltage is applied between any two points of the conductive wiring 50 of the solid-state imaging device 1 taken out after being immersed in the electrolytic solution 102 and energized. Then, the quality of the protective insulating film 4 may be determined by measuring any one of resistance, current, and voltage and inspecting whether the resistance is increased due to corrosion caused by pinholes.
[0072]
And in the said embodiment, ITO etc. were used as an electrode of an electric element, and this was immersed in the processing tank 103 as a cathode, and the presence or absence of the pinhole of the protective insulating film 4 was confirmed, but ITO is oxidized more. Since the transmittance is increased and the resistivity is increased, a device having a higher transmittance by applying a voltage so that ITO under the protective insulating film 4 becomes an anode or a device having a higher resistance is regarded as defective. You may judge. An example of the transmittance is the transmittance with respect to light.
[0073]
If the electrode of the electric element is oxidized as a cathode, the electrode under the protective insulating film 4 is not limited to a transparent electrode. Even if it is opaque, the presence or absence of a pinhole can be determined only by measuring a change in electrical characteristics such as resistance. Can be confirmed.
[0074]
【The invention's effect】
According to the present invention, by immersing the protective film on the electrode in an electrolytic solution and applying a voltage to the electrode, it is possible to determine whether or not there is a change in the characteristics of the electrode due to defects in the protective film. A device having a defect and a device having no defect in the protective insulating film can be easily selected.
[Brief description of the drawings]
FIG. 1 is a plan view showing a solid-state imaging device to be inspected.
FIG. 2 (a) is a plan view showing one pixel of the solid-state imaging device, and FIG. 2 (b) is a cross-sectional view taken along the line AA.
3A is a cross-sectional view showing the II-II cross-section and the III-III cross-section of FIG. 1, and FIG. 3B is a cross-sectional view showing the IV-IV cross-section of FIG. FIG. 3C is a cross-sectional view showing the VV cross section of FIG.
FIG. 4 is a schematic diagram showing an oxidation-reduction apparatus used for inspecting the solid-state imaging device.
FIG. 5 is a plan view showing a form of the solid-state imaging device after a manufacturing process is further performed after the inspection.
6 (a) is a cross-sectional view showing a VII-VII cross section of FIG. 5, FIG. 6 (b) is a cross-sectional view showing a VIII-VIII cross section of FIG. 5, and FIG. ) Is a cross-sectional view showing an IX-IX cross section.
FIG. 7 is a plan view showing the solid-state imaging device in which an electrostatic protection electrode is formed on the surface and a driver is connected.
8A is a cross-sectional view showing the XX cross section of FIG. 7, FIG. 8B is a cross-sectional view showing the XI-XI cross section of FIG. 7, and FIG. ) Is a cross-sectional view showing a XI-XI cross section of FIG. 7.
9 is a cross-sectional view showing the DG-Tr shown in FIG.
[Explanation of symbols]
1 Solid-state imaging device (device)
2 Transparent substrate (substrate)
3 Double-gate transistor (electrical element)
21 Bottom gate electrode (another electrode)
27 Drain electrode (another electrode)
28 Source electrode (another electrode)
30 Top gate electrode (electrode)
101 power supply

Claims (6)

A substrate, a plurality of light receiving elements arranged in a matrix and having transparent electrodes, and a transparent protective film covering at least a part of the electrodes,
Immerse the protective film of a solid-state imaging device that acquires an image of a subject by directly contacting the protective film with an electrolyte, immerse a counter electrode in the electrolyte, and apply a voltage between the electrode and the counter electrode. And inspecting a visual change in which the transparent electrode becomes opaque . The device inspection method according to claim 1, wherein the light receiving element has an electrode different from the electrode, and the another electrode and the electrode are connected. The device inspection method according to claim 2, wherein the electrode and the other electrode of the light receiving element are insulated from each other after the inspection. Other portions device inspection method according to any one of claims 1 to 3, characterized in that it is exposed from the protective film of the electrode. As the electrode functions as a cathode, and, as the counter electrode functions as an anode, any one of 4 from claim 1, wherein applying a voltage between the electrode and the counter electrode The device inspection method according to 1. The device device inspection method according to any one of claims 1 to 5, comprising a plurality of said light receiving element, between the electrodes of the light receiving element is characterized by being connected to each other by wiring.

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