JP4510052B2 - Semiconductor integrated circuit device and duty control method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device and a duty control method. For example, the present invention relates to a clock duty control method in a processor core including a critical path that is active during a period when the clock is at “H” level and a critical path that is active during a period when it is “L”.

  In recent years, there has been a remarkable increase in the operation speed of semiconductor integrated circuits (LSIs). In order to increase the speed of this operation, a processor that operates in synchronization with both the rising edge and falling edge of the clock is widely used.

  In an LSI using a processor as described above, the duty of the clock greatly affects the operation, characteristics, yield, etc. of the LSI. Therefore, it is important to adjust the duty appropriately, and various proposals have been made for that purpose (for example, see Patent Documents 1 and 2).

However, the conventional method is not sufficient in terms of appropriately adjusting the duty. For this reason, it has been difficult to further improve the operating speed of an LSI operating at a high frequency.
JP 2005-159613 A JP 2004-088434 A

  The present invention provides a semiconductor integrated circuit device and a duty control method capable of improving the operation speed.

  A semiconductor integrated circuit device according to an aspect of the present invention operates in synchronization with a first clock, and is active during a period in which the first clock is at an “H” level, and an “L” level. A processor core including a second critical path that is active in a certain period, a first clock generation unit that generates a first clock by controlling a duty of a second clock input from the outside, and the first clock And a first phase difference from a third clock obtained by delaying the first clock by a delay time occurring in the first critical path, the first clock, and the first clock occurring in the second critical path. A second phase difference from the fourth clock obtained by delaying by the delay time is detected, and the duty is set so that the difference between the first phase difference and the second phase difference is minimized. To control the tee, and a control unit for instructing the first clock generator.

  A duty control method according to an aspect of the present invention is a duty control method of a first clock for operating a processor core, the step of generating the first clock based on a second clock input from the outside, Generating a third clock obtained by delaying the first clock by a delay time generated in a first critical path that is active in a period in which the first clock is at an “H” level in the processor core; and Generating a fourth clock delayed by a delay time generated in a second critical path that is active in a period in which the first clock is at an “L” level in the processor core; and the first clock and the third clock Detecting a first phase difference between the first clock and the fourth clock Detecting a second phase difference, the difference between the second phase difference between the first phase difference so as to minimize, and a step of controlling the duty of the first clock.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device and a duty control method capable of improving the operation speed.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor integrated circuit device and a duty control method according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an LSI according to this embodiment.

  As illustrated, the LSI 1 includes a processor core 2, a duty adjuster 3, and a control unit 4.

  The processor core 2 operates in synchronization with the first clock CLK1 generated by the duty adjuster 3. The processor core 2 includes a plurality of logic circuits including a flip-flop 10 and a combinational circuit 11. In these logic circuits, the one that becomes active while the first clock CLK1 is at “H” level, that is, the one that operates in synchronization with the rising timing of the first clock CLK1, and the first clock CLK1 that is “L”. And those that become active during a certain period, that is, those that operate in synchronization with the falling timing of the first clock CLK1. A critical path exists for each logic circuit that performs each operation. The critical path is a path (path) that takes the most time for signal propagation, and the operation speed of the processor core 2 is limited by the critical path. Hereinafter, a critical path for a path that is active during a period when the first clock CLK1 is at the “H” level is referred to as a first critical path 12. A critical path for a path that is active during a period when the first clock CLK1 is at the “L” level is referred to as a second critical path 13.

  The first and second critical paths 12 and 13 have predetermined delay times Δtd1 and Δtd2, respectively. That is, the first clock CLK1 is delayed by Δtd1 by passing through the first critical path 12, and is delayed by Δtd2 by passing through the second critical path 13. Hereinafter, the first clock CLK1 delayed by the first and second critical paths 12 and 13 will be referred to as a third clock CLK3 and a fourth clock CLK4, respectively.

  The duty adjuster 3 adjusts the duty of the second clock CLK2 given from the outside, and supplies this to the processor core 2 as the first clock CLK1. The duty is the ratio of the “H” level period in one cycle of the clock. The duty adjuster 3 controls the duty of the second clock CLK <b> 2 according to the control signal CNT given from the control unit 4. Note that the duty adjuster 3 in the present embodiment controls the duty by adjusting the falling timing of the second clock CLK2.

  The control unit 4 includes an inverter 20, a first phase comparison unit 21, a second phase comparison unit 22, a charge pump circuit 23, and a low pass filter 24. The inverter 20 inverts the first clock CLK1 generated by the duty adjuster 2. Hereinafter, for simplification of description, the output of the inverter 20 is referred to as a first clock / CLK1.

  The first phase comparison unit 21 detects a phase difference between the first clock / CLK1 and the third clock CLK3 output from the processor core 2, and outputs a first phase difference signal UP according to the detected phase difference. To do. More specifically, the first phase comparison unit 21 detects the phase difference between the rising timing of the first clock / CLK1 and the rising timing of the third clock CLK3, for example.

  The second phase comparison unit 22 detects a phase difference between the first clock CLK1 and the fourth clock CLK4 output from the processor core 2, and outputs a second phase difference signal DN according to the detected phase difference. . More specifically, the second phase comparison unit 22 detects the phase difference between the rising timing of the first clock CLK1 and the rising timing of the fourth clock CLK4, for example.

  The charge pump circuit 23 generates a voltage corresponding to the first and second phase difference signals UP and DN output from the first and second phase comparison units 21 and 22. This voltage is supplied to the duty adjuster 2 as the control signal CNT via the low-pass filter 24. In other words, the charge pump circuit 23 and the low-pass filter 24 convert the phase difference between the first clock CLK1, the third clock CLK3, and the fourth clock CLK4 into a voltage. The duty adjustment in the duty adjuster 2 is controlled by this voltage.

  Next, the details of the first clock CLK1, / CLK1, the third clock CLK3, the fourth clock CLK4, the first phase difference signal UP, and the second phase difference signal DN and the duty in the duty adjuster 2 will be described with reference to FIG. The adjustment method of will be described. FIG. 2 is a timing chart of the various signals.

  As shown in the drawing, the first clock CLK1 rises at time t1, falls at time t3, and rises again at time t5. That is, the period of one cycle is the length of time t1 to t5. Then, the length Δt_H during which the first clock CLK1 is at the “H” level is adjusted by the duty adjuster 2.

  The third clock CLK3 is a signal that rises with a delay of Δtd1 from the rising timing (time t1) of the clock CLK1. For example, the third clock CLK3 rises at time t2.

  The fourth clock CLK4 is a signal that rises with a delay of Δt2 from the falling timing (time t3) of the clock CLK1. For example, the fourth clock CLK4 rises at time t4.

  The first phase difference signal UP is “H” in a period from the rising timing (time t2) of the third clock CLK3 to the falling timing of the first clock CLK1, that is, the rising timing (time t3) of the first clock / CLK1. This is a level signal. This period is hereinafter referred to as Δt_UP.

  The second phase difference signal DN is a signal that becomes “H” level during a period from the rising timing (time t4) of the fourth clock CLK4 to the rising timing (time t5) of the first clock CLK1. This period is hereinafter referred to as Δt_DN.

  The duty adjuster 2 adjusts the Δt_H of the clock CLK1, that is, the duty so that the difference between Δt_UP and Δt_DN becomes a minimum value, preferably equal. That is, when Δt_UP <Δt_DN, Δt_H is increased (duty is increased). Conversely, when Δt_UP> Δt_DN, Δt_H is decreased (duty is decreased). The minimum value is a minimum value that can be set in the duty adjuster 2.

  Next, details of the duty adjustment method in the LSI having the above configuration will be described with reference to FIG. FIG. 3 is a flowchart of the duty adjustment method.

  As shown in the drawing, when the second clock CLK2 is first input from the outside, the duty adjuster 3 generates the first clock CLK1 based on it (step S10). The duty of the first clock CLK1 that is generated first may be the same as that of the second clock CLK2, or may be adjusted to a predetermined duty based on the control of the control unit 4.

  By supplying the first clock CLK1 from the duty adjuster 3 to the processor core 2, the third clock CLK3 is output from the first critical path 12, and the fourth clock CLK4 is output from the second critical path 13 (step S11). ). These are given to the first and second phase comparison units 21 and 22, respectively.

  Then, the first phase comparison unit 21 detects the phase difference between the first clock CLK1 (actually / CLK1) and the third clock CLK3 and outputs the first phase difference signal UP, and the second phase comparison unit 22 The phase difference between the first clock CLK1 and the fourth clock CLK4 is detected, and the second phase difference signal DN is output (step S12).

  If Δt_UP is smaller than Δt_DN (step S13, NO, step S14, YES), the charge pump circuit 23 and the low-pass filter 24 generate a control signal CNT for lengthening the period of “H” level by a predetermined width Δt. And output to the duty adjuster 3. Based on the control signal CNT, the duty adjuster 3 lengthens the period during which the second clock CLK2 is at the “H” level. That is, the duty of the first clock CLK1 is increased (step S15).

  On the other hand, if Δt_UP is larger than Δt_DN (step S13, NO, step S14, NO), the charge pump circuit 23 and the low-pass filter 24 control the control signal CNT to shorten the period during which the “H” level is set by the predetermined width Δt. Is output to the duty adjuster 3. Based on the control signal CNT, the duty adjuster 3 shortens the period during which the second clock CLK2 is at the “H” level. That is, the duty of the first clock CLK1 is reduced (step S16).

  Then, the process returns to step S10, and the above processing is repeated until Δt_UP = Δt_DN (step S13, YES).

  Note that the size of the predetermined width Δt in the above steps S15 and S16 may be constant at all times, may be reduced each time it is repeated, or small when the magnitude relationship between Δt_UP and Δt_DN is reversed. It may be a value.

  A specific example of the adjustment method will be described with reference to FIG. FIG. 4 is a timing chart of the first clock CLK1, the third clock CLK3, the fourth clock CLK4, the first phase difference signal UP, and the second phase difference signal DN at the time of adjusting the duty. It shows the case where is optimized. FIG. 4 shows a case where Δt is reduced when the magnitude relationship between Δt_UP and Δt_DN is reversed.

  As shown in the drawing, Δt_UP <Δt_DN is satisfied in the first clock CLK1 generated first based on the second clock CLK2 (step S14, YES). That is, in this state, the period during which the first clock CLK1 is at the “H” level is too short. This is the “initial state” in the figure.

  Therefore, the duty adjuster 3 next increases the period during which the first clock CLK1 is at the “H” level by Δt1. This is the “state after the first correction”. That is, the falling timing of the first clock CLK1 changes from time t3 to time t7. As a result of this correction, contrary to the initial state, Δt_UP> Δt_DN is satisfied (step S14, NO). That is, the period during which the first clock CLK1 is “L” is too short.

  Therefore, next, the duty adjuster 3 shortens the period during which the first clock CLK1 is at the “H” level by Δt2. This is the “state after the second correction”. That is, the falling timing of the first clock CLK1 changes from time t7 to time t10. Note that, since the magnitude relationship between Δt_UP and Δt_DN is inverted compared to when the state is shifted from the initial state to the first corrected state, the duty adjuster 3 sets the value of Δt2 to be smaller than Δt1. As a result of this correction, Δt_UP <Δt_DN is satisfied (step S14, YES). That is, the period during which the first clock CLK1 is “H” is too short.

  Therefore, next, the duty adjuster 3 lengthens the period during which the first clock CLK1 is at the “H” level by Δt3. This is the “state after the third correction”. That is, the falling timing of the first clock CLK1 changes from time t10 to time t13. Note that Δt3 <Δt2. As a result of this correction, Δt_UP = Δt_DN (step S13, YES). Therefore, the duty adjustment is completed, and thereafter the duty adjuster 3 generates the first clock CLK1 that is at the “H” level for the length of the period from the time t1 to the time t13.

As described above, with the duty adjustment method according to the first embodiment of the present invention, the following effect (1) can be obtained.
(1) The operation speed of the LSI can be improved.
According to the configuration of the present embodiment, the control unit 4 monitors the phase difference between the first clock CLK1 and the third clock CLK3, and further monitors the phase difference between the first clock CLK1 and the fourth clock CLK4. . Then, the control unit 4 instructs the duty adjuster 3 to adjust the duty so that both phase differences are equal. As a result, the operation speed of the LSI can be significantly improved. This effect will be described in detail below.

  As described in FIG. 2, Δt_UP is a period from when the third clock CLK3 rises to when the first clock CLK1 falls. The timing at which the third clock CLK3 rises is after the delay time in the first critical path 12 has elapsed since the first clock CLK1 rises. That is, in order for the first critical path 12 to operate normally, Δt_H of the first clock CLK1 must be at least equal to or greater than Δtd1. In other words, the phase difference Δt_UP between the first clock CLK1 and the third clock CLK3 means an operation margin of the first critical path 12 with respect to the first clock CLK1.

  Of course, a logic circuit that is active in the period when the first clock CLK1 is at “H” level in the processor core 2 does not operate correctly unless at least the first clock CLK1 in which the first critical path 12 operates normally. . This is because the path with the longest delay in these logic circuits is the first critical path 12.

  The same applies to Δt_DN. That is, in order for the second critical path 13 to operate normally, the “L” level period in one cycle of the first clock CLK1 must be at least equal to or longer than Δtd2. That is, the phase difference Δt_DN between the first clock CLK1 and the fourth clock CLK4 also means an operation margin of the second critical path 13 with respect to the first clock CLK1. A logic circuit that is active in the period when the first clock CLK1 is at the “L” level in the processor core 2 does not operate correctly unless at least the first clock CLK1 in which the second critical path 13 operates normally.

  In this regard, in the configuration according to the present embodiment, Δt_UP and Δt_DN are equalized by the control unit 4 (the minimum value is possible in the duty adjuster 3). Therefore, the frequency of the first clock CLK1 can be maximized. This is shown in FIG. FIG. 5 is a timing chart showing a situation when the frequency of the first clock CLK1 is increased in two cases (CASE1, CASE2). CASE1 is a case where Δt_UP << Δt_DN, and CASE2 is a case where Δt_UP = Δt_DN by the method according to the present embodiment.

  As shown in the figure, it is assumed that the period of one cycle of the first clock CLK1 is Δtc1. In both cases CASE1 and CASE2, the period during which the first clock CLK1 is at the “H” level must be equal to or greater than Δtd1, and the period during which the first clock CLK1 is at the “L” level must be equal to or greater than Δtd2.

  Then, in the case of CASE 1, while there is a sufficient operation margin (Δt_DN) in the “L” level period, there is almost no operation margin (Δt_UP) in the “H” level period. As a result, the frequency of the first clock CLK1 is limited to Δt_UP and can hardly be increased.

  On the other hand, in the case of CASE2, Δt_UP = Δt_DN. Accordingly, it is possible to set the period during which the first clock CLK1 is at the “H” level to Δtd1, and the period for which the “L” level is at Δtd2. That is, the frequency of the first clock CLK1 can be maximized (Δtc3 << Δtc2). Therefore, the operation speed of the LSI can be improved.

[Second Embodiment]
Next explained is a semiconductor integrated circuit device and a duty control method according to the second embodiment of the invention. In this embodiment, replica circuits of the first and second critical paths 12 and 13 are provided in the first embodiment. FIG. 6 is a block diagram of the LSI according to the present embodiment.

  As shown in the figure, the LSI 1 according to the present embodiment has a configuration in which a replica circuit 5 is provided in the configuration of FIG. 1 described in the first embodiment. In place of the processor core 2, the replica circuit 5 outputs the third clock CLK3 and the fourth clock CLK4.

The replica circuit 5 holds circuits similar to the first critical path 12 and the second critical path 13 in the processor core 2, that is, these replicas. In the figure, the first delay circuit 30 in the replica circuit 5 is a replica of the first critical path 12, and the second delay circuit 31 is a replica of the second critical path 13. The first clock CLK1 is input to the first and second delay circuits 30 and 31 by the duty adjuster 3. The first and second delay circuits 30 and 31 output the third and fourth clocks CLK3 and CLK4, respectively.
Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  Next, a duty adjustment method in the LSI according to the present embodiment will be described with reference to FIG. FIG. 7 is a flowchart of the duty adjustment method.

  As shown in the drawing, the difference from FIG. 3 described in the first embodiment is that the third clock CLK3 and the fourth clock CLK4 are generated by the first delay circuit 30 and the second delay circuit 31 ( Step S20). Others are the same as FIG.

As described above, in the duty adjustment method according to this embodiment, the following effect (2) can be obtained in addition to the effect (1) described in the first embodiment.
(2) The effect (1) can be obtained while maintaining the operational reliability of the LSI.
In the configuration according to this embodiment, the replica circuit 5 generates the third and fourth clocks CLK3 and CLK4 for use in the control unit 4. That is, the processor core 2 is unrelated to the operation of the control unit 4. Therefore, even if a failure or the like occurs in the control unit 4 for some reason, which causes an adverse effect on the replica circuit 5, the influence does not reach the processor core 2. For this reason, it is possible to prevent the operation of the processor core 2 from being hindered and to prevent the operation reliability of the LSI from being lowered.

  In the above embodiment, the case where the first and second delay circuits 30 and 31 are replicas of the first and second critical paths 12 and 13 has been described. However, the present invention is not limited to such a case. That is, the first and second delay circuits 30 and 31 may be provided in the replica circuit 5 separately from the replicas of the first and second critical paths 12 and 13. The first and second delay circuits 30 and 31 may be dedicated circuits for generating the third and fourth clocks CLK4 using the first and second critical paths 12 and 13, respectively.

[Third Embodiment]
Next explained is a semiconductor integrated circuit device and a duty control method according to the third embodiment of the invention. In this embodiment, replicas of the first and second critical paths 12 and 13 are provided in the first embodiment, and the duty is adjusted digitally. FIG. 8 is a block diagram of the LSI according to the present embodiment.

  As illustrated, the LSI 1 according to this embodiment includes a processor core 2, a duty adjuster 3, a control unit 4, and a replica circuit 5. The configuration of the processor core 2 is as described in the first embodiment. However, the processor core 2 does not need to output the third clock CLK3 and the fourth clock CLK4 to the outside. The configuration of the duty adjuster 3 is also as described in the first embodiment, and the duty is adjusted according to the control signal CNT given from the control unit 4. A specific duty adjustment method will be described later.

  As in the case of the second embodiment, the replica circuit 5 includes a replica of the first critical path 12 and a replica of the second critical path 13. Further, the replica circuit 5 includes a third delay circuit 32 and a fourth delay circuit 33. The third delay circuit 32 generates a fifth clock CLK5 based on the first clock CLK1. The fifth clock CLK5 is a signal obtained by delaying the first clock CLK1 by a time that is several percent longer than the delay time Δtd1 occurring in the first critical path 12. The fourth delay circuit 33 generates the sixth clock CLK6 based on the first clock CLK1. The sixth clock CLK6 is a signal obtained by delaying the first clock CLK1 by a time that is several percent longer than the delay time Δtd2 generated in the second critical path 13.

The control unit 4 includes an inverter 20, first and second phase comparison units 21 and 22, and a counter circuit 25. The inverter 20 inverts the first clock CLK1 as in the first embodiment.
The first phase comparator 21 detects a phase difference between the first clock / CLK1 and the fifth clock CLK5 output from the replica circuit 5, and outputs a first phase difference signal UP according to the detected phase difference. To do. More specifically, the first phase comparison unit 21 detects the phase difference between the rising timing of the first clock / CLK1 and the rising timing of the fifth clock CLK3, for example.
The second phase comparison unit 22 detects a phase difference between the first clock CLK1 and the sixth clock CLK6 output from the replica circuit 5, and outputs a second phase difference signal DN according to the detected phase difference. . More specifically, the second phase comparison unit 22 detects the phase difference between the rising timing of the first clock CLK1 and the rising timing of the sixth clock CLK6, for example.
The counter circuit 25 counts the first phase difference signal UP output from the first phase comparison unit 21 and the second phase difference signal DN output from the second phase comparison unit 22 at each step during duty adjustment. . Then, a control signal CNT for controlling the duty adjuster 3 is output according to which of the first phase difference signal UP and the second phase difference signal DN is counted.

  Next, the details of the first clock CLK1, / CLK1, the fifth clock CLK5, the sixth clock CLK6, the first phase difference signal UP, and the second phase difference signal DN and the duty adjuster will be described with reference to FIGS. The method for adjusting the duty in 2 will be briefly described. 9 and 10 are timing charts of the various signals.

  First, the case of FIG. 9 will be described. As shown, the first clock CLK1 rises at time t1, falls at time t2, and rises again at time t5. That is, the period of one cycle is the length of time t1 to t5. The length Δt_H of the period during which the first clock CLK1 is at the “H” level is adjusted by the duty adjuster 2.

  The fifth clock CLK5 is a signal that rises with a delay of (Δtd1 + C1 · Δtd1) from the rising timing (time t1) of the first clock CLK1. For example, C1 = about 0.01 to 0.09, and the fifth clock CLK5 rises at time t3. That is, for example, if C1 = 0.01, the fifth clock CLK5 is a signal that rises with a delay time that is 1% greater than Δtd1 from the rise of the first clock CLK1.

  The sixth clock CLK6 is a signal that rises with a delay of (Δtd2 + C2 · Δtd2) from the falling timing (time t2) of the first clock CLK1. For example, C2 = about 0.01 to 0.09, and the sixth clock CLK6 falls at time t4. That is, for example, if C2 = 0.01, the sixth clock CLK6 is a signal that rises with a delay time larger by 1% than Δtd2 from the fall of the first clock CLK1.

  The first phase difference signal UP is “H” at the falling timing of the first clock when the falling timing of the first clock (that is, the rising timing of the first clock / CLK1) is earlier than the rising timing of the fifth clock CLK5. It is a signal that becomes “level”. Accordingly, in the case of FIG. 9, the first phase difference signal UP rises at time t2. The first phase difference signal UP falls to the “L” level at the rising timing of the first clock (that is, the falling timing of the first clock / CLK1). The period during which the first phase difference signal UP is at the “H” level is hereinafter referred to as Δt_UP.

The second phase difference signal DN is a signal that becomes “H” level at the rising timing of the first clock when the rising timing of the first clock is earlier than the rising timing of the sixth clock CLK6. Therefore, in the case of FIG. 9, the second phase difference signal DN is always at the “L” level.

  Next, the case of FIG. 10 will be described. FIG. 10 shows a case where the second phase difference signal DN is at the “H” level, contrary to the case of FIG. As shown in the figure, the first clock CLK1 rises at time t1, falls at time t3, and rises again at time t4.

  The fifth clock CLK5 rises before the first clock CLK1 falls (time t2). The sixth clock CLK6 rises later than the rising timing of the first clock CLK1 (time t5). As a result, the first phase difference signal UP is always at “L” level. On the other hand, the second phase difference signal DN becomes “H” level at the rising timing (time t4) of the first clock CLK1. The second phase difference signal DN falls to “L” level at the fall timing of the first clock. Hereinafter, the period during which the second phase difference signal DN is at the “H” level is referred to as Δt_DN.

  The duty adjuster 2 lengthens Δt_H of the clock CLK1 when UP = “H” (increases the duty), and decreases Δt_H when DN = “H” (decreases the duty).

  Next, details of the duty adjustment method of the LSI according to the present embodiment will be described with reference to FIG. FIG. 11 is a flowchart of the duty adjustment method.

  As shown in the figure, first, a first clock CLK1 is generated (step S10). By supplying the first clock CLK1 from the duty adjuster 3 to the processor core 2, the fifth clock CLK5 is output from the third delay circuit 32, and the sixth clock CLK6 is output from the fourth delay circuit 33 (step S30). ). These are given to the first and second phase comparison units 21 and 22, respectively.

  Then, the first phase comparison unit 21 detects the phase difference between the first clock CLK1 (actually / CLK1) and the third clock CLK3. If the falling timing of the first clock CLK1 is earlier than the rising timing of the fifth clock CLK5, the first phase difference signal UP is set to the “H” level. The second phase comparison unit 22 detects the phase difference between the first clock CLK1 and the sixth clock CLK6. If the rising timing of the first clock CLK1 is earlier than the rising timing of the sixth clock CLK6, the second phase difference signal DN is set to the “H” level (step S31).

  If the first phase difference signal UP is “H” level, that is, if DN = “L” (step S32, NO, step S33, YES), the fact is counted by the counter circuit 25. That is, the count number for the first phase difference signal UP is counted up. Then, the counter circuit 25 generates a control signal CNT for increasing the period of “H” level by a predetermined width Δt, and outputs the control signal CNT to the duty adjuster 3. Based on the control signal CNT, the duty adjuster 3 lengthens the period during which the second clock CLK2 is at the “H” level. That is, the duty of the first clock CLK1 is increased (step S15).

  On the contrary, if the first phase difference signal DN is “H” level, that is, if UP = “L” (step S32, NO, step S33, NO), the fact is counted by the counter circuit 25. That is, the count number for the second phase difference signal DN is counted up. Then, the counter circuit 25 generates a control signal CNT for shortening the period during which the “H” level is set by a predetermined width Δt, and outputs the control signal CNT to the duty adjuster 3. Based on the control signal CNT, the duty adjuster 3 shortens the period during which the second clock CLK2 is at the “H” level. That is, the duty of the first clock CLK1 is reduced (step S16).

  Then, the process returns to step S10, and the above processing is repeated until both the first and second phase difference signals UP and DN become “L” level (YES in step S32).

  The predetermined width Δt in steps S15 and S16 is always constant. Of course, Δt may be changed each time duty adjustment is repeated.

  Specific examples of the adjustment method will be described below, divided into a case where the duty is optimized by increasing Δt_H (CASE 1) and a case where the duty is optimized by reducing Δt_H (CASE 2).

(CASE1)
First, CASE 1 will be described with reference to FIG. FIG. 12 is a timing chart of the first clock CLK1, the fifth clock CLK5, the sixth clock CLK6, the first phase difference signal UP, and the second phase difference signal DN at the time of adjusting the duty. It shows the case where is optimized. FIG. 12 shows a case where Δt in steps S15 and S16 is constant Δt4. Also, (Δtd1 + C1 · Δtd1) is expressed as Δtd3, and (Δtd2 + C2 · Δtd2) is expressed as Δtd4.

  As shown in the figure, the first clock CLK1 generated first based on the second clock CLK2 falls before the rising timing (time t3) of the fifth clock CLK5 (time t2). Accordingly, the first phase difference signal UP = "H" and the second phase difference signal DN = "L" (step S33, YES). That is, in this state, the period during which the first clock CLK1 is at the “H” level is too short. This is the “initial state” in the figure.

  Therefore, the duty adjuster 3 next increases the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the first correction”. That is, the falling timing of the first clock CLK1 changes from time t2 to time t6. However, the falling timing (time t6) of the first clock CLK1 is still earlier than the rising timing (time t3) of the fifth clock CLK5. Accordingly, the first phase difference signal UP = "H" and the second phase difference signal DN = "L" (step S33, YES). That is, in this state, the period during which the first clock CLK1 is at the “H” level is still too short.

  Therefore, the duty adjuster 3 further increases the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the second correction”. That is, the falling timing of the first clock CLK1 changes from time t2 to time t8. However, the falling timing (time t8) of the first clock CLK1 is still earlier than the rising timing (time t3) of the fifth clock CLK5. Accordingly, the first phase difference signal UP = "H" and the second phase difference signal DN = "L" (step S33, YES). That is, in this state, the period during which the first clock CLK1 is at the “H” level is still too short.

  Therefore, the duty adjuster 3 further increases the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the third correction”. That is, the falling timing of the first clock CLK1 changes from time t2 to time t3. As a result, the falling timing of the first clock CLK1 coincides with the rising timing (time t3) of the fifth clock CLK5. Accordingly, the first phase difference signal UP = "L" and the second phase difference signal DN = "L" (step S32, YES). Thus, the duty adjustment is completed, and thereafter, the duty adjuster 3 generates the first clock CLK1 that is at the “H” level for the length of the period from the time t1 to the time t3.

  In the state after the third correction in FIG. 12, the falling timing of the first clock CLK1 is simultaneous with the rising timing of the fifth clock CLK5, but may be later than the rising timing of the fifth clock CLK5. Needless to say.

(CASE2)
Next, CASE 2 will be described with reference to FIG. FIG. 13 is a timing chart of the first clock CLK1, the fifth clock CLK5, the sixth clock CLK6, the first phase difference signal UP, and the second phase difference signal DN at the time of adjusting the duty. It shows the case where is optimized. FIG. 13 also shows the case where Δt in steps S15 and S16 is constant Δt4, as in FIG. Also, (Δtd1 + C1 · Δtd1) is expressed as Δtd3, and (Δtd2 + C2 · Δtd2) is expressed as Δtd4.

  As illustrated, the first clock CLK1 generated first based on the second clock CLK2 falls after the rising timing (time t3) of the fifth clock CLK5 (time t2), and the rising of the sixth clock CLK6. It rises before the timing (time t5) (time t4). Therefore, the first phase difference signal UP = “L” and the second phase difference signal DN = “H” (step S33, NO). That is, in this state, the period during which the first clock CLK1 is at the “H” level is too long. This is the “initial state” in the figure.

  Therefore, the duty adjuster 3 shortens the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the first correction”. That is, the falling timing of the first clock CLK1 changes from time t3 to time t6. However, the rising timing (time t4) of the first clock CLK1 is still earlier than the rising timing (time t7) of the sixth clock CLK6. Therefore, the first phase difference signal UP = “L” and the second phase difference signal DN = “H” (step S33, NO). That is, in this state, the period during which the first clock CLK1 is at the “H” level is still too short.

  Therefore, next, the duty adjuster 3 further reduces the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the second correction”. That is, the falling timing of the first clock CLK1 changes from time t6 to time t8. However, the rising timing (time t4) of the first clock CLK1 is still earlier than the rising timing (time t9) of the sixth clock CLK6. Therefore, the first phase difference signal UP = “L” and the second phase difference signal DN = “H” (step S33, NO). That is, in this state, the period during which the first clock CLK1 is at the “H” level is still too long.

  Therefore, the duty adjuster 3 further reduces the period during which the first clock CLK1 is at the “H” level by Δt4. This is the “state after the third correction”. That is, the falling timing of the first clock CLK1 changes from time t8 to time t10. As a result, the rising timing of the first clock CLK1 coincides with the rising timing (time t4) of the sixth clock CLK6. Accordingly, the first phase difference signal UP = "L" and the second phase difference signal DN = "L" (step S32, YES). Therefore, the duty adjustment is completed, and thereafter the duty adjuster 3 generates the first clock CLK1 that is at the “H” level for the length of the period from the time t1 to the time t10.

As described above, with the duty adjustment method according to this embodiment, the effects (1) and (2) described in the first and second embodiments can be obtained.
In the method according to this embodiment, unlike the first embodiment, the operation margin related to the first critical path 12 and the operation margin related to the second critical path 13 are not necessarily the same. This is because, in the present embodiment, the duty adjustment ends when the “H” level period of the first clock CLK1 becomes Δtd3 or more or the “L” level period becomes Δtd4 or more.

  However, Δtd3 is a certain value larger than the delay time Δtd1 of the first critical path 12, and Δtd4 is a certain value larger than the delay time Δtd2 of the second critical path 13. Therefore, when the frequency of the first clock CLK1 is increased, the period of one cycle of the first clock CLK1 can be shortened at least to the certain period. Therefore, the operation speed of the LSI can be improved.

  In the present embodiment, the case where the third delay circuit 32 and the fourth delay circuit 33 are provided in the replica circuit 5 has been described. However, a configuration in which the replica circuit 5 is not provided may be used as in the first embodiment. The configuration of the LSI 1 in this case is shown in FIG. As illustrated, the third delay circuit 32 and the fourth delay circuit 33 are provided in the processor core 2. The fifth clock CLK5 and the sixth clock CLK6 are output from the processor core 2.

  As described above, in the semiconductor integrated circuit device and the duty control method according to the first to third embodiments of the present invention, the processor core is operated using information given from the critical path in the processor core. The clock duty is optimized.

  More specifically, the delay time Δtd1 of the first critical path 12 that is active while the clock is at “H” level, and the delay time Δtd2 of the second critical path 13 that is active when the clock is “L” level. And are used. In the first and second embodiments, the operation margin (Δt_H−Δtd1) for the first critical path 12 and the operation margin (“L” level period−Δtd2) for the second critical path 13 are equal. So that the duty is adjusted. In the third embodiment, either the operation margin (C1 · Δtd1) given to the first critical path 12 or the operation margin (C1 · Δtd2) given to the second critical path 13 is selected. The duty is adjusted to satisfy Therefore, the clock frequency can be improved and the operation of the processor core can be speeded up.

  Further, the above-described duty control is performed by the control unit 4. Therefore, the clock duty can be dynamically changed. That is, even after the LSI 1 is manufactured, the duty can be adjusted as appropriate. As a result, even if variations occur during the manufacturing process of the LSI 1, the deterioration of the duty caused by the variations can be corrected by the control unit 4. When the duty cannot be adjusted dynamically as in the prior art, the duty may not be optimal due to process variations. In order to optimally correct all the chips, the evaluation result of the critical path for each chip must be fed back to the chip design, and the test time becomes very long. This is particularly noticeable when both a circuit that is active during the “H” level period of the clock and a circuit that is active during the “L” level period are included. However, with the configuration according to the present embodiment, the duty can be optimized even after the chip is manufactured. As a result, the yield of the chip can be improved and the test time can be shortened, so that the manufacturing cost can be reduced. Further, since the duty can be adjusted even during the operation of the LSI 1, the duty can be optimized in accordance with fluctuations in operating conditions such as ambient temperature and operating voltage. As a result, the performance of the LSI 1 can be optimized regardless of the operating conditions.

  In particular, the above-described embodiment can achieve a remarkable effect when applied to, for example, a semiconductor memory using a DDR (Double Data Rate) mode, a microprocessor whose timing is designed using a very high frequency clock, and the like.

  In the first and second embodiments, the first and second phase comparison units 21 and 22 determine the rising timings of the first clocks CLK1 and / CLK1 and the rising timings of the third and fourth clocks CLK3 and CLK4. Comparing. In the third embodiment, the rising timings of the first clocks CLK1 and / CLK1 are compared with the rising timings of the fifth and sixth clocks CLK5 and CLK6. However, the rising timing and the falling timing may be compared, or the falling timings may be compared. That is, the third to sixth clocks CLK3 to CLK6 may be any signals that are delayed and inverted by Δtd1 to Δtd4 with respect to the first clock CLK1. Furthermore, in other words, the third and fourth clocks CLK3 and CLK4 may be signals that can understand the length of delay in the first and second critical paths 12 and 13. Further, the fifth and sixth clocks CLK5 and CLK6 only need to be signals that can understand the length of time in which the delay length in the first and second critical paths 12 and 13 and the operation allowance time are combined. Of course, the duty adjuster 3 is not limited to the one that adjusts the falling timing of the clock, but may be one that adjusts the rising timing, or that adjusts both the rising timing and the falling timing.

  Further, the duty adjustment described in the above embodiment is not necessarily performed inside the LSI 1. That is, the control unit 4 may not be in the LSI 1. Such a configuration is shown in FIG. FIG. 15 is a block diagram showing a state of the test process of the LSI 1 before shipment. As shown in the figure, the LSI 1 is connected to the duty control controller 6 in the test process. The duty control controller 6 includes the configuration of the control unit 4 described in the first and third embodiments. Then, the control signal CNT is generated using the third clock CLK3 and the fourth clock CLK4, or the fifth clock CLK5 and the sixth clock CLK6 output from the LSI 1, and the duty of the LSI 1 is controlled.

  In the third embodiment, the fifth clock CLK5 rises with a delay of Δtd3 from the rise of the first clock CLK1. The sixth clock CLK6 rises with a delay of Δtd4 from the fall of the first clock CLK1. Δtd3 is obtained by adding C1 · Δtd1 to the delay time td1 in the first critical path 12, and Δtd4 is obtained by adding C2 · Δtd2 to the delay time td2 in the second critical path 13. The values of C1 and C2 can be selected as appropriate, and both C1 and C2 may be the same value or different values. In addition, the delay times Δtd1 and Δtd2 generated in the first and second critical paths 12 and 13 are not constant values, but dynamically vary depending on the operating environment such as voltage and temperature. Therefore, even if duty correction is performed using Δtd1 and Δtd2 under certain conditions (voltage and temperature), the duty correction performed with Δtd1 and Δtd2 may not be sufficient under different continuous conditions. Therefore, sufficient duty correction can be performed by adding C1 · Δtd1 and C2 · Δtd2 to Δtd1 and Δtd2 respectively as the plus alpha portion of the delay time that dynamically varies depending on the operating environment.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of an LSI according to a first embodiment of the present invention. 4 is a timing chart of various signals used in the LSI according to the first embodiment of the present invention. The flowchart of the duty control method which concerns on 1st Embodiment of this invention. The timing chart of the various signals at the time of execution of the duty control method concerning a 1st embodiment of this invention. The timing chart of the 1st clock in the case where it does not use the case where the duty control method concerning a 1st embodiment of this invention is used. The block diagram of LSI concerning the 2nd Embodiment of this invention. The flowchart of the duty control method which concerns on 2nd Embodiment of this invention. The block diagram of LSI concerning the 3rd Embodiment of this invention. 10 is a timing chart of various signals used in an LSI according to a third embodiment of the invention. 10 is a timing chart of various signals used in an LSI according to a third embodiment of the invention. The flowchart of the duty control method which concerns on 3rd Embodiment of this invention. The timing chart of the various signals at the time of duty control method execution concerning a 3rd embodiment of this invention. The timing chart of various signals at the time of execution of the duty control method concerning a 3rd embodiment of this invention. The block diagram of LSI which concerns on the modification of the 3rd Embodiment of this invention. The block diagram of LSI which concerns on the modification of the 1st thru | or 3rd embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... LSI, 2 ... Processor core, 3 ... Duty regulator, 4 ... Control part, 5 ... Replica circuit, 6 ... Duty control controller, 10 ... Flip-flop, 11 ... Combination circuit, 12, 13 ... Critical path, 20 ... Inverter, 21, 22 ... Phase comparator, 23 ... Charge pump circuit, 24 ... Low pass filter, 25 ... Counter circuit, 30-33 ... Delay circuit

Claims (5)

A first critical path that operates in synchronization with the first clock and becomes active when the first clock is at the “H” level, and a second critical path that is active when the first clock is at the “L” level. A processor core,
A first clock generator for controlling the duty of a second clock input from the outside to generate the first clock;
A first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time occurring in the first critical path, the first clock, and the first clock being the second clock The second phase difference from the fourth clock obtained with a delay by a delay time occurring in the critical path is detected, and the duty is controlled so that the difference between the first phase difference and the second phase difference is minimized. And a control unit that commands the first clock generation unit. The controller generates a first pulse corresponding to a period from a rising timing of the third clock to a rising timing of an inverted signal of the first clock;
A second phase difference detector that generates a second pulse corresponding to a period from the rising timing of the fourth clock to the rising timing of the first clock;
A conversion unit that converts a difference between the pulse width of the first pulse and the pulse width of the second pulse into a voltage, and the control unit controls the duty according to the voltage obtained by the conversion unit. The semiconductor integrated circuit device according to claim 1. A replica circuit of the first and second critical paths;
The semiconductor integrated circuit device according to claim 1, wherein the control unit detects the first and second phase differences using the third and fourth clocks generated by the replica circuit. A first critical path that operates in synchronization with the first clock and becomes active when the first clock is at the “H” level, and a second critical path that is active when the first clock is at the “L” level. A processor core,
A first clock generator for controlling the duty of a second clock input from the outside to generate the first clock;
A third clock generator for generating a third clock indicating a timing delayed by a delay time larger than the delay time generated in the first critical path from the rising edge of the first clock;
A fourth clock generator for generating a fourth clock indicating a timing delayed by a delay time larger than the delay time generated in the second critical path from the falling edge of the first clock;
The phase difference between the first clock and the third clock and the phase difference between the first clock and the fourth clock are detected, and the duty is controlled so that any one of the phase differences is minimized. And a control unit that commands the first clock generation unit. A duty control method of a first clock for operating a processor core,
Generating the first clock based on a second clock input from the outside;
Generating a third clock obtained by delaying the first clock by a delay time generated in a first critical path that is active in a period in which the first clock is at an “H” level in the processor core;
Generating a fourth clock obtained by delaying the first clock by a delay time generated in a second critical path that is active in a period in which the first clock is at an “L” level in the processor core;
Detecting a first phase difference between the first clock and the third clock;
Detecting a second phase difference between the first clock and the fourth clock;
Controlling the duty of the first clock so that the difference between the first phase difference and the second phase difference is minimized.

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