JP4517846B2 - Write circuit for magnetic memory device and magnetic memory device - Google Patents

Description

  The present invention relates to a write circuit for a magnetic memory device having a memory cell including a magnetoresistive effect body and capable of recording and reading information, and a magnetic memory device having the write circuit for the magnetic memory device It is about.

  As this type of magnetic memory device, a magnetic memory device disclosed in Japanese Patent Application Laid-Open No. 2004-178623 already proposed by the present applicant is known. This magnetic memory device is a magnetic random access memory (hereinafter also referred to as “MRAM: Magnetic Random Access Memory”), and includes a plurality of recording cells each including a pair of magnetoresistive elements and a pair of backflow prevention diodes. Dimensionally arranged. In this case, the binarized information is stored in each memory cell by increasing the resistance value of one of the pair of magnetoresistive elements as compared with the other.

In this magnetic memory device, an X-direction current drive circuit as one write circuit included in the X-direction current drive circuit group and a Y-circuit as one write circuit included in the Y-direction current drive circuit group. As a result of selecting the directional current drive circuit, the write current is supplied to the write bit line and the write word line to which the selected X direction current drive circuit and Y direction current drive circuit are connected, respectively. Information is stored in a memory cell arranged at an intersection of the write bit line and the write word line among the plurality of memory cells included in the memory cell group. In this case, the X-direction current drive circuit and the Y-direction current drive circuit are configured using transistors Q1 to Q8 and resistors R1 to R4 as shown in FIG.
JP 2004-178623 A

  However, as a result of further examination of the above-described conventional write circuit for a magnetic memory device, the inventors have found the following points to be improved. That is, when increasing the number of storage cells included in the memory cell group in order to increase the storage capacity of the magnetic memory device, it is necessary to increase the degree of integration of the recording cell group. As a result of inevitably reducing the line width of the line and the word line for writing, the resistance values of the bit line for writing and the word line for writing increase. Specifically, each resistance value that was less than 1000Ω increases to a range of 1000Ω to 1500Ω. However, in this magnetic memory device write circuit, the potential difference between the drive points to which the write bit line (and write word line) is connected is not so large, so the write bit line (and write) When the resistance value of the write word line increases, it becomes difficult to supply a write current of a specified value to the write bit line (and the write word line). Therefore, in this magnetic memory device write circuit, as indicated by the symbol T in FIG. 4, a write current having a specified value (with a resistance value within a range W of 1000Ω to 1500Ω is applied to the write line ( In the figure, about 1100 mA) cannot be supplied. Therefore, it is preferable that this magnetic memory device write circuit can supply a write current having a specified value to a write bit line (and a write word line) having a larger resistance value.

  The present invention has been made to solve such a problem, and a write circuit for a magnetic memory device and a magnetic memory device capable of supplying a write current having a specified value even to a write line having a larger resistance value. The main purpose is to provide

  In order to achieve the above object, a magnetic memory device writing circuit according to the present invention is disposed close to a pair of magnetoresistive effect members in a recording cell and one end thereof is connected to each other. A first current control circuit that controls a write current flowing in a write line having a pair of lines to a constant value, and an open-side end on the other end side of one of the pair of lines. And a first transistor that supplies the write current to the write line from the open end in the on state, and an open end on the other end of the other line of the pair of lines. And a second transistor that supplies the write current from the open end to the write line in the on state, and is connected to the open end of the one line and by the second transistor. Supply A third transistor that outputs the write current to the first current control circuit in an on state, and is connected to the open-side end of the other line and is turned on / off of the third transistor. A fourth transistor that is controlled to an on / off state opposite to the off state and outputs the write current supplied by the first transistor to the first current control circuit in the on state; The fifth and sixth transistors whose output terminals are connected to each other, and a second current control circuit that controls a total value of currents flowing through the fifth and sixth transistors to a constant value, When the third transistor is turned on and the fourth transistor is turned off, the fifth transistor and the sixth transistor are The first transistor and the second transistor are shifted to the off state and the on state, respectively, by shifting to the off state and the on state, respectively, the fourth transistor is shifted to the on state, and the third When the fifth transistor and the sixth transistor shift to the off state, the fifth transistor and the sixth transistor shift to the on state and the off state, respectively, thereby turning the first transistor and the second transistor on and off, respectively. A differential amplifier circuit to be shifted to a state; and disposed between the open side end of the one line and the control terminal of the fifth transistor, from the first transistor via the open side end. A first unidirectional element that allows passage of current toward the control terminal and the other line. A second terminal disposed between the open-side end and the control terminal of the sixth transistor and allowing a current to pass from the second transistor to the control terminal via the open-side end. Unidirectional element. In the present invention, the “transistor” is a concept including a bipolar transistor and a field effect transistor. The “control terminal” means a base terminal in a bipolar transistor and a gate terminal in a field effect transistor. The “output terminal” means an emitter terminal in a bipolar transistor, and a source terminal in a field effect transistor.

  In this case, the first unidirectional element and the second unidirectional element can be formed of diodes.

  A silicon diode can be adopted as the diode.

  Further, as the first unidirectional element, a transistor disposed between the first transistor and the fifth transistor and connected as an emitter follower is adopted, and as the second unidirectional element, A transistor disposed between the second transistor and the sixth transistor and connected in an emitter follower can be employed.

  The magnetic memory device according to the present invention is provided with a recording cell having a pair of magnetoresistive effect members whose resistance values are changed by an external magnetic field, and in close proximity to the pair of magnetoresistive effect members. A write line having a pair of lines whose one ends are connected to each other, a first current control circuit for controlling a write current flowing in the write line to a constant value, and the pair of lines A first transistor that is connected to an open end on the other end of the one line and supplies the write current from the open end to the write line in an ON state; and A second transistor connected to the open end of the other line of the other line and capable of supplying the write current from the open end to the write line in the on state; Said opening in the track A third transistor connected to a side end and supplying the write current supplied by the second transistor to the first current control circuit in an ON state; and the open side of the other line The write current supplied by the first transistor is connected to the end portion and controlled to be on / off state opposite to the on / off state of the third transistor. The fourth transistor supplied to the first current control circuit, the fifth and sixth transistors whose output terminals are connected to each other, and the total value of the currents flowing through the fifth and sixth transistors are controlled to a constant value. And the third transistor is turned on, and the fourth transistor is turned off. Sometimes, the fifth transistor and the sixth transistor shift to an off state and an on state, respectively, thereby causing the first transistor and the second transistor to shift to an off state and an on state, respectively. When the first transistor is turned on and the third transistor is turned off, the fifth transistor and the sixth transistor are turned on and off, respectively. And a differential amplifier circuit for switching the second transistor to an on state and an off state, respectively, and disposed between the open-side end portion of the one line and the control terminal of the fifth transistor, and Electricity from the first transistor to the control terminal via the open end. A first unidirectional element that allows passage of current; and the open side end of the other line and the control terminal of the sixth transistor, the open side from the second transistor. And a second unidirectional element that allows passage of current toward the control terminal via the side end portion.

  In this case, the first unidirectional element and the second unidirectional element can be formed of diodes.

  A silicon diode can be adopted as the diode.

  Further, as the first unidirectional element, a transistor disposed between the first transistor and the fifth transistor and connected as an emitter follower is adopted, and as the second unidirectional element, A transistor disposed between the second transistor and the sixth transistor and connected in an emitter follower can be employed.

  According to the magnetic memory device writing circuit and the magnetic memory device including the magnetic memory device writing circuit according to the present invention, the open-side end portion of one of the write lines and the control terminal of the fifth transistor Between the first transistor and the first unidirectional element that allows current to flow from the first transistor to the control terminal via the open end, and the open end of the other line By disposing a second unidirectional element that allows passage of current from the second transistor toward the control terminal via the open-side end portion between the control terminal of the sixth transistor, for example, When the first transistor is in the off state and the second transistor is in the on state, the second unidirectional element is present, so that the second unidirectional element is compared with the second unidirectional element. Transistor output The potential of the control terminal of the sixth transistor (base potential in the case of a bipolar transistor) relative to the potential of the child (the open side end of the other line) is made lower by the voltage drop of the second unidirectional element. It can be a potential. Accordingly, since the base current of the sixth transistor can be reduced when the fifth transistor is in the off state and the sixth transistor is in the on state, the second transistor is controlled by the second current control circuit. In the situation where the total value of each output current (collector current in the case of a bipolar transistor) and each control current (base current in the case of a bipolar transistor) is controlled to be constant, Unlike the normal operation (the operation in which the collector current increases as the base current increases), the collector current of the sixth transistor can be increased. As a result, the first transistor can be brought into a deeper off state. For example, the write line becomes thin and the resistance increases to some extent, and accordingly, the write line flows due to the write current flowing therethrough. As a result, the first transistor can be reliably maintained in the off state even if the voltage drop at the first transistor increases and the output potential of the first transistor (the emitter potential in the case of a bipolar transistor) decreases. Can be supplied with a predetermined write current. Similarly, a write current having a specified current value can be supplied to the write line even when the first transistor is on and the second transistor is off.

  Therefore, according to this magnetic memory device, in order to increase the storage capacity, the number of memory cells included in each row or each column of the memory cell group is increased, and as a result, the resistance value of the write line is increased. However, it is possible to supply a write current of a specified value to the write line. For this reason, as a result of being able to apply a sufficient magnetic field to each memory cell, the information of the corresponding bit can be reliably stored in each memory cell.

  According to the magnetic memory device writing circuit and the magnetic memory device having the magnetic memory device writing circuit according to the present invention, the first unidirectional element and the second unidirectional element are diodes or Although it is configured with an emitter-follower-connected transistor, the potential of the control terminal of the fifth transistor in the on state of the first transistor and the potential of the sixth transistor in the on state of the second transistor are simplified. The potential of the control terminal can be lowered.

  Furthermore, according to the write circuit for a magnetic memory device and the magnetic memory device provided with the write circuit for the magnetic memory device according to the present invention, by using a silicon diode as a diode, it is compared with a Schottky diode or a germanium diode. Since the forward voltage drop is large, the potentials of the control terminals of the fifth and sixth transistors can be sufficiently lowered, and the resistance value of the write line is larger (the line width is narrower). Even in the configuration, the write current of the specified value can be reliably supplied.

  Hereinafter, the best mode of a magnetic memory device according to the present invention will be described with reference to the accompanying drawings.

  First, the configuration of a magnetic memory device M according to the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the magnetic memory device M includes an address buffer 11, a data buffer 12, a control logic unit 13, a memory cell group 14, a Y-direction drive control circuit unit 21, and an X-direction drive control circuit unit 31. . In this case, the Y-direction drive control circuit unit 21 includes a Y-direction address decoder circuit 22, a read circuit group 23, and a Y-direction current drive circuit group 24. On the other hand, the X direction drive control circuit unit 31 includes an X direction address decoder circuit 32, a constant current circuit group 33, and an X direction current drive circuit group 34. In the magnetic memory device M, data (input via the data buffer 12) is input to the memory cell group 14, the read circuit group 23, the Y-direction current drive circuit group 24, the constant current circuit group 33, and the X-direction current drive circuit group 34. The number of bits is equal to the number of bits (eight in this example as an example), and when the predetermined data is stored in the predetermined address specified by the address input via the address buffer 11, the predetermined data is stored. Information (“1” or “0”) of each bit constituting data is configured to be stored in one memory cell 1 of this predetermined address in the memory cell group 14 corresponding to each bit. Each component included in the magnetic memory device M is operated by a DC voltage Vcc supplied from a DC voltage source between the power supply terminal PW and the ground terminal GND.

  The address buffer 11 includes external address input terminals A0 to A20, and an address signal (for example, a higher-order address signal among the address signals) fetched from the external address input terminals A0 to A20 is transmitted via the Y-direction address bus 15 to the Y-direction address bus 15. In addition to outputting to the direction address decoder circuit 22, an address signal (for example, a lower address signal of the address signals) is output to the X direction address decoder circuit 32 via the X direction address bus 16.

  The data buffer 12 includes external data terminals D0 to D7, an input buffer 12a, and an output buffer 12b. The data buffer 12 is connected to the control logic unit 13 via the control signal line 13a. In this case, the input buffer 12a is connected to each X-direction current drive circuit group 34 via the X-direction write data bus 17, and each Y-direction current drive circuit via the Y-direction write data bus 18. Information of each bit included in the data input via the external data terminals D0 to D7 is connected to the group 24 and stored in the memory cell group 14 corresponding to each bit of the eight memory cell groups 14. Therefore, the same logical information as the information of each bit and the logical information opposite to the information of each bit are output to each X direction current drive circuit group 34 and each Y direction current drive circuit group 24 corresponding to each bit, respectively. . Specifically, as shown in FIG. 2, the input buffer 12a uses the same logical information as the kth bit information input via the external data terminal Dk (k is an integer of 0 to 7) for X-direction writing. Through the data line Dxk of the data bus 17 and the logic information opposite to the k-th bit information is transferred to the memory cell group 14k corresponding to k bits via the data line Rxk of the X-direction write data bus 17. The data is output to the included X direction current drive circuit group 34. Further, the input buffer 12a sends the same logical information as the k-th bit information via the data line Dyk of the Y-direction write data bus 18, and the reverse logical information to the k-th bit information in the Y direction. The data is output to the Y-direction current drive circuit group 24 included in the memory cell group 14k corresponding to k bits via the data line Ryk of the write data bus 18. On the other hand, the output buffer 12 b is connected to the read circuit group 23 via the Y-direction read data bus 19. Further, the output buffer 12b inputs information of each bit read by the read circuit group 23 of each memory cell group 14k through the Y-direction read data bus 19, and inputs the input data to the external data terminals D0 to D0. Output to D7. The input buffer 12a and the output buffer 12b operate according to a control signal input from the control logic unit 13 via the control signal line 13a.

  The control logic unit 13 includes an input terminal CS and an input terminal OE, and controls operations of the data buffer 12, the read circuit group 23, the Y-direction current drive circuit group 24, and the X-direction current drive circuit group 34. Specifically, the control logic unit 13 selects either the input buffer 12a or the output buffer 12b based on the chip select signal input via the input terminal CS and the output permission signal input via the input terminal OE. In addition to determining whether to activate, a control signal for operating the input buffer 12a and the output buffer 12b is generated in accordance with this determination, and is output to the data buffer 12 via the control signal line 13a.

  As shown in FIG. 2, each memory cell group 14 is arranged in parallel with each other and one end P1, P2 (downward end in FIG. 2) located in the same direction is connected to each other. A plurality of (j lines, j is an integer of 2 or more) write bit lines 3 (corresponding to the write lines in the present invention) arranged in parallel along the X direction in FIG. 2) and a pair of lines 4a and 4b in which one end portions P3 and P4 (end portions in the right direction in the figure) which are arranged in parallel and located in the same direction are connected to each other. A plurality (i lines, i is an integer of 2 or more) of write word lines 4 which are configured and intersect with the lines 3a and 3b of the write bit line 3 and are arranged in parallel along the Y direction in FIG. (Corresponding to the write line in the present invention, see FIG. 2), the write bit line 3 and the write word A plurality of ((i × j)) memory cells (magnetic memory cells) arranged in a two-dimensional manner (arranged in a matrix of i rows and j columns as an example) ) 1, a plurality of (j) read bit lines (not shown) each of which is composed of a pair of lines arranged in parallel with each other and arranged in parallel with each write bit line 3, and each write word line 4 and a plurality of (i) read word lines (not shown) arranged in parallel. As shown in FIG. 2, one line 4a constituting each write word line 4 is formed substantially linearly, and the other line 4b is connected to each write bit line 3 as shown in FIG. It is formed in a rectangular wave shape as a whole by being bent in an inverted U shape (or U shape) at the intersection. Therefore, at each intersection of the write bit line 3 and the write word line 4, the lines 3a and 3b of the write bit line 3 and one line 4b of the write word line 4 are parallel to each other. Two parallel portions 10a and 10b are formed. With this configuration, when a current flows in each write word line 4 in a predetermined direction, each line 4b of one of the write word lines 4 included in the two parallel portions 10a and 10b at each crossing portion is provided. The directions of the currents flowing through the parts (current directions with reference to the Y direction) are opposite to each other.

  As shown in FIG. 2, each memory cell 1 includes a pair of memory elements 1a and 1b. Each of the memory elements 1a and 1b includes magnetoresistive effect expressing bodies 2a and 2b configured using GMR (Giant Magneto-Resitive) or TMR (Tunneling Magneto-Resitive), respectively. Further, as shown in the figure, the memory elements 1a and 1b of each memory cell 1 are disposed in the vicinity of one of the two parallel portions 10a and 10b and the other parallel portion 10b, respectively. Yes. Each memory cell 1 has a resistance value of the magnetoresistive element 2a in the memory element 1a according to the direction of the combined magnetic field generated due to the current supplied to the write bit line 3 and the write word line 4. Is smaller than the resistance value of the magnetoresistive element 2b in the memory element 1b, and the resistance value of the magnetoresistive element 2a in the memory element 1a is equal to the resistance of the magnetoresistive element 2b in the memory element 1b. By shifting to one of the states larger than the value, information of each bit constituting the data is stored.

  The Y-direction address decoder circuit 22 of the Y-direction drive control circuit unit 21 includes j readout circuits included in the readout circuit group 23 based on the address signal input via the Y-direction address bus 15 and the Y-direction One of j bit decode lines Y1,..., Yn,..., Yj connected to j Y direction current drive circuits included in the current drive circuit group 24 (bit decode line) Yn, where n is an integer between 1 and j, and a predetermined voltage is applied to the selected bit decode line Yn.

  On the other hand, the X-direction address decoder circuit 32 of the X-direction drive control circuit unit 31 includes i constant current circuits included in the constant current circuit group 33 based on an address signal input via the X direction address bus 16. , And one of i word decode lines X1,..., Xm,..., Xi connected to i X-direction current drive circuits included in the X-direction current drive circuit group 34, respectively. (Word decode line Xm, where m is an integer between 1 and i) and a predetermined voltage is applied to the selected word decode line Xm.

  Further, each Y-direction current drive circuit of the Y-direction current drive circuit group 24 (as an example, an n-th Y-direction current drive circuit 24n included in the memory cell group 14k corresponding to k bits will be described as an example. ) Is a write circuit for a magnetic memory device according to the present invention. As shown in FIG. 3, the first to fourth transistors Q1 to Q4, the first current control circuit 51, the differential amplifier circuit 61, and Each of the lines 3a and 3b of the write bit line 3 that includes the diodes D1 and D2 and is disposed in the vicinity of the i memory cells 1 included in the nth column of the memory cell group 14 A write current Iw1 is supplied.

  In this case, the first transistor Q1 is composed of an NPN transistor, its collector terminal is connected to the power supply terminal PW, and its emitter terminal is the other end of one line 3a of the pair of lines 3a and 3b. Side open side end portion P5 (upper end portion in the figure). The first transistor Q1 supplies a write current Iw1 to the write bit line 3 from the open end P5 of one line 3a in the on state. The second transistor Q2 is composed of an NPN type transistor, its collector terminal is connected to the power supply terminal PW, and its emitter terminal is open at the other end of the other line 3b of the pair of lines 3a and 3b. It is connected to the side end P6 (upper end in the figure). In the on state, the second transistor Q2 has a write current Iw1 that flows from the open end P6 of the other line 3b to the write bit line 3 in the direction opposite to that in the on state of the first transistor Q1. Supply. The third transistor Q3 is composed of an NPN transistor, and its collector terminal is connected to the open end P5 of one line 3a, and its emitter terminal is connected to the first current control circuit 51, A base terminal is connected to the data line Dyk. When the bit information output to the data line Dyk is “1”, the third transistor Q3 shifts to the on state, and the write current Iw1 flowing through the write bit line 3 is changed to the first transistor Q3. The current is output to the current control circuit 51. On the other hand, the third transistor Q3 shifts to the off state when the bit information output to the data line Dyk is “0”, and the first transistor Q3 of the write current Iw1 flowing in the write bit line 3 is changed. The output to the current control circuit 51 is stopped. The fourth transistor Q4 is composed of an NPN transistor, and its collector terminal is connected to the open end P6 of the other line 3b, and its emitter terminal is connected to the first current control circuit 51, A base terminal is connected to the data line Ryk. The fourth transistor Q4 is turned on when the bit information output to the data line Ryk is "1", and the write current Iw1 flowing through the write bit line 3 is changed to the first transistor Q4. The current is output to the current control circuit 51. On the other hand, the fourth transistor Q4 shifts to the OFF state when the bit information output to the data line Ryk is “0”, and the first transistor Q1 of the write current Iw1 flowing in the write bit line 3 is changed. The output to the current control circuit 51 is stopped. That is, the fourth transistor Q4 is controlled to shift to the off state when the third transistor Q3 shifts to the on state, and to shift to the on state when the third transistor Q3 shifts to the off state.

  The first current control circuit 51 has a collector terminal connected to the emitter terminals of the third transistor Q3 and the fourth transistor Q4, and is connected between the emitter terminal of the transistor Q7 and the ground terminal GND. Resistor R4, a diode D3 that applies a predetermined voltage applied to the bit decode line Yn to the base terminal of the transistor Q7, and a voltage that is applied to the base terminal of the transistor Q7 via the diode D3. And a stabilization circuit (a pair of diodes D4 and D5 connected in series as an example). With this configuration, the first current control circuit 51 functions as a constant current circuit that keeps the current value of the write current Iw1 input via the third transistor Q3 or the fourth transistor Q4 constant.

  The differential amplifier circuit 61 includes resistors R1 and R2 having the same resistance value, a fifth transistor Q5 composed of an NPN transistor, a sixth transistor Q6 composed of an NPN transistor, and a second current control. Circuit 62. In this case, each of the resistors R1 and R2 has one end connected to the power supply terminal PW and the other end connected to each base terminal of the second transistor Q2 and the first transistor Q1 as a bias resistor. Each functions. The fifth transistor Q5 has a collector terminal connected to the other end of the resistor R1. The sixth transistor Q6 has a collector terminal connected to the other end of the resistor R2, and an emitter terminal connected to the emitter terminal of the fifth transistor Q5. The second current control circuit 62 is composed of an NPN transistor, its collector terminal is connected to the emitter terminals of the fifth and sixth transistors Q5 and Q6, and the emitter terminal is connected to the ground terminal via the resistor R3. The transistor Q8 connected to the GND and the respective diodes D3, D4, D5 shared with the first current control circuit 51 are provided. Similarly to the first current control circuit 51, the transistor Q8 is connected via the diode D3. A pair of diodes D4 and D5 stabilizes the voltage applied to the base terminal to a predetermined voltage (about 1.5 volts as an example), so that the total value of the base current and collector current of each transistor Q5 and Q6 is constant. Functions as a constant current circuit. In the differential amplifier circuit 61, the collector terminal of the fifth transistor Q5 is connected to the base terminal of the second transistor Q2, and the collector terminal of the sixth transistor Q6 is connected to the base terminal of the first transistor Q1. ing.

  The diode D1 (the first unidirectional element in the present invention) has its anode terminal connected to the open end P5 of one line 3a and its cathode terminal connected to the base terminal of the fifth transistor Q5. As a result, the line 3a is disposed between the open end P5 and the base terminal of the fifth transistor Q5. The diode D1 is a fifth transistor in which a part of the write current Iw1 supplied to the one line 3a of the write bit line 3 by the first transistor Q1 is used as an operating current IB5 (base current of the fifth transistor Q5). Is supplied to the base terminal of the transistor Q5 (allowing current to flow toward the base terminal). The diode D2 (second unidirectional element in the present invention) has its anode terminal connected to the open end P6 of the other line 3b and its cathode terminal connected to the base terminal of the sixth transistor Q6. By doing so, it is disposed between the open end P6 of the other line 3b and the base terminal of the sixth transistor Q6. This diode D2 uses the second transistor Q2 as the sixth operating current IB6 (the base current of the sixth transistor Q6) as a part of the write current Iw1 supplied to the other line 3b of the write bit line 3 by the sixth transistor Q2. Is supplied to the base terminal of the transistor Q6 (allowing current to flow toward the base terminal).

  Each X-direction current drive circuit included in the X-direction current drive circuit group 34 will be described by taking the X-direction current drive circuit 34m included in the memory cell group 14k corresponding to k bits as an example. ) Is a write circuit for a magnetic memory device according to the present invention, and includes the same components as those of the Y-direction current drive circuits included in the Y-direction current drive circuit group 24 described above. Thus, the write current Iw2 is supplied to the lines 4a and 4b of the write word line 4 disposed in the vicinity of the j memory cells 1 included in the m-th row of the memory cell group 14. In this case, in the X-direction current drive circuit 34m, the emitter terminal of the first transistor Q1 is connected to the open end P7 (the left end in FIG. 2) on the other end side of the one line 4a, and the second transistor The emitter terminal of Q2 is connected to the open end P8 (the left end in FIG. 2) on the other end side of the other line 4b. A data line Dxk is connected to the base terminal of the third transistor Q3 instead of the data line Dyk. A data line Rxk is connected to the base terminal of the fourth transistor Q4 instead of the data line Ryk. Further, a word decode line Xm is connected to the diode D3 instead of the bit decode line Yn.

  Next, an information writing operation in the magnetic memory device M will be described.

  First, the address signal input from the address buffer 11 via the external address input terminals A0 to A20 is sent to the X-direction address decoder circuit 32 and the Y-direction address decoder circuit 22 via the X-direction address bus 16 and the Y-direction address bus 15, respectively. Output to. At this time, the Y-direction address decoder circuit 22 selects one of the bit decode lines Y1 to Yj (bit decode line Yn as an example) based on the input address signal. Similarly, the X-direction address decoder circuit 32 selects one of the word decode lines X1 to Xi (for example, the word decode line Xm) based on the input address signal. In addition, the input buffer 12a receives the information of each bit included in the data input via the external data terminals D0 to D7, and each X direction current drive circuit group 34 of the memory cell group 14 corresponding to each bit and each of the bits. The data is output to the Y-direction current drive circuit group 24 via the X-direction write data bus 17 and the Y-direction write data bus 18, respectively. In this case, the output buffer 12 b is maintained in an inoperative state by a control signal output from the control signal line 13 a of the control logic unit 13.

  In this case, each Y-direction current drive circuit 24n of each memory cell group 14 selected by the bit decode line Yn shifts to an operating state by applying a predetermined voltage via the bit decode line Yn. A write current Iw1 is supplied to the embedded bit line 3. Specifically, in each Y-direction current drive circuit 24n, when the bit information input via the data line Dyk is “1” (the bit information input via the data line Ryk is “0”). ”), The potential of the base terminal of the third transistor Q3 becomes high and the base terminal of the fourth transistor Q4 becomes low, so that the third transistor Q3 shifts to the ON state and Transistor Q4 of the transistor shifts to the off state. As a result, the collector current flowing through the third transistor Q3 becomes larger than the collector current flowing through the fourth transistor Q4. For this reason, the base current supplied to the base terminal of the sixth transistor Q6 via the diode D2 is larger than the base current supplied to the base terminal of the fifth transistor Q5 via the diode D1, Further, the total current value of the collector current of the fifth transistor Q5 and the collector current of the sixth transistor Q6 is controlled to be constant by the second current control circuit 62. As a result, the collector current of the fifth transistor Q5 is However, the collector current of the sixth transistor Q6 is larger. Therefore, the voltage drop generated in the resistor R2 is larger than the voltage drop generated in the resistor R1, and the base voltage of the second transistor Q2 is higher than the base voltage of the first transistor Q1. The transistor Q1 starts to turn off and the second transistor Q2 starts to turn on. Further, as a result of the first transistor Q1 and the second transistor Q2 starting to shift to the off state and the on state, respectively, the base current supplied to the base terminal of the fifth transistor Q5 via the first transistor Q1 is further increased. On the other hand, as a result of the further increase in the base current supplied to the base terminal of the sixth transistor Q6 via the second transistor Q2, the fifth transistor Q5 is rapidly turned off and 6 transistor Q6 is rapidly turned on. Accordingly, since the base voltage of the second transistor Q2 rapidly becomes higher than the base voltage of the first transistor Q1, the base current of the first transistor Q1 decreases rapidly, while the second voltage of the second transistor Q1 decreases. The base current of transistor Q2 increases rapidly. Therefore, the first transistor Q1 is rapidly (instantly) turned off, and the second transistor Q2 is rapidly (instantly) turned on. As a result, the second transistor Q2 passes through the other line 3b of the write bit line 3, the one line 3a of the write bit line 3, and the third transistor Q3 to the first current control circuit 51. The write current Iw1 flows (outputs), and the write current Iw1 is controlled to a constant current value by the first current control circuit 51.

  In this case, since the diode D2 is present, the potential of the base terminal of the sixth transistor Q6 with respect to the emitter terminal of the second transistor Q2 is lower than that of the configuration without the diode D2. The base current of the sixth transistor Q6 is reduced. In this case, the second current control circuit 62 of the differential amplifier circuit 61 mainly controls the total value of the collector currents of the fifth transistor Q5 and the sixth transistor Q6 to be constant as described above. In the second current control circuit 62, since the base currents of the fifth and sixth transistors Q5 and Q6 also flow along with the collector current, the base currents of the fifth and sixth transistors Q5 and Q6 and The total value of the collector current is controlled to be constant. Therefore, when the base current of the sixth transistor Q6 decreases when the fifth transistor Q5 is in the off state and the sixth transistor Q6 is in the on state, the normal operation of the transistor (the collector current is Unlike the operation that changes in proportion to the base current, the collector current increases by the amount of decrease in the base current. As a result, the voltage drop at the resistor R2 increases by the increase in the collector current of the sixth transistor Q6. As a result, the base potential of the first transistor Q1 further decreases. On the other hand, when the lines 3a and 3b of the write bit line 3 are thinned, the write current Iw1 having a constant current value is supplied to the write bit line 3 from the second transistor Q2. Since the DC resistance value of the bit line 3 increases to some extent, the voltage drop in the write bit line 3 increases. In this case, since the base potential of the first transistor Q1 further decreases, even if the potential of the emitter terminal of the first transistor Q1 decreases with respect to the emitter terminal of the second transistor Q2, the first transistor The off state of Q1 is maintained well. As a result, in the Y-direction current drive circuit 24n, the write current having a specified current value is supplied from the second transistor Q2 to the first current control circuit 51 via the write bit line 3 and the third transistor Q3. Since the operation in which Iw1 flows (outputs) is maintained satisfactorily, a sufficient magnetic field is supplied to each storage element 1a, 1b of each storage cell 1 adjacent to this write bit line 3.

  On the other hand, in each Y-direction current drive circuit 24n, when the bit information input via the data line Dyk is "0" (when the bit information input via the data line Ryk is "1") ), Each of the transistors Q1 to Q6 has a bit information input through the data line Dyk of “1” (when the bit information input through the data line Ryk is “0”). It shifts to the on / off state opposite to). The first current control circuit 51 and the second current control circuit 62 of the differential amplifier circuit 61 repeat the above operation. Therefore, the first transistor Q1 passes through the one line 3a of the write bit line 3, the other line 3b of the write bit line 3, and the fourth transistor Q4 to the first current control circuit 51. The write current Iw1 flows (outputs), and the write current Iw1 is controlled to a constant current value by the first current control circuit 51. Therefore, in the same way as when the bit information input via the data line Dyk is “1” (when the bit information input via the data line Ryk is “0”), Since the lines 3a and 3b of the embedded bit line 3 become thinner and the DC resistance value increases to some extent, the voltage drop in the write bit line 3 increases and the emitter terminal of the first transistor Q1 is used as a reference. Even if the potential of the emitter terminal of the second transistor Q2 decreases, the off state of the second transistor Q2 is maintained well. As a result, in the Y-direction current drive circuit 24n, the write current having a specified current value is transferred from the first transistor Q1 to the first current control circuit 51 via the write bit line 3 and the fourth transistor Q4. Since the operation of flowing (outputting) Iw1 is maintained satisfactorily, a sufficiently reverse magnetic field is supplied to each storage element 1a, 1b of each storage cell 1 adjacent to this write bit line 3.

  In addition, each X-direction current drive circuit 34m of each memory cell group 14 selected by the word decode line Xm shifts to an operating state when a predetermined voltage is applied via the word decode line Xm to perform writing. A write current Iw2 is supplied to the word line 4. The X-direction current drive circuit 34m of the X-direction current drive circuit group 34 is configured in the same manner as the Y-direction current drive circuit 24n of the Y-direction current drive circuit group 24 and operates in the same manner. In the description of the operation of the circuit 34m, the same components as those in the Y-direction current drive circuit 24n are denoted by the same reference numerals. Specifically, in the X direction current drive circuit 34m, when the information input via the data line Dxk is “1” (the information input via the data line Rxk is “0”), the Y direction Similarly to the current drive circuit 24n, the second transistor Q2 is connected to the first line 4b via the other line 4b of the write word line 4, the one line 4a of the write word line 4, and the third transistor Q3. The write current Iw2 flows (outputs) in the current control circuit 51, and the write current Iw2 is controlled to a constant current value by the first current control circuit 51. On the other hand, when the information input via the data line Dxk is “0” (when the information input via the data line Rxk is “1”), the X-direction current drive circuit 34m In the same manner as the directional current drive circuit 24n, the first transistor Q1 passes through one line 4a of the write word line 4, the other line 4b of the write word line 4, and the fourth transistor Q4. The write current Iw2 flows (outputs) in one current control circuit 51, and the write current Iw2 is controlled to a constant current value by the first current control circuit 51. In this case, since the diodes D1 and D2 are also present in the X-direction current drive circuit 34m, the lines 4a and 4b of the write word line 4 become thin and the DC resistance value increases to some extent. Even if the voltage drop in the write word line 4 increases, the off state of the first transistor Q1 or the off state of the second transistor Q2 is favorably maintained. As a result, in the X-direction current drive circuit 34m, the operation in which the write current Iw2 having the specified current value flows (outputs) to the write word line 4 is maintained satisfactorily. Sufficient magnetic field is supplied to each storage element 1a, 1b of each storage cell 1 to be operated.

  As described above, the Y-direction current drive circuit 24n and the X-direction current drive circuit 34m are connected to each other according to the information input via the data lines Dyk and Ryk and the data lines Dxk and Rxk, respectively. A write current Iw1 and a write current Iw2 in a predetermined direction are supplied to the write bit line 3 and the write word line 4, respectively. As a result, the direction of the current flowing through the write bit line 3 and the write word line 4 is the same in the two parallel portions 10a and 10b formed at the intersection of the write bit line 3 and the write word line 4. And the direction of the current flowing in the write bit line 3 (line 3a) and write word line 4 (line 4b) in the parallel portion 10a and the write bit line 3 (line 3b) and write word line in the parallel portion 10b The direction of the current flowing through 4 (line 4b) is reversed. Accordingly, the magnetic elements in the opposite direction are supplied to the memory elements 1a and 1b of the memory cell 1 arranged close to the parallel portions 10a and 10b, respectively. As a result, for example, the data lines Dyk and Ryk and the data lines Dxk , Rxk, one storage element of the memory cell 1 shifts to a high resistance state (a state in which the resistance value is larger than the other), and the other has a low resistance. It shifts to a value state (a state in which the resistance value is smaller than one). As a result, the information of each corresponding bit is stored in each memory cell 1 at the same address in each memory cell group 14, and as a result, the entire memory cell group 14 is input via the external data terminals D 0 to D 7. Data is stored in an address indicated by an address signal input via external address input terminals A0 to A20.

  Thus, according to the magnetic memory device M, in the Y-direction current drive circuit in the Y-direction current drive circuit group 24 and the X-direction current drive circuit in the X-direction current drive circuit group 34, the line 3a (or 4a) Between the open end P5 (P7) and the base terminal of the fifth transistor Q5 in the differential amplifier circuit 61, the open end P5 of the one line 3a (or 4a) from the first transistor Q1. A diode D1 that allows passage of current toward the base terminal of the fifth transistor Q5 through (P7) is provided, and the open-side end of the other line 3b (or 4b) of the write bit line 3 Between P6 (P8) and the base terminal of the sixth transistor Q6 in the differential amplifier circuit 61, the second transistor Q2 and the other line 3b (or 4b) is provided with a diode D2 that allows the passage of current toward the base terminal of the sixth transistor Q6 via the open side end P6 (P8), so that, for example, the first transistor Q1 is turned off. When the second transistor Q2 is in the on state, the diode D2 is present, so that the potential of the emitter terminal of the second transistor Q2 (the open-side end P6 (P8) in the other line 3b (or 4b)). As a reference, the potential of the base terminal of the sixth transistor Q6 can be made lower than that of the configuration without the diode D2.

  Accordingly, the base current of the sixth transistor Q6 can be reduced when the fifth transistor Q5 is in the off state and the sixth transistor Q6 is in the on state. Therefore, in a situation where the second current control circuit 62 controls the collector current and base current of the fifth transistor Q5 and the sixth transistor Q6 to be constant, the transistor normal Unlike the operation (the operation in which the collector current increases due to the increase in the base current), the collector current of the sixth transistor Q6 can be increased. As a result, the voltage at the resistor R2 through which the collector current of the sixth transistor Q6 flows. The descent can be increased sufficiently. Accordingly, since the base potential of the first transistor Q1 can be further lowered, for example, the lines 3a and 3b (or 4a and 4b) are thinned and the resistance is increased to some extent, and accordingly, the write current Iw1 is reduced. Even if the voltage drop in the write bit line 3 increases due to the flow and the emitter potential of the first transistor Q1 decreases, the first transistor Q1 can be reliably maintained in the OFF state. The write current Iw1 having a specified value can be supplied to the write bit line 3. Similarly, the write current Iw1 having a specified current value can be supplied to the write bit line 3 even when the first transistor Q1 is in the on state and the second transistor Q2 is in the off state.

  Therefore, according to this magnetic memory device M, the wiring width is reduced in order to increase the number of the storage cells 1 included in each row or each column of the storage cell group 14 and increase the storage capacity. Even if the resistance value of the write bit line 3 or the write word line 4 increases, the write current Iw1 or the write current Iw2 having a specified value can be supplied to the write bit line 3 or the write word line 4. . Specifically, in the configuration in which each of the diodes D1 and D2 is not provided, the resistance value of the write bit line 3 (or the write word line 4) is 1000Ω as indicated by the characteristic line T indicated by a broken line in FIG. When the current exceeds the write current Iw1 (or Iw2), the specified value (about 1100 mA as an example) cannot be maintained. In the configuration in which the diodes D1 and D2 are disposed, the characteristic line S indicated by the solid line in FIG. As shown, the write current Iw1 (or Iw2) is maintained at a specified value (about 1100 mA as an example) even in the range W until the resistance value of the write bit line 3 (or write word line 4) reaches 1500Ω. can do. For this reason, as a result of applying a sufficient magnetic field to each storage element 1a, 1b of each storage cell 1, information on the corresponding bit can be reliably stored in each storage cell 1.

  Further, diodes are provided between the open end P5 of one line 3a and the base terminal of the fifth transistor Q5, and between the open end P6 of the other line 3b and the base terminal of the sixth transistor Q6. Although D1 and D2 are provided, the base potential of the fifth transistor Q5 in the on state of the first transistor Q1 and the sixth transistor Q6 in the on state of the second transistor Q2 are simplified, although the configuration is simple. Each of the base potentials can be lowered. In this case, Schottky diodes or germanium diodes can be used as the diodes D1 and D2, but by using a silicon diode having a large forward voltage drop compared to these diodes, the base of the fifth transistor Q5 can be used. Since the potential and the base potential of the sixth transistor Q6 can be sufficiently lowered, the regulation is also provided in the configuration in which the resistance value of the write bit line 3 or the write word line 4 is larger (the line width is narrower). Value write currents Iw1 and Iw2 can be reliably supplied.

  The present invention is not limited to the configuration described above. For example, instead of the bipolar transistors Q1 to Q8, a configuration using field effect transistors can be adopted.

  In the above configuration, the open side end P5 of one line 3a and the base terminal of the fifth transistor Q5, and the open side end P6 of the other line 3b and the base terminal of the sixth transistor Q6 The diodes D1 and D2 are used as the unidirectional elements respectively disposed between them, but for example, an NPN type transistor (such as a Y-direction current drive circuit 24nA (or an X-direction current drive circuit 34mA) shown in FIG. As an example, it is possible to adopt a configuration in which silicon transistors (Q11, Q12) are used by connecting emitter followers. A field effect transistor can also be used. In this case, the transistor Q11 is connected between the transistors Q1 and Q5 such that the base-emitter diode is in series with the base-emitter diodes of the first transistor Q1 and the fifth transistor Q5. (Arranged). Specifically, the transistor Q11 has its collector terminal connected to the power supply terminal PW, its base terminal connected to the emitter terminal of the first transistor Q1, and its emitter terminal connected to the base terminal of the fifth transistor Q5. Similarly, the transistor Q12 has a base-emitter diode in series with the base-emitter diodes of the second transistor 6 and the sixth transistor Q6, so that the transistor Q12 is connected between the transistors Q2 and Q6. Connected (arranged). Specifically, the transistor Q12 has its collector terminal connected to the power supply terminal PW, its base terminal connected to the emitter terminal of the second transistor Q2, and its emitter terminal connected to the base terminal of the sixth transistor Q6. With this configuration, in each of the transistors Q11 and Q12, the potential of each emitter terminal is lowered by the voltage of one diode from the potential of each base terminal. Therefore, in the same manner as when the diodes D1 and D2 are used as the unidirectional elements, the potential of the base terminal of the fifth transistor Q5 with respect to the emitter terminal of the first transistor Q1, and the second transistor Q2 The potential of the base terminal of the sixth transistor Q6 with respect to the emitter terminal of each can be further lowered. The Y-direction current drive circuit 24nA (or the X-direction current drive circuit 34mA) is the same as the Y-direction current drive circuit 24n (or the X-direction current drive) except that the transistors Q11 and Q12 are used instead of the diodes D1 and D2. Since it is the same as the circuit 34m), the same components are denoted by the same reference numerals and redundant description is omitted.

  According to this configuration, each diode formed of a P-type semiconductor and an N-type semiconductor formed between the base terminal and the emitter terminal of each of the transistors Q11 and Q12 is similar to the diodes D1 and D2, Arranged between the open end P5 of one line 3a and the base terminal of the fifth transistor Q5, and between the open end P6 of the other line 3b and the base terminal of the sixth transistor Q6. As a result, similarly to the Y-direction current drive circuit 24n (or the X-direction current drive circuit 34m), the Y-direction current drive circuit 24nA (or the X-direction current drive circuit 34mA) has a larger resistance value (line width). Write currents Iw1 and Iw of specified values also for write bit line 3 (or write word line 4). It is possible to reliably supply the.

  Further, like the Y-direction current drive circuit 24nB (or the X-direction current drive circuit 34mB) shown in FIG. 6, the diodes D6 and D7 are connected to the open end P5 of one line 3a and the base of the fifth transistor Q5. It is also possible to adopt a configuration in which the diodes D1 and D2 are arranged in series with each other between the terminals and between the open end P6 of the other line 3b and the base terminal of the sixth transistor Q6. According to this Y-direction current drive circuit 24nB (or X-direction current drive circuit 34mB), the base potential of the fifth transistor Q5 when the first transistor Q1 is on and the sixth potential when the second transistor Q2 is on. Since the base potential of each transistor Q6 of the transistor Q6 can be further lowered, the write bit line 3 (or the write word line 4) having a larger resistance value (a narrower and longer line width) can also be set to the specified value. Write currents Iw1 and Iw2 can be reliably supplied.

1 is a block diagram showing an overall configuration of a magnetic memory device M. FIG. FIG. 3 is a block diagram showing configurations of a Y-direction current drive circuit 24n (24nA, 24nB), an X-direction current drive circuit 34m (34mA, 34mB), a write bit line 3, a write word line 4, and a memory cell 1. It is a circuit diagram of a Y-direction current drive circuit 24n (or an X-direction current drive circuit 34m). FIG. 6 is a characteristic diagram showing a relationship between a resistance value of a write bit line 3 (or write word line 4) and a write current Iw1 (or Iw2). It is a circuit diagram of a Y-direction current drive circuit 24nA (or an X-direction current drive circuit 34mA). It is a circuit diagram of a Y-direction current drive circuit 24nB (or an X-direction current drive circuit 34mB).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell 2a, 2b Magnetoresistive effect body 3 Write bit line 3a, 3b Each line of write bit line 4 Write word line 4a, 4b Each line of write word line 51 1st current control circuit 61 Difference Dynamic amplifier circuit 62 Second current control circuit D1, D2 Diode (first and second unidirectional elements)
Q1 1st transistor Q2 2nd transistor Q3 3rd transistor Q4 4th transistor Q5 5th transistor Q6 6th transistor Q11, Q12 Transistor Iw1, Iw2 Write current M Magnetic memory device

Claims (8)

A write current flowing in a write line having a pair of lines arranged close to each of the pair of magnetoresistive effect members in the recording cell and having one end connected to each other is controlled to a constant value. A first current control circuit;
A first transistor connected to an open end on the other end of one of the pair of lines and supplying the write current from the open end to the write line in an ON state; ,
A second transistor connected to the open end on the other end of the other line of the pair of lines and supplying the write current from the open end to the write line in the on state; ,
A third transistor connected to the open end of the one line and outputting the write current supplied by the second transistor to the first current control circuit in an on state;
The book connected to the open end of the other line and controlled by an on / off state opposite to the on / off state of the third transistor and supplied by the first transistor. A fourth transistor that outputs a sunk current to the first current control circuit in the on state;
The fifth and sixth transistors whose output terminals are connected to each other, and a second current control circuit that controls a total value of currents flowing through the fifth and sixth transistors to a constant value, When the third transistor shifts to the on state and the fourth transistor shifts to the off state, the fifth transistor and the sixth transistor shift to the off state and the on state, respectively. And the second transistor are turned off and on, respectively, the fourth transistor is turned on, and the third transistor is turned off and the fifth transistor and the second transistor are turned on. When the sixth transistor shifts to an on state and an off state, respectively, the first transistor A differential amplifier circuit for shifting register and the second transistor respectively turned on and off states,
Passing current passing from the first transistor to the control terminal through the open-side end, disposed between the open-side end of the one line and the control terminal of the fifth transistor. A first unidirectional element to allow;
Current passing from the second transistor to the control terminal through the open-side end portion is disposed between the open-side end portion of the other line and the control terminal of the sixth transistor. A write circuit for a magnetic memory device, comprising a second unidirectional element to be allowed.   The write circuit for a magnetic memory device according to claim 1, wherein the first unidirectional element and the second unidirectional element are diodes.   The write circuit for a magnetic memory device according to claim 2, wherein the diode is a silicon diode.   The first unidirectional element is an emitter-follower-connected transistor disposed between the first transistor and the fifth transistor, and the second unidirectional element is the second transistor. The write circuit for a magnetic memory device according to claim 1, wherein the write circuit is disposed between the sixth transistor and an emitter follower. A recording cell comprising a pair of magnetoresistive effect members whose resistance value varies with an external magnetic field;
A writing line having a pair of lines disposed in proximity to the pair of magnetoresistive bodies and having one end connected to each other;
A first current control circuit for controlling a write current flowing in the write line to a constant value;
A first transistor connected to an open end on the other end of one of the pair of lines and supplying the write current from the open end to the write line in an ON state; ,
A second transistor connected to the open end on the other end of the pair of lines and capable of supplying the write current from the open end to the write line in the ON state When,
A third transistor connected to the open side end of the one line and supplying the write current supplied by the second transistor to the first current control circuit in an on state;
The book connected to the open end of the other line and controlled by an on / off state opposite to the on / off state of the third transistor and supplied by the first transistor. A fourth transistor for supplying a built-in current to the first current control circuit in the ON state;
The fifth and sixth transistors whose output terminals are connected to each other, and a second current control circuit that controls a total value of currents flowing through the fifth and sixth transistors to a constant value, When the third transistor shifts to the on state and the fourth transistor shifts to the off state, the fifth transistor and the sixth transistor shift to the off state and the on state, respectively. And the second transistor are turned off and on, respectively, the fourth transistor is turned on, and the third transistor is turned off and the fifth transistor and the second transistor are turned on. When the sixth transistor shifts to an on state and an off state, respectively, the first transistor A differential amplifier circuit for shifting register and the second transistor respectively turned on and off states,
Passing current passing from the first transistor to the control terminal through the open-side end, disposed between the open-side end of the one line and the control terminal of the fifth transistor. A first unidirectional element to allow;
Current passing from the second transistor to the control terminal through the open-side end portion is disposed between the open-side end portion of the other line and the control terminal of the sixth transistor. A magnetic memory device comprising a second unidirectional element to allow.   6. The magnetic memory device of claim 5, wherein the first unidirectional element and the second unidirectional element are diodes.   The magnetic memory device of claim 6, wherein the diode is a silicon diode.   The first unidirectional element is an emitter-follower-connected transistor disposed between the first transistor and the fifth transistor, and the second unidirectional element is the second transistor. The magnetic memory device according to claim 5, wherein the transistor is disposed between the sixth transistor and an emitter follower connection.

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