JP4525188B2 - Multiprocessor system - Google Patents

Description

  The present invention relates to a multiprocessor system composed of a plurality of processors.

  With the recent demand for smaller, faster, and higher performance electronic devices, multiprocessor systems have been developed that can process a large amount of data in a short time by simultaneously driving a plurality of processors.

  In this multiprocessor system, a plurality of processors are connected to a shared bus, and various peripheral devices such as an I / O, a memory, and a sensor are directly or indirectly connected to each processor via a bus.

  In the multiprocessor system, a unique processor ID (processor identification factor) is assigned to each processor, and various controls are performed by operating each processor in the priority order based on the processor ID.

  Thus, in order to assign a unique processor ID to each processor, a specific processor ID is set in advance in a boot program executed by each processor, and the processor ID of each processor is fixed. In some cases, a processor ID is set for each processor so that the processor ID can be varied at each boot time.

Among these, when the processor ID can be changed at every boot time, a combination of a plurality of processors becomes free, and an optimum processor ID can be assigned according to the control executed in the multiprocessor system. The versatility increases.
Therefore, in recent multiprocessor systems, the processor ID can be changed at each boot time. Specifically, a boot controller is connected to a plurality of processors, and each processor is booted from the boot controller to each processor. By transmitting individual processor IDs, each processor can recognize its own processor ID.
JP-A-9-269896

  Thus, in the conventional multiprocessor system, a processor controller must be connected to each processor in order to make each processor recognize its own processor ID.

  For this reason, in the conventional multiprocessor system, the number of components increases by the amount of the processor controller, which increases the size of the multiprocessor system and increases the manufacturing cost.

Therefore, in the present invention according to claim 1, in a multiprocessor system composed of a plurality of processors having different connection statuses of peripheral devices, each processor is directly connected to each processor through a dedicated bus at the time of booting. Based on the correspondence table in which the connection status of the peripheral device and the processor ID are associated with each other, it is recognized whether the processor ID of the device is a master or a slave .

Also, in the present invention according to claim 2, in the present invention according to claim 1, each of the processors executes a unique boot program at the time of booting, initializes the peripheral device, and then performs the dedicated bus. The connection status of peripheral devices that are directly connected via the network is determined .

According to the third aspect of the present invention, in a multiprocessor system including a plurality of processors connected to a shared memory, the processors are booted in a preset order, and the boot information area of the shared memory is booted at the time of booting . of the area for writing the boot information of its own processor writes the boot information, before reading out the information from the area for writing the boot information of the other processors among Kivu over preparative information area, the read information from the other processor If written not boot information, recognizes the processor ID of the self as a master, if the read out information is boot information written from the other processor, slave self processor ID It was made to recognize that.

  And in this invention, there exists an effect described below.

Therefore, in the present invention according to claim 1, in a multiprocessor system composed of a plurality of processors having different connection statuses of peripheral devices, each processor is directly connected to each processor through a dedicated bus at the time of booting. And determining whether the processor ID of the peripheral device is a master or a slave based on the correspondence table in which the connection status of the peripheral device and the processor ID are associated with each other. This eliminates the need for preparation, reduces the number of parts constituting the multiprocessor system, reduces the size of the multiprocessor system, and reduces the cost of the multiprocessor system.

  In addition, an optimal processor ID can be assigned to each processor according to the connection status between the processor and peripheral devices, and the multiprocessor system can be easily optimized.

In addition , each processor determines the peripheral device directly connected, and recognizes its own processor ID based on a correspondence table in which the connection status of the peripheral device is associated with the processor ID. The processor ID assigned to each processor can be easily changed by simply changing the correspondence table.

According to the third aspect of the present invention, in a multiprocessor system including a plurality of processors connected to a shared memory, the processors are booted in a preset order, and the boot information area of the shared memory is set at the time of booting . of the area for writing the boot information of its own processor writes the boot information, before reading out the information from the area for writing the boot information of the other processors among Kivu over preparative information area, the read information from the other processor If written not boot information, recognizes the processor ID of the self as a master, if the read out information is boot information written from the other processor, slave self processor ID Therefore, it is necessary to prepare a boot controller separately. No longer, it is possible to reduce the number of parts constituting a multiprocessor system, it is possible to reduce the size of the multi-processor system, thereby reducing the size of the structure of a multiprocessor system. In addition, the processor ID assigned to each processor can be easily changed by simply changing the boot order.

  Moreover, even in a multiprocessor system in which all processors and peripheral devices have the same connection status, each processor can surely recognize its own processor ID.

  In the multiprocessor system according to the present invention, a plurality of processors are connected to a shared bus, and various peripheral devices such as I / O, memory, and sensors are directly or indirectly connected to each processor via the bus. Is. The multiprocessor system according to the present invention may be a multiprocessor module in which a plurality of processors are mounted on the same board, and each processor is mounted on a plurality of boards and the plurality of processors are connected to each other. It may be what you did.

  In the multiprocessor system according to the present invention, instead of assigning a processor ID to each processor by a boot controller as in the prior art, each processor recognizes its own processor ID. There is no need to prepare a separate boot controller, the number of parts constituting the multiprocessor system can be reduced, the multiprocessor system can be reduced in size, and the multiprocessor system can be reduced in cost. It is.

  The method for this differs depending on the connection form between the processor and the peripheral device in the multiprocessor system.

  That is, in the case of a multiprocessor system composed of a plurality of processors having different connection statuses of peripheral devices, each processor recognizes its own processor ID based on the peripheral device directly connected to each processor at the time of booting. ing. In this case, an optimal processor ID can be assigned to each processor in accordance with the connection status between the processor and peripheral devices, and the multiprocessor system can be easily optimized.

  More specifically, a peripheral device to which each processor is directly connected is determined, and its own processor ID is recognized based on a correspondence table in which the connection status of the peripheral device and the processor ID are associated with each other. In this case, the processor ID assigned to each processor can be easily changed by simply changing the correspondence table.

  In addition, in the case of a multiprocessor system composed of a plurality of processors having the same peripheral device connection status and composed of a plurality of processors connected to a shared memory, each processor is set to a shared memory at the time of booting. The processor ID is recognized based on the data stored in. In this case, each processor can surely recognize its own processor ID even in a multiprocessor system in which all processors and peripheral devices have the same connection status.

  More specifically, each processor is booted in a preset order, and boot information specific to the boot information area of the shared memory is written at the time of booting, and is written by another processor from the boot information area of the shared memory. The boot information is read, and its own processor ID is recognized based on the read boot information. In this case, the processor ID assigned to each processor can be easily changed simply by changing the boot order as appropriate.

  Note that the boot in the present invention is not limited to booting immediately after power-on, and includes rebooting by a reset signal.

  A specific configuration of the multiprocessor system according to the present invention will be described below with reference to the drawings. In the following description, peripheral devices refer to various peripheral devices such as I / O, memory, and sensors.

  First, a case of a multiprocessor system constituted by a plurality of processors having different connection statuses of peripheral devices will be described.

  As shown in FIG. 1, the multiprocessor system 1 connects a first processor 2 and a second processor 3 via a shared bus 4.

  A first peripheral device 5 is connected to the first processor 2 via a dedicated bus 6, while a second peripheral device 7 is connected to the second processor 3 via a dedicated bus 8. Connected.

  In the multiprocessor system 1, peripheral devices 9, 10, and 11 are connected to the first and second processors 2 and 3 via the shared bus 4.

  In the multiprocessor system 1, the first and second processors 2 and 3 execute their own boot programs simultaneously.

  The processors 2 and 3 initialize the peripheral devices 5, 7, 9, 10, and 11 when the boot program is executed, and then the peripheral devices 5 are connected to the processors 2 and 3 via the dedicated buses 6 and 8, respectively. , 7 is used to determine whether or not there are peripheral devices 5, 7 directly connected to the processors 2, 3 via dedicated buses 6, 8.

  As a result of the determination, each processor 2, 3 recognizes its own processor ID based on the correspondence table between the peripheral device connection status and the processor ID in FIG.

  For example, in the present embodiment, in the case of the first processor 2, it is determined that the peripheral device 5 is directly connected, and it is determined that the peripheral device 7 is not directly connected. Based on the correspondence table of FIG. 2, the processor ID is recognized as “master A”. On the other hand, in the case of the second processor 3, it is determined that the peripheral device 5 is not directly connected, It is determined that the peripheral device 7 is directly connected, and in this case, it is recognized that its own processor ID is “slave A” based on the correspondence table of FIG.

  If it is determined that the peripheral device 5 is directly connected and the peripheral device 7 is also directly connected, it recognizes that its own processor ID is “master B”, and If it is determined that the peripheral device 5 is not directly connected and the peripheral device 7 is also not directly connected, it recognizes that its own processor ID is “slave B”.

  As described above, the processors 2 and 3 can recognize their own processor IDs without using the boot controller.

  Next, a description will be given of the case of a multiprocessor system configured by a plurality of processors having the same connection status of peripheral devices and configured by a plurality of processors connected to a shared memory.

  As shown in FIG. 3, the multiprocessor system 21 connects a first processor 22 and a second processor 23 via a shared bus 24.

  A shared memory 25 is connected to the first and second processors 22 and 23 via dedicated buses 26 and 27, respectively.

  In the multiprocessor system 21, peripheral devices 30, 31, and 32 are connected to the first and second processors 22 and 23 via a shared bus 24.

  The multiprocessor system 21 boots the first processor 22 with the first boot signal 28, while booting the second processor 23 with the second boot signal 29. The boot signals 28 and 29 are used to boot the processors 22 and 23 at different timings.

  In the multiprocessor system 21, the first and second processors 22 and 23 execute their own boot programs in response to the first and second boot signals 28 and 29, respectively.

  The processors 22 and 23 execute the boot program shown in FIG. 4, and first, initialize the peripheral devices 30, 31, and 32 immediately after the boot program is executed (step S1).

  Next, each of the processors 22 and 23 writes its own boot information at an address in which its own boot information is written in the boot information area of the shared memory 25 (step S2).

  Next, each of the processors 22 and 23 reads the boot information from the address in which the boot information of the other processors 22 and 23 in the boot information area of the shared memory 25 is written (step S3).

  Then, each processor 22, 23 recognizes its own processor ID based on the boot information read from the address for writing the boot information of the other processors 22, 23 in the boot information area of the shared memory 25 (step S4). ).

  More specifically, as shown in FIG. 5, the first processor 22 is booted first and then the second processor 23 is booted. First, the first processor 22 boots according to the boot program. After the first processor 22 initializes the peripheral devices 30, 31, and 32, the address (# 1) to which the boot information of the first processor 22 in the boot information area of the shared memory 25 is written The boot information (“RDY”) of the first processor 22 is written in

  Next, the second processor 23 starts booting according to the boot program.

  Next, the first processor 22 receives the boot information (here, the initial value “INT”) from the address (# 2) where the boot information of the second processor 23 in the boot information area of the shared memory 25 is written. Read.

  Next, the boot information (“RDY”) of the second processor 23 is stored in the address (# 2) where the second processor 23 writes the boot information of the second processor 23 in the boot information area of the shared memory 25. Write.

  Next, the boot information read from the address (# 2) where the first processor 22 writes the boot information of the second processor 23 in the boot information area of the shared memory 25 (here, the initial value “INT”) To recognize its own processor ID. Here, when the read boot information is “INT”, “master” is recognized as the processor ID, and when the read boot information is “RDY”, “slave” is recognized as the processor ID. As a result, the first processor 22 recognizes “master” as the processor ID because the boot information read is “INT”.

  Next, the second processor 23 obtains boot information (here, the initial value “RDY”) from the address (# 1) to which the boot information of the first processor 22 in the boot information area of the shared memory 25 is written. Read.

  Next, the boot information read from the address (# 1) where the second processor 23 writes the boot information of the first processor 22 in the boot information area of the shared memory 25 (here, initial value “RDY”) To recognize its own processor ID. Here, when the read boot information is “INT”, “master” is recognized as the processor ID, and when the read boot information is “RDY”, “slave” is recognized as the processor ID. Thus, the second processor 23 recognizes “slave” as the processor ID because the boot information read out is “RDY”.

  As described above, the processors 22 and 23 can recognize their own processor IDs without using the boot controller.

1 is a block diagram showing a multiprocessor system according to the present invention. The correspondence table showing the relationship between the connection status of peripheral devices and the processor ID. The block diagram which shows another multiprocessor system. The flowchart which shows a boot program. Explanatory drawing which shows operation | movement at the time of booting of a multiprocessor system.

Explanation of symbols

1,21 Multiprocessor system
2,22 1st processor
3,23 second processor
4,24 shared bus
5,7,9,10,11,30,31,32 Peripheral devices
6,8,26,27 Private bus
25 shared memory

Claims (3)

In a multiprocessor system consisting of multiple processors with different connection status of peripheral devices,
Each processor determines a peripheral device directly connected to each processor through a dedicated bus at the time of booting, and based on a correspondence table in which the connection status of the peripheral device is associated with the processor ID, A multiprocessor system characterized by recognizing whether it is a master or a slave.   Each of the processors executes a unique boot program at the time of booting, initializes the peripheral device, and then determines a connection status of the peripheral device directly connected via the dedicated bus. Item 4. The multiprocessor system according to Item 1. In a multiprocessor system consisting of multiple processors connected to a shared memory,
Each processor is booted in a preset order, the area for writing the boot information of its own processor of the boot information region of the shared memory at boot writes the boot information, another of the pre-Kivu over preparative information area reads the information from the area for writing the boot information processor, when the read information is not booted information written from the other processor, to recognize the processor ID of itself and the master, the read-out information is the If a boot information written by other processors, features and to luma multiprocessor system to recognize and the self processor ID is the slave.

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