JP4533004B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state image sensor, and more particularly, to a solid-state image sensor that suppresses disturbance caused by an analog-digital conversion unit on a pixel unit.

  Conventionally, a CCD (Charge Coupled Device) is known as a solid-state imaging device that converts an image signal into an electrical signal. This CCD has a photodiode array, and a pulse voltage is applied to the electric charge accumulated in each photodiode to read it out as an electric signal. In recent years, a CMOS area sensor in which a photodiode and a MOS transistor are integrated on a single chip is used as a solid-state imaging device.

  Compared with a CCD, a CMOS area sensor has advantages such as low power consumption, low driving power, and high speed, and future demand is expected to increase.

In recent years, an example in which an analog-digital conversion circuit is built in a chip using this CMOS sensor (Patent Document 1) and an example in which the speed is increased by using an AD converter for each column have been proposed. (Patent Document 2 and Non-Patent Document 1)
In these methods, a voltage comparator and a digital memory are provided in each column or each pixel, and a digital A / D conversion architecture in which the digital memory is connected to a common counter by a sensor is mainly used.

  In the architecture, a signal from a pixel is applied to one end of a voltage comparator in each AD converter, a triangular wave is applied to the other end, and the counter value when the comparator in each column is inverted is used as a digital memory in each column. To perform AD conversion.

Furthermore, in Non-Patent Document 2, there is an example in which a 0.35 μm rule is used to form a three-layer metal and two-layer Pol process, and the digital part and the analog part of the sensor are supplied with 3.3 V supply. It is disclosed.
JP-A-10-224696 JP 05-48460 A A 2e-Noise 1.3 Megapixel COMS Sensor (2003 IEEE Workshop on CCD and Advanced Image Sensors May 15-17 2003) A Multi-Resolution 100 GOPS 4 Gpixels / s Programmable CMOS Image Sensor for Machine Vision (2003 IEEE Workshop on CCD3 and Advanced Image15SensorMs17)

  However, in the above prior art, since all circuits including the photoelectric conversion unit and the digital circuit unit are basically driven by a single power source, the respective configurations are not optimized and the configuration optimal for the photoelectric conversion unit is not achieved. There are problems such as an increase in power consumption and restrictions on speeding up. On the other hand, in the optimization other than the photoelectric conversion unit, it is conceivable that the performance of the photoelectric conversion unit, that is, the photodiode is lowered because the voltage is lowered.

  In addition, in any of the above prior arts, there is no description regarding the wells of the digital circuit part and the sensor part, and it does not seem to use a special process for separating the wells. In particular, an accurate process is required for the well layer of the photodiode.

  In the prior art, since the well layer of the photodiode is formed by performing thermal diffusion after ion implantation, the concentration distribution in the substrate depth direction has gradually decreased as shown in FIG. .

  As a result, the structure does not have a potential barrier in the substrate depth direction, and a part of the light absorbed in the P-type well is lost in the substrate direction and thus does not contribute as a photoelectric conversion signal. In particular, the required sensitivity could not be obtained as the pixel size was reduced.

  Therefore, an object of the present invention is to achieve a high-speed response with low power consumption and improve various characteristics including sensitivity of a photodiode in a CMOS sensor capable of high-speed operation.

The solid-state imaging device of the present invention includes a pixel unit including a photoelectric conversion unit formed on a semiconductor substrate, an analog-digital conversion unit that performs analog-digital conversion on an electrical signal photoelectrically converted by the photoelectric conversion unit, and the photoelectric conversion unit. A circuit unit for driving the conversion unit, the analog-digital conversion unit is formed in a well in which the pixel unit is formed, and the circuit unit is formed with the pixel unit and the analog-digital conversion unit It is not formed in the well, but is electrically isolated from the well.

  According to the present invention, it is possible to individually optimize the characteristics of the photodiode and the circuit characteristics, and to obtain a high-performance imaging device in which noise of the AD conversion unit operating at high speed is suppressed.

  In addition, by forming a plurality of well layers in the photodiode portion and making the well concentration in the deepest portion higher than the well concentration in the uppermost portion, a potential barrier is formed between them, and incident light carriers are transferred to the photodiode side. Therefore, the sensitivity can be improved.

  With such a photodiode configuration, a highly sensitive photodiode can be formed, and optimization can be performed separately from other circuits, particularly digital circuits.

  Further, by individually setting the power supply voltage of the photoelectric conversion unit and the power supply voltage of at least a part of the digital signal unit to optimum values, low power consumption and high speed can be realized with the photodiode configuration.

  In addition, multiple analog-to-digital converters connected to each column can be built in, and the speed can be increased. In particular, the use of Multi-Slope integrating AD Converter in the analog-to-digital converter further increases the speed. It is possible to achieve high speed and low power consumption after eliminating disturbances such as noise due to the high speed.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a plan view showing a CMOS sensor as a first embodiment of the present invention.

  The pixel area 100 is composed of a plurality of pixels 101 composed of a CMOS sensor formed by a photoelectric conversion portion and a transistor. In this embodiment, a description will be given using a 3 × 3 example. There is no particular limitation, and for example, those arranged in a line are also included.

  An analog output from each pixel is input to a circuit unit 102 such as CDS (correlated double sampling) by a signal from the scanning circuit 105 in the vertical direction.

  Next, the signals sequentially extracted by the signal of the scanning circuit 104 are finally extracted as digital outputs through the AD converter 103. Reference numeral 100 denotes a pixel portion, 102, 104 and 105 denote peripheral circuit portions, and 103 denotes an AD conversion portion.

  FIG. 2 is a schematic cross-sectional view showing a schematic cross section of FIG.

  The substrate 106 is an N substrate in this embodiment. The pixel portion 107, that is, the photodiode portion is a P-type well 107, which is formed as a deep well in order to improve sensitivity. Among them, there is an N well region 108 that is electrically isolated from the N substrate.

The N well 110 of the peripheral circuit unit 102 is formed by using an N substrate as a well or further implanting N type ions. The electrical N-well 108 and N-well 110 that has been completely separated.

  Although the P well 109 of the AD conversion unit is formed in the pixel unit of the CMOS area sensor, characteristics such as a threshold value may be changed by changing the well configuration and changing only the surface concentration.

  In this configuration, an AD conversion unit is created in a large well that forms a photodiode, and the well is formed independently. The pixel unit, the AD conversion unit, and the peripheral circuit unit MOS transistor These configurations can be formed and optimized separately. Furthermore, disturbance in the high-speed operation AD conversion unit that affects the peripheral circuit unit such as the pixel unit and the CDS can be suppressed.

Furthermore, it is also possible to change the power supply voltage during individual optimization. For example, the photodiode section and the peripheral circuit section that drives the photodiode section are driven with 5v. That is, the N well 110 and the substrate 106 are fixed to 5v, while only the AD conversion unit or its digital circuit portion that requires high frequency driving is operated with a 1.6V system, that is, the N well 108 is set to 1.6v. Can do. By doing so, the AD converter can achieve high speed and low power consumption.

  The photodiode in the pixel portion can operate at 5v, and a highly sensitive and low noise solid-state imaging device can be formed. In addition, since the P well of the AD conversion section exists in the deep P well for increasing sensitivity, there is an advantage that a low resistance P well can be formed and a stable ground level can be achieved, contributing to low noise. it can.

  Further, since the P well of the peripheral circuit section is also separated, it is possible to use a part of this voltage as a negative potential, thereby increasing the degree of freedom of the readout voltage of the photodiode and suppressing noise.

  FIG. 3 is a cross-sectional view for describing the manufacturing method of this embodiment.

  Here, reference numeral 200 denotes a pixel portion, 201 denotes a digital portion, and 202 denotes a peripheral circuit portion.

First, a deep P well region 107 is formed in an N-type substrate 106 by implanting B ions and performing heat treatment for a long time at a high temperature. B concentration is about 4E16 / cm ^3.

  Next, the field oxide film 5 is formed using a normal LOCOS isolation method or a recess LOCOS method. Then, after forming the N-type channel stop layer 6 under the field oxide film 5, a shallow region P well 111 and N wells 108 and 110 are sequentially formed. Although this formation method is not particularly limited, a general retrograde well was used.

Further , a gate oxide film process was performed at 850 degrees, and channel doping for threshold adjustment was performed for each MOS transistor. After forming the polysilicon electrode 7, the photodiode N-type charge storage region 8, the P-type surface layer 9, the N-type high concentration layer 10 and the P-type high concentration layer are formed by ion implantation. NMOS transistors, pMOS transistors, nMOS transistors, pMOS transistors, diffusion capacitors, diffusion resistors, and the like of the AD conversion unit are formed.

  After forming the insulating film, a contact hole is opened, and then a metal process is performed. Since the subsequent manufacturing method is the same as that of the conventional CMOS area sensor, the description thereof is omitted.

  As described above, each transistor formation region can be formed separately. Particularly, since the N well of the AD conversion unit that operates at high speed is separated from the N well of the peripheral circuit unit, the power supply generated by AD, etc. The influence of the noise on the analog circuit part, which is a peripheral circuit part, can be suppressed.

  Furthermore, transistors having respective optimum transistor characteristics can be formed. That is, the photodiode part and the peripheral circuit part are designed to have a characteristic of 5v or higher, and high sensitivity, low noise, and a high saturation amount are possible.

  On the other hand, the digital part of the AD conversion part is a 3.3v system, and high speed and low power consumption can be achieved. Low power consumption and high speed with a high-quality photodiode with high sensitivity were achieved, and a high-performance solid-state imaging device could be formed.

[Second Embodiment]
The configuration of the high sensitivity photodiode will be described.

  FIG. 4 shows the transfer MOS transistor section 2. Reference numeral 3 denotes an N-type silicon substrate, and 4 denotes a P-type well composed of a plurality of layers. In this embodiment, the four-layer structure is 4A to 4D.

  N-type semiconductor layers 4E to 4G are sandwiched between the well layers 4A to 4D. 7 is a gate electrode of a transfer MOS transistor, 8 is an N-type charge storage region of the photodiode, 9 is a surface P-type region for embedding the photodiode, 5 is a field oxide film for element isolation, and 10 is a floating This is an N-type high concentration region that becomes a diffusion.

  11 is a silicon oxide film that insulates the gate electrode and the metal first layer, 12 is a contact plug, 13 is a metal first layer, 14 is an interlayer insulating film that insulates the metal first layer 13 and the metal second layer 15, The metal second layer 16 is an interlayer insulating film that insulates the metal second layer 15 and the metal third layer 17, 17 is a metal third layer, and 18 is a passivation film.

  Further, a color filter layer (not shown) and a microlens for improving sensitivity are formed on the passivation film 18. In this embodiment, three wiring layers are formed. However, depending on the specifications of the sensor, the wiring layers may be one layer or two layers in order to ensure optical characteristics.

  The four layers 4A to 4D of the multi-layer P-type well 4 perform the following functions.

  FIG. 5 is a graph showing the P-type well layer concentration distribution in the depth direction of the photodiode portion of the present embodiment, and FIG. 10 is a general P-type well layer concentration distribution of the prior art as a comparative example. It is a graph which shows.

  In 4B to 4D located in the shallow part of the structure part, a connecting part that guides the optical carrier to the photodiode in the pixel is formed, and the deepest part 4A forms a potential peak that determines the spectral sensitivity.

  Here, by setting the concentration of 4A, which is the deepest well layer, to be 5 times or more that of 4B, a sufficient potential barrier is formed between them, and carriers generated by incident light are lost in the substrate direction. Therefore, it is possible to efficiently lead to the photodiode without any problem, so that the sensitivity can be improved. The number of saturated charges that can be held in the N-type charge storage region 8 can also be controlled by controlling the concentration and depth of the 4D and 4C diffusion layers.

  In the present embodiment, the P-type well layer 4 composed of a plurality of layers has a four-layer structure of three connecting well layers and the deepest well layer. The number of connecting well layers depends on the required sensitivity. Therefore, the upper limit of the number of layers is not particularly set. Further, if at least one connecting well is formed, the effect of improving the sensitivity can be obtained.

  There is no problem even if there is no N-type region sandwiched between a plurality of P-type diffusion layers. In addition, when the P-type diffusion layers are arranged apart from each other, the two P-type diffusion layers are not in contact with each other. As a result, there is no problem even if an N-type layer exists between the P-type diffusion layers. However, in this case, it is necessary that the N-type region sandwiched between the two P-type diffusion layers is depleted.

  A manufacturing process of the photodiode portion will be described. The process up to the preparation of the P well is the same as that of the first embodiment. Thereafter, the P-type well layer 4 composed of a plurality of layers is sequentially implanted with P-type impurities (boron or the like) four times from a deep layer in this embodiment using a high-energy ion implantation apparatus, and then driven in. It is formed by not performing a high temperature heat treatment. The subsequent heat treatment is at most about 950 ° C. Since this P-type well layer 4 does not perform thermal diffusion, it becomes easy to control the concentration of each well layer.

  By reducing the concentration of 4B to 4D in the upper layer portion, the potential at this position can be lowered, so that the sensitivity is improved and a potential difference with the deepest layer 4A is easily formed. Next, after patterning with a photoresist, phosphorus is ion-implanted into the P-type well to form an N-well, and the subsequent manufacturing method is the same as that in the first embodiment, and is therefore omitted.

  As described above, the photocarrier absorbed in the well layer is lost in the direction of the substrate by making the well portion of the photodiode portion into a plurality of layers and making the concentration of the deepest well layer higher than the concentration of the well layer above it. Therefore, it is possible to efficiently lead to the photodiode, and the sensitivity can be improved as compared with the case of the first embodiment.

  Furthermore, by utilizing the well of this photodiode and forming an N well therein, it is possible to separate and form the N well used in the AD conversion section by a simple process, reducing noise and separating power. As a result, a high-quality solid-state imaging device could be formed as in the first embodiment.

[Third Embodiment]
The third embodiment will be described below. In the present embodiment, a silicide process using Co or the like is used for a part necessary for the AD conversion unit 103 shown in FIG. 1 to perform high-speed operation, thereby reducing wiring resistance and contact resistance. High speed was made possible. 100, 102, 104 and 105 in FIG. 1 are not silicided.

  This is because metal contamination is not brought into the photodiode, and dark current and other characteristics of the photodiode are not different from those of the first embodiment. The digital circuit section including the AD conversion section can be increased in speed by about 20%, and a high-performance solid-state image sensor can be realized.

[Fourth Embodiment]
Hereinafter, a fourth embodiment will be described. In the present embodiment, the gate oxide film at the portion requiring the high speed operation of the AD conversion unit 103 in FIG. 1 is made thinner than the other portions, thereby further increasing the speed.

  The gate oxide film of elements other than 103 in FIG. 1 is not thinned. This is to enable driving with a high voltage, and the characteristics of the dark current and other photodiodes are the same as those in the first and second embodiments. The digital circuit unit including the AD conversion unit can be increased in speed by about 20%, and a high-performance solid-state imaging device can be realized. Needless to say, this technique is more effective when combined with the third embodiment, which is a tradeoff between process complexity and performance.

[Fifth Embodiment]
FIG. 6 is a block diagram showing a fifth embodiment of the present invention. The pixel area 100 includes a CMOS sensor pixel 101 formed of a photoelectric conversion unit and a transistor.

  Although this embodiment is described with a 3 × 3 example, the number is not particularly limited, and for example, those arranged in a line are also included. An analog output from each pixel is input to a circuit unit 102 such as a CDS (correlated double sampling) by a signal from the scanning circuit 105 in the vertical direction.

  Next, the analog signal of each column is converted into a digital signal by the AD converter for each column indicated by 112. Subsequently, signals are sequentially taken out by signals from the scanning circuit 118.

  Since a signal for each column is converted into a digital signal, high-speed operation is possible. On the other hand, there are many circuits that perform high-speed operation as compared with the first embodiment, and adjacent to the analog circuit unit 102. Because of the presence of noise, disturbances in noise caused by high-speed operation become a major issue, and the configuration of this embodiment is necessary.

  Furthermore, it is more preferable to separate the power supply voltage for higher speed and lower power consumption. In this embodiment, a part of the AD conversion unit indicated by 104 or 112 is lowered to reduce power consumption. And low noise was realized.

  FIG. 7 is a circuit diagram showing an example of an AD converter.

  As shown in FIG. 7, the AD converter includes a comparator 113, a storage unit 114, a transfer switch 115, a readout switch 116, a counter 117, and a scanning circuit 118. Basically, it is preferable to lower the voltage for the circuit block after the change to a digital signal. In the example of FIG. 6, it is preferable to lower the voltages of 114, 115, 116, 117, and 118. There is nothing. For example, if the dynamic range of the analog output from the pixel is small, it is needless to say that there is an effect even if the voltage is lowered including 113 and 102, and there is no particular limitation.

[Sixth Embodiment]
FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.

  In the sixth embodiment, a Multi-Slope integrating AD Converter is used as the AD converter for each column. Since the comparator 113 and subsequent circuits are basically the same as those in the fifth embodiment, a description thereof will be omitted. Reference numeral 119 denotes an integrator that outputs an integrated value of the voltage depending on the output signal. 120 is two kinds of reference voltages, and 121 is a reference voltage to the comparator. Reference numeral 123 denotes a counter, a scanning circuit, and other circuits thereafter.

  FIG. 9 is a timing chart showing the operation of the present embodiment. The switch 122 integrates the output value from the pixel for a certain period (input voltage integration period) and inputs it to the comparator.

  Next, the input to the integrator is changed from the pixel to the reference voltage 1, and the higher bit of the output from the pixel is determined. This is realized by storing the signal when the reference voltage for comparison (reference voltage 3) is exceeded.

Next, the integration is performed by changing the input to the integrator to the reference voltage 2 for the determination of the lower bits. Rather than 2 ¹² steps when performing for example 12-bit AD conversion doing so, 2 ⁶ Step 2 ⁶ steps and lower bits with upper bits, is converted by a total of 2 ⁷ steps are possible completion faster.

  At this time, since the high-speed digital operation is performed adjacent to the pixel region and the CDS region as in the fifth embodiment, well separation is very effective against noise in order to prevent this disturbance.

  In particular, in the present embodiment, an analog circuit sensitive to noise such as an integrator is used for the solid-state imaging device, and the configuration of the present invention is very effective.

  Further, in reducing the voltage and power consumption, it is effective to change the power supply voltage, and further, the photodiode configuration can be individually optimized, so that it is combined with the photodiode configuration described in the second embodiment. Implementation will make a dramatic leap in performance.

It is a top view which shows the CMOS sensor as the 1st Embodiment of this invention. It is a schematic cross section which shows the typical cross section of FIG. It is sectional drawing for demonstrating the preparation methods of embodiment of this invention. The transfer MOS transistor section 2 is shown. It is a graph which shows the P-type well layer density | concentration distribution to the depth direction of the photodiode part of embodiment of this invention. It is a block diagram which shows the 5th Embodiment of this invention. It is a circuit diagram which shows an example of AD converter. It is a circuit diagram which shows the 6th Embodiment of this invention. It is a timing chart which shows operation | movement of embodiment of this invention. It is a graph which shows the density | concentration distribution of the substrate depth direction of the well layer of the conventional photodiode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Pixel part 101 Pixel 102 Peripheral circuit part 103 Analog-digital conversion part 104 Scan circuit 105 Scan circuit

Claims (5)

A circuit for driving the digital conversion unit, the photoelectric conversion unit, - a pixel unit including a photoelectric conversion portion formed on a semiconductor substrate, an electrical signal photoelectrically converted analog by the photoelectric conversion unit - an analog to digital conversion In a solid-state imaging device comprising:
Wherein the pixel portion web in Le formed analog - digital conversion unit is formed, the circuit section, said pixel section and said analog - not formed in said well-digital conversion unit is formed, the A solid-state imaging device characterized by being electrically separated from a well . The photoelectric conversion unit is provided with a photodiode, the photodiode comprises a plurality of layers of the same conductivity type are stacked in the depth direction of the semiconductor substrate in the well, the deepest layer of the plurality of layers The solid-state imaging device according to claim 1, wherein the density is higher than that of other layers. 3. The solid-state imaging device according to claim 2, wherein the concentration of the deepest layer is at least five times the concentration of the other layer. Wherein the plurality of layers, respectively, the solid-state imaging device according to claim 2 or 3 further characterized in that a peak of the impurity concentration. The power supply voltage of the photoelectric conversion unit analog - digital conversion of at least a portion of the power supply voltage and the solid-state imaging device according to any one of claims 1 to 4, characterized in that it is set individually.

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