JP4536788B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device connected to a differential communication line.

  A semiconductor device connected to a differential communication line is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2007-318734 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2006-67543 (Patent Document 2).

  FIG. 15 is a configuration diagram of a differential communication network disclosed in Patent Document 1.

  The differential communication network shown in FIG. 15 is a network that is mounted on a vehicle and in which a plurality of nodes are connected in parallel by bus for control communication between the nodes. The differential communication network includes a plurality of nodes (semiconductor devices) 10 and a differential communication line (bus line) 12 that connects the plurality of nodes 10 to each other.

  Each node 10 is a control controller (hereinafter referred to as an ECU) for controlling an actuator based on information from the sensors and sensors for detecting the state of the vehicle. Further, the differential communication line 12 is a line that mediates a control communication signal between the sensor and the ECU, and includes a pair of twisted lines. Hereinafter, the phase conductors of the differential communication line 12 are referred to as 12a and 12b. The differential conductors 12a and 12b of the differential communication line 12 carry differential signals that are in opposite phases to each other and cause a potential difference.

  Each node 10 is provided with a communication circuit. In the communication circuit, the node 10 converts transmission data and reception data in accordance with a communication protocol in the differential communication line 12 and communicates with other nodes 10 via the differential communication line 12.

  The differential communication line 12 is mounted on the body 14 of the vehicle and is stretched around the vehicle body in the front-rear and left-right directions. In the middle of the differential communication line 12, a hub 16 incorporating two bus bars for branching the differential communication line 12 and a through connector 18 for freely connecting / disconnecting with the network are provided. Is provided.

In the differential communication line 12, a part in which a harness group 20 such as a power line for driving different types of communication lines and actuators used in an in-vehicle system different from the differential communication network runs in parallel (part of FIG. 15 shows a part thereof). ) The parallel running harness group 20 includes a differential harness, a single end harness that returns to the vehicle body, and the like. The parallel running portion of the differential communication line 12 and the parallel running harness group 20 is a harness bundle 22 that is previously tightly bundled with a tape or the like. The position of the harness bundle 22 is, for example, a portion under the vehicle door that connects the front portion and the rear portion of the vehicle.
JP 2007-318734 A JP 2006-67543 A

  In the configuration diagram of the differential communication network illustrated in FIG. 15, when a surge such as ESD (Electro Static Discharge) is applied to the phase conductors 12 a and 12 b of the differential communication line 12, the semiconductor device of each node 10 is destroyed. There is a risk. Further, in the semiconductor device at each node 10, if there is an overshoot (ringing) at the rising and falling of the voltage of the input signal from each phase conductor 12a, 12b, a malfunction occurs in the semiconductor device.

  Accordingly, an object of the present invention is a semiconductor device connected to a differential communication line, and prevents surge current from flowing into the semiconductor device when a surge is applied to each phase conductor of the differential communication line. An object of the present invention is to provide a semiconductor device capable of preventing malfunction of the semiconductor device by suppressing overshoot (ringing) superimposed on the input signal waveform from each phase conductor.

  The semiconductor device according to claim 1 is a semiconductor device connected to a differential communication line, and is disposed as an input circuit between each phase conductor of the differential communication line and a ground line or a power line. Breakdown when a surge of a predetermined voltage or more is applied to each phase conductor, and a break-off element that releases the surge to the ground line or the power line, and is inserted between each phase conductor of the differential communication line, An impedance control circuit that changes the impedance of the phase conductor when the potential difference between the phase conductors is greater than a predetermined voltage, and is connected to the impedance control circuit on a semiconductor substrate on which the breakdown element is formed A third contact region of the wiring is connected to the ground line or the power supply line of the breakdown element. In between, and it is characterized by comprising formed opposite to the first contact region of the wiring connected to the phase conductor of the breakdown element.

  The semiconductor device has, as an input circuit, a breakdown element inserted between each phase conductor and a ground line or a power supply line, and an impedance control circuit inserted between each phase conductor of the differential communication line. is doing. The breakdown element does not affect the normal operation of the semiconductor device, breaks down when a surge is applied to each phase conductor of the differential communication line, and releases the surge current to the ground line or the power supply line. Prevents surge current from flowing into the. The impedance control circuit also suppresses overshoot (ringing) by changing its own impedance to a small extent when the input signal waveform from each phase conductor of the differential communication line has overshoot (ringing). Prevents malfunction.

  Further, when a surge is applied to the first contact region connected to each phase conductor of the breakdown element, the surge current is promptly applied from the first contact region to the second contact region connected to the ground line or the power supply line. Flows in. For this reason, the surge current can be prevented from flowing into the third contact region connected to the impedance control circuit arranged on the opposite side of the first contact region with the second contact region interposed therebetween. Therefore, in the semiconductor device, not only the surge current flows into the internal circuit but also the impedance control circuit can be suppressed, and the impedance control circuit can be prevented from being destroyed by the surge current.

  As described above, the semiconductor device is a semiconductor device connected to a differential communication line, and when a surge is applied to each phase conductor of the differential communication line, a surge current flows into the semiconductor device. In addition, the semiconductor device can prevent malfunction by suppressing overshoot (ringing) superimposed on the input signal waveform from each phase conductor.

  The breakdown element in the semiconductor device can be composed of, for example, two symmetrical MOS transistors or diodes connected in series as described in claim 2. According to this, it is possible to cope with the case where the input signal of each phase conductor of the differential communication line can take both a positive voltage and a negative voltage.

  On the other hand, when the input signal of each phase conductor of the differential communication line is only one of a positive voltage and a negative voltage, for example, as in claim 3, the breakdown element is connected to one lateral MOS. You may comprise with a transistor or a diode.

  In the semiconductor device, for example, the semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film, and the breakdown element is formed of a lateral MOS transistor. A MOS transistor is formed in an SOI layer region surrounded by an insulating isolation trench that reaches the buried oxide film, the first contact region is a drain region of the lateral MOS transistor, and the second contact region is The third MOS region may be a source region of the lateral MOS transistor, and the third contact region may be formed in the SOI layer region.

  Further, for example, as in claim 5, the semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film, the breakdown element is formed of a diode, and the diode is formed of the buried oxide. Formed in an SOI layer region surrounded by an insulating isolation trench reaching the film, wherein the first contact region is a cathode region of the diode, and the second contact region is an anode region of the diode; The third contact region may be formed in the SOI layer region.

  In the semiconductor device described above, it is preferable that an insulating trench is disposed between the third contact region and the second contact region. The insulation trench can block the shortest current path to suppress the surge current from flowing into the impedance control circuit and the internal circuit.

  According to a seventh aspect of the present invention, a diffusion region having a conductivity type opposite to that of the semiconductor substrate may be disposed between the third contact region and the second contact region. Also in this case, the shortest current path is blocked by the diffusion region, so that the surge current can be prevented from flowing into the impedance control circuit and the internal circuit.

  The impedance control circuit in the semiconductor device can be configured by a MOS transistor or a bipolar transistor, as described in claim 8, for example.

  As described above, the semiconductor device is a semiconductor device connected to a differential communication line, and when a surge is applied to each phase conductor of the differential communication line, a surge current flows into the semiconductor device. In addition, the overshoot (ringing) superimposed on the input signal waveform from each phase conductor can be suppressed, and malfunction of the semiconductor device can be prevented.

  Therefore, as described in claim 9, the semiconductor device is suitable as an in-vehicle semiconductor device that is used in a harsh environment where the surge or overshoot (ringing) is likely to occur.

  The present invention relates to a semiconductor device connected to a differential communication line. The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of a semiconductor device 100 as an example of the semiconductor device of the present invention. FIG. 2 is a diagram in which the semiconductor device 100 of FIG. 1 is embodied by circuit elements, and is an equivalent circuit diagram of the semiconductor device 100. 3 and 4 are more specific views of the semiconductor device 100 of FIG. 2, and are a cross-sectional view and a top view schematically showing the structure of the semiconductor device 100, respectively.

  A semiconductor device 100 shown in FIG. 1 is an in-vehicle semiconductor device connected to a differential communication line (bus line), and is a semiconductor device corresponding to each node 10 in the differential communication network shown in FIG. . In FIG. 1, each phase conductor of the differential communication line is indicated by BP (bus line plus) and BM (bus line minus).

  As shown in FIG. 1, the semiconductor device 100 includes breakdown elements E1 and E2 and an impedance control circuit K1 as input circuits.

  Breakdown elements E1 and E2 are inserted between the phase conductors BP and BM of the differential communication line and the ground line, and break down when a surge of a predetermined voltage or higher is applied to each phase conductor BP and BM. , Miss surge to ground line. The breakdown elements E1 and E2 in the semiconductor device 100 are respectively composed of two symmetrical MOS transistors L11 and L12 and L21 and L22 connected in series as shown in FIG. In the semiconductor device 100, both the breakdown elements E1 and E2 are inserted between the phase conductors BP and BM of the differential communication line and the ground line. However, the present invention is not limited to this, and one or both of the breakdown elements E1 and E2 are inserted between the phase conductors BP and BM and the power supply line, and a surge of a predetermined voltage or more is applied to each phase conductor BP and BM. When applied, the surge may escape to the power line.

  As described above, the breakdown elements E1 and E2 do not affect the normal operation of the semiconductor device 100, and break down to generate a surge current when a surge is applied to the phase conductors BP and BM of the differential communication line. It escapes to the ground line or the power supply line and prevents the surge current from flowing into the semiconductor device 100.

  The impedance control circuit K1 is inserted between the phase conductors BP and BM of the differential communication line, and changes its own impedance small when the potential difference between the phase conductors BP and BM is larger than a predetermined voltage. As shown in FIG. 2, the impedance control circuit K1 of the semiconductor device 100 is configured by MOS transistors M1 and M2. However, the present invention is not limited thereto, and may be configured by, for example, a bipolar transistor.

  FIG. 5 is a diagram illustrating the function of the impedance control circuit K1. FIG. 5A is a diagram showing an input signal waveform with overshoot (ringing) from the phase conductors BP and BM of the differential communication line, and FIG. 5B is a diagram after passing through the impedance control circuit K1. It is the figure which showed the signal waveform of each phase conductor BP, BM. As shown in FIG. 5, when there is an overshoot (ringing) in the input signal waveforms from the phase conductors BP and BM of the differential communication line, the impedance control circuit K1 changes its own impedance to a small value to overshoot ( Ringing) and the malfunction of the semiconductor device 100 is prevented.

  More specifically, the impedance control circuit K1 detects the voltage between the phase conductors BP and BM, and adjusts the impedance between the phase conductors BP and BM based on the potential difference. When the potential difference between the phase conductors BP and BM is small, the impedance is high and switching is performed at high speed. When the potential difference becomes larger than a certain threshold value, the impedance is lowered and the switching speed is lowered. As a result, voltage ringing is reduced, noise emission can be reduced, and a sufficient potential difference between the phase conductors BM and BM necessary for communication can be secured.

  As described above, the breakdown elements E1 and E2 in the semiconductor device 100 are each composed of two symmetrical MOS transistors L11 and L12 and L21 and L22 that are connected in series. This corresponds to the case where the input signals of the phase conductors BP and BM of the differential communication line shown in FIG. 5 can take both positive and negative voltages.

  As shown in FIG. 3, the semiconductor device 100 is formed on an SOI structure semiconductor substrate (SOI layer) 1 having a buried oxide film 2. Further, the lateral MOS transistors L11, L12, L21, L22 constituting the breakdown elements E1, E2 are formed in the SOI layer region surrounded by the insulating isolation trench T1 reaching the buried oxide film 2. Further, in the SOI layer region where the lateral MOS transistor L11 of the breakdown element E1 is formed, the third contact region C3 of the wiring SP connected to the impedance control circuit K1 is the second contact of the wiring connected to the ground line. It is formed on the side opposite to the first contact region (drain region) C1 of the wiring connected to each phase conductor BP with the region (source region) C2 interposed therebetween. Similarly, in the SOI layer region in which the lateral MOS transistor L21 of the breakdown element E2 is formed, the third contact region C6 of the wiring SM connected to the impedance control circuit K1 is the second wiring connected to the ground line. It is formed on the side opposite to the first contact region (drain region) C4 of the wiring connected to each phase conductor BM with the contact region (source region) C5 interposed therebetween.

  In the semiconductor device 100, when a surge is applied to the first contact regions (drain regions) C1 and C4 connected to the phase conductors BP and BM in the lateral MOS transistors L11 and L21 of the breakdown elements E1 and E2, respectively. The surge current immediately flows from the first contact regions C1 and C4 into the second contact regions (source regions) C2 and C5 connected to the ground line (or power supply line). Therefore, the surge current is prevented from flowing into the third contact regions C3 and C6 connected to the impedance control circuit disposed on the opposite side of the first contact regions C1 and C4 with the second contact regions C2 and C5 interposed therebetween. can do. Therefore, in the semiconductor device 100, not only the surge current can flow into the internal circuit but also the flow into the impedance control circuit K1 can be suppressed, and the destruction of the impedance control circuit K1 due to the surge current can be prevented.

  As described above, the semiconductor device 100 shown in FIGS. 1 to 4 is a semiconductor device connected to the differential communication line, and when a surge is applied to the phase conductors BP and BM of the differential communication line. In addition, the semiconductor device 100 can prevent a surge current from flowing into the semiconductor device 100 and suppress overshoot (ringing) superimposed on the input signal waveforms from the phase conductors BP and BM, thereby preventing malfunction. ing.

  6 to 8 are examples of other semiconductor devices, and FIG. 6 is an equivalent circuit diagram of the semiconductor device 101. 7 and 8 are a cross-sectional view and a top view schematically showing the structure of the semiconductor device 101, respectively. In addition, in each semiconductor device illustrated below, the same code | symbol was attached | subjected about the part similar to the semiconductor device 100 shown in FIGS. 1-4. Further, in the cross-sectional views of the respective semiconductor devices exemplified below, the impedance control circuit K1 is not shown for simplification.

  In the semiconductor device 100 shown in FIGS. 1 to 4, the breakdown elements E1 and E2 are each composed of two symmetrical MOS transistors L11 and L12 and L21 and L22 that are connected in series. On the other hand, in the semiconductor device 101 shown in FIGS. 6 to 8, the breakdown elements E3 and E4 are each composed of one lateral MOS transistor L11 and L21. When the input signal of each phase conductor BP, BM of the differential communication line shown in FIG. 5 is only one of a positive voltage and a negative voltage, one piece is provided as in the semiconductor device 101 shown in FIGS. The surge current may be escaped to the ground line or the power supply line by the element.

  Also in the semiconductor device 101, as shown in FIG. 7, the wiring SP connected to the impedance control circuit K1 in the SOI layer region where the lateral MOS transistors L11 and L21 of the breakdown elements E3 and E4 are formed, respectively. The third contact regions C3 and C6 of the wiring connected to the respective phase conductors BP and BM with the second contact regions (source regions) C2 and C5 of the wiring connected to the ground line in between. The drain region is formed on the side opposite to C1 and C4. Accordingly, in the semiconductor device 101 shown in FIGS. 6 to 8, not only the surge current flows into the internal circuit but also the impedance control circuit K1 as in the semiconductor device 100 shown in FIGS. Therefore, it is possible to prevent the impedance control circuit K1 from being damaged by the surge current.

  The above effect will be described in more detail with the semiconductor device 101 of FIGS. 6 to 8, which is simpler than the semiconductor device 100 of FIGS. In the breakdown element E3 of the semiconductor device 101, for example, a positive voltage ESD surge applied to each phase conductor BP passes through the drain region n from the first contact region (drain region n +) C1 of the lateral MOS transistor L11, and the semiconductor substrate. (SOI layer n−) 1 is applied. Therefore, a breakdown occurs with the body region p of the lateral MOS transistor L11, and a surge current passes through the second contact region (source region) C2 to the ground line (or power supply line) connected with low impedance. Flow away.

  A third contact region (diffusion region n +) C3 is disposed outside the current path, and is connected to the impedance control circuit K1 by a wiring SP. For this reason, most of the surge current flows into the second contact region (source region) C2, and the surge current is prevented from flowing into the impedance control circuit K1. The third contact region C3 is connected by the same N conductivity type semiconductor layer as the first contact region (drain region n +) C1 of the lateral MOS transistor L11 to which each phase conductor BP is connected. The wiring SP connected to the control circuit K1 has substantially the same potential. As described above, in the semiconductor device 101, it is possible to prevent the impedance control circuit K1 connected to each phase conductor BP from being damaged by the surge current. The breakdown element E4 of the semiconductor device 101 also functions in the same manner as described above.

  As described above, in the semiconductor device 101, the potentials of the phase conductors BP and BM are guided to the impedance control circuit K1 by the wirings SP and SM, and the potential difference between the phase conductors BP and BM (potential difference of the wirings SP and SM) The impedance of the impedance control circuit K1 is changed.

  9 and 10 are also examples of another semiconductor device. FIG. 9 is an equivalent circuit diagram of the semiconductor device 102, and FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor device 102. FIG.

  In the semiconductor device 100 shown in FIGS. 1 to 4, the breakdown elements E1 and E2 are each composed of two symmetrical MOS transistors L11 and L12 and L21 and L22 that are connected in series. On the other hand, in the semiconductor device 102 shown in FIGS. 9 and 10, the breakdown elements E5 and E6 are constituted by two symmetrically connected diodes D11, D12 and D21, D22.

  Also in the semiconductor device 102, as shown in FIG. 10, the third contact of the wiring SP connected to the impedance control circuit K1 in the SOI layer region where the diodes D11 and D21 of the breakdown elements E5 and E6 are formed. Regions C3 and C6 are first contact regions (cathode regions) C1 of wirings connected to the respective phase conductors BP and BM, with second contact regions (anode regions) C2 and 5 of wirings connected to the ground line interposed therebetween. , C4 is formed on the opposite side. Therefore, in the semiconductor device 102 shown in FIGS. 9 and 10, not only the surge current flows into the internal circuit but also the impedance control circuit K1 as in the semiconductor device 100 shown in FIGS. Therefore, it is possible to prevent the impedance control circuit K1 from being damaged by the surge current.

  The breakdown elements E5 and E6 in the semiconductor device 102 are each composed of two symmetrically connected diodes D11 and D12 and D21 and D22. This corresponds to the case where the input signals of the phase conductors BP and BM of the differential communication line shown in FIG. 5 can take both positive and negative voltages. As in the case of the semiconductor devices 100 and 101 in which the breakdown element is configured by a lateral MOS transistor, the input signal of each phase conductor BP and BM of the differential communication line shown in FIG. 5 is either a positive voltage or a negative voltage. In the case of only one of them, it is possible to configure each of the breakdown elements with one diode even in a semiconductor device in which the breakdown elements are configured with diodes.

  Next, a more preferable form of the semiconductor devices 100 to 102 will be described.

  FIG. 11 is a cross-sectional view schematically showing the structure of the semiconductor device 103.

  In the structure of the breakdown elements E7 and E8 in the semiconductor device 103 of FIG. 11, the third contact regions C3 and C6 and the second contact region are compared with the structure of the breakdown elements E3 and E4 of the semiconductor device 101 shown in FIG. An insulating trench T2 that does not reach the buried oxide film 2 is disposed between C2 and C5 so as to block the shortest current path. With the insulating trench T2, the semiconductor device 103 in FIG. 11 can further suppress the surge current from flowing into the impedance control circuit and the internal circuit as compared with the semiconductor device 101 in FIG.

  12 and 13 are top views schematically showing the structures of the semiconductor devices 104 and 105, respectively.

  The structure of the breakdown elements E9, E10 and E11, E12 in the semiconductor devices 104, 105 of FIGS. 12 and 13 is compared with the structure of the breakdown elements E3, E4 in the semiconductor device 101 shown in FIG. Between the regions C3 and C6 and the second contact regions C2 and C5, insulating trenches T3 and T4 formed so as to protrude from the insulating isolation trench T1 are disposed so as to block the shortest current path. With the insulating trenches T3 and T4, the semiconductor devices 104 and 105 in FIGS. 12 and 13 can further suppress the surge current from flowing into the impedance control circuit and the internal circuit as compared with the semiconductor device 101 in FIG. . Since the insulating trenches T3 and T4 in the semiconductor devices 104 and 105 in FIGS. 12 and 13 can be formed simultaneously by the process of forming the insulating isolation trench T1, the process cost is low. Further, the impedance between the first contact regions C1, C4 and the third contact regions C3, C6 can be controlled by the gap interval between the insulating trenches T3, T4.

  FIG. 14 is a cross-sectional view schematically showing the structure of the semiconductor device 106.

  In the structure of the breakdown elements E13 and E14 in the semiconductor device 103 of FIG. 14, the third contact regions C3 and C6 and the second contact region are compared with the structure of the breakdown elements E3 and E4 of the semiconductor device 101 shown in FIG. Between C2 and C5, a diffusion region S1 having a conductivity type opposite to that of the semiconductor substrate 1 is disposed so as to block the shortest current path. With the diffusion region S1, the semiconductor device 106 in FIG. 14 can further suppress the surge current from flowing into the impedance control circuit and the internal circuit as compared with the semiconductor device 101 in FIG.

As described above, in FIGS. 11 to 14, the breakdown element composed of one lateral MOS transistor has been described as an example. However, the breakdown element composed of two symmetrical series-connected lateral MOS transistors. In addition, the same effect can be obtained for the breakdown element constituted by a diode by disposing the insulating trenches T2 to T4 and the diffusion region S1.

  The semiconductor devices 100 to 106 use the SOI structure semiconductor substrate. However, the present invention is not limited to this, and a bulk silicon single crystal substrate may be used as the semiconductor substrate, and each element may be separated by PN junction, for example.

  As described above, the semiconductor device is a semiconductor device connected to a differential communication line, and when a surge is applied to each phase conductor of the differential communication line, a surge current flows into the semiconductor device. In addition, the overshoot (ringing) superimposed on the input signal waveform from each phase conductor can be suppressed, and malfunction of the semiconductor device can be prevented.

  Therefore, the semiconductor device is suitable as a vehicle-mounted semiconductor device that is used in a harsh environment in which surge and overshoot (ringing) are likely to occur.

1 is a block diagram of a semiconductor device 100 as an example of a semiconductor device of the present invention. FIG. 2 is a diagram in which the semiconductor device 100 of FIG. 1 is embodied by circuit elements and is an equivalent circuit diagram of the semiconductor device 100. FIG. 3 is a more specific view of the semiconductor device 100 of FIG. 2, and is a cross-sectional view schematically showing the structure of the semiconductor device 100. FIG. 3 is a more specific view of the semiconductor device 100 of FIG. 2, and is a top view schematically showing the structure of the semiconductor device 100. FIG. 6A is a diagram illustrating the function of the impedance control circuit K1, and FIG. 5A is a diagram illustrating an input signal waveform with overshoot (ringing) from each phase conductor BP, BM of the differential communication line; These are the figures which showed the signal waveform of each phase conductor BP and BM after passing impedance control circuit K1. FIG. 6 is an equivalent circuit diagram of the semiconductor device 101 as another example of the semiconductor device. 2 is a cross-sectional view schematically showing the structure of a semiconductor device 101. FIG. 1 is a top view schematically showing the structure of a semiconductor device 101. FIG. FIG. 5 is an equivalent circuit diagram of the semiconductor device 102 as another example of the semiconductor device. 2 is a cross-sectional view schematically showing the structure of a semiconductor device 102. FIG. 2 is a cross-sectional view schematically showing the structure of a semiconductor device 103. FIG. 3 is a top view schematically showing the structure of a semiconductor device 104. FIG. 2 is a top view schematically showing the structure of a semiconductor device 105. FIG. 2 is a cross-sectional view schematically showing the structure of a semiconductor device 106. FIG. 1 is a configuration diagram of a differential communication network disclosed in Patent Document 1. FIG.

Explanation of symbols

100 to 106 Semiconductor device BP, BM Phase conductors E1 to E14 Breakdown elements L11, L12, L21, L22 Horizontal MOS transistors D11, D12, D21, D22 Diode C1 First contact region C2 Second contact region C3 Third contact region SP, SM wiring K1 Impedance control circuit M1, M2 MOS transistor 1 Semiconductor substrate (SOI layer)
2 buried insulating film T1 insulating isolation trench T2 to T4 insulating trench S1 diffusion region

Claims (9)

A semiconductor device connected to a differential communication line,
As an input circuit,
The differential communication line is inserted and disposed between each phase conductor and a ground line or a power supply line, and breaks down when a surge of a predetermined voltage or more is applied to each phase conductor, and the surge is broken into the ground line or power supply line. Breakdown element to miss,
An impedance control circuit that is inserted between the phase conductors of the differential communication line, and that changes its own impedance when the potential difference between the phase conductors is greater than a predetermined voltage;
A third contact region of the wiring connected to the impedance control circuit is interposed between the second contact region of the wiring connected to the ground line or the power supply line of the breakdown device on the semiconductor substrate on which the breakdown device is formed. A semiconductor device, wherein the semiconductor device is formed on the opposite side of the first contact region of the wiring connected to each phase conductor of the breakdown element.   2. The semiconductor device according to claim 1, wherein the breakdown element is composed of two symmetrical MOS transistors or diodes connected in series.   2. The semiconductor device according to claim 1, wherein the breakdown element is composed of one lateral MOS transistor or a diode. The semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film;
The breakdown element is composed of a lateral MOS transistor,
The lateral MOS transistor is formed in an SOI layer region surrounded by an insulating isolation trench reaching the buried oxide film;
The first contact region is a drain region of the lateral MOS transistor;
The second contact region is a source region of the lateral MOS transistor;
4. The semiconductor device according to claim 1, wherein the third contact region is formed in the SOI layer region. 5. The semiconductor substrate is an SOI structure semiconductor substrate having a buried oxide film;
The breakdown element is composed of a diode;
The diode is formed in an SOI layer region surrounded by an insulating isolation trench reaching the buried oxide film;
The first contact region is a cathode region of the diode;
The second contact region is an anode region of the diode;
4. The semiconductor device according to claim 1, wherein the third contact region is formed in the SOI layer region. 5.   The semiconductor device according to claim 1, wherein an insulating trench is disposed between the third contact region and the second contact region.   The semiconductor device according to claim 1, wherein a diffusion region having a conductivity type opposite to that of the semiconductor substrate is disposed between the third contact region and the second contact region. . The impedance control circuit is
The semiconductor device according to claim 1, comprising a MOS transistor or a bipolar transistor.   The semiconductor device according to claim 1, wherein the semiconductor device is for in-vehicle use.

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