JP4538508B2 - Receiver, electronic device - Google Patents

Description

  The present invention relates to a receiver, and in particular, a digital signal in which an optical signal is a pulse train having a known pulse width and having at least a first pulse having a short pulse width and a second pulse having a long pulse width. The present invention relates to a receiver that can receive signals.

  Infrared communication is a communication means applied in various electronic devices such as mobile phone terminals and wireless earphones. Among them, an IrDA communication device that is an infrared communication device compliant with IrDA (Infra-red Data Association), which is a global standard in infrared communication, is applied to many mobile phone terminals as an information exchange means between users.

  An example of a general connection configuration of an electronic apparatus including such an IrDA communication device is shown in FIG.

  As shown in FIG. 13, the electronic device 130 includes an IrDA communication device 131 as a receiver, and a control system 132 is connected to the subsequent stage. The control system 132 performs various controls on the IrDA communication device 131. Examples of the control system 132 include an application processor and a UART (universal asynchronous receiver / transmitter). “RX” shown in FIG. 13 indicates an optical signal acquired from the outside by the IrDA communication device 131 through infrared communication, and “TX” shown in FIG. 13 controls the IrDA communication device 131 by the control system 132. The control signal for doing is shown.

  In recent years, the use of IrDA communication devices conforming to the FIR (Fast Infra Red) standard with a maximum communication speed of 4 Mbps is remarkable.

  In infrared communication compliant with the above FIR standard, a four-value PPM (Pulse Position Modulation) modulation method is employed as a modulation method of a transmitted optical signal. In the 4-level PPM modulation method, an optical signal is transmitted after being modulated into a data string whose pulse position is defined in units of 2 bits. “00”, “01”, “10”, and “11” have a known pulse width that is the same as each other and the pulse positions are different from each other. This is a pulse train having four types of pulses (see FIG. 14). Here, as shown in FIG. 14, in the above pulse train, when the “00” pulse is transmitted after the “11” pulse, the “11” pulse and the “00” pulse are combined. Thus, a pulse having a pulse width corresponding to twice the known pulse width is generated. In the FIR standard, a pulse having a pulse width corresponding to twice the known pulse width (that is, the above-mentioned coalescence is generated) is a double pulse, and a pulse having a known pulse width (that is, the above-mentioned coalescence is not generated). ) The pulse is called a single pulse.

  By the way, in infrared communication devices such as an IrDA communication device, the pulse width may vary during transmission of a pulse train (data train) due to its characteristics. In the present application, “pulse width variation” means a phenomenon in which a pulse train received by a communication device on the receiving side is different from a pulse train transmitted by the communication device on the transmitting side on the time axis. Examples of fluctuations in the pulse width include pulse thickening (a phenomenon in which the pulse width of a specific pulse widens), pulse thinning (a phenomenon in which the pulse width of a specific pulse narrows due to partial loss of the pulse), and pulse cracking (a pulse The phenomenon of one pulse being separated into a plurality of pulses due to partial defects) and the generation of false pulses (pulses that should not exist originally) can be mentioned. This fluctuation of the pulse width also occurs in a data string in which the pulse position is defined in units of 2 bits, and occurs more frequently as the distance of data communication becomes longer. In addition, the fluctuation of the pulse width may occur due to the influence of disturbance light or the like.

  In the infrared communication conforming to the FIR standard, when the above-described fluctuation of the pulse width occurs in the data string in which the pulse position is defined in units of 2 bits, an electronic device including the infrared communication device as a receiver has a single pulse and a double pulse. There is a possibility of misrecognizing. For example, when a pulse fatness occurs in a single pulse, the electronic device may erroneously recognize the single pulse as a double pulse. On the contrary, when the pulse narrows in the double pulse, the electronic device may erroneously recognize the double pulse as a single pulse. When such erroneous recognition of a single pulse and a double pulse occurs, it becomes difficult for an electronic device to receive accurate data. For this reason, in such an electronic device, it is necessary to distinguish between a single pulse and a double pulse.

  Conventionally, discrimination of single pulse and double pulse in the electronic apparatus has been mainly performed on the control system side. However, when discrimination is performed on the control system side, a discrimination error occurs if the performance of the control system is low. In other words, as the distance of data communication increases, the control system misrecognizes a single pulse with a fat pulse as a double pulse, or misrecognizes a double pulse with a thin pulse as a single pulse. The risk of doing so increases. As a result, the control system receives incorrect data.

  In realizing the above control system, it is necessary to fully consider compatibility with an infrared communication device. Therefore, it is never easy to realize a control system that is compatible with the infrared communication device.

  Therefore, Patent Document 1 proposes the following pulse data demodulator as a technique that can receive a single pulse and a double pulse without making an error.

The demodulator disclosed in Patent Document 1 analyzes the pulse width of a single pulse and a double pulse defined by the packet format for each packet unit, and based on the analysis result, calculates a single pulse and a double pulse. A threshold value for discrimination is determined. And in the demodulator disclosed in Patent Document 1, the pulse data is compared with a threshold value, so as to discriminate between a single pulse and a double pulse. As a result, the demodulator disclosed in Patent Document 1 receives the pulse data without erroneously discriminating between the single pulse and the double pulse even when the pulse data fluctuates. It is possible.
Japanese Patent Laying-Open No. 2006-211510 (released on August 10, 2006)

  In the technique disclosed in Patent Document 1, a single pulse and a double pulse are discriminated based on a threshold value determined based on a single pulse and a double pulse defined by a packet format. Note that the demodulator disclosed in Patent Document 1 uses a preamble as a single pulse used to determine a threshold and a start flag as a double pulse used to determine a threshold.

  However, when the reception characteristics of the receiver change drastically and fluctuations in the pulse width occur in the single pulse and the double pulse specified in the packet format, the determined threshold value itself is the single pulse in the pulse data. Therefore, it may be an inappropriate value for the discrimination between the double pulse and the double pulse, which may hinder accurate discrimination. As a result, in the technique disclosed in Patent Document 1, there is a possibility that a determination error between a single pulse and a double pulse may occur. Then, when the receiver transmits an erroneous signal to the control system due to the determination error, the control system cannot properly control the receiver, and a reception error occurs in the entire electronic device. The problem that there is a possibility that it may occur occurs.

  In the technique disclosed in Patent Document 1, the pulse width of a pulse train having a single pulse and a double pulse is adjusted by an adjustment circuit.

  However, when the reception characteristics of the receiver change rapidly after the adjustment of the pulse width by the adjustment circuit, there is a possibility that the fluctuation of the pulse width occurs in the adjusted pulse train. When the fluctuation of the pulse width occurs in this way, the receiver eventually transmits an incorrect signal to the subsequent control system. As a result, a control system that has received an erroneous signal cannot properly control the receiver, and a problem arises that a reception error may occur in the entire electronic device.

  The present invention has been made in view of the above problems, and its purpose is to prevent a wrong signal from being transmitted to the outside in a receiver that performs data transmission using two types of optical signals having known pulse widths. It is an object of the present invention to provide a receiver that can be reduced and an electronic device including the receiver.

In order to solve the above problem, a receiver according to the present invention transmits a transmitted optical signal to a first pulse having a known pulse width, a known pulse width, and the first pulse. A receiver that receives a second pulse having a pulse width longer than that of the pulse as a digital signal that is a pulse train, wherein the first reference digital signal and the second reference digital signal are received based on the received optical signal. By generating and comparing these reference digital signals, the fluctuation of the pulse width generated in the received optical signal is detected. When the fluctuation of the pulse width is detected, the external of the received optical signal is detected. Pulse width variation detecting means for stopping output for a predetermined period is provided . The first reference digital signal includes a first reference pulse that is a digital signal that becomes high immediately after the rising edge of the edge detection signal that is a digital signal that becomes high immediately after the falling edge of the received optical signal, and the edge It is a digital signal that is at a high level immediately after the rise of the detection signal, and is a signal that indicates an exclusive OR with a second reference pulse having a high level period different from that of the first reference pulse. The digital signal is a digital signal that becomes a high level immediately after the rising of the received optical signal.

  According to said structure, the receiver which concerns on this invention is a pulse train which has a known pulse width for the transmitted optical signal, Comprising: A pulse width is longer than the said 1st pulse. It is a receiver which receives as a digital signal which is a pulse train having a second pulse. When the receiver according to the present invention is a receiver that receives a signal in accordance with a method conforming to the IrDA FIR standard, the single pulse corresponds to the first pulse, and the double pulse corresponds to the second pulse. To do.

  In addition, the receiver according to the present invention includes pulse width variation detection means. This pulse width fluctuation detecting means stops the external output of the received optical signal for a predetermined period when the fluctuation of the pulse width generated in the received optical signal is detected.

  According to the above configuration, when the fluctuation of the pulse width occurs in the optical signal due to, for example, a sudden change in the reception characteristics of the receiver, the external output itself of the optical signal is stopped. Therefore, the receiver according to the present invention can greatly reduce the possibility of transmitting an erroneous signal to the outside.

  The pulse width variation detection means generates a first reference digital signal and a second reference digital signal based on the received optical signal, and compares the reference digital signals with each other, thereby receiving the received optical signal. The processing for detecting the fluctuation of the pulse width generated in the above is performed.

  Therefore, when the pulse that causes fluctuations in the pulse width is a single pulse and a double pulse specified in the packet format, the pulse generated in the single pulse and the double pulse specified in the packet format by the above processing. Variations in width can be detected. In addition, when the pulse in which the fluctuation of the pulse width occurs is a single pulse and a double pulse in the pulse data, the above processing detects the fluctuation in the pulse width generated in the single pulse and the double pulse in the pulse data. be able to. That is, the fluctuation of the pulse width generated in the single pulse and the double pulse defined by the packet format does not hinder accurate discrimination between the single pulse and the double pulse in the pulse data. As a result, the receiver according to the present invention can further reduce the possibility of transmitting an erroneous signal to the outside.

  Therefore, in a receiver that performs data transmission using optical signals having two types of known pulse widths, it is possible to reduce the possibility of transmitting an erroneous signal to the outside.

In the receiver according to the present invention, the received optical signal is a negative logic digital signal, the pulse width variation detecting means generates a start edge detection signal and outputs the start edge detection signal , and the start edge First reference digital signal generation means for generating and outputting the first reference digital signal based on an edge detection signal output by the edge detection means; and second reference digital signal generation for generating and outputting the second reference digital signal And a stop signal generating means for generating and outputting a stop signal which is a digital signal that becomes a high level immediately after the rise of a signal indicating a logical product of the first reference digital signal and the second reference digital signal, and the stop signal stop signal generating means is output is high level period, as characterized by and an output signal stop unit for stopping an external output of the optical signal thus received That.

  According to the above configuration, the start edge detection unit outputs an edge detection signal that is a digital signal that becomes high immediately after the fall of the received optical signal, and the first reference digital signal generation unit outputs the edge detection signal. Based on the first reference digital signal. On the other hand, the second reference digital signal generating means outputs the second reference digital signal which is a digital signal that becomes high level immediately after the rising of the received optical signal. Here, the first reference digital signal becomes a high level immediately after the first reference pulse, which is a digital signal that becomes a high level immediately after the rising edge of the edge detection signal output from the start edge detection means, and the rising edge of the edge detection signal. In addition to being a digital signal, the first reference pulse is a signal indicating an exclusive OR with a second reference pulse having a high level period different from that of the first reference pulse.

  Then, the stop signal generation means compares these reference digital signals by obtaining a logical product of the first reference digital signal and the second reference digital signal. That is, when the signal indicating the logical product of the first reference digital signal and the second reference digital signal is at a high level, that is, when the first reference digital signal and the second reference digital signal are output simultaneously, the stop signal The generating means generates and outputs a stop signal which is a digital signal that becomes high level immediately after the rise of the signal indicating the logical product. Thus, the high level period in the first reference pulse and the second reference pulse is set so that the high level period in the first reference digital signal is equal to the period in which the optical signal in which the pulse width variation occurs rises. Thus, it can be seen that the stop signal generation means can detect the fluctuation of the pulse width.

  Then, the output signal stop device stops the external output of the received optical signal for a period in which the stop signal output from the stop signal generating means is at a high level.

  The start edge detecting means only needs to have a configuration capable of outputting a high level signal immediately after the falling edge of the digital signal input to itself. Therefore, the start edge detection means can adopt a very simple and simple configuration using a known differentiation circuit or the like. For the same reason, the second reference digital signal generation unit can adopt a very simple and simple configuration using a known differentiation circuit or the like.

  Further, the first reference digital signal generation unit and the stop signal generation unit need only have a configuration capable of setting a high-level period in the digital signal input to itself to a predetermined period. Therefore, the first reference digital signal generation unit and the stop signal generation unit can adopt a very simple and simple configuration using a known monostable multivibrator or the like.

  Furthermore, the output signal stop device only needs to be configured to be able to stop the external output of the received optical signal during a period in which the stop signal from the stop signal generating means is at a high level. Therefore, the output signal stop device can be realized with a simple and simple configuration by combining the logic circuit and the inverter.

  Therefore, any of the above-described members constituting the pulse width variation detecting means can be realized with a simple and simple configuration by a known circuit.

  In the receiver according to the present invention, the pulse width of the first reference pulse is shorter than the pulse width of the second reference pulse and longer than the pulse width of the first pulse. The pulse width is shorter than the pulse width of the second pulse.

  According to the above configuration, the signal indicating the exclusive OR of the first reference pulse and the second reference pulse has a high level period from the rising edge of the first pulse to the rising edge of the second pulse. Signal. By setting the first reference pulse and the second reference pulse in this way, the receiver according to the present invention can simultaneously detect the pulse fatness generated in the first pulse and the pulse thinness generated in the second pulse. Is possible.

  The receiver according to the present invention is characterized in that a pulse width of the stop signal is longer than a pulse width corresponding to one period of the received optical signal.

  According to the above configuration, it is possible to more reliably stop the external output of the optical signal in which the fluctuation of the pulse width occurs by making the pulse width longer than the pulse width corresponding to one period of the received optical signal. It is.

  In the receiver according to the present invention, the first reference digital signal generation means includes a monostable multivibrator, and the monostable multivibrator adjusts the pulse width of the first reference digital signal. The variable current supply means is provided.

  According to the above configuration, since the pulse width of the first reference digital signal can be adjusted by the variable current supply means, the pulse width of the first reference digital signal can be appropriately controlled without changing the design. .

  Further, in the receiver according to the present invention, the first reference digital signal generation means includes a monostable multivibrator, and the monostable multivibrator includes a comparator and is connected to an inverting input terminal of the comparator. Is characterized in that a voltage from a band gap voltage source is applied.

  According to said structure, the voltage from a band gap voltage source is applied to the inverting input terminal of the comparator of the monostable multivibrator of the 1st reference digital signal generation means which outputs a 1st reference digital signal. . Therefore, a voltage that does not depend on the power supply voltage and temperature can be applied to the inverting input terminal of the comparator. Therefore, fluctuations in the pulse width of the first reference digital signal due to changes in the environment in which the receiver according to the present invention is used can be suppressed.

  An electronic apparatus according to the present invention includes any one of the receivers described above, and receives a transmitted optical signal by the receiver.

  According to said structure, in an electronic device provided with the receiver which concerns on this invention, a possibility that an incorrect signal may be transmitted to the back | latter stage of a receiver can be reduced. For example, when a control system for controlling the receiver is connected to the subsequent stage of the electronic apparatus according to the present invention, it is possible to reduce the possibility of transmitting an erroneous signal to the control system. As a result, the control system can reduce the possibility that the receiver cannot be appropriately controlled, and can reduce the possibility that a reception error will occur in the entire electronic device. It becomes.

As described above, the receiver according to the present invention can transmit a transmitted optical signal by using a first pulse having a known pulse width, a known pulse width, and a pulse width larger than that of the first pulse. Is a receiver that receives a digital signal that is a pulse train having a long second pulse, and generates a first reference digital signal and a second reference digital signal based on the received optical signal, and By comparing the reference digital signals with each other, a variation in the pulse width generated in the received optical signal is detected. When the variation in the pulse width is detected, the external output of the received optical signal is output for a predetermined period. The pulse width variation detecting means for stopping is provided. The first reference digital signal includes a first reference pulse that is a digital signal that becomes high immediately after the rising edge of the edge detection signal that is a digital signal that becomes high immediately after the falling edge of the received optical signal, and the edge It is a digital signal that is at a high level immediately after the rise of the detection signal, and is a signal that indicates an exclusive OR with a second reference pulse having a high level period different from that of the first reference pulse. The digital signal is a digital signal that becomes a high level immediately after the rising of the received optical signal. In the receiver according to the present invention, the pulse width of the first reference pulse is shorter than the pulse width of the second reference pulse and longer than the pulse width of the first pulse. The pulse width is shorter than the pulse width of the second pulse.

Therefore, in a receiver that performs data transmission using optical signals having two types of known pulse widths, it is possible to reduce the possibility of transmitting an erroneous signal to the outside. Furthermore, in the receiver according to the present invention, it is possible to simultaneously detect the pulse fatness generated in the first pulse and the pulse thinness generated in the second pulse.

  An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a receiver according to the present invention.

  An optical receiver (receiver) 1 shown in FIG. 1 includes a receiving device 11 and a pulse width monitoring device (pulse width variation detecting means) 12. A control system (not shown) such as an application processor or UART is connected to the subsequent stage of the pulse width monitoring device 12.

  For example, the receiving device 11 receives a signal transmitted from a transmitter (not shown) and outputs the signal to the pulse width monitoring device 12.

  Here, for example, an IrDA communication device compliant with the IrDA FIR standard is preferably used as the receiving device 11. When the receiving device 11 is an IrDA communication device, the signal received by the receiving device 11 is, for example, an optical signal that has been modulated by a four-value PPM modulation method.

  However, the apparatus suitably used as the receiving apparatus 11 is not limited to the above. That is, the receiving device 11 is not particularly limited as long as it receives an optical signal as a digital signal that is a pulse train having a known pulse width and a pulse train having two types of pulses having different pulse widths. Examples of such a receiving device 11 include a device that receives an optical signal that has been modulated by a 16-value PPM modulation method.

  The pulse width monitoring device 12 performs the following processing based on the signal from the receiving device 11.

  That is, the pulse width monitoring device 12 generates two types of reference digital signals, a first reference digital signal and a second reference digital signal, based on the signal from the receiving device 11, and compares these reference digital signals with each other. . And the fluctuation | variation of the pulse width which generate | occur | produced in the signal from the receiver 11 is detected from the comparison result. When the fluctuation of the pulse width is detected, the pulse width monitoring device 12 stops the external output to the subsequent circuit, for example, the control system. Detailed description regarding the pulse width monitoring device 12 will be described later.

  Note that the pulse width monitoring device 12 outputs the signal from the receiving device 11 as it is to the subsequent circuit when it does not detect the fluctuation of the pulse width generated in the signal from the receiving device 11.

  The configuration of the pulse width variation detecting means according to the present invention will be described with reference to FIG.

  Here, the pulse width variation detecting means according to the present invention is a digital signal which is a pulse train having a known pulse width and having two kinds of pulses having different pulse widths, that is, an input signal a1 which will be described later. Receive. In the present application, in order to more suitably explain the present invention, of the two types of pulses, a pulse having a shorter pulse width is referred to as a “first pulse”, and a pulse having a longer pulse width is referred to as a “second pulse”. Referred to as “pulses”. That is, the first pulse and the second pulse are both pulses having a known pulse width, but the pulse width of the second pulse is longer than the pulse width of the first pulse. When the pulse width variation detecting means according to the present invention receives a signal from an IrDA communication device compliant with the IrDA FIR standard, the single pulse corresponds to the first pulse and the double pulse corresponds to the second pulse. Corresponding to

  Further, in the present application, as an example, the cycle of the input signal a1 is 500 (nsec), the period corresponding to the pulse width of the first pulse is 125 (nsec), and corresponds to the pulse width of the second pulse. The description will be made assuming that the period is 250 (nsec).

  Further, here, the description will be made assuming that the input signal a1 is a negative logic signal.

  FIG. 2 is a block diagram showing a configuration of the pulse width monitoring device 12.

  2 includes a start edge detection circuit (start edge detection means) 20, a reference pulse generation circuit (first reference digital signal generation means) 21, and an end edge detection circuit (second reference digital signal generation means). ) 22, a stop signal generation circuit (stop signal generation means) 23, and an output signal stop device 24.

  An input signal a <b> 1 from the receiving device 11 is input to the start edge detection circuit 20. Then, the start edge detection circuit 20 generates an edge detection signal a3 that detects a falling edge of the input signal a1, and outputs the edge detection signal a3 to the reference pulse generation circuit 21. Here, the falling edge of the signal means the moment when the pulse of the signal falls.

  The reference pulse generation circuit 21 is connected to the subsequent stage of the start edge detection circuit 20. The reference pulse generation circuit 21 generates a reference pulse (first reference digital signal) c4 based on the edge detection signal a3, and outputs the reference pulse c4 to the stop signal generation circuit 23.

  The end edge detection circuit 22 is connected in parallel with the start edge detection circuit 20, and the input signal a <b> 1 is input in the same manner as the start edge detection circuit 20. The end edge detection circuit 22 generates an edge detection signal b3 that detects a rising edge of the input signal a1, and outputs the edge detection signal b3 to the stop signal generation circuit 23. The edge detection signal b3 is a second reference digital signal according to the present invention. Here, the rising edge of the signal means the rising edge of the pulse in the signal.

  The stop signal generation circuit 23 is connected to the subsequent stage of the reference pulse generation circuit 21 and the end edge detection circuit 22. The stop signal generation circuit 23 generates a stop signal d2 based on the reference pulse c4 and the edge detection signal b3, that is, by comparing the reference pulse c4 with the edge detection signal b3, and outputs the stop signal d2. The signal is output to the signal stop device 24.

  Similarly to the start edge detection circuit 20 and the end edge detection circuit 22, the output signal stop device 24 receives the input signal a1. Furthermore, the output signal stop device 24 receives the stop signal d2 generated by the stop signal generation circuit 23. In response to the stop signal d2, the output signal stop device 24 switches between a state in which the input signal a1 is directly output to the subsequent circuit and a state in which the output of the input signal a1 to the subsequent circuit is stopped for a predetermined period. . Here, e is a signal output from the output signal stopping device 24.

  From here, based on FIGS. 3-10, the structure and operation | movement of each member which comprise the said pulse width monitoring apparatus are demonstrated in detail.

  FIG. 3A is a circuit diagram illustrating a configuration example of the start edge detection circuit 20. FIGS. 3B to 3D are graphs showing the waveforms of signals passing through the start edge detection circuit 20. In each of the graphs shown in FIGS. 3B to 3D, the vertical axis represents the signal level and the horizontal axis represents time.

  As shown in FIG. 3A, the start edge detection circuit 20 includes a capacitor 31, a resistor 32, and an inverter 33. One end of the capacitor 31 is connected to the receiving device 11. The other end of the capacitor 31 is connected to the input end of the inverter 33. The output terminal of the inverter 33 is connected to the reference pulse generation circuit 21. One end of the resistor 32 is connected to a connection point 34 between the other end of the capacitor 31 and the input end of the inverter 33, and the other end of the resistor 32 is connected to the drive voltage source ("power supply" in FIG. 3A). Voltage ”).

  The capacitor 31 and the resistor 32 of the start edge detection circuit 20 constitute a general differentiation circuit. In addition, the input signal a1 having the waveform shown in FIG. 3B has a very high frequency component at the moment when the pulse rises and falls. For this reason, at the moment when the input signal a1 falls, the voltage at the connection point 34 changes rapidly from the high level to the low level due to the differential action of the capacitor 31 and the resistor 32. In the present application, the high level is the level of the power supply voltage (for example, the voltage of the drive voltage source in the case of the start edge detection circuit 20) in each member according to the present invention, and the low level is the ground level. Shall.

  Then, since the input signal a1 is constantly at a low level, the voltage at the connection point 34 gradually increases from a low level to a high level.

  On the other hand, at the moment when the input signal a1 rises, the voltage at the connection point 34 suddenly changes to a voltage exceeding the high level due to the differential action. At this time, a voltage exceeding the high level is generated at the connection point 34, but the input signal a1 is constantly at the high level. Therefore, the voltage at the connection point 34 gradually decreases from a voltage exceeding the high level to the high level.

  With the above operation, the input signal a1 is converted to the signal a2 having the waveform shown in FIG.

  Then, by outputting the signal a2 via the inverter 33, the start edge detection circuit 20 outputs an edge detection signal a3 having a waveform shown in FIG. That is, the inverter 33 compares the signal a2 with a predetermined threshold value (usually, a voltage value not lower than the low level and not higher than the high level). If the level of the signal a2 is equal to or higher than the threshold, a low level is output. If the level of the signal a2 is lower than the threshold, a high level is output. Thus, the start edge detection circuit 20 outputs the signal a2 via the inverter 33, thereby generating and outputting an edge detection signal a3 having the waveform shown in FIG. The start edge detection circuit 20 outputs the generated edge detection signal a3 to the reference pulse generation circuit 21.

  Here, the edge detection signal a3 is a signal whose voltage rises from a low level to a high level with a slight delay from the falling edge of the input signal a1. The delay time can be slightly adjusted according to the capacitance of the capacitor 31 and the resistance value of the resistor 32, but is approximately 5 (nsec).

  FIG. 4A is a block diagram illustrating a configuration example of the reference pulse generation circuit 21. 4B to 4E are graphs showing waveforms of signals passing through the reference pulse generation circuit 21. FIG. In each of the graphs shown in FIGS. 4B to 4E, the vertical axis represents the signal level and the horizontal axis represents time.

  The reference pulse generation circuit 21 has a configuration in which outputs of parallel circuits of the one-shot circuits 41 and 42 are connected to an input terminal of an EXOR (exclusive OR) circuit 43. An output terminal of the EXOR (exclusive OR) circuit 43 is connected to the stop signal generation circuit 23.

  The edge detection signal a3 having the waveform shown in FIG. 4B input to the reference pulse generation circuit 21 is input to the one-shot circuits 41 and. The one-shot circuit 41 is a pulse that becomes high level immediately after the rising edge of the edge detection signal a3 and has a waveform shown in FIG. 4C (first reference pulse) having a high-level period t1. ) Generate c2 and output it. The one-shot circuit 42 is a pulse that becomes a high level immediately after the rising edge of the edge detection signal a3, and has a waveform shown in FIG. Pulse) c3 is generated and output. Note that the period t1 and the period t2 are different from each other.

  The pulse signal c2 output from the one-shot circuit 41 and the pulse signal c3 output from the one-shot circuit 42 are input to the EXOR circuit 43. The EXOR circuit 43 generates, as the reference pulse c4, a pulse signal having the waveform shown in FIG. 4E that indicates the exclusive OR of the pulse signal c2 and the pulse signal c3, and outputs the pulse signal to the stop signal generation circuit 23. .

  Here, a configuration suitable for the one-shot circuit will be described with reference to FIGS.

  FIG. 5 is a circuit diagram showing a configuration of a one-shot circuit suitably used in the present invention.

  The one-shot circuit 50 shown in FIG. 5 is a so-called monostable multivibrator circuit (monostable multivibrator) including a transistor 51, a current source 52, a capacitor 53, a reference voltage source 54, a comparator 55, and an inverter 56. is there. The base terminal of the transistor 51 is connected to the output terminal of the inverter 33 (see FIG. 3) of the start edge detection circuit 20. The collector terminal of the transistor 51 is connected to the current source 52. The emitter terminal of the transistor 51 is grounded. The non-inverting input terminal of the comparator 55 is connected between the collector terminal of the transistor 51 and the current source 52. One end of the capacitor 53 is connected to the subsequent stage between the collector terminal of the transistor 51 and the current source 52 and to the previous stage of the non-inverting input terminal of the comparator 55. The other end of the capacitor 53 is connected between the emitter terminal of the transistor 51 and its ground plane. The positive terminal of the reference voltage source 54 is connected to the inverting input terminal of the comparator 55, and the negative terminal of the reference voltage source 54 is grounded. The output terminal of the comparator 55 is connected to the input terminal of the inverter 56. The output terminal of the inverter 56 is connected to the input terminal of the EXOR circuit 43 (see FIG. 4).

  When a pulse signal (for example, the edge detection signal a3 in the case of the one-shot circuit 41) is input to the base terminal of the transistor 51, the transistor 51 becomes conductive only while the input signal is at a high level. At this time, the capacitor 53 discharges the charge stored therein through the transistor 51. At this time, the power supply line to which the capacitor 53 is connected is at the ground level, and the voltage applied to the non-inverting input terminal of the comparator 55 is zero. On the other hand, the reference voltage vref 1 of the reference voltage source 54 is applied to the inverting input terminal of the comparator 55. As a result, since the voltage at the non-inverting input terminal of the comparator 55 is less than the voltage at the inverting input terminal of the comparator 55, the output of the comparator 55 is at a low level.

  Next, when the signal input to the base terminal of the transistor 51 changes from a high level to a low level, the transistor 51 is turned off. At this time, the current from the current source 52 is supplied to the collector terminal of the transistor 51. As a result, the capacitor 53 is charged by the current source 52. At this time, the voltage of the power supply line to which the capacitor 53 is connected gradually increases, and accordingly, the voltage applied to the non-inverting input terminal of the comparator 55 gradually increases. When the voltage applied to the non-inverting input terminal of the comparator 55 becomes equal to or higher than the reference voltage vref1, the output of the comparator 55 changes to a high level.

  Note that the period t during which the output of the comparator 55 is at a low level can be set by the following formula (1).

t = (C · vref1) / Ia (nsec) (1)
(C: capacitance of capacitor 53, vref1: reference voltage value of reference voltage source 54, Ia: current value supplied to collector terminal of transistor 51)
The output of the comparator 55 obtained by the above operation is output via the inverter 56. For example, in the case of the one-shot circuit 41, the signal output from the inverter 56 is the signal c2 shown in FIG.

  As a result, the one-shot circuit 50 is based on the pulse signal input to the base terminal of the transistor 51, and is a pulse that becomes high level immediately after the rising of the signal, and the pulse signal whose period of high level is t Is generated.

  When the one-shot circuit 50 is used as the one-shot circuit 41 shown in FIG. 4A, the period t corresponds to the period t1 in which the pulse signal c2 output from the one-shot circuit 41 is at a high level. When the one-shot circuit 50 is used as the one-shot circuit 42 shown in FIG. 4A, the period t corresponds to the period t2 in which the pulse signal c3 output from the one-shot circuit 42 is at a high level. . Further, when this one-shot circuit 50 is used as a one-shot circuit 91 shown in FIG. 9 described later, the period t corresponds to a period t3 in which the stop signal d2 output from the one-shot circuit 91 is at a high level.

  FIG. 6 is a circuit diagram showing another configuration of a one-shot circuit suitably used in the present invention.

  The one-shot circuit 60 shown in FIG. 6 is configured to further include a trimming circuit (variable current supply means) 61 in the configuration of the one-shot circuit 50 shown in FIG.

  As shown in FIG. 6, the trimming circuit 61 includes a series circuit of a current source 63 and a switch Do [0], a series circuit of a current source 64 and a switch Do [1], and a current source 65 and a switch Do [2]. Are connected in parallel to each other from one end of the current source 52 to the other end. The series circuit of the current source 63 and the switch Do [0], the series circuit of the current source 64 and the switch Do [1], and the series circuit of the current source 65 and the switch Do [2] are all on the switch side. Are connected to the collector terminal of the transistor 51, and the current sources 63 to 65 are connected to a drive voltage source (see “power supply voltage” in FIG. 6).

  Here, the current values of the current sources 63 to 65 have the following relationship, for example.

(Current value of current source 64) = (Current value of current source 63) · 2
(Current value of current source 65) = (Current value of current source 63) · 4
In the one-shot circuit 60, the current value supplied to the collector terminal of the transistor 51 is changed according to the on / off switching of the switches Do [0] to Do [2] connected in series to the current sources 63 to 65. It can be changed as appropriate.

  Thereby, in the one-shot circuit 60, the period t during which the output of the comparator 55 is at a low level can be controlled without changing the design by appropriately changing the current value supplied to the collector terminal of the transistor 51. This makes it possible to design a more flexible system.

  In the one-shot circuit 60, when the current value of the current source 52 is I1 and the current value of the current source 63 is I2, the period t ′ during which the output of the comparator 55 is at the low level is expressed by the following equation (2). , Can be set.

t ′ = (C · vref1) / (I1 + n · I2) (nsec) (2)
That is, in this case, it can be said that the on / off switching of the switches Do [0] to Do [2] means changing the numerical value of the variable “n” in the above equation (2).

  Incidentally, in the one-shot circuit 60 shown in FIG. 6, the current value supplied to the collector terminal of the transistor 51 is set to 8 values (3) by using the current sources 63 to 65 whose current values have the above relationship as current sources. Bit) variable, but is not limited to this. That is, in the one-shot circuit according to the embodiment shown in FIG. 6, the current value supplied to the collector terminal of the transistor corresponding to the transistor 51 of the one-shot circuit 60 may be controlled as a variable other than eight values. Note that as the number of variables increases, the one-shot circuit according to the embodiment illustrated in FIG. 6 can set the high-level period of the reference pulse generated by itself more precisely.

  FIG. 7 is a circuit diagram showing a configuration of a bandgap voltage source preferably used in the present invention.

  The band gap voltage source 70 shown in FIG. 7 is for outputting the reference voltage vref1 as the reference voltage source 54 in the one-shot circuit 50 shown in FIG. 5 and the one-shot circuit 60 shown in FIG. By using the band gap voltage source 70 as the reference voltage source 54, a voltage of about 1.25 V can be generated as the reference voltage vref1 regardless of temperature changes.

  The band gap voltage source 70 shown in FIG. 7 is provided with PNP type MOS (Metal Oxide Semiconductor) field effect transistors QP1 to QP3. The base terminal of the transistor QP1, the base terminal of the transistor QP2, and the base terminal of the transistor QP3 are connected to each other. All the emitter terminals of the transistors QP1 to QP3 are connected to the power supply line. The base terminal of the transistor QP1 is further connected to the collector terminal of the transistor QP1 itself.

  The band gap voltage source 70 shown in FIG. 7 is provided with NPN type MOS field effect transistors QN1 and QN2. The base terminal of the transistor QN1 and the base terminal of the transistor QN2 are connected to each other. The emitter terminal of the transistor QN1 is grounded. The emitter terminal of the transistor QN2 is grounded via the resistor R0. The base terminal of transistor QN2 is further connected to the collector terminal of transistor QN2 itself. The collector terminal of transistor QN1 is connected to the collector terminal of transistor QP1. The collector terminal of transistor QN2 is connected to the collector terminal of transistor QP2.

  The band gap voltage source 70 shown in FIG. 7 is provided with an NPN-type MOS field effect transistor QN3. The collector terminal of transistor QN3 is connected to the collector terminal of transistor QP3. The collector terminal of transistor QN3 is further connected to the base terminal of transistor QN3 itself. The emitter terminal of the transistor QN3 is grounded via the resistor R1.

  In the band gap voltage source 70 shown in FIG. 7, an output terminal 71 is provided between the collector terminal of the transistor QP3 and the collector terminal of the transistor QN3. The output terminal 71 corresponds to a positive terminal of the reference voltage source 54 in the one-shot circuit 50 shown in FIG. 5 or the one-shot circuit 60 shown in FIG.

  In general, it is easy to generate a PTAT (Proportional to Absolute Temperature) current using a monolithic IC.

  The PTAT current Iref1 is expressed by the following mathematical formulas (3) and (4).

Iref1 = Vt · (ln N) / R0 (3)
Vt = k · T / q (4)
(K: Boltzmann constant, T: absolute temperature, q: elementary charge of electrons, N: size ratio of transistors QP1, QN1 and transistors QP2, QN2)
Here, when the reference voltage vref1 is configured by “vref1 = R1 · Iref1 + Vbe”, the reference voltage vref1 is expressed by the following formula (5).

vref1 = R1 · Vt · (ln N) / R0 + Vbe (5)
The temperature coefficient is expressed by the following mathematical formulas (6) to (9).

(∂vref1 / ∂T) = {R1 · Vt · (ln N) / R0} / T + (∂Vbe / ∂T) (6)
(∂vref1 / ∂T) / vref1 = A · (1 / T) + B · (∂Vbe / ∂T) / Vbe (7)
A = {R1 · Vt · (ln N) / R0} / vref1 (8)
B = Vbe / vref1 (9)
Here, in Equation (7), (1 / T) is positive. On the other hand, (∂Vbe / ∂T) / Vbe is usually negative in Equation (7). Therefore, the temperature coefficient can be brought close to 0 by adjusting the value of A by the above equation (8) and the value of B by the above equation (9).

  When the temperature coefficient is asymptotic to 0, the voltage of the reference voltage vref1 is approximately 1.25V. This reference voltage vref1 is used as a reference voltage in various one-shot circuits according to the present invention.

  As a result, when the band gap voltage source is applied as the reference voltage source, the reference voltage can be set without depending on the power supply voltage and the temperature, and therefore the environment in which the receiver according to the present invention is used. It is possible to suppress fluctuations in the pulse width of the reference pulse caused by the change in.

  FIG. 8A is a circuit diagram showing a configuration example of the end edge detection circuit 22. 8B to 8D are graphs showing waveforms of signals that pass through the end edge detection circuit 22. In each of the graphs shown in FIGS. 8B to 8D, the vertical axis represents the signal level and the horizontal axis represents time.

  As shown in FIG. 8A, the end edge detection circuit 22 has a configuration in which the other end of the resistor 32 is grounded in the configuration of the start edge detection circuit 20 shown in FIG. The other end of the resistor 32 is not connected to the drive voltage source. Further, in the end edge detection circuit 22 shown in FIG. 8A, an inverter 35 is further provided at the subsequent stage of the inverter 33.

  Note that one end of the capacitor 31 in the end edge detection circuit 22 shown in FIG. 8A is connected to the receiving device 11, and the output end of the inverter 33 is connected to the input end of the inverter 35. Is connected to the stop signal generation circuit 23.

  The end edge detection circuit 22 receives the input signal a1 (see FIG. 8B) in the same manner as the start edge detection circuit 20. The end edge detection circuit 22 performs the same operation as the start edge detection circuit 20.

  Here, since the other end of the resistor 32 is grounded, the connection point 34 of the end edge detection circuit 22 is normally held at the ground level, that is, the low level. Therefore, the signal b2 obtained at the connection point 34 is a signal having the waveform shown in FIG. Then, the signal b2 is output via the inverter 33 and the inverter 35, so that the signal b2 is logically inverted twice, and the end edge detection circuit 22 generates the edge detection signal b3 having the waveform shown in FIG. To do. Then, the end edge detection circuit 22 outputs the edge detection signal b3 to the stop signal generation circuit 23.

  Here, the edge detection signal b3 is a signal whose voltage rises from a low level to a high level with a slight delay from the rising edge of the input signal a1. The delay time can be slightly adjusted according to the capacitance of the capacitor 31 and the resistance value of the resistor 32, but is approximately 5 (nsec).

  FIG. 9 is a circuit diagram illustrating a configuration example of the stop signal generation circuit 23.

  The stop signal generation circuit 23 shown in FIG. 9 includes an AND (logical product) circuit 90 and a one-shot circuit 91.

  The AND circuit 90 has one input terminal connected to the output of the reference pulse generation circuit 21, the other input terminal connected to the output of the end edge detection circuit 22, and the output terminal connected to the one-shot circuit 91. When the reference pulse c4 output from the reference pulse generation circuit 21 and the edge detection signal b3 output from the end edge detection circuit 22 are input, the AND circuit 90 generates a signal d1 indicating the logical product of these signals. Output to the shot circuit 91.

  The one-shot circuit 91 is, for example, a circuit having the same configuration as the one-shot circuit 50 shown in FIG. 5 and the one-shot circuit 60 shown in FIG. Of course, the one-shot circuit 91 may include a band gap voltage source 70. Therefore, detailed description of the one-shot circuit 91 is omitted here. The one-shot circuit 91 generates a stop signal d2 that is a pulse that goes high immediately after the rise of the signal d1 output from the AND circuit 90 and that has a high-level period t3. Refer to FIG. 11 for the waveform of the stop signal d2. The one-shot circuit 91 outputs a stop signal d2 to the output signal stop device 24 shown in FIG.

  FIG. 10 is a circuit diagram illustrating a configuration example of the output signal stop device 24.

  The output signal stopping device 24 illustrated in FIG. 10 includes an inverter 100, a NAND (Negative AND) circuit 101, and an inverter 102.

  The input terminal of the inverter 100 is connected to the output of the stop signal generation circuit 23. The output terminal of the inverter 100 is connected to one input terminal of the NAND circuit 101. The other input terminal of the NAND circuit 101 is connected to the receiving device 11. The output terminal of the NAND circuit 101 is connected to the input terminal of the inverter 102. The output terminal of the inverter 102 is connected to a subsequent circuit (for example, the subsequent system shown in FIG. 10).

  The NAND circuit 101 receives the stop signal d2 via the inverter 100 and the input signal a1. Then, when the stop signal d2 that has passed through the inverter 100 and the input signal a1 are input, the NAND circuit 101 generates a signal indicating a negative logical product of these signals and outputs the signal via the inverter 102. Note that the signal output from the inverter 102 is the signal e.

  Thus, the output signal stop device 24 makes the waveform of the input signal a1 and the waveform of the signal e output from the inverter 102 the same while the stop signal d2 is at a low level. On the other hand, the output signal stop device 24 holds the waveform of the signal e output from the inverter 102 at a high level regardless of the waveform of the input signal a1 while the stop signal d2 is at a high level.

  FIG. 11 shows a timing chart for explaining a specific operation principle of the pulse width variation detecting means according to the present invention having the above configuration. In the timing chart shown in FIG. 11, the vertical axis represents the signal level, and the horizontal axis represents time (period). Hereinafter, the operation principle until the pulse width variation detecting means according to the present invention detects the variation of the pulse width and stops the external output will be described.

  An input signal a1 shown in FIG. 11 is an optical signal that has been modulated by a four-value PPM modulation method. In this case, the input signal a1 is the first pulse N1 and has four types of pulses “00”, “01”, “10”, and “11”, each having a different pulse position (however, here, For the sake of convenience, it is assumed that the input signal a1 is made up of three types of pulses except “10”). Here, in the portion of the input signal a1 where the “00” pulse is output after the “11” pulse, the first pulse N1 in the “11” pulse and the first pulse in the “00” pulse. Adjacent to the pulse N1 generates the second pulse N2.

  An edge detection signal a3 shown in FIG. 11 detects a falling edge of the input signal a1. Specifically, the edge detection signal a3 is a signal that is at a high level for a short period of time immediately after the input signal a1 falls.

  The output c2 of the one-shot circuit 41 shown in FIG. 11 is a pulse that becomes high level immediately after the rising edge of the edge detection signal a3. The period during which the output c2 of the one-shot circuit 41 is held at the high level is t1.

  In the output c2 of the one-shot circuit 41 shown in FIG. 11, two types of periods ta and tb are employed as the period t1. This can be done by using the one-shot circuit 60 shown in FIG. 6 as the one-shot circuit 41 and controlling the period t1 as described above. However, as the period t1, only one type of period may naturally be adopted, or three or more types of periods may be adopted.

  The period t1 is preferably longer than a period corresponding to the pulse width of the first pulse N1 and shorter than a period t2 described later. As described above, the period corresponding to the pulse width of the first pulse N1 is 125 (nsec). Therefore, as the period t1, for example, the period ta is set to 150 (nsec) corresponding to 1.2 times the period corresponding to the pulse width of the first pulse N1, and the period tb is slightly longer than the period ta. (Nsec) may be used.

  The output c3 of the one-shot circuit 42 shown in FIG. 11 is a pulse that becomes high level immediately after the rising edge of the edge detection signal a3. The period during which the output c3 of the one-shot circuit 42 is held at the high level is t2.

  Note that the output c3 of the one-shot circuit 42 shown in FIG. 11 employs two types of periods tc and td as the period t2, as in the output c2 of the one-shot circuit 41, but is not limited thereto. . Of course, only one type of period may be employed as the period t2, or three or more types of periods may be employed.

  The period t2 is preferably longer than the period t1 described above and shorter than the period corresponding to the pulse width of the second pulse N2. As described above, the period corresponding to the pulse width of the second pulse N2 is 250 (nsec). Therefore, as the period t2, for example, the period tc is set to 200 (nsec) corresponding to 0.8 times the period corresponding to the pulse width of the second pulse N2, and the period td is slightly longer than the period tc. (Nsec) may be used.

  As a result, the output (reference pulse) c4 of the EXOR circuit 43 shown in FIG. 11 is a pulse that is at a high level only for a period corresponding to 50 (nsec), and one pulse is output for each period of the input signal a1. It becomes.

  On the other hand, the edge detection signal b3 shown in FIG. 11 detects the rising edge of the input signal a1. Specifically, the edge detection signal b3 is a signal that remains high for a short period of time immediately after the rising of the input signal a1.

  The output d1 of the AND circuit 90 shown in FIG. 11 is a signal indicating the logical product of the reference pulse c4 and the edge detection signal b3 as described above.

  Here, when the fluctuation of the pulse width does not occur in the input signal a1, a period in which both the output c4 of the EXOR circuit 43 and the edge detection signal b3 shown in FIG. 11 are at a high level does not occur. Note that the case where the fluctuation of the pulse width does not occur in the input signal a1 means that the normal second pulse 110 or the normal first pulse 111 is output as the input signal a1 in the case of FIG. Means. At this time, the output d1 of the AND circuit 90 is held at a low level.

  On the other hand, when the pulse width fluctuates in the input signal a1, a period in which both the output c4 of the EXOR circuit 43 and the edge detection signal b3 shown in FIG. 11 are at a high level occurs. Note that when the input signal a1 has a fluctuation in pulse width, in the case of FIG. 11, the second pulse 112 in which the pulse narrowing has occurred or the pulse fatness has occurred in the input signal a1. This means that one pulse 113 is output. At this time, the output d1 of the AND circuit 90 becomes a high level during the period in which both the output c4 of the EXOR circuit 43 and the edge detection signal b3 shown in FIG. 11 are at a high level.

  The stop signal d2 shown in FIG. 11 is a pulse that goes high immediately after the rise of the output d1 of the AND circuit 90. The period during which the stop signal d2 is held at the high level is t3. The period t3 may be at least one period of the input signal a1, but is more preferably a period corresponding to one packet of the input signal a1.

  The output e of the inverter 102 shown in FIG. 11 has the same waveform as that of the signal supplied to the subsequent circuit (for example, the subsequent system shown in FIG. 10) by the receiver according to the present invention. That is, the signal e is an external output of the optical receiver 1.

  In a state where the stop signal d2 is held at a low level, the output e of the inverter 102 shown in FIG. 11 outputs a signal having the same waveform as the input signal a1.

  On the other hand, in a state where the stop signal d2 is held at the high level, the output e of the inverter 102 shown in FIG. 11 is held at the high level similarly to the stop signal d2.

  The input signal a1 is originally input as a negative logic signal. For this reason, while the output e of the inverter 102 shown in FIG. 11 is held at a high level, there is substantially no signal input from the receiving device 11 to the subsequent circuit. That is, while the output e of the inverter 102 shown in FIG. 11 is held at a high level, the external output of the input signal a1 is stopped.

  As a result, in the output signal stop device 24 of the pulse width monitoring device 12 shown in FIG. 2 and the like, the external output of the input signal a1 is output during the period t3 in which the stop signal d2 output from the stop signal generation circuit 23 is held at a high level. You can see that you can stop.

  Thus, in the receiver according to the present invention, when the pulse width monitoring device detects fluctuations in the pulse width generated in the signal from the receiving device, external output to the subsequent circuit can be stopped.

  In the present application, the signal from the receiving device, that is, the input signal a1 has been described as a negative logic signal.

  However, in the receiver according to the present invention, even if the signal from the receiving device is a positive logic signal, the variation in the pulse width generated in the signal from the receiving device is performed in the same manner as described above. When the pulse width variation is detected, the external output to the subsequent circuit can be stopped.

  That is, when the signal from the receiving device is a positive logic signal, the pulse width monitoring device 12 ′ shown in FIG. 12 in which the inverter 120 is provided in the forefront of the pulse width monitoring device 12 shown in FIG. In the pulse width monitoring device 12 ′, an input signal a 1 that is a signal from the receiving device is input to the start edge detection circuit 20, the end edge detection circuit 22, and the output signal stop device 24 in a logic inverted state. That is, the signal a1 ′ input to the start edge detection circuit 20, the end edge detection circuit 22, and the output signal stop device 24 is a signal obtained by converting the input signal a1 that is a positive logic signal into a negative logic signal. It can be said that there is. Then, in the pulse width monitoring device 12 ′ shown in FIG. 12, the start edge detection circuit 20, the reference pulse generation circuit 21, the end edge detection circuit 22, the stop signal generation circuit 23, and the output signal stop device 24 are supplied to the signal a1 ′. On the other hand, the above-described series of processing is performed. As a result, in the receiver according to the present invention, even if the signal from the receiving device is a positive logic signal, the variation in the pulse width generated in the signal from the receiving device is performed in the same manner as described above. Can be detected, and external output to the subsequent circuit can be stopped.

  FIG. 15 illustrates an embodiment of the present invention and is a block diagram illustrating a configuration example of an electronic device. For convenience of explanation, members having the same functions as those already described with reference to the drawings are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 15, the electronic apparatus has an infrared communication function compliant with, for example, the IrDA standard, and performs data communication with other communication devices using infrared rays. The electronic device illustrated in FIG. 15 includes an IrDA module 700, an interface circuit 702, a battery 703, and a housing 704.

  The IrDA module 700, which is an infrared communication element, includes a transmission circuit 711 and a reception circuit 712, and includes a light emitting element 715 and a light receiving element 701. The light emitting element 715 and the light receiving element 701 are exposed to the outside. It is attached to the body 704. An interface circuit 702 and a battery 703 are provided in the housing 704.

  The interface circuit 702 generates transmission data (transmission signal) to be given to the transmission circuit 711 by performing modulation processing or the like based on the transmission information. The interface circuit 702 outputs reception information by performing demodulation processing and the like based on the reception data (reception signal) from the reception circuit 712.

  The battery 703 is provided to supply power to the IrDA module 700, and is connected to the IrDA module 700 via a power supply line (Vcc) and a GND line. Note that the battery 703 may supply power to the interface circuit 702. A member denoted by reference numeral Icc, which is not described, is a power line for a protection circuit (not shown).

  The receiving circuit 712 is a circuit that amplifies an electrical signal obtained by photoelectrically converting the optical signal received by the light receiving element 701 and outputs received data. As the receiving circuit 712, the optical receiver 1 (see FIG. 1) is used.

  The transmission circuit 711 includes a drive circuit that drives the light emitting element 715 in order to convert a transmission signal (electric signal) into an optical signal by the light emitting element 715 and transmit it to the outside.

  By applying the optical receiver 1 to the receiving circuit 712, it is possible to reduce the possibility that an erroneous signal is transmitted to the outside in a receiver that performs data transmission using optical signals having two types of known pulse widths. A machine is feasible.

  Thus, the receiver according to the present invention can be suitably applied as a receiver in an electronic apparatus that receives a transmitted optical signal. Examples of such electronic devices include mobile terminals such as mobile phones and infrared wireless earphones that wirelessly receive transmitted optical signals.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can receive an optical signal as a digital signal that is a pulse train having a known pulse width and having at least a first pulse having a short pulse width and a second pulse having a long pulse width. It can be suitably used as a machine.

It is a block diagram which shows the structure of the receiver which concerns on this invention. It is a block diagram which shows the structure of the pulse width fluctuation | variation detection means based on this invention in case a negative logic signal is input. FIG. 3A is a circuit diagram showing a configuration example of the start edge detecting means according to the present invention, and FIGS. 3B to 3D pass through the start edge detecting means shown in FIG. It is a graph which shows the waveform of a signal. FIG. 4A is a block diagram showing a configuration example of the reference pulse generating means according to the present invention, and FIGS. 4B to 4E pass through the reference pulse generating means shown in FIG. It is a graph which shows the waveform of a signal. It is a circuit diagram which shows the structure of the one-shot circuit used suitably in this invention. It is a circuit diagram which shows another structure of the one-shot circuit used suitably in this invention. It is a circuit diagram which shows the structure of the band gap voltage source used suitably in this invention. FIG. 8A is a circuit diagram showing a configuration example of the end edge detecting means according to the present invention, and FIGS. 8B to 8D pass through the end edge detecting means shown in FIG. It is a graph which shows the waveform of a signal. It is a circuit diagram which shows the structural example of the stop signal production | generation means based on this invention. It is a circuit diagram which shows the structural example of the output signal stop apparatus which concerns on this invention. It is a timing chart explaining the specific operation principle of the pulse width fluctuation | variation detection means which concerns on this invention. It is a block diagram which shows the structural example of the pulse width fluctuation | variation detection means which concerns on this invention in case a positive logic signal is input. It is a block diagram which shows an example of the general connection structure of a receiver provided with an IrDA communication device. It is a figure which shows an example of the pulse train in a 4-value PPM modulation system. It is a block diagram which shows the structure of the electronic device provided with the receiver which concerns on this invention.

Explanation of symbols

1 Optical receiver (receiver)
11 Receiving device 12 Pulse width monitoring device (pulse width fluctuation detecting means)
20 Start edge detection circuit (start edge detection means)
21 Reference pulse generation circuit (first reference digital signal generation means)
22 End edge detection circuit (second reference digital signal generation means)
23 Stop signal generation circuit (stop signal generation means)
24 Output signal stop device 41, 42, 50, 60, 91
One-shot circuit (monostable multivibrator)
61 Trimming circuit (variable current supply means)
70 Bandgap voltage source 712 Receiver circuit

Claims (6)

The transmitted optical signal is a pulse train having a first pulse having a known pulse width and a second pulse having a known pulse width and a longer pulse width than the first pulse. A receiver that receives as a digital signal,
Based on the received optical signal, a first reference digital signal and a second reference digital signal are generated, and these reference digital signals are compared with each other to detect a variation in pulse width generated in the received optical signal. And when the fluctuation of the pulse width is detected, it comprises a pulse width fluctuation detecting means for stopping the external output of the received optical signal for a predetermined period ,
The first reference digital signal includes a first reference pulse that is a digital signal that becomes high immediately after the rising edge of the edge detection signal that is a digital signal that becomes high immediately after the falling edge of the received optical signal, and the edge detection signal Is a digital signal that is at a high level immediately after the rise of the signal, and a signal that indicates an exclusive OR with a second reference pulse having a high-level period different from the first reference pulse,
The second reference digital signal is a digital signal that becomes a high level immediately after the rising of the received optical signal,
The pulse width of the first reference pulse is shorter than the pulse width of the second reference pulse and longer than the pulse width of the first pulse,
The receiver , wherein a pulse width of the second reference pulse is shorter than a pulse width of the second pulse . The received optical signal is a negative logic digital signal,
The pulse width variation detecting means is
Start edge detection means for generating and outputting the edge detection signal ;
First reference digital signal generation means for generating and outputting the first reference digital signal based on the edge detection signal output by the start edge detection means;
A second reference digital signal generating means for generating and outputting the second reference digital signal,
Stop signal generating means for generating and outputting a stop signal that is a digital signal that becomes a high level immediately after the rise of the signal indicating the logical product of the first reference digital signal and the second reference digital signal;
The receiver according to claim 1, characterized in that it comprises a period stop signal the stop signal generating means outputs is high, the output signal stop device for stopping an external output of the optical signal thus received, a. The receiver according to claim 2 , wherein a pulse width of the stop signal is longer than a pulse width corresponding to one cycle of the received optical signal . The first reference digital signal generating means includes a monostable multivibrator,
4. The receiver according to claim 2, wherein the monostable multivibrator includes variable current supply means for adjusting a pulse width of the first reference digital signal . The first reference digital signal generating means includes a monostable multivibrator,
The monostable multivibrator includes a comparator,
4. The receiver according to claim 2, wherein a voltage from a band gap voltage source is applied to an inverting input terminal of the comparator . An electronic device comprising the receiver according to claim 1 and receiving a transmitted optical signal by the receiver.

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