JP4544407B2 - Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus - Google Patents

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

  It is known that a plurality of semiconductor chips are stacked via a spacer to manufacture one semiconductor device. The wiring pattern of the wiring board and the electrode of the semiconductor chip are electrically connected by, for example, a wire. In wire bonding connection, so-called reverse bonding is known in which a wire is first bonded to a wiring pattern and second bonded on a semiconductor chip. In reverse bonding, the semiconductor device can be thinned by reducing the loop of the wire.

  Furthermore, in order to reduce the thickness of the semiconductor device, it is preferable to make the spacer thin and narrow the space between the upper and lower semiconductor chips. In the prior art, since the wire is drawn obliquely downward from the top of the wire to enter the space between the upper and lower semiconductor chips, a certain thickness is required for the spacer. In reverse bonding, if the rising portion (neck portion) from the first bonding is tilted at a steep angle, the wire may be damaged, and the reliability of the semiconductor device may be impaired.

An object of the present invention is to achieve high reliability and thinning of a semiconductor device.
Japanese Patent No. 3370539

(1) A semiconductor device according to the present invention includes:
A wiring board having a wiring pattern;
A first semiconductor chip mounted on the wiring board and having a first electrode;
A second semiconductor chip mounted on the first semiconductor chip so as to overlap the first electrode at an interval;
A spacer interposed between the first semiconductor chip and the second semiconductor chip;
A wire for electrically connecting the wiring pattern and the first electrode;
Including
The wire is
The topmost part is located outside the overlapping range of the second semiconductor chip, and
A portion from the boundary portion of the overlapping range of the second semiconductor chip to the connection portion with the first electrode extends substantially parallel to the surface of the wiring board. According to the present invention, the wire has a portion from the boundary portion of the overlapping range of the upper second semiconductor chip to the connection portion with the first electrode of the lower first semiconductor chip. It is extended so as to be almost parallel to the surface. Therefore, the distance between the upper and lower semiconductor chips can be made as narrow as possible, and the semiconductor device can be made thinner. In addition, the uppermost portion of the wire is located outside the overlapping range of the upper second semiconductor chip. Therefore, it is possible to prevent the rising portion of the wire from the wiring pattern from being tilted at a steep angle, to avoid damage to the wire, and to improve the reliability of the semiconductor device.
(2) In this semiconductor device,
The wire is
Having a bump disposed on the wiring pattern;
Extending from the bump to a first intermediate point so as to rise substantially perpendicular to the surface of the wiring board,
Extending from the first intermediate point to the second intermediate point in a direction approaching the first electrode and away from the wiring board;
Extending from the second intermediate point to the third intermediate point in a direction approaching the first electrode, so as to have the topmost part in any one of
Extending from the third intermediate point to the fourth intermediate point in a direction approaching the first electrode and approaching the wiring board,
A semiconductor device that extends from the fourth intermediate point to the connection portion so as to pass through the boundary portion and substantially parallel to the surface of the wiring board.
(3) In this semiconductor device,
A portion of the wire extending from the second intermediate point to the third intermediate point extends substantially parallel to the surface of the wiring board.
(4) In this semiconductor device,
The topmost portion of the wire is a semiconductor device arranged at a position higher than the bottommost surface of the second semiconductor chip. As a result, the trajectory to the top of the wire has a gentle curve, so that damage to the wire can be avoided.
(5) In this semiconductor device,
The semiconductor device in which the planar shape of the first semiconductor chip is substantially the same as the planar shape of the second semiconductor chip.
(6) In this semiconductor device,
A semiconductor device in which a planar shape of the first semiconductor chip is smaller than a planar shape of the second semiconductor chip.
(7) In this semiconductor device,
The second semiconductor chip has a second electrode,
A semiconductor device further comprising another wire for electrically connecting the wiring pattern and the second electrode.
(8) The semiconductor device is mounted on a circuit board according to the present invention.
(9) An electronic apparatus according to the present invention includes the semiconductor device.
(10) A method for manufacturing a semiconductor device according to the present invention includes:
(A) mounting a first semiconductor chip having a first electrode on a wiring board having the wiring pattern;
(B) bonding a wire to the wiring pattern so as to electrically connect the wiring pattern and the first electrode, and then bonding to the first electrode;
(C) mounting the second semiconductor chip on the first semiconductor chip so as to overlap the first electrode at an interval;
Including
In the step (b), the wire is
The topmost part is located outside the overlapping range of the second semiconductor chip, and
A portion from the boundary portion of the overlapping range of the second semiconductor chip to the connection portion with the first electrode extends substantially in parallel with the surface of the wiring board. According to the present invention, the portion of the wire from the boundary portion of the overlapping range of the upper second semiconductor chip to the connection portion with the first electrode of the lower first semiconductor chip is formed on the wiring board. Extend so that it is almost parallel to the surface. Therefore, the distance between the upper and lower semiconductor chips can be made as narrow as possible, and the semiconductor device can be made thinner. Further, the wire is formed so that the topmost part is located outside the overlapping range of the upper second semiconductor chip. Therefore, it is possible to prevent the rising portion of the wire from the wiring pattern from being tilted at a steep angle, to avoid damage to the wire, and to improve the reliability of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a modification thereof. 3A to 5C are views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5C illustrates a wire shape of the semiconductor device. As shown in FIG. 1, the semiconductor device 1 includes a wiring board 10, a first semiconductor chip 20, a second semiconductor chip 30, a spacer 40, and a wire (first wire) 50.

  In the example illustrated in FIG. 1, the wiring substrate 10 includes a base substrate 12 and wiring patterns 14 and 16 formed on the base substrate 12. The base substrate 12 may be composed of an organic material such as a resin substrate (for example, an epoxy substrate or a polyimide substrate), or may be composed of an inorganic material such as a ceramic substrate or a glass substrate, or those materials. The composite structure substrate (for example, a glass epoxy substrate) may be used. Wiring patterns (for example, Cu patterns) 14 and 16 may be formed on both surfaces of the base substrate 12. Each of the wiring patterns 14 and 16 includes a plurality of wirings, and a part of each wiring is a connection portion (for example, a land). A through hole (not shown) may be formed in the base substrate 12 so that electrical connection between both surfaces (wiring patterns 14 and 16) of the wiring substrate 10 may be achieved. An insulating film (not shown) is formed on the wiring substrate 10 so as to cover a part of the wiring patterns 14 and 16. The wiring board 10 may be an interposer for a semiconductor package, may be a single layer board or a multilayer board, and may be a rigid board or a flexible board.

  As a modification, the wiring board may be a metal board. As the metal substrate, a lead frame formed by punching a metallic plate material may be used. The lead frame has a wiring pattern composed of a plurality of leads.

  The first semiconductor chip (first integrated circuit chip) 20 includes an integrated circuit 22 and a plurality of first electrodes 24 electrically connected to the integrated circuit 22. The plurality of first electrodes 24 are arranged on the surface of the first semiconductor chip 20 on the side of the integrated circuit 22 and are outside the integrated circuit 22 (for example, regions along the four sides or two sides of the outer shape of the first semiconductor chip). ) May be arranged. The first electrode 24 may be only a thin and flat pad (for example, an aluminum pad), but may further have a bump (for example, a ball bump) protruding on the pad as shown in FIG. Note that a passivation film (for example, a silicon oxide film) (not shown) is formed on the first semiconductor chip 20.

  The second semiconductor chip (second integrated circuit chip) 30 includes an integrated circuit 32 and a plurality of second electrodes 34 electrically connected to the integrated circuit 32. The arrangement and structure of the second electrode 34 can apply the contents of the first electrode 24. A passivation film (for example, a silicon oxide film) (not shown) is formed on the second semiconductor chip 30.

  In the example shown in FIG. 1, the planar shape of the first semiconductor chip 20 is substantially the same as the planar shape of the second semiconductor chip 30. The planar shape of the first and second semiconductor chips 20 and 30 may be a rectangular shape.

  The first semiconductor chip 20 is mounted on the wiring board 10. The first semiconductor chip 20 is mounted such that the surface opposite to the surface on which the first electrode 24 is formed faces the wiring substrate 10 side (that is, face up). An adhesive material 18 may be interposed between the first semiconductor chip 20 and the wiring substrate 10.

  The second semiconductor chip 30 is mounted on the first semiconductor chip 20 via the spacer 40. Since the spacer 40 has a predetermined thickness and is interposed between the first semiconductor chip 20 and the second semiconductor chip 30, it is between the first semiconductor chip 20 and the second semiconductor chip 30. A predetermined interval can be provided. In the example shown in FIG. 1, all of the first and second semiconductor chips 20 and 30 may overlap each other. The second semiconductor chip 30 overlaps the first electrode 24 with a gap.

  The spacer 40 is made of an insulating material and may be formed of a resin (for example, a thermosetting resin). As shown in FIG. 1, the spacer 40 may seal a part of the wire 50 and the first electrode 24 described later, but may be provided so as to avoid the wire 50 and the first electrode 24. . The spacer 40 may have a plurality of balls (lumps) 42 dispersed therein. The ball 42 is also made of an insulating material. Since the spacer 40 includes the plurality of balls 42, at least one ball 42 is interposed between the first semiconductor chip 20 and the second semiconductor chip 30, so that the first semiconductor chip 20 and the second semiconductor chip 20 are arranged. A predetermined interval can be easily and reliably provided between the chip 30 and the chip 30.

  The wire 50 electrically connects the wiring substrate 10 (wiring pattern 14) and the first semiconductor chip 20 (first electrode 24). Each of the plurality of connection portions of the wiring pattern 14 may be electrically connected to any of the plurality of first electrodes 24. The wire 50 is made of a conductive material, and may be a gold wire, for example. The wire 50 may be formed by so-called reverse bonding in which first bonding is performed on the wiring pattern 14 and then second bonding is performed on the first electrode 24.

  The loop shape of the wire 50 will be described. As shown in FIG. 1, the wire 50 has a bump 51 disposed on the wiring pattern 14 (connection portion), and extends in a direction (upward) away from the bump 51 to the wiring substrate 10. The topmost portion (the highest portion) 54 of the wire 50 is located outside the overlapping range of the second semiconductor chip 30. The topmost portion 54 may be disposed at a position higher than the bottommost surface (the surface opposite to the surface on which the second electrode 34 is formed) of the upper second semiconductor chip 30, or the uppermost second semiconductor chip 30. You may arrange | position in the position substantially the same as the uppermost surface (formation surface of the 2nd electrode 34) of the chip | tip 30, or higher than it. According to this, since the trajectory to the top 54 of the wire 50 has a gentle curve, it is possible to avoid damage to the wire 50. The wire 50 extends from the top 54 in a direction approaching the wiring substrate 10 (obliquely below), and enters the space between the first semiconductor chip 20 and the second semiconductor chip 30. The wire 50 passes through the boundary portion 57 in the overlapping range of the second semiconductor chip 30 and extends to the connection portion 58 with the first electrode 24. Here, the boundary portion 57 is a portion disposed immediately below the end portion of the second semiconductor chip 30 of the wire 50, and the connection portion 58 is a portion disposed directly above the first electrode 24 of the wire 50. is there. As shown in FIG. 1, the portion from the boundary portion 57 to the connection portion 58 of the wire 50 is almost included in the error range with respect to the surface of the wiring substrate 10 (or the surface of the first semiconductor chip 20). It extends in parallel. A portion from the boundary portion 57 to the connection portion 58 of the wire 50 extends linearly. The position of the boundary portion 57 (connecting portion 58) in the height direction is such that the top surface of the first semiconductor chip 20 (the surface on which the first electrode 24 is formed) and the bottom surface of the second semiconductor chip 30 (second surface). And a surface opposite to the surface on which the electrode 34 is formed).

  A specific example of the loop shape of the wire 50 will be described with reference to FIG. In the example shown in FIG. 5C, a plurality of wires 50 are provided between the wiring pattern 14 (bump 51) of the wiring substrate 10 and the first electrode 24 (connecting portion 58) of the first semiconductor chip 20. Intermediate points (first to fourth intermediate points 52, 53, 55, 56). The wire 50 is bent at each intermediate point.

  A portion of the wire 50 from the bump 51 to the first intermediate point 52 extends so as to rise substantially perpendicular to the surface of the wiring substrate 10.

  A portion of the wire 50 from the first intermediate point 52 to the second intermediate point 53 extends in a direction approaching the first electrode 24 and away from the wiring substrate 10, that is, obliquely upward. An angle θ between the plane parallel to the surface of the wiring substrate 10 and a line connecting the first intermediate point 52 and the second intermediate point 53 on the first semiconductor chip 20 side is, for example, 45 ° ≦ θ ≦ 75. It may be °. With such an angle, it is possible to prevent the wire 50 from being tilted at a steep angle, and damage to the wire 50 can be avoided.

  A portion from the second intermediate point 53 to the third intermediate point 55 of the wire 50 extends in a direction approaching the first electrode 24. Such a portion of the wire 50 may extend substantially parallel to the surface of the wiring substrate 10, may extend obliquely upward, or may extend obliquely downward. Note that the topmost portion 54 is disposed at any position on the wire 50.

  A portion from the third intermediate point 53 to the fourth intermediate point 56 of the wire 50 extends in a direction approaching the first electrode 24 and approaching the wiring substrate 10, that is, obliquely downward. The position of the fourth intermediate point 56 in the height direction is that the top surface (formation surface of the first electrode 24) of the first semiconductor chip 20 and the bottom surface (the second electrode 34 of the second electrode 34). (The surface opposite to the forming surface). As shown in FIG. 5C, the fourth intermediate point 56 may be disposed outside the overlapping range of the second semiconductor chip 30.

  A portion of the wire 50 from the fourth intermediate point 56 to the connection portion 58 passes through the boundary portion 57 described above and extends substantially parallel to the surface of the wiring board 10. Apart from the example shown in FIG. 5C, the boundary 57 and the fourth intermediate point 56 may coincide with each other.

  The semiconductor device 1 includes another wire (second wire) 60 that electrically connects the wiring pattern 14 and the second electrode 34, and components on the wiring substrate 10 (for example, the first and second semiconductor chips 20). , 30 and the like, and at least one of a plurality of external terminals (for example, solder balls) 64 electrically connected to the wiring board 10 (wiring pattern 16). May be.

  According to the present embodiment, the wire 50 is connected to the first electrode 24 of the lower first semiconductor chip 20 from the boundary 57 in the overlapping range of the upper second semiconductor chip 30. The portion up to is extended so as to be substantially parallel to the surface of the wiring board 10. Therefore, the distance between the upper and lower semiconductor chips can be made as narrow as possible, and the semiconductor device can be made thinner. Further, the uppermost portion 54 of the wire 50 is located outside the overlapping range of the upper second semiconductor chip 30. Therefore, it is possible to prevent the rising portion of the wire 50 from the wiring pattern 14 from being tilted at a steep angle and to prevent the wire 50 from being damaged, and to improve the reliability of the semiconductor device. Can do.

  As a modification of the present embodiment, as shown in FIG. 2, the planar shape of the first semiconductor chip 120 may be smaller than the planar shape of the second semiconductor chip 30. The first semiconductor chip 120 includes an integrated circuit 122 and a first electrode 124, and the description thereof is as described above. In the example shown in FIG. 2, a part (for example, the central part) of the upper second semiconductor chip 30 overlaps the entire first semiconductor chip 120. The second semiconductor chip 30 may protrude from the entire outer periphery of the first semiconductor chip 120 (so that it protrudes).

  The present invention is not limited to the case where two semiconductor chips are stacked on the wiring substrate 10, and can also be applied to the case where three or more semiconductor chips are stacked. In that case, when the upper semiconductor chip overlaps the electrodes of the lower semiconductor chip with a gap, the above-described effects can be achieved by applying the form of the wire 50.

  The manufacturing method of the semiconductor device according to the present embodiment includes a wire bonding step shown in FIGS. 3 (A) to 5 (C). The method for manufacturing a semiconductor device includes manufacturing steps necessary for obtaining the above-described semiconductor device. After mounting the first semiconductor chip 20 on the wiring substrate 10, a wire bonding process is performed. In the wire bonding process, first bonding is performed on the wiring pattern 14 and then second bonding is performed on the first electrode 24.

  A tool (for example, a capillary) 70 that supports the wire 50 is prepared, and the tip of the wire 50 protruding from the tip of the tool 70 is melted and formed into a ball shape. Then, the tool 70 is disposed above the connection portion (for example, land) of the wiring pattern 14, and the tip of the wire 50 is bonded to the connection portion of the wiring pattern 14. Pressure, heat, and ultrasonic vibration may be applied during bonding. In this way, bumps 51 are formed on the wiring pattern 14.

  As shown in FIG. 3A, the tool 70 is vertically moved upward (relative to the surface of the wiring board 10), and the wire 50 is extended straight upward from the bump 51.

  Next, as shown in FIG. 3B, the tool 70 is moved horizontally (relative to the surface of the wiring board 10) in a direction away from the first electrode 24 at the second bonding point. That is, the portion of the wire 50 from the bump 51 to the first intermediate point 52 can be extended straight upward, and the portion from the first intermediate point 52 to the tip of the tool 70 can be extended obliquely upward. .

  Next, as shown in FIG. 3C, the tool 70 is vertically moved from the second intermediate point 53 as a starting point. Thereby, the wire 50 can be bent at the second intermediate point 53. A portion from the second intermediate point 53 of the wire 50 to the tip of the tool 70 extends straight upward.

  Next, as shown in FIG. 4A, the tool 70 is moved horizontally in a direction away from the first electrode 24. Thus, the portion from the second intermediate point 53 of the wire 50 to the tip of the tool 70 can be extended obliquely upward.

  Next, as shown in FIG. 4B, the tool 70 is moved vertically upward from the third intermediate point 55 as a starting point. Thereby, the wire 50 can be bent at the third intermediate point 55. A portion from the third intermediate point 53 of the wire 50 to the tip of the tool 70 extends straight upward.

  Next, as shown in FIG. 5A, the tool 70 is horizontally moved in a direction approaching the first electrode 24. In this way, the portion from the third intermediate point 55 of the wire 50 to the tip of the tool 70 can be extended obliquely upward.

  Next, as shown in FIG. 5B, the tool 70 is moved vertically upward from the fourth intermediate point 56 as a starting point. Thereby, the wire 50 can be bent at the fourth intermediate point 56. The portion from the fourth intermediate point 56 of the wire 50 to the tip of the tool 70 extends straight upward.

  Finally, as shown in FIG. 5C, the tool 70 is rotationally moved around the bump 51 which is the first bonding point, and a part of the wire 50 is bonded to the first electrode 24. Pressure, heat, and ultrasonic vibration may be applied during bonding. Thus, the wiring pattern 14 and the first electrode 24 can be connected by wire bonding.

  After the above-described wire bonding process is completed, the second semiconductor chip 30 is mounted on the first semiconductor chip 20 so as to overlap the first electrode 24 with a gap. Thereafter, the wiring pattern 14 and the second electrode 34 may be electrically connected by the wire 60, and the components on the wiring board 10 may be resin-sealed (for example, molded). External terminals 64 may be provided on the wiring board 10. Thus, the semiconductor device 1 shown in FIG. 1 can be manufactured. According to the present embodiment, a thin and highly reliable semiconductor device can be manufactured.

  FIG. 6 shows a circuit board 1000 on which the above-described semiconductor device 1 is mounted. As an electronic apparatus according to this embodiment, a notebook personal computer 2000 is shown in FIG. 7, and a mobile phone 3000 is shown in FIG.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing a semiconductor device according to a modification of the embodiment of the present invention. 3A to 3C are diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 4A and 4B are diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 5A to 5C are diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a diagram showing a circuit board on which the semiconductor device according to the embodiment of the present invention is mounted. FIG. 7 is a diagram showing an electronic apparatus having the semiconductor device according to the embodiment of the present invention. FIG. 8 is a diagram showing an electronic apparatus having the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wiring board 14 ... Wiring pattern 20 ... 1st semiconductor chip 24 ... 1st electrode 30 ... 2nd semiconductor chip 34 ... 2nd electrode 40 ... Spacer 50 ... Wire 51 ... Bump 52 ... 1st intermediate point 53 ... second intermediate point 54 ... topmost part 55 ... third intermediate point 56 ... fourth intermediate point 57 ... boundary part 58 ... connecting part 60 ... wire 120 ... first semiconductor chip 124 ... first electrode

Claims (9)

A wiring board having a wiring pattern;
A first semiconductor chip mounted on the wiring board and having a first electrode;
A second semiconductor chip mounted on the first semiconductor chip so as to overlap the first electrode at an interval;
A spacer interposed between the first semiconductor chip and the second semiconductor chip;
A wire for electrically connecting the wiring pattern and the first electrode;
Including
The wire has a topmost portion located outside an overlapping range of the second semiconductor chip, and a connecting portion between the boundary of the overlapping range of the second semiconductor chip and the first electrode portions until the, Ri Na is extended substantially parallel to the plane of the wiring board,
The wire further includes a bump disposed on the wiring pattern,
The wire extends from the bump to a first intermediate point so as to rise substantially perpendicular to the surface of the wiring board,
Extending from the first intermediate point to the second intermediate point in a direction approaching the first electrode and away from the wiring board;
Extending from the second intermediate point to the third intermediate point in a direction approaching the first electrode,
Extending from the third intermediate point to the fourth intermediate point in a direction approaching the first electrode and approaching the wiring board,
Extending from the fourth intermediate point to the connection portion, passing through the boundary portion and substantially parallel to the surface of the wiring board,
The topmost part is a semiconductor device located between the second intermediate point and the third intermediate point . The semiconductor device according to claim 1 ,
A portion of the wire extending from the second intermediate point to the third intermediate point extends substantially parallel to the surface of the wiring board. The semiconductor device according to claim 1 or 2 ,
The topmost portion of the wire is a semiconductor device arranged at a position higher than the bottommost surface of the second semiconductor chip. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device in which the planar shape of the first semiconductor chip is substantially the same as the planar shape of the second semiconductor chip. The semiconductor device according to any one of claims 1 to 4,
A semiconductor device in which a planar shape of the first semiconductor chip is smaller than a planar shape of the second semiconductor chip. The semiconductor device according to any one of claims 1 to 5,
The second semiconductor chip has a second electrode,
A semiconductor device further comprising another wire for electrically connecting the wiring pattern and the second electrode. A circuit board on which the semiconductor device according is mounted to any one of claims 1 to 6. An electronic device having a semiconductor device as claimed in any one of claims 6. (A) mounting a first semiconductor chip having a first electrode on a wiring board having the wiring pattern;
(B) bonding a wire to the wiring pattern so as to electrically connect the wiring pattern and the first electrode, and then bonding to the first electrode;
(C) mounting the second semiconductor chip on the first semiconductor chip so as to overlap the first electrode at an interval;
Including
In the step (b), the wire is
Extending from the bumps arranged on the wiring pattern of the wire to the first intermediate point so as to rise substantially perpendicular to the surface of the wiring board,
Extending from the first intermediate point to the second intermediate point in a direction approaching the first electrode and away from the wiring board,
Extending from the second intermediate point to the third intermediate point in a direction approaching the first electrode,
Extending from the third intermediate point to the fourth intermediate point in a direction approaching the first electrode and approaching the wiring board;
Extending from the fourth intermediate point to the connecting portion, passing through the boundary portion and substantially parallel to the surface of the wiring board,
The topmost part is located outside the overlapping range of the second semiconductor chip, and
The portion from the boundary portion of the overlapping range of the second semiconductor chip to the connection portion with the first electrode extends substantially parallel to the surface of the wiring board ,
The semiconductor device manufacturing method , wherein the topmost portion is formed so as to be positioned between the second intermediate point and the third intermediate point of the wire .

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