JP4545576B2 - Switching regulator - Google Patents

Description

  The present invention relates to a switching regulator, and more particularly to a switching regulator capable of saving power in a light load operation state.

  The switching regulator is a small voltage rectifier or current rectifier circuit for obtaining a desired output voltage. In order to obtain a desired output voltage, the switching regulator controls the ratio between the ON time and the OFF time of the input DC current.

  FIG. 1 shows an example of a conventional switching regulator 900. The switching regulator 900 includes an oscillation circuit 901, a triangular wave generation circuit 902, two comparators (COMP) 903, 904, a control circuit 905, a switch 906, an inductor L907, and a smoothing capacitor C908. A load (RL) 909 is connected to the output OUT.

  The oscillation circuit 901 is composed of, for example, a VCO (Voltage Control Oscillator) or the like, and outputs a rectangular signal having a predetermined frequency corresponding to the applied voltage. The rectangular signal output from the oscillation circuit 901 is input to the triangular wave generation circuit 902. The triangular wave generation circuit 902 outputs a triangular wave SAWOUT having a predetermined frequency (the potential is Vsawout) based on the input rectangular signal. The triangular wave SAWOUT output from the triangular wave generation circuit 902 is input to the inverting input terminal of the comparator 903. On the other hand, the output potential Vout of the switching regulator 900 is fed back to the non-inverting input terminal of the comparator 903. The comparator 903 compares the triangular wave potential (Vsawout) with the output potential Vout of the switching regulator 900 and applies the comparison result to the control circuit 905. Further, an output potential Vsw from a switch 906 or 907 described later is applied to the inverting input terminal of the other comparator 904. The ground potential GND is applied to the non-inverting input terminal of the comparator 904. The comparator 904 compares the output potential Vsw from the switch 906 or 907 with the ground potential GND, and applies the comparison result to the control circuit 905.

  The control circuit 905 controls the switch 906 based on the comparison results input from the two comparators 903 and 904, respectively. Two outputs of the control circuit 905 are input to control terminals of the two switching elements 906a and 906b constituting the switch 906, respectively. The control circuit 905 controls on (off) / off (off) of the switching elements 906a and 906b based on the comparison results applied from the two comparators 903 and 904.

  The switching elements 906a and 906b have two terminals in addition to the control terminal, and turn on / off conduction between the two terminals based on a potential applied to the control terminal. The input voltage Vin is applied from one input terminal IN to one terminal of the switching element 906a. The other terminal is connected to one terminal of an inductor L907 and a switching element 906b provided in the output stage of the switching regulator 900. In addition, one terminal of the switching element 906b is connected to an inductor L907 provided at the output stage of the switching regulator 900 in addition to the one terminal of the switching element 906a. The other terminal of the switching element 906b is grounded.

  An inductor L907 is connected to the output of the switch 906. The inductor L907 is connected to the output terminal OUT. That is, the output of the switch 906 is connected to the output terminal OUT via the inductor L907. A smoothing capacitor C908 having one terminal grounded is connected between the inductor L907 and the output terminal OUT.

  In this configuration, for example, when the output potential Vout of the switching regulator 900 is smaller than the potential (Vsawout) of the triangular wave SAWOUT, the L level is applied from the comparator 903 to the control circuit 905. In this case, the control circuit 905 turns on the switching element 906a. As a result, the current IL flows from the input terminal IN to the inductor L907 via the switching element 906a, and the output potential Vout of the output terminal OUT rises. At this time, since the potential of the node P (see FIG. 1) located at the output stage of the switch 906, that is, the output potential Vsw of the switch 906 is equal to or higher than the ground potential GND, the L level is applied from the comparator 904 to the control circuit 905. The When the L level is applied from the comparator 904, the control circuit 905 turns off the switching element 906b.

  As a result of the increase in the output potential Vout, when this value becomes larger than the potential (Vsawout) of the triangular wave SAWOUT, the H level is applied from the comparator 903 to the control circuit 905. When the H level is applied from the comparator 903, the control circuit 905 turns off the switching element 906a. At this time, the inductor L907 works to keep the current flowing, so the potential Vsw of the node P becomes lower than the ground potential GND. Accordingly, a potential lower than the ground potential GND is applied to the inverting input terminal of the comparator 904, and the comparator 904 outputs an H level. When the H level is applied from the comparator 904, the control circuit 905 turns on the switching element 906b. As a result, one terminal of the inductor L907 is grounded via the switching element 906b, and the output potential Vout of the output terminal OUT drops.

  As a result of the drop in the output potential Vout, when this value becomes smaller than the inverted potential (−Vsawout) of the triangular wave SAWOUT, a positive potential is applied from the comparator 903 to the control circuit 905 as described above, and the switching element 906a is turned on. . Thereby, a current flows from the input terminal IN to the inductor L907 via the switching element 906a, and the output potential Vout of the output terminal OUT rises. Note that when the output potential of the switch 906 becomes equal to or higher than the ground potential GND, a negative potential is applied from the comparator 904 to the control circuit 905, and the switching element 906b is turned off.

  The operation state of the switching regulator configured as described above is divided into a heavy load operation state, a medium load operation state, and a light load operation state according to the resistance value given to the output (the load 909 in the example shown in FIG. 1). be able to. The heavy load operation state is an operation state when the impedance on the output side is small. On the other hand, the light load operating state is an operating state in which the impedance on the output side is large and a small current flows compared to the heavy load operating state. The medium load operation state is an operation state positioned between the heavy load operation state and the light load operation state.

The operation state as described above can be detected by monitoring the potential applied to the inductor L907 in FIG. 1, that is, the potential of the node P as disclosed in, for example, Patent Document 1 shown below. . For reference, a technique for stabilizing the operation when the power supply voltage drops is disclosed in, for example, Patent Document 2 shown below.
JP 2002-44939 A JP 2002-223563 A

  Here, FIG. 2 shows waveform diagrams of respective signals in the heavy load operation state, the medium load operation state, and the light load operation state. FIG. 2A shows the output potential Vsawout of the triangular wave generation circuit 902, the output potential Vout of the switching regulator 900, the potential Vcomp1 output from the comparator 903, the potential Vcomp2 output from the comparator 904, and the inductor L907 in the heavy load operation state. FIG. 2B is a waveform diagram of the flowing current IL. FIG. 2B shows the output potential Vsawout of the triangular wave generation circuit 902, the output potential Vout of the switching regulator 900, the potential Vcomp1 output from the comparator 903, and the comparator 904 in the middle load operation state. FIG. 2C is a waveform diagram of the potential Vcomp2 output from the inductor L907 and the current IL flowing through the inductor L907, and FIG. 2C shows the output potential Vsawout of the triangular wave generation circuit 902, the output potential Vout of the switching regulator 900, and the comparator in the middle load operating state. Output from 903 That is a waveform diagram of the current IL flowing through the potential Vcomp1 the potential Vcomp2 an inductor L907 which is output from the comparator 904. In addition, the comparison said below refers to the comparison with another operation state unless otherwise stated.

  As shown in FIGS. 2A to 2C, the triangular wave generation circuit 902 outputs a triangular wave SAWOUT having a fixed period having a peak potential VH and a bottom potential VL in each operation state. On the other hand, in the heavy load operation state, as shown in FIG. 2A, the switching regulator 900 outputs a relatively small output potential Vout between VH and VL. Accordingly, a control signal (potential Vcomp1) is output from one comparator 903, and a control signal (potential Vcomp2) is output from the other comparator 904 (see FIG. 2A). Thereby, the current IL continuously flows through the inductor L907 (see FIG. 2A). That is, during the heavy load operation state, a current always flows through the inductor L907.

  In the middle load operation state, as shown in FIG. 2B, the switching regulator 900 outputs an output potential Vout having a value larger than that in the heavy load operation state. Therefore, one comparator 903 outputs a control signal (potential Vcomp1) having a duty ratio larger than that in the heavy load operation state, and the other comparator 904 has a control signal having a duty ratio smaller than that in the heavy load operation state. (Potential Vcomp2) is output (see FIG. 2B). As a result, the current IL having a smaller peak than that in the heavy load operation state flows intermittently through the inductor L907 (see FIG. 2B). That is, in the medium load operation state, there is a period in which the current flowing through the inductor is 0 [A (ampere)].

  In contrast to the operation state as described above, when the light load operation state is set, as shown in FIG. 2C, the switching regulator 900 outputs an output potential Vout having a larger value than that in the medium load operation state. Therefore, one comparator 903 outputs a control signal (potential Vcomp1) having a larger duty ratio than that in the other operating state, and the other comparator 904 has a control signal having a smaller duty ratio than in the other operating state. (Potential Vcomp2) is output (see FIG. 2C). As a result, a current IL having a smaller peak than that in other operating states instantaneously flows through the inductor L907 (see FIG. 2C). That is, in the light load operation state, a current flows instantaneously through the inductor during the switching operation.

  Thus, in the conventional switching regulator 900, since the switching operation is performed even when the current flowing through the load 909 is further reduced (light load operation state), the current flows slightly every time as described above, and the efficiency is improved. There was a problem of lowering.

  The switching of the switching element 906b is affected by the delay time of the comparator 904 and the like. For this reason, even if the potential of the node P exceeds 0 [V], it takes time until the switching element 906b is completely turned off due to the delay time of the comparator 904, and the reverse current flowing through the inductor L907 at this time is reduced. It becomes difficult to eliminate them completely. Such factors have promoted the problem of efficiency reduction as described above.

  The present invention has been made in view of the above problems, and an object thereof is to provide a switching regulator capable of realizing an efficient switching operation.

  In order to achieve such an object, a switching regulator according to the present invention includes a triangular wave generating circuit that generates a triangular wave having a first voltage as a peak and a second voltage as a bottom, an inductor for smoothing an output potential, and a subsequent stage of the inductor And a switching circuit for switching the output from the triangular wave generation circuit based on the potential of

  The operating state of the switching regulator is determined by the load applied to the output of the switching regulator. The operating state can be determined based on the potential at the latter stage of the inductor, that is, the output potential of the switching regulator. Therefore, the present invention is based on the potential at the latter stage of the inductor. For example, when the switching regulator is in a light load operation state, the output of the triangular wave generation circuit is lower than the output potential in a heavy load or medium load operation state. Switch to As a result, it is possible to reduce the number of times the switching regulator performs the switching operation by detecting that the output potential of the switching regulator has become larger than the output potential of the triangular wave generating circuit in the light load operation state. As a result, a switching loss can be reduced, and a switching regulator capable of realizing an efficient switching operation without greatly degrading the voltage conversion efficiency even in a light load operation state can be realized.

  According to the present invention, it is possible to realize a switching regulator capable of realizing an efficient switching operation.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram showing the configuration of the switching regulator 1 according to this embodiment.

〔Constitution〕
As shown in FIG. 3, the switching regulator 1 includes a triangular wave generation circuit 10, comparators 21 and 22, a control circuit 20 a, a switch 20 b, an inductor 28, a smoothing capacitor 29, and a comparator 31. The inductor 28 and the smoothing capacitor 29 are used to smooth the output of the switching regulator 1. A load 100 is connected to the output OUT of the switching regulator 1.

・ Triangular wave generation circuit 10
3 includes a charge / discharge current generation circuit 10a, a capacitor 15, a comparator 16, an inverter 32, a 2-input NOR circuit (hereinafter referred to as a 2-input NOR circuit) 33 and 34, and an N-MOS (Metal). -Oxide Semiconductor) transistors 17, 18 and 35. The inverter 32, the two-input NOR circuits 33 and 34, and the N-MOS transistor 35 together with the comparator 31 described later constitute a switching circuit 30.

..Charge / discharge current generation circuit 10a
The charge / discharge current generation circuit 10a in the triangular wave generation circuit 10 is connected in series between the P-MOS transistor 12 and the N-MOS transistor 13 connected in series, and between the P-MOS transistor 12 and the power supply line (power supply voltage VDD). It has a connected P-MOS transistor 11 and an N-MOS transistor 14 connected in series between the N-MOS transistor 13 and the ground. An output (control voltage) of a comparator 16 described later is applied to the gates of the P-MOS transistor 11 and the N-MOS transistor 14. With this configuration, the charge / discharge current generation circuit 10 a generates a charge / discharge current based on the control voltage from the comparator 16. A bias voltage VB1 output from a bias circuit (not shown) is applied to the gate of the P-MOS transistor 12. As a result, the P-MOS transistor 12 is always on (conductive). A bias voltage VB2 output from a bias circuit (not shown) is applied to the gate of the N-MOSFET 13. Thereby, the N-MOS transistor 13 is always turned on. The P-MOS transistor 12 and the N-MOS transistor 13 are provided for the purpose of noise removal. That is, the source-drain resistance of the P-MOS transistor 12 or the source-drain resistance of the N-MOS transistor 13 forms a time constant together with the capacitance of the capacitor 15 described later. Thereby, the noise to the inside of the triangular wave generation circuit 10 is removed. That is, the P-MOS transistor 12 and the N-MOS transistor 13 function as a means for removing noise together with the capacitor 15.

  The output of the charge / discharge current generation circuit 10a matches the output of the triangular wave generation circuit 10. In FIG. 3, this output is referred to as a node S. A capacitor 15 having one end grounded is connected to the node S. When the charging / discharging current generation circuit 10a performs the charging operation, that is, when the P-MOS transistor 11 is turned on, the current output from the charging / discharging current generation circuit 10a is stored in the capacitor 15. As a result, the potential of the node S increases. That is, a rising line of the triangular wave SAWOUT is formed. At this time, the N-MOS transistor 14 is off (cut off). The rising line may be a straight line or a curved line. Hereinafter, the ascending straight line will be described as an example.

  When the charge / discharge current generation circuit 10a performs a discharge operation, that is, when the N-MOS transistor 14 is turned on, the current stored in the capacitor 15 flows out to the ground via the charge / discharge current generation circuit 10a. As a result, the potential of the node S drops. That is, a descending straight line of the triangular wave SAWOUT is formed. At this time, the P-MOS transistor 11 is off. The triangular wave generation circuit 10 outputs the triangular wave SAWOUT by repeating this charging / discharging.

..N-MOS transistors 17, 18, 35
The output (node S) of the charge / discharge current generation circuit 10 a is connected to the non-inverting input terminal of the comparator 16. One end of the N-MOS transistors 17, 18 and 35 is connected to the inverting input terminal of the comparator 16.

  A voltage VL that is a bottom voltage (also referred to as a lower limit peak) of the triangular wave SAWOUT output from the triangular wave generation circuit 10 is applied to the other end of the N-MOS transistor 17. The output of the comparator 16 is connected to the gate of the N-MOS transistor 17. Therefore, the N-MOS transistor 17 functions as a switch that controls conduction / cutoff between the terminal of the voltage VL and the inverting input terminal of the comparator 16 based on the control voltage from the comparator 16.

  The other end of the N-MOS transistor 18 is applied with a voltage VH that is a peak voltage of the triangular wave SAWOUT output from the triangular wave generating circuit 10 during the heavy load operation state and the middle load operation state. The gate of the N-MOS transistor 18 is connected to the output of a two-input OR circuit (hereinafter referred to as a two-input NOR circuit) 34 constituting a selection circuit 30a in the switching circuit 30 described later. As will be described later, the output of the comparator 16 and the output of the comparator 31 are connected to the two inputs of the 2-input NOR circuit 34, respectively. Therefore, the N-MOS transistor 18 functions as a switch for controlling conduction / cutoff between the terminal of the voltage VH and the inverting input terminal of the comparator 16 based on the control voltage from the comparator 16 and the control voltage from the comparator 31. .

  The other end of the N-MOS transistor 35 is applied with a voltage VHPS which is a peak voltage of the triangular wave SAWOUT output from the triangular wave generation circuit 10 in the light load operation state. The voltage VHPS will be described later. The gate of the N-MOS transistor 35 is connected to the output of a two-input NOR circuit 33 constituting a selection circuit 30a in the switching circuit 30 described later. As will be described later, the output of the comparator 16 and the output of the inverter 32 are connected to the two inputs of the 2-input NOR circuit 33, respectively. As will be described later, the output of the comparator 31 is connected to the input of the inverter 32. That is, the output of the comparator 31 is inverted and input to one input of the 2-input NOR circuit 33. Therefore, the N-MOS transistor 35 is a switch that controls conduction / cutoff between the terminal of the voltage VHPS and the inverting input terminal of the comparator 16 based on the control voltage from the comparator 16 and the inverted control voltage from the comparator 31. Function.

..Comparator 16
The comparator 16 applies a voltage VL, VH or VHPS to the inverting input terminal via the N-MOS transistors 17, 18 and 35 as described above, thereby controlling the charge / discharge current generation circuit 10a. (Corresponding to an output potential Vcomp3 described later) is generated.

・ Switching circuit 30
The switching circuit 30 in FIG. 3 functions as a means for switching the voltage applied to the inverting input terminal of the comparator 16 to either the voltage VH or VHPS when forming the rising straight line of the triangular wave SAWOUT. That is, the switching circuit 30 switches the peak voltage of the triangular wave SAWOUT output from the triangular wave generation circuit 10 to either the voltage VH or the voltage VHPS. The switching circuit 30 includes a comparator 31 and a selection circuit 30a.

..Comparator 31
An output of an inductor 28 described later, that is, an output OUT of the switching regulator 1 is fed back to the non-inverting input terminal of the comparator 31. A reference voltage VM is applied to the inverting input terminal. The reference voltage VM will be described later. The comparator 31 compares the output OUT of the switching regulator 1 with the reference voltage VM to generate a control voltage (corresponding to an output potential Vcomp4 described later) for controlling the selection circuit 30a.

..Selection circuit 30a
The selection circuit 30 a includes an inverter 32 and two two-input NOR circuits 33 and 34 incorporated in the triangular wave generation circuit 10. The output of the comparator 31 is connected to the input of the inverter 32. As mentioned above, the output of the inverter 32 is connected to one input of the 2-input NOR circuit 33. That is, the inverted voltage of the control voltage from the comparator 31 is applied to one input of the 2-input NOR circuit 33. The output of the comparator 16 is connected to the other input of the 2-input NOR circuit 33. The output of the 2-input NOR circuit 33 is connected to the gate of the N-MOS transistor 35.

  Similarly, as mentioned above, the output of the comparator 31 is connected to one input of the two-input NOR circuit 34. The output of the comparator 16 is connected to the other input of the 2-input NOR circuit 34. The output of the 2-input NOR circuit 34 is connected to the gate of the N-MOS transistor 18.

  With the above configuration, when the rising straight line of the triangular wave SAWOUT is generated, for example, if the output potential Vout at the output OUT of the switching regulator 1 is smaller than the reference voltage VM, the selection circuit 30a turns off the N-MOS transistor 35 and N- The MOS transistor 18 is turned on. As a result, the voltage VH is applied to the inverting input terminal of the comparator 16, and a triangular wave SAWOUT having a peak voltage VH is generated. On the other hand, if the output potential Vout at the output OUT of the switching regulator 1 is larger than the reference voltage VM, the selection circuit 30a turns off the N-MOS transistor 18 and turns on the N-MOS transistor 35. As a result, the voltage VHPS is applied to the inverting input terminal of the comparator 16, and a triangular wave SAWOUT having a peak voltage of VHPS is generated.

・ Reference voltage VM, voltage VL, VH, VHPS
Here, the relationship between the reference voltage VM, the voltages VL, VH, and VHPS, the triangular wave SAWOUT output from the triangular wave generation circuit 10, and the output OUT of the switching regulator 1 will be described.

  The voltage VL is a voltage for generating a descending straight line of the triangular wave SAWOUT in the present embodiment. Therefore, the voltage VL has the lowest value compared to the other voltages VH, VHPS, and the reference voltage VM. By applying such a voltage VL to the inverting input terminal of the comparator 16, the potential of the capacitor 15 (the potential on the side not grounded to the ground; hereinafter simply referred to as the potential of the capacitor 15) is higher than the voltage VL. Since the comparator 16 outputs the H level, the charge / discharge current generation circuit 10a performs the discharge operation. That is, the N-MOS transistor 14 is turned on, and the charge accumulated in the capacitor 15 flows out. Note that the potential of the capacitor 15 is applied to the non-inverting input terminal of the comparator 16. This discharging operation is continued until the potential of the capacitor 15 matches the voltage VL, that is, until the two potentials input to the comparator 16 match. As a result, a triangular wave SAWOUT having a bottom voltage of VL is generated.

  The voltage VH is a voltage for generating a rising straight line of the triangular wave SAWOUT in the heavy load operation state and the medium load operation state in this embodiment. Therefore, the voltage VH has the highest value compared with the voltages VL and VHPS and the reference voltage VM. By applying such a voltage VH to the inverting input terminal of the comparator 16, the comparator 16 outputs an L level while the potential of the capacitor 15 is lower than the voltage VH, so that the charge / discharge current generation circuit 10a performs the charging operation. Do. That is, the P-MOS transistor 11 is turned on, and charges are accumulated in the capacitor 15. Note that the potential of the capacitor 15 is applied to the non-inverting input terminal of the comparator 16. This charging operation is continued until the potential of the capacitor 15 matches the voltage VH, that is, until the two potentials input to the comparator 16 match. As a result, a triangular wave SAWOUT having a peak voltage VH is generated.

  The reference voltage VM is a voltage for detecting a light load operation state in the present embodiment. That is, in this embodiment, a state where the output potential Vout of the switching regulator 1 is lower than the reference voltage VM is detected as a light load operation state. Therefore, in this embodiment, the reference voltage VM is configured to have a value higher than the voltage VL and lower than the voltage VH. However, the reference voltage VM has a value higher than the output potential Vout of the output OUT in a heavy load operation state, that is, in an operation state in which there is no period in which a current IL flowing through an inductor 28 described later is 0 [A]. Must be configured. This is to prevent the peak voltage of the triangular wave SAWOUT from becoming other than VH (for example, VHPS) during the heavy load operation state. For these reasons, in this embodiment, the reference voltage VM is set so as to have a value higher than the output potential Vout of the switching regulator 1 and lower than the voltage VH in an operating state without a period during which the current IL is 0 [A]. Is configured. For example, the reference voltage VM can be set to a voltage value of about 90% of the voltage VH.

  The voltage VHPS is a voltage for generating a rising straight line of the triangular wave SAWOUT in the light load operation state in this embodiment. In this embodiment, it is configured to have a value higher than the voltage VL and lower than the reference voltage VM. By applying such a voltage VHPS to the inverting input terminal of the comparator 16, the comparator 16 outputs an L level during a period when the potential of the capacitor 15 is lower than the voltage VHPS. Therefore, the charge / discharge current generation circuit 10a performs the charging operation. Do. That is, the P-MOS transistor 11 is turned on, and charges are accumulated in the capacitor 15. Note that the potential of the capacitor 15 is applied to the non-inverting input terminal of the comparator 16. This charging operation is continued until the potential of the capacitor 15 matches the voltage VHPS, that is, until the two potentials input to the comparator 16 match. Thereby, a triangular wave SAWOUT having a voltage VHPS whose peak voltage is lower than the reference voltage VM is generated. In this embodiment, the triangular wave SAWOUT having a voltage VHPS whose peak voltage is lower than the reference voltage VM is used to reduce the number of switching operations in the switch 20b described later. Thereby, the loss by switching can be reduced and the switching regulator 1 in which the voltage conversion efficiency is not greatly deteriorated even in the light load operation state can be realized. However, if the voltage VHPS is set to a value that is too close to the voltage VL, the period of the triangular wave SAWOUT is shortened, which may increase power consumption. For this reason, in this embodiment, the voltage VHPS is configured to have a value sufficiently higher than the voltage VL and lower than the voltage VM.

・ Other configurations ・ ・ Comparator 21
Next, returning to FIG. 3, another configuration of the switching regulator 1 will be described. The output potential Vsawout of the triangular wave generation circuit 10 is applied to the inverting input terminal of the comparator 21. In other words, the node S is connected to the inverting input terminal of the comparator 21. An output of an inductor 28 described later, that is, an output OUT of the switching regulator 1 is branched and connected to the non-inverting input terminal of the comparator 21. In other words, the output OUT of the switching regulator 1 is fed back to the non-inverting input terminal of the comparator 21. The comparator 21 compares the output potential Vsawout of the triangular wave SAWOUT with the output potential Vout of the switching regulator 1 to control a P-MOS transistor 24 of the switch 20b described later (corresponding to an output potential Vcomp1 described later). Is generated.

..Comparator 22
On the other hand, an inverting input terminal of the comparator 22 is branched and connected to an output of a switch 20b, which will be described later, that is, a node P positioned in front of the inductor 28. In other words, the output (node P) of the switch 20 b is fed back to the non-inverting input terminal of the comparator 22. The non-inverting input terminal of the comparator 22 is grounded. The comparator 22 compares the potential of the node P with the ground potential to generate a control voltage (corresponding to an output potential Vcomp2 described later) for controlling an N-MOS transistor 27 of the switch 20b described later.

..Control circuit 20a
The control voltage output from the comparators 21 and 22 is input to the control circuit 20a. The control circuit 20a includes buffers 23 and 26 and a two-input AND circuit (hereinafter referred to as a two-input AND circuit) 25. The input of the buffer 23 is connected to the output of the comparator 21. The output of the buffer 23 is connected to the gate of a P-MOS transistor 24 constituting a switch 20b described later. That is, on / off of the P-MOS transistor 24 of the switch 20b is controlled based on the control voltage output from the comparator 21. One input of the 2-input AND circuit 25 is connected to the output of the comparator 21. The other input of the 2-input AND circuit 25 is connected to the output of the comparator 22. That is, the 2-input AND circuit 25 performs an AND operation on the outputs of the two comparators 21 and 22. The output of the 2-input AND circuit 25 is connected to the input of the buffer 26. The output of the buffer 26 is connected to the gate of an N-MOS transistor 27 constituting a switch 20b described later. That is, conduction / cutoff of the N-MOS transistor 27 of the switch 20b is controlled based on the control voltage output from the comparators 21 and 22. In this way, the control circuit 20a functions as a means for controlling the switch 20b based on the outputs of the comparators 21 and 22.

・ Switch 20b
The switch 20 b has a push-pull configuration including a P-MOS transistor 24 and an N-MOS transistor 27. An input voltage Vin is applied to one end of the P-MOS transistor 24 from the input terminal IN. One end of the N-MOS transistor 27 is grounded. The other end of the P-MOS transistor 24 and the other end of the N-MOS transistor 27 are connected and branched. In FIG. 3, this branch portion, that is, the output of the switch 20 b is denoted as a node P.

  The switch 20b having such a configuration functions as a means for controlling the amount of current flowing in the inductor 28 provided in the subsequent stage. That is, when the output potential Vout of the switching regulator 1 is lower than the output potential Vsawout of the triangular wave generation circuit 10, the comparator 21 outputs L (Low) level, so that the P-MOS transistor 24 is turned on. As a result, the input voltage Vin is applied to the node P via the input terminal IN, and the amount of current IL flowing through the inductor 28 increases. Since the output of the 2-input AND circuit 25 is at L level, the N-MOS transistor 27 is off.

  On the other hand, when the output potential Vout of the switching regulator 1 becomes higher than the output potential Vsawout of the triangular wave generation circuit 10, the comparator 21 outputs an H (High) level, so that the P-MOS transistor 24 is turned off. At this time, since an inertial current continues to flow through the inductor 28, the potential of the node P becomes 0 [V (volt)] or less. Accordingly, a voltage equal to or lower than the ground potential is applied to the inverting input terminal of the comparator 22, the H level is output from the comparator 22, and the output of the 2-input AND circuit 25 becomes the H level. As a result, the N-MOS transistor 27 is turned on, the node P is grounded, and the amount of current IL flowing through the inductor 28 decreases or becomes 0 [A]. This continues until the output potential Vout of the switching regulator 1 becomes lower than the output potential Vsawout of the triangular wave generation circuit 10. Thereafter, the switching regulator 1 repeats the same operation to supply stable power to the load 100 via the smoothing capacitor 29.

[Operation]
Next, the operation of the switching regulator 1 according to the present embodiment will be described in detail with reference to the drawings.

-In the heavy load operation state First, the operation in the heavy load operation state will be described with reference to the operation waveform diagram shown in FIG. 4 shows the output potential Vsawout (hereinafter simply referred to as output potential Vsawout) of the triangular wave generation circuit 10 and the output potential Vout (hereinafter simply referred to as output potential Vout) of the switching regulator 1 and the node A in the heavy load operation state. (Potential Vcomp1 output from comparator 21; hereinafter simply referred to as output potential Vcomp1), node B (potential Vcomp2 output from comparator 22, hereinafter referred to simply as output potential Vcomp2), and node C (output from comparator 16). FIG. 4 is a waveform diagram of a potential Vcomp3 (hereinafter simply referred to as output potential Vcomp3), a node D (potential Vcomp4 output from the comparator 31; hereinafter simply referred to as output potential Vcomp4), and a current IL flowing through the inductor 28.

  In the heavy load operation state, since the output potential Vout is lower than the reference voltage VM (see Vout and VM in FIG. 4), the output potential Vcomp4 of the comparator 31 becomes L level. That is, the potential of the node D in FIG. 3 becomes L level (see D in FIG. 4). Therefore, the L level is applied to the gate of the N-MOS transistor 35 via the inverter 32 and the two-input NOR circuit 33. That is, when the output potential Vout is lower than the reference voltage VM, the N-MOS transistor 35 is always off. In other words, in a state where the output potential Vout is lower than the reference voltage VM, that is, in a heavy load operation state, the configuration for applying the voltage VHPS to the inverting input terminal of the comparator 16 is switched to invalid.

  In this state, for example, when the output potential Vcomp3 of the comparator 16 becomes L level, that is, when the node D in FIG. 3 is L level and the node C is L level (see C in FIG. 4), the N-MOS transistor 18 The H level is applied to the gate of the first through the two-input NOR circuit 34. As a result, the voltage VH is applied to the inverting input terminal of the comparator 16. That is, the comparator 16 compares the voltage VH with the output potential Vsawout. Note that the N-MOS transistor 17 to which the L level output from the comparator 16 is applied to the gate is off.

  The L level output from the comparator 16 is also supplied to the charge / discharge current generation circuit 10a. As a result, the P-MOS transistor 11 is turned on and the N-MOS transistor 14 is turned off, so that the capacitor 15 is charged via the P-MOS transistors 11 and 12, and the output potential Vsawout, that is, the potential of the node S rises. (See Vsawout in FIG. 4). That is, a rising straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 4).

  Thereafter, when the output potential Vsawout (the potential of the node S) exceeds the voltage VH (see Vsawout and VH in FIG. 4), that is, when the potential of the non-inverting input terminal of the comparator 16 exceeds the potential of the inverting input terminal, The output potential Vcomp3 becomes H level. That is, the node C in FIG. 3 becomes H level (see C in FIG. 4). As a result, the P-MOS transistor 11 in the charge / discharge current generation circuit 10a is turned off and the N-MOS transistor 14 is turned on, so that current flows out of the capacitor 15 via the N-MOS transistors 13 and 14, and the output potential Vsawout, That is, the potential of the node S falls (see Vsawout in FIG. 4). That is, a descending straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 4).

  Further, the N-MOS transistor 17 is turned on and the N-MOS transistor 18 is turned off by the H level output from the comparator 16. For this reason, the voltage VL is applied to the inverting input terminal of the comparator 16.

  Thereafter, when the output potential Vsawout (potential of the node S) falls below the voltage VL, that is, when the potential of the non-inverting input terminal of the comparator 16 falls below the potential of the inverting input terminal, the output potential Vcomp3 of the comparator 16 becomes L level. . That is, the node C in FIG. 3 becomes L level (see C in FIG. 4). Thereby, as described above, the capacitor 15 is charged, and the output potential Vsawout, that is, the potential of the node S rises (see Vsawout in FIG. 4). Thereafter, by repeating the same operation, a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output (see Vsawout in FIG. 4).

  The operation other than the triangular wave generation circuit 10 is as follows. For example, when the output potential Vout of the switching regulator 1 is smaller than the output potential Vsawout generated by the triangular wave generation circuit 10 as described above, the output potential Vcomp1 of the comparator 21 becomes L level. That is, the node A in FIG. 3 becomes L level (see A in FIG. 4). As a result, the P-MOS transistor 24 is turned on, so that the voltage at the input terminal IN (hereinafter simply referred to as input potential) Vin is applied to the node P, and the current IL flowing through the inductor 28 increases (see IL in FIG. 4). ), The output potential Vout rises (see Vout in FIG. 4).

  Thereafter, when the output potential Vout becomes larger than the output potential Vsawout, the output potential Vcomp1 of the comparator 21 becomes H level. That is, the node A in FIG. 3 becomes H level (see A in FIG. 4). As a result, the P-MOS transistor 24 is turned off. At this time, since the inductor 28 tries to keep an inertial current flowing, the potential of the node P becomes smaller than the ground potential (0 [V]). As a result, since a potential equal to or lower than the ground potential is applied to the inverting input terminal of the comparator 22, the output potential Vcomp2 of the comparator 22 becomes H level. That is, the node B in FIG. 3 becomes H level (see B in FIG. 4). As a result, the N-MOS transistor 27 is turned on, so that the node P is grounded, the current IL flowing through the inductor 28 is reduced (see IL in FIG. 4), and the output potential Vout is lowered (see Vout in FIG. 4). . This operation state is continued until the output potential Vout becomes smaller than the output potential Vsawout.

  As described above, in the heavy load operation state, the switching regulator 1 increases the current IL flowing through the inductor 28 by turning on the P-MOS transistor 24 during a period when the output potential Vsawout is larger than the output potential Vout. During the period when the output potential Vsawout is smaller than the output potential Vout, the N-MOS transistor 27 is turned on to continue the current IL flowing through the inductor 28 while decreasing. Thereafter, by repeating the same operation, stable power is supplied to the load 100 via the smoothing capacitor 29.

-During Medium Load Operation State Next, the operation during the medium load operation state will be described with reference to the operation waveform diagram shown in FIG. 5 shows the output potential Vsawout, the output potential Vout, the node A (output potential Vcomp1), the node B (output potential Vcomp2), the node C (output potential Vcomp3), and the node D (output potential Vcomp4) in the middle load operation state. 4 is a waveform diagram of current IL flowing through inductor 28. FIG.

  The operation of the triangular wave generation circuit 10 in the medium load operation state is the same as the operation of the triangular wave generation circuit 10 in the heavy load operation state described above. That is, since the comparator 31 continues to output the L level, that is, the node D (output potential Vcomp4) continues to maintain the L level, the comparator 16 compares the voltage VH or the voltage VL with the potential of the capacitor 15. As a result, a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output. In addition, since the same operation is performed, the operation waveforms of the output potential Vsawout, the node C (output potential Vcomp3), and the node D (output potential Vcomp4) are also the same as clearly shown in FIG. 4 and FIG. It becomes the waveform.

  The operation other than the triangular wave generation circuit 10 is as follows. For example, when the output potential Vout of the switching regulator 1 is smaller than the output potential Vsawout of the triangular wave SAWOUT generated as described above, the output potential Vcomp1 of the comparator 21 becomes L level. That is, the node A in FIG. 3 becomes L level (see A in FIG. 5). Thereby, since the P-MOS transistor 24 is turned on, the input potential Vin is applied to the node P, the current IL flowing through the inductor 28 increases (see IL in FIG. 5), and the output potential Vout increases (see FIG. 5). Vout reference).

  Thereafter, when the output potential Vout becomes larger than the output potential Vsawout, the output potential Vcomp1 of the comparator 21 becomes H level. That is, the node A in FIG. 3 becomes H level (see A in FIG. 5). As a result, the P-MOS transistor 24 is turned off. At this time, since the inductor 28 tries to keep an inertial current flowing, the potential of the node P becomes smaller than the ground potential (0 [V]). As a result, since a potential equal to or lower than the ground potential is applied to the inverting input terminal of the comparator 22, the output potential Vcomp2 of the comparator 22 becomes H level. That is, the node B in FIG. 3 becomes H level (see B in FIG. 5). As a result, the N-MOS transistor 27 is turned on, the node P is grounded, the current IL flowing through the inductor 28 is reduced (see IL in FIG. 5), and the output potential Vout is lowered (see Vout in FIG. 5). . However, when the current IL flowing through the inductor 28 becomes 0 [A] or less, that is, when the current flows through the inductor 28 in the reverse direction (direction from the output OUT to the node P), the potential of the node P becomes 0 [V] or more. Therefore, the output potential Vcomp2 of the comparator 22 becomes L level. That is, the node B in FIG. 3 becomes L level (see B in FIG. 5). As a result, the N-MOS transistor 27 is turned off, and a reverse current IL is prevented from flowing through the inductor 28. This operation state is continued until the output potential Vout becomes smaller than the output potential Vsawout.

  As described above, in the middle load operation state, the switching regulator 1 increases the current IL flowing through the inductor 28 by turning on the P-MOS transistor 24 during a period when the output potential Vsawout is larger than the output potential Vout. When the output potential Vsawout is smaller than the output potential Vout, the N-MOS transistor 27 is turned on to continue the current IL flowing through the inductor 28 while reducing the potential at the node P to 0 [V] or less. At this time, the N-MOS transistor 27 is turned off to prevent the reverse current IL from flowing through the inductor. Thereafter, by repeating the same operation, stable power is supplied to the load 100 via the smoothing capacitor 29. In this configuration, by using the P-MOS transistor 24 and the N-MOS transistor 27 having a small on-resistance, less power is consumed in this portion, so that an efficient switching regulator 1 can be realized. it can.

-Light load operation state Next, the operation in the light load operation state will be described with reference to the operation waveform diagram shown in FIG. 6 shows the output potential Vsawout, output potential Vout, node A (output potential Vcomp1), node B (output potential Vcomp2), node C (output potential Vcomp3), and node D (output potential Vcomp4) in the light load operation state. And FIG. 6 is a waveform diagram of current IL.

  In the light load operation state, there is a period in which the output potential Vout is higher than the reference voltage VM (see Vout and VM in FIG. 6). For this reason, the comparator 31 outputs an H level during this period, that is, during the period when the output potential Vout is higher than the reference voltage VM. In other words, a period in which the potential of the node D in FIG. 3 is at an H level occurs (see D in FIG. 6). During this period, since the H level is input to one input of the 2-input NOR circuit 34, the output of the 2-input NOR circuit 34 is always at the L level. That is, the N-MOS transistor 18 is always off during a period when the output potential Vout is higher than the reference voltage VM. In other words, the configuration for applying the voltage VH to the inverting input terminal of the comparator 16 during the period when the output potential Vout is higher than the reference voltage VM, that is, in the light load operation state, is switched to invalid.

  When the output potential Vcomp4 of the comparator 31 is at the H level, for example, when the output potential Vcomp3 of the comparator 16 is at the L level, that is, when the node D in FIG. 3 is at the H level and the node C is at the L level (FIG. 6). (See C) The L level is applied to the two inputs of the two-input NOR circuit 33. As a result, since the H level is output from the 2-input NOR circuit 33, the H level is applied to the gate of the N-MOS transistor 35, and the N-MOS transistor 35 is turned on. Therefore, the voltage VHPS is applied to the inverting input terminal of the comparator 16. That is, the comparator 16 compares the voltage VHPS with the output voltage Vsawout. Note that the N-MOS transistor 17 to which the L level output from the comparator 16 is applied to the gate is off.

  The L level output from the comparator 16 is also supplied to the charge / discharge current generation circuit 10a. As a result, the P-MOS transistor 11 is turned on and the N-MOS transistor 14 is turned off, so that the capacitor 15 is charged via the P-MOS transistors 11 and 12, and the output potential Vsawout, that is, the potential of the node S rises. (See Vsawout in FIG. 6). That is, a rising straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 6).

  Thereafter, when the output potential Vsawout (potential of the node S) exceeds the voltage VHPS (see Vsawout and VHPS in FIG. 6), that is, when the potential of the non-inverting input terminal of the comparator 16 exceeds the potential of the inverting input terminal, The output potential Vcomp3 becomes H level. That is, the node C in FIG. 3 becomes H level (see C in FIG. 6). As a result, the P-MOS transistor 11 in the charge / discharge current generation circuit 10a is turned off and the N-MOS transistor 14 is turned on, so that current flows out of the capacitor 15 via the N-MOS transistors 13 and 14, and the output potential Vsawout, That is, the potential of the node S falls (see Vsawout in FIG. 6). That is, a descending straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 6).

  Further, the N-MOS transistor 17 is turned on and the N-MOS transistor 35 is turned off by the H level output from the comparator 16. For this reason, the voltage VL is applied to the inverting input terminal of the comparator 16.

  Thereafter, when the output potential Vsawout (potential of the node S) falls below the voltage VL, that is, when the potential of the non-inverting input terminal of the comparator 16 falls below the potential of the inverting input terminal, the output potential Vcomp3 of the comparator 16 becomes L level. . That is, the node C in FIG. 3 becomes L level (see C in FIG. 6). Thereby, as described above, the capacitor 15 is charged, and the output potential Vsawout, that is, the potential of the node S rises (see Vsawout in FIG. 6). Thereafter, by repeating the above-described operation while the output potential Vout is higher than the reference voltage VM, a triangular wave SAWOUT having a peak voltage of VHPS and a bottom voltage of VL is output (see Vsawout in FIG. 6).

  However, in the light load operation state according to the present embodiment, the output potential Vout may be lower than the reference voltage VM. In this embodiment, since the L level is output from the comparator 31 while the output potential Vout is lower than the reference voltage VM, the triangular wave generation circuit 10 performs the same operation as in the heavy load operation state or the intermediate load operation state. Thus, a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output (see Vsawout in FIG. 6).

  The operation other than the triangular wave generation circuit 10 is as follows. As described above, since the peak voltage of the triangular wave SAWOUT is switched to the voltage VHPS lower than the voltage VH, the state in which the output potential Vout of the switching regulator 1 becomes higher than the output potential Vsawout of the triangular wave generation circuit 10 continues for a while ( (See Vsawout and Vout in FIG. 6). For this reason, the period during which the output potential Vcomp1 of the comparator 21 is at the H level continues for a while (see A in FIG. 6). During this period, the P-MOS transistor 24 in the switch 20b does not perform a switching operation. Further, during the same period, that is, a period in which the output potential Vout is larger than the output potential Vsawout and larger than the reference voltage VM (see Vsawout, Vout and VM in FIG. 6), the potential of the node P in FIG. 3 falls below 0 [V]. Therefore, the output potential Vcomp2 of the comparator 22 is at the L level. That is, the node B in FIG. 3 becomes L level (see B in FIG. 6). Therefore, during this period, the N-MOS transistor 27 does not perform a switching operation. However, since a current is supplied to the load 100, the voltage of the capacitor 29 decreases, and the output potential Vout of the switching regulator 2 decreases (see Vout in FIG. 6).

  Thereafter, when the output potential Vout becomes lower than the reference voltage VM, the output potential Vcomp4 of the comparator 31 becomes L level. That is, the node D in FIG. 3 becomes L level (see D in FIG. 6). As a result, the configuration for applying the voltage VHPS to the comparator 16 is invalidated and the configuration for applying the voltage VH to the comparator 16 functions as in the heavy load operation state and the medium load operation state described above. In order to start, a triangular wave SAWOUT having a peak potential VH is output from the triangular wave generating circuit 10 (see Vsawout in FIG. 6).

  As described above, when the triangular wave SAWOUT having the peak potential VH is generated, the output potential Vout is smaller than the peak voltage VH. Therefore, when the next peak of the triangular wave SAWOUT is input to the comparator 21, the output potential Vout is A period smaller than the output potential Vsawout occurs (see Vout and Vsawout in FIG. 6). That is, a period in which the output potential Vcomp1 of the comparator 21 is at the L level occurs. During this period, the node A in FIG. 3 is at the L level (see A in FIG. 6). Further, since the P-MOS transistor 24 in the switch 20b is turned on during the synchronization, the input voltage Vin is applied to the node P, the amount of current IL flowing through the inductor 28 increases (see IL in FIG. 6), and the output potential Vout. (See Vout in FIG. 6). Thereafter, when the output potential Vout becomes higher than the reference voltage VM, the output potential Vcomp4 of the comparator 31 becomes H level, that is, the node D becomes H level (see D in FIG. 6), so that the voltage VHPS is applied to the comparator 16. The configuration to do begins to work.

  Even in this operation, when the output potential Vout of the switching regulator 1 becomes larger than the output potential Vsawout of the triangular wave generation circuit 10, the comparator 21 outputs the H level as in the above-described middle load operation state. Thus, the node A in FIG. 3 becomes H level (see A in FIG. 6), and the P-MOS transistor 24 is turned off. At this time, since the inductor 28 tries to keep an inertial current flowing, the potential of the node P becomes smaller than the ground potential (0 [V]). For this reason, the comparator 22 outputs H level, the node B in FIG. 3 becomes H level (see B in FIG. 6), and the N-MOS transistor 27 is turned on. As a result, the node P is grounded, the current IL flowing through the inductor 28 decreases (see IL in FIG. 6), and the potential Vout of the output OUT decreases (see Vout in FIG. 6). However, when the current IL flowing through the inductor 28 becomes 0 [A] or less, that is, when the current flows through the inductor 28 in the reverse direction (direction from the output OUT to the node P), the potential of the node P becomes 0 [V] or more. Therefore, the comparator 22 outputs L level, and the node B in FIG. 3 becomes L level (see B in FIG. 6). As a result, the N-MOS transistor 27 is turned off and the current IL is prevented from flowing through the inductor 28 in the reverse direction. This operation state is continued until the output potential Vout of the switching regulator 1 becomes smaller than the output potential Vsawout of the triangular wave SAWOUT.

  As described above, when the peak voltage of the triangular wave SAWOUT is switched to the voltage VHPS lower than the voltage VH during the light load operation state, the state where the output potential Vout becomes larger than the output potential Vsawout can be continued for a while. Therefore, during this period, the switching operation by the switch 20b can be invalidated. As a result, it is possible to reduce the switching loss, and it is possible to realize the switching regulator 1 capable of realizing an efficient switching operation without greatly degrading the voltage conversion efficiency even in a light load operation state.

  In this embodiment, the case where a negative OR circuit is used has been described as an example. However, the present invention is not limited to this, and can be configured using, for example, an OR circuit. In this case, the N-MOS transistor and the P-MOS transistor are appropriately replaced with the P-MOS transistor and the N-MOS transistor, respectively, or an inverter is appropriately provided at the output stage of the OR circuit. Further, in the present invention, particularly in the scope of the claims, all of these including the logical OR circuit are the logical OR circuit.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment.

〔Constitution〕
FIG. 7 shows a circuit configuration of the switching regulator 2 according to this embodiment. As shown in FIG. 7, the switching regulator 2 includes a triangular wave generation circuit 10 ′, comparators 21 and 22, a control circuit 20 a, a switch 20 b, an inductor 28, a smoothing capacitor 29, and a comparator 31. The inductor 28 and the smoothing capacitor 29 are used to smooth the output of the switching regulator 1. A load 100 is connected to the output OUT of the switching regulator 2.

・ Triangular wave generation circuit 10 '
7 includes a charge / discharge current generation circuit 10a, a 2-input OR circuit (hereinafter referred to as 2-input OR circuit) 41, a 2-input NOR circuit 42, a capacitor 15, a comparator 46, and inverters 43 and 45. And N-MOS transistors 17, 18 and 44. The 2-input OR circuit 41, the 2-input NOR circuit 42, the inverter 43, the comparator 46, and the N-MOS transistors 17, 18 and 44 constitute a switching circuit 40 together with the comparator 31.

..Charge / discharge current generation circuit 10a
The charge / discharge current generation circuit 10a in the triangular wave generation circuit 10 ′ includes a P-MOS transistor 12 and an N-MOS transistor 13 connected in series, a P-MOS transistor 12 and a power supply line (power supply voltage) as in the first embodiment. P-MOS transistor 11 connected in series with VDD), and N-MOS transistor 14 connected in series between N-MOS transistor 13 and ground. The gate of the P-MOS transistor 11 is connected to the output of the 2-input OR circuit 41 in the switching circuit 40 described later. The two inputs of the two-input OR circuit 41 are connected to the output of the comparator 46 and the output of the comparator 31, respectively. On the other hand, the output of the 2-input NOR circuit 42 in the switching circuit 40, which will be described later, is connected to the gate of the N-MOS transistor 14. The two inputs of the 2-input NOR circuit 42 are connected to the output of the comparator 31 and the output of the inverter 43, respectively. The output of the comparator 46 is connected to the input of the inverter 43. That is, the inverted control voltage of the comparator 46 is applied to one input of the 2-input NOR circuit 42. With this configuration, the charge / discharge current generation circuit 10 a generates a charge / discharge current based on the control voltage from the comparators 46 and 31. A bias voltage VB1 output from a bias circuit (not shown) is applied to the gate of the P-MOS transistor 12. As a result, the P-MOS transistor 12 is always on (conductive). A bias voltage VB2 output from a bias circuit (not shown) is applied to the gate of the N-MOSFET 13. Thereby, the N-MOS transistor 13 is always turned on. The P-MOS transistor 12 and the N-MOS transistor 13 are provided for the purpose of noise removal as in the first embodiment.

  The output of the charge / discharge current generation circuit 10a matches the output of the triangular wave generation circuit 10 '. In FIG. 7, this output is referred to as a node S. A capacitor 15 having one end grounded is connected to the node S. When the charging / discharging current generation circuit 10a performs the charging operation, that is, when the P-MOS transistor 11 is turned on, the current output from the charging / discharging current generation circuit 10a is stored in the capacitor 15. As a result, the potential of the node S increases. That is, a rising straight line of the triangular wave SAWOUT is formed. At this time, the N-MOS transistor 14 is off (cut off). When the charge / discharge current generation circuit 10a performs a discharge operation, that is, when the N-MOS transistor 14 is turned on, the current stored in the capacitor 15 flows out to the ground via the charge / discharge current generation circuit 10a. As a result, the potential of the node S drops. That is, a descending straight line of the triangular wave SAWOUT is formed. At this time, the P-MOS transistor 11 is off. The triangular wave generation circuit 10 'outputs a triangular wave SAWOUT by repeating this charging and discharging.

..N-MOS transistors 17 and 18
The output (node S) of the charge / discharge current generation circuit 10 a is connected to the non-inverting input terminal of the comparator 46. The comparator 46 has a configuration in which a control terminal for powering down the comparator 46 is added to the configuration similar to the comparator 16 according to the first embodiment. The output of the comparator 31 is connected to this control terminal. That is, the operation / non-operation of the comparator 46 is controlled based on the output of the comparator 31. One end of the N-MOS transistors 17 and 18 is connected to the inverting input terminal of the comparator 46.

  A voltage VL that is a bottom voltage (also referred to as a lower limit peak) of the triangular wave SAWOUT output from the triangular wave generating circuit 10 ′ is applied to the other end of the N-MOS transistor 17. The output of the comparator 46 is connected to the gate of the N-MOS transistor 17. Therefore, the N-MOS transistor 17 functions as a switch that controls conduction / cutoff between the terminal of the voltage VL and the inverting input terminal of the comparator 46 based on the control voltage from the comparator 46.

  The other end of the N-MOS transistor 18 is applied with a voltage VH which is a peak voltage of the triangular wave SAWOUT output from the triangular wave generating circuit 10 'during the heavy load operation state and the middle load operation state. The output of the comparator 46 is connected to the gate of the N-MOS transistor 18 via the inverter 45. Therefore, the N-MOS transistor 18 functions as a switch that controls conduction / cutoff between the terminal of the voltage VH and the inverting input terminal of the comparator 46 based on the inverted control voltage from the comparator 46.

..Comparator 46
The comparator 46 applies a voltage VL or VH to the inverting input terminal via the N-MOS transistors 17 and 18 as described above, thereby controlling the charge / discharge current generating circuit 10a (output described later). Potential Vcomp3).

・ Switching circuit 40
7 functions as a means for switching the output voltage Vsawout output from the triangular wave generation circuit 10 ′, that is, the potential of the node S to the voltage VL when the comparator 31 detects the light load operation state. . That is, the switching circuit 40 performs switching so that the voltage VL is output from the triangular wave generation circuit 10 ′ during the light load operation state. The switching circuit 40 includes a comparator 31 and a selection circuit 40a.

..Comparator 31
The comparator 31 is the same as the comparator 31 described in the first embodiment. That is, the output of the inductor 28 described later, that is, the output OUT of the switching regulator 2 is fed back to the non-inverting input terminal of the comparator 31. A reference voltage VM is applied to the inverting input terminal. The comparator 31 compares the output OUT of the switching regulator 2 with the reference voltage VM to generate a control voltage (corresponding to an output potential Vcomp4 described later) for controlling the selection circuit 40a.

..Selection circuit 40a
The selection circuit 40a includes a 2-input OR circuit 41, a 2-input NOR circuit 42, an inverter 43, an N-MOS transistor 44, and a comparator 46 (particularly a control terminal portion) incorporated in the triangular wave generation circuit 10 ′. As mentioned above, the output of the comparator 46 is connected to one input of the two-input OR circuit 41. The output of the comparator 31 is connected to the other input of the 2-input OR circuit 41. The output of the 2-input OR circuit 41 is connected to the gate of the P-MOS transistor 11. Therefore, the charge / discharge current generation circuit 10a according to the present embodiment has a rising straight line of the triangular wave SAWOUT when the L level is output from both the comparators 31 and 46, that is, the output potential Vout of the switching regulator 2 is smaller than the reference voltage VM. Only when it is formed, the P-MOS transistor 11 is turned on to perform a charging operation.

  Similarly, as mentioned above, the output of the comparator 31 is connected to one input of the two-input NOR circuit 42. The other input of the two-input MOR circuit 42 is connected to the output of the comparator 46 via the inverter 43. The output of the 2-input NOR circuit 42 is connected to the gate of the N-MOS transistor 14. Therefore, the charge / discharge current generation circuit 10a according to the present embodiment is configured such that when the L level is output from the comparator 31 and the H level is output from the comparator 46, that is, the output potential Vout of the switching regulator 2 is smaller than the reference voltage VM. Only when the descending straight line of the triangular wave SAWOUT is formed, the N-MOS transistor 14 is turned on and the discharging operation is performed.

  Similarly, as mentioned above, the output of the comparator 31 is connected to the control terminal of the comparator 46. Therefore, the comparator 46 is powered down when, for example, an H level is input from the comparator 31 to the control terminal. As a result, the output of the comparator 46, that is, the node C becomes L level. In other words, when the light load operation state is detected in the comparator 31, the comparator 46 is turned off and becomes inoperable. As a result, the node C becomes L level.

  The output of the comparator 31 is connected to the gate of an N-MOS transistor 44 provided between the terminal to which the voltage VL is applied and the output (node S) of the charge / discharge current generation circuit 10a. That is, when a light load operation state is detected in the comparator 31, the triangular wave generation circuit 10 ′ according to the present embodiment does not generate the triangular wave SAWOUT by powering down the comparator 46, but instead generates a constant level voltage VL. Output.

  With the above configuration, in this embodiment, when the L level is output from the comparator 31, in other words, only in the heavy load operation state or the medium load operation state, the comparator 46 operates and the charge / discharge current generation circuit 10a is operated. Is controlled to perform a charge / discharge operation, and a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output. In addition, when the H level is output from the comparator 31, in other words, when a light load operation state is detected, the comparator 46 is powered down and the input terminal of the voltage VL and the node S (triangular wave) The voltage VL is output from the triangular wave generating circuit 10 ′ instead of the triangular wave SAWOUT.

・ Other configurations ・ ・ Comparator 21
7 are the same as those in the first embodiment, and thus detailed description thereof is omitted here. In FIG. 7, the other configurations (comparator 22, control circuit 20a, switch 20b, inductor 28, and smoothing capacitor 29) are the same as those in the first embodiment.

[Operation]
Next, the operation of the switching regulator 2 according to the present embodiment will be described in detail with reference to the drawings.

・ In the heavy load operation state First, the operation in the heavy load operation state will be described. Note that the operation waveform at this time is the same as the operation waveform described with reference to FIG. 4 in the first embodiment, and will be described here with reference to this.

  In the heavy load operation state, since the output potential Vout is lower than the reference voltage VM (see Vout and VM in FIG. 4), the output potential Vcomp4 of the comparator 31 becomes L level. That is, the potential of the node D in FIG. 7 becomes L level (see D in FIG. 4). Therefore, one input of the 2-input OR circuit 41 and 2-input NOR circuit 42 constituting the switching circuit 40 (particularly the selection circuit 40a), the gate of the N-MOS transistor 44, and the control terminal of the comparator 46 are respectively connected to L A level is entered. As a result, the N-MOS transistor 44 is turned off and the comparator 46 is in an operating state.

  In this state, for example, when the output potential Vcomp3 of the comparator 46 becomes L level, that is, when the node D in FIG. 7 is L level and the node C is L level (see C in FIG. 4), the N-MOS transistor 18 The H level is input to the gate of the first through the inverter 45. As a result, the voltage VH is applied to the inverting input terminal of the comparator 46. That is, the comparator 46 compares the voltage VH with the output potential Vsawout. Note that the N-MOS transistor 17 to which the L level output from the comparator 46 is applied to the gate is off.

  The L level output from the comparator 46 is also applied to the other input of the two-input OR circuit 41 and the input of the inverter 43 that constitute the switching circuit 40 (particularly the selection circuit 40a). Note that the output of the inverter 43 is connected to the other input of the two-input NOR circuit 42. Here, since the output potential Vcomp4 of the comparator 31 is also at the L level, the L level is input to the two inputs of the 2-input OR circuit 41. Therefore, the 2-input OR circuit 41 outputs L level and turns on the P-MOS transistor 11. On the other hand, L level and H level are input to the two inputs of the 2-input NOR circuit 42. For this reason, the two-input NOR circuit 42 outputs an L level and turns off the N-MOS transistor 14. As a result, the capacitor 15 is charged through the P-MOS transistors 11 and 12, and the output potential Vsawout, that is, the potential of the node S rises (see Vsawout in FIG. 4). That is, a rising straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 4).

  Thereafter, when the output potential Vsawout (the potential of the node S) exceeds the voltage VH (see Vsawout and VH in FIG. 4), that is, when the potential of the non-inverting input terminal of the comparator 46 exceeds the potential of the inverting input terminal, The output potential Vcomp3 becomes H level. That is, the node C in FIG. 7 becomes H level (see C in FIG. 4). Accordingly, since the two inputs of the 2-input OR circuit 41 are L level or H level, respectively, and the two inputs of the 2-input NOR circuit 42 are both L level, the P-MOS transistor 11 is turned off, and N- The MOS transistor 14 is turned on. As a result, current flows out of the capacitor 15 via the N-MOS transistors 13 and 14, and the output potential Vsawout, that is, the potential of the node S drops (see Vsawout in FIG. 4). That is, a descending straight line of the triangular wave SAWOUT is formed (see Vsawout in FIG. 4).

  Further, the N-MOS transistor 17 is turned on and the N-MOS transistor 18 is turned off by the H level output from the comparator 46. For this reason, the voltage VL is applied to the inverting input terminal of the comparator 46.

  Thereafter, when the output potential Vsawout (the potential of the node S) falls below the voltage VL, that is, when the potential of the non-inverting input terminal of the comparator 46 falls below the potential of the inverting input terminal, the output potential Vcomp3 of the comparator 46 becomes L level. . That is, the node C in FIG. 7 becomes L level (see C in FIG. 4). Thereby, as described above, the capacitor 15 is charged, and the output potential Vsawout, that is, the potential of the node S rises (see Vsawout in FIG. 4). Thereafter, by repeating the same operation, a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output (see Vsawout in FIG. 4).

  The operations other than the triangular wave generation circuit 10 'are the same as the operations during the heavy load operation described in the first embodiment, and thus detailed description thereof is omitted here.

・ In the middle load operation state Next, the operation in the middle load operation state will be described. Note that the operation waveform at this time is the same as the operation waveform described with reference to FIG. 5 in the first embodiment, and will be described here with reference to this.

  The operation of the triangular wave generation circuit 10 'in the medium load operation state is the same as the operation of the triangular wave generation circuit 10 in the heavy load operation state described above. That is, since the comparator 31 continues to output the L level, that is, the node D (output potential Vcomp4) continues to maintain the L level, the comparator 46 compares the voltage VH or the voltage VL with the potential of the capacitor 15. As a result, a triangular wave SAWOUT having a peak voltage of VH and a bottom voltage of VL is output. In addition, since the same operation is performed, the operation waveforms of the output potential Vsawout, the node C (output potential Vcomp3), and the node D (output potential Vcomp4) are also the same as clearly shown in FIG. 4 and FIG. It becomes the waveform.

  The operations other than the triangular wave generation circuit 10 'are the same as the operations in the medium load operation state described in the first embodiment, and thus detailed description thereof is omitted here.

-Light load operation state Next, the operation in the light load operation state will be described with reference to the operation waveform diagram shown in FIG. 8 shows the output potential Vsawout, output potential Vout, node A (output potential Vcomp1), node B (output potential Vcomp2), node C (output potential Vcomp3), and node D (output potential Vcomp4) in the light load operation state. And FIG. 6 is a waveform diagram of current IL.

  In the light load operation state, there is a period in which the output potential Vout is higher than the reference voltage VM (see Vout and VM in FIG. 8). For this reason, the comparator 31 outputs an H level during this period, that is, during the period when the output potential Vout is higher than the reference voltage VM. In other words, a period in which the potential of the node D in FIG. 7 is at an H level occurs (see D in FIG. 8). During this period, since the H level is input to the control terminal of the comparator 46 in the switching circuit 40 (particularly the selection circuit 40a), the comparator 46 is powered down. As a result, the comparator 46 is in the same state as always outputting the L level. In addition, since the H level output from the comparator 31 is input to one input of the 2-input OR circuit 41 in the switching circuit 40 (particularly the selection circuit 40a), the 2-input OR circuit 41 maintains the H level during this period. As a result, the P-MOS transistor 11 continues to be turned off. Further, since the H level output from the comparator 31 is input to one input of the 2-input NOR circuit 42 in the switching circuit 40 (particularly the selection circuit 40a), the 2-input NOR circuit 42 outputs an L level during this period. Thus, the N-MOS transistor 14 continues to be turned off. That is, the charging / discharging current generation circuit 10a is disabled during a period when the output potential Vout is higher than the reference voltage VM, in other words, in a light load operating state.

  Further, during the above period, since the H level output from the comparator 31 is applied to the gate of the N-MOS transistor 44 in the switching circuit 40 (particularly the selection circuit 40a), it is connected to one terminal of the N-MOS transistor 44. The output of the node S, that is, the triangular wave generation circuit 10 ′ becomes the voltage VL applied to the other terminal of the N-MOS transistor 44. That is, during a period when the output potential Vout is higher than the reference voltage VM, in other words, in the light load operation state, the voltage VL is continuously output from the triangular wave generation circuit 10 '.

  The operation other than the triangular wave generation circuit 10 'is as follows. As described above, since the output voltage Vsawout of the triangular wave generation circuit 10 ′ is maintained at the voltage VL corresponding to the bottom voltage of the triangular wave SAWOUT, the output potential Vout of the switching regulator 2 is higher than the output potential Vsawout of the triangular wave generation circuit 10 ′. The state of increasing continues for a while (see Vsawout and Vout in FIG. 8). For this reason, the period during which the output potential Vcomp1 of the comparator 21 is at the H level continues for a while (see A in FIG. 6). During this period, the P-MOS transistor 24 in the switch 20b does not perform a switching operation (see A in FIG. 8). Further, during the same period, that is, a period in which the output potential Vout is larger than the output potential Vsawout and larger than the reference voltage VM (see Vsawout, Vout and VM in FIG. 8), the potential of the node P in FIG. 7 falls below 0 [V]. Therefore, the output potential Vcomp2 of the comparator 22 is at the L level. That is, the node B in FIG. 7 becomes L level (see B in FIG. 8). Therefore, during this period, the N-MOS transistor 27 does not perform a switching operation. However, since a current is supplied to the load 100, the voltage of the capacitor 29 decreases, and the output potential Vout of the switching regulator 2 decreases (see Vout in FIG. 8).

  Thereafter, when the output potential Vout becomes lower than the reference voltage VM, the output potential Vcomp4 of the comparator 31 becomes L level. That is, the node D in FIG. 7 becomes L level (see D in FIG. 8). As a result, as in the above-described heavy load operation state and medium load operation state, the charge / discharge current generation circuit 10a and the comparator 46 begin to function, and the N-MOS transistor 44 is turned off. A triangular wave SAWOUT having a peak potential of VH is output (see Vsawout in FIG. 8).

  As described above, when the triangular wave SAWOUT having the peak potential VH is generated, the output potential Vout is smaller than the peak voltage VH. Therefore, when the next peak of the triangular wave SAWOUT is input to the comparator 21, the output potential Vout is A period smaller than the output potential Vsawout occurs (see Vout and Vsawout in FIG. 8). That is, a period in which the output potential Vcomp1 of the comparator 21 is at the L level occurs. During this period, the node A in FIG. 7 is at the L level (see A in FIG. 8). Further, since the P-MOS transistor 24 in the switch 20b is turned on during the synchronization, the input voltage Vin is applied to the node P, the amount of current IL flowing through the inductor 28 increases (see IL in FIG. 8), and the output potential Vout. Increases (see Vout in FIG. 8). Thereafter, when the output potential Vout becomes higher than the reference voltage VM, the output potential Vcomp4 of the comparator 31 becomes H level, that is, the node D becomes H level (see D in FIG. 8). Since the comparator 46 is disabled and the N-MOS transistor 44 is turned on, the voltage VL appears at the node S.

  Even in this operation, when the output potential Vout of the switching regulator 2 becomes larger than the output potential Vsawout of the triangular wave generation circuit 10 ′, the comparator 21 outputs the H level as in the above-described middle load operation state. Then, the node A in FIG. 7 becomes H level (see A in FIG. 8), and the P-MOS transistor 24 is turned off. At this time, since the inductor 28 tries to keep an inertial current flowing, the potential of the node P becomes smaller than the ground potential (0 [V]). Therefore, the comparator 22 outputs H level, the node B in FIG. 7 becomes H level (see B in FIG. 8), and the N-MOS transistor 27 is turned on. As a result, the node P is grounded, the current IL flowing through the inductor 28 decreases (see IL in FIG. 8), and the potential Vout of the output OUT decreases (see Vout in FIG. 8). However, when the current IL flowing through the inductor 28 becomes 0 [A] or less, that is, when the current flows through the inductor 28 in the reverse direction (direction from the output OUT to the node P), the potential of the node P becomes 0 [V] or more. Therefore, the comparator 22 outputs L level, and the node B in FIG. 7 becomes L level (see B in FIG. 8). As a result, the N-MOS transistor 27 is turned off and the current IL is prevented from flowing through the inductor 28 in the reverse direction. This operation state is continued until the output potential Vout of the switching regulator 2 becomes smaller than the output potential Vsawout of the triangular wave SAWOUT.

  As described above, the state in which the output potential Vout becomes larger than the output potential Vsawout is maintained for a while by switching from the triangular wave generation circuit 10 ′ to output VL which is the bottom voltage of the triangular wave SAWOUT in the light load operation state. Therefore, the switching operation by the switch 20b can be invalidated during this period. As a result, it is possible to realize a switching regulator 2 that can reduce loss due to switching and can realize an efficient switching operation without greatly degrading voltage conversion efficiency even in a light load operation state.

  Further, since the switching regulator 2 according to the present embodiment is configured so that the comparator 46 is powered down in the light load operation state and the charge / discharge current generation circuit 10a does not perform the charge / discharge operation. Power consumption during the state is further reduced, and more efficient switching operation is possible.

  In this embodiment, the case where a negative OR circuit is used has been described as an example. However, the present invention is not limited to this, and can be configured using, for example, an OR circuit. In this case, the N-MOS transistor and the P-MOS transistor are appropriately replaced with the P-MOS transistor and the N-MOS transistor, respectively, or an inverter is appropriately provided at the output stage of the OR circuit. Further, in the present invention, particularly in the scope of the claims, all of these including the logical OR circuit are the logical OR circuit.

  In addition, the above-described Example 1 and Example 2 are only examples for carrying out the present invention, and the present invention is not limited to these, and various modifications of these Examples are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

1 is a schematic diagram showing a configuration of a general switching regulator 900. FIG. It is a figure which shows the operation | movement waveform of each signal in a general switching regulator. It is a circuit diagram which shows the structure of the switching regulator 1 by Example 1 of this invention. It is a figure which shows the operation | movement waveform of each signal at the time of the heavy load operation state of the switching regulator 1 by Example 1 of this invention. It is a figure which shows the operation | movement waveform of each signal at the time of the medium load operation state of the switching regulator 1 by Example 1 of this invention. It is a figure which shows the operation waveform of each signal at the time of the light load operation state of the switching regulator 1 by Example 1 of this invention. It is a circuit diagram which shows the structure of the switching regulator 2 by Example 2 of this invention. It is a figure which shows the operation waveform of each signal at the time of the light load operation state of the switching regulator 2 by Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2, Switching regulator 10, 10 'Triangular wave generation circuit 10a Charge / discharge current generation circuit 11, 12, 24 P-MOS transistor 13, 14, 17, 18, 27, 35, 44 N-MOS transistor 15 Capacitor 16, 21, 22, 31, 46 Comparator 20a Control circuit 20b Switch 23, 26 Buffer 25 2-input NAND circuit 28 Inductor 29 Smoothing capacitor 30, 40 Switching circuit 30a, 40a Selection circuit 32, 43, 45 Inverter 33, 34, 42 2-input NOR circuit 41 2-input OR circuit 100 Load A, B, C, D, P, S Node IN Input terminal OUT Output SAWOUT Triangular wave VB1, VB2 Bias voltage VDD Power supply voltage VH, VL, VHPS voltage VM Reference voltage Vcomp1, Vcomp2, Vcomp3, Vcom p4 Output potential Vsawout, Vout output potential

Claims (12)

A triangular wave generating circuit for generating a triangular wave having a first voltage as a peak and a second voltage as a bottom;
An inductor for smoothing the output potential;
The fixed inductor subsequent potential is higher than the lower third voltage than the first voltage, the triangular wave generation circuit or we switch switching circuit a peak voltage of the outputted the triangular wave to a lower fourth voltage than the third voltage And a switching regulator comprising: A triangular wave generating circuit for generating a triangular wave having a first voltage as a peak and a second voltage as a bottom;
An inductor for smoothing the output potential;
A first comparator for comparing a third voltage lower than the first voltage with a potential at the latter stage of the inductor, and a voltage for forming the rising line of the triangular wave based on a comparison result by the first comparator. A selection circuit that selects from the first voltage and a fourth voltage that is lower than the third voltage , and a switching circuit that switches an output from the triangular wave generation circuit based on a potential at the latter stage of the inductor. A switching regulator characterized by that. The triangular wave generation circuit includes a second comparator that compares the first, second, or fourth voltage with an output of the triangular wave generation circuit;
The selection circuit has a first OR circuit in which an inverted value of the comparison result from the first comparator is input to one input, and a comparison result from the second comparator is input to the other input; A transistor for applying the fourth voltage to one input of the second comparator based on an output of the OR circuit, a comparison result by the third comparator to one input, and the second input to the second comparator. A comparison result from two comparators is input, and an output has a second OR circuit connected to a control terminal of a transistor for applying the first voltage to one input of the second comparator. The switching regulator according to claim 2 . 4. The switching regulator according to claim 2 , wherein the switching circuit switches a peak voltage of the triangular wave output from the triangular wave generating circuit. 5. A switch for controlling the amount of current flowing through the inductor;
A third comparator for comparing the potential of the triangular wave output from the triangular wave generating circuit with the potential of the latter stage of the inductor;
The switching regulator of claim 1 or claim 4, characterized in that it further comprises a control circuit for controlling the switch based on the comparison result of the third comparator. A fourth comparator for comparing the potential before the inductor and the ground potential;
6. The switching regulator according to claim 5, wherein the control circuit controls the switch based on a comparison result of the third and fourth comparators. A triangular wave generating circuit for generating a triangular wave having a first voltage as a peak and a second voltage as a bottom;
An inductor for smoothing the output potential;
A fifth comparator that compares a third voltage lower than the first voltage with the potential at the subsequent stage of the inductor, and a voltage output from the triangular wave generation circuit based on a comparison result by the fifth comparator. And a switching circuit for switching an output from the triangular wave generation circuit based on a potential at the latter stage of the inductor. The triangular wave generation circuit includes a capacitor provided at the output stage of the triangular wave generation circuit and at least two transistors connected in series between a power source and a ground, and charges or discharges charges accumulated in the capacitor. A discharge current generation circuit,
The selection circuit is the one input first or second voltage is applied, the potential of the capacitor applied to the other input, the operation or non-operation based on the fifth comparator comparison result 6 The comparison result from the fifth comparator is input to one input of the comparator, the comparison result from the sixth comparator is input to the other input, and the output is any of the transistors in the charge / discharge current generation circuit A comparison result of the fifth comparator is input to one input, an inverted value of the comparison result of the sixth comparator is input to the other input, and the output is the charge and discharge current and the second logical sum circuit connected to the gate of one of the transistors in the generation circuit, the output of the triangular wave generating circuit said second voltage based on the comparison result by said fifth comparator The switching regulator of claim 7, characterized in that it comprises a application transistors. 9. The switching regulator according to claim 7 , wherein the switching circuit switches the output from the triangular wave generation circuit to a predetermined voltage. A switch for controlling the amount of current flowing through the inductor;
A seventh comparator that compares the potential of the triangular wave output from the triangular wave generating circuit with the potential of the latter stage of the inductor;
A control circuit for controlling the switch based on an output of the seventh comparator;
The switching regulator according to claim 9 , further comprising: An eighth comparator for comparing the potential before the inductor and the ground potential;
The switching regulator according to claim 10, wherein the control circuit controls the switch based on a comparison result of the seventh and eighth comparators. The third voltage is claim wherein the current flowing through the inductor is high and a value lower than the first voltage than the output voltage at 0 [A] and made during the period is not the operating state 1 The switching regulator according to claim 1, claim 2, claim 3, claim 7, and claim 8 .

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