JP4548735B2 - Substrate processing system - Google Patents

Description

The present invention relates to a substrate processing system that performs lithography processing on a substrate such as a semiconductor wafer or an LCD glass substrate.

  In general, in the manufacture of semiconductor devices, a photolithography technique is used to form an ITO (Indium Tin Oxide) thin film or an electrode pattern on a substrate such as a semiconductor wafer or an LCD glass substrate. In this photolithography technique, a photoresist (hereinafter referred to as a resist) is applied to a substrate, a resist film formed thereby is exposed in accordance with a predetermined circuit pattern, and the exposure pattern is developed to form a resist film. In this process, a desired circuit pattern is formed by a series of lithography processes.

  Such processing is generally performed on a resist coating processing unit that applies a resist solution to a substrate for processing, a heating processing unit that heats a substrate after completion of the resist coating processing or a substrate after exposure processing, and development on a substrate after exposure processing. This is performed by a coating / development processing system provided with a plurality of development processing units or the like for supplying a liquid for development processing.

  Incidentally, in recent years, there has been an increasing demand for miniaturization of device patterns. As one of the miniaturization methods, a so-called multi-patterning technique using a lithography process a plurality of times has been studied. In this multi-patterning technology, in addition to a plurality of lithography processes, an etching process for performing microfabrication of a resist is necessary, and a plurality of processing apparatuses for performing a lithography process and a simplified form of transporting a substrate to the etching apparatus Is important.

  2. Description of the Related Art Conventionally, an apparatus that transports a substrate to a plurality of processing apparatuses and etching apparatuses that perform lithography processing and performs lithography processing and etching processing is known (for example, see Patent Document 1). The technique described in Patent Document 1 is configured such that the lithography process can be repeatedly performed.

Further, there is known a substrate transport method (apparatus) that uses a transport line for transporting a substrate to a plurality of processing apparatuses and another transport line for transporting a substrate (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 7-66265 (Claims, FIG. 1) JP 2003-282669 A (Claims, FIG. 4)

  However, in the former technique, that is, in the technique described in Japanese Patent Laid-Open No. 7-66265, since the lithography process can be repeated, a multi-pattern can be formed on the substrate. In the apparatus described in 1), since the processing apparatus and the etching apparatus for the lithography process are formed separately, there is a concern that the number of apparatuses increases and the apparatus becomes large. Further, there is a problem that throughput is lowered and cost is increased with an increase in the substrate transport process.

  On the other hand, according to the latter, that is, according to the technique described in Japanese Patent Application Laid-Open No. 2003-282669, it is possible to selectively use the transport line as necessary, so that a decrease in throughput can be prevented as compared with the former. Since a plurality of processing apparatuses are arranged along the transfer line, it is necessary to transfer a substrate between the transfer line and each processing apparatus, and there is a problem that throughput decreases and costs increase with an increase in the number of processes.

  Furthermore, none of the techniques described in JP-A-7-66265 and JP-A-2003-282669 refers to the multi-patterning technique, and there is a problem with the accuracy of patterning dimensions in miniaturization. It is left.

The present invention has been made in view of the above circumstances, and is a substrate capable of preventing a reduction in the throughput of the lithography process accompanying the miniaturization of the device, reducing the cost, and improving the patterning dimensional accuracy in the miniaturization. An object is to provide a processing system .

In order to solve the above-described problems, the invention described in claim 1 includes: a substrate loading / unloading unit; a coating / developing unit having a resist coating device, a developing device, and a heating device; and the coating / developing unit. An etching process is performed between the coating / development processing unit and the exposure unit, and an interface unit that delivers the substrate to be processed between the exposure unit and the exposure apparatus, and a pattern formed on the substrate to be processed after the development process as a mask. An etching processing unit having an etching device, a measuring unit having a measuring device for measuring a line width of a pattern formed on the substrate to be processed, and information measured by the measuring device are stored, and the stored information is stored in the stored information. Based on the exposure correction in the exposure process of the second and subsequent lithography processes, the temperature correction in the heat treatment after exposure and / or the etch in the etching process Will be provided with control means for correcting, and the etching processing unit positioned adjacent to the coating and developing processing unit, formed by the measuring portion disposed adjacent to the loading and unloading unit, it It is characterized by.

According to a second aspect of the present invention, there is provided a substrate carry-in / carry-out unit, a coating / development processing unit having a resist coating device, a developing device and a heating device, and the coating / development processing unit and the exposure device. An interface unit that manages delivery of the substrate to be processed between the coating / development processing unit and the exposure apparatus; and an etching processing unit that has an etching apparatus that performs an etching process using a pattern formed on the substrate to be processed after the development process as a mask; A measuring unit having a measuring device for measuring the line width of the pattern formed on the substrate to be processed; and information measured by the measuring device, and the second and subsequent lithography based on the stored information Control means for performing exposure correction in the exposure process of the process, temperature correction in the heating process after exposure, and / or etching correction in the etching process; Bei to be in, between the coating and developing unit the loading and unloading unit, the measuring unit and the etching unit arranged in parallel and arranged to etching treatment unit in the coating and developing processing unit side, measured parts and comprising disposed in loading and unloading unit side, characterized in that.

Further, the invention described in claim 3 is the substrate processing system according to claim 1 or 2, wherein the pattern formed by the second lithography process or later by the control means is a pattern formed by the previous lithography process. It is characterized by forming between .

4. The substrate processing system according to claim 1, wherein the measurement apparatus irradiates the pattern with light, detects a light intensity distribution of the reflected light, and a plurality of virtual lines having different line widths. By collating the calculated light intensity distribution of the reflected light with respect to the pattern and the light intensity distribution of the detected actual pattern, and setting the line width of the virtual pattern to which the light intensity distribution matches as the line width of the actual pattern It is preferable to measure the line width (claim 4) .

5. The substrate processing system according to claim 1, wherein the etching apparatus is constituted by a dry etching apparatus and a shield capable of blocking electromagnetic waves is provided on a casing constituting the etching processing unit. (Claim 5 ).

According to the first and second aspects of the present invention, a lithography process for forming a predetermined pattern by performing a lithography process such as a resist coating process, an exposure process, a post-exposure heating process, and a developing process on the substrate to be processed, and the developing process An etching process using a later pattern as a mask can be performed a plurality of times to form a multi-pattern on the substrate to be processed. Moreover, based on the measurement information of the line width of the pattern, exposure correction in the exposure process in the second and subsequent lithography processes, temperature correction in the heating process after exposure, and / or etching correction in the etching process can be performed.

According to the first aspect of the present invention, the etching process unit is disposed adjacent to the coating / development process unit, and the measurement unit is disposed adjacent to the carry-in / carry-out unit. In addition to being integrated into one system, the lithography process and the etching process can be performed continuously. Further, by disposing the measurement unit adjacent to the carry-in / carry-out unit, it is possible to carry in the measurement in a short time by carrying the substrate to be processed that performs only the measurement from the carry-in / carry-out unit into the measurement unit .

According to the third aspect of the present invention, the pattern formed by the second and subsequent lithography processes is formed between the patterns formed by the previous lithography process, which is impossible in one lithography process. The pattern can be miniaturized.

According to the invention of claim 2 , the measurement unit and the etching processing unit are arranged between the carry-in / carry-out unit and the coating / development processing unit, and the measurement unit and the etching processing unit are arranged in parallel, In addition, by arranging the etching processing unit on the coating / developing processing unit side and the measurement unit on the loading / unloading unit side, the lithography process and the etching process can be integrated into one system, and the lithography process The etching process can be performed continuously. Further, by disposing the measurement unit on the carry-in / carry-out unit side, it is possible to carry in the measurement in a short time by carrying the substrate to be processed which performs only the measurement from the carry-in / carry-out unit into the measurement unit.

According to the fifth aspect of the invention, the influence of the electromagnetic wave can be suppressed by applying the shield capable of blocking the electromagnetic wave to the casing constituting the etching processing unit having the dry etching apparatus.

  As described above, since the substrate processing method and the substrate processing system of the present invention are configured as described above, the following effects can be obtained.

(1) According to the first, second, and fourth aspects of the invention, the lithography process and the etching process can be performed a plurality of times to form a multi-pattern on the substrate to be processed, and the line width of the pattern can be measured. Based on the information, exposure correction in the exposure process of the second and subsequent lithography processes, temperature correction in the post-exposure heating process, and / or etching correction in the etching process can be performed, which increases for device miniaturization. The lithography process and the etching process can be integrated to prevent a reduction in throughput and reduce the cost, and to improve the patterning dimension accuracy in miniaturization.

(2) According to the invention described in claim 3 , since the pattern can be miniaturized which is impossible in one lithography process, the pattern can be further miniaturized.

(3) According to the first and second aspects of the invention, the lithography process and the etching process can be integrated into one system, and the lithography process and the etching process can be performed continuously, thereby improving the throughput. In addition, the cost can be reduced. In addition, by placing the measurement unit adjacent to the carry-in / carry-out unit, or placing the measurement unit on the carry-in / carry-out unit side, the substrate to be processed that only performs measurement is carried into the measurement unit from the carry-in / carry-out unit. It can be measured in a short time.

(4) According to the invention described in claim 5 , since the shield constituting the etching processing unit having the dry etching apparatus is provided with a shield capable of blocking the electromagnetic wave, the influence of the electromagnetic wave can be suppressed. In addition to the above (1) to (3), the effects of electromagnetic waves in the apparatus can be further prevented, and the stability and safety of the apparatus can be maintained.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the best embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, a case will be described in which the substrate processing system according to the present invention is applied to a semiconductor wafer resist coating / development processing system.

  1 is a schematic plan view showing an example of the resist coating / developing system, FIG. 2 is a schematic perspective view, FIG. 3 is a schematic front view, and FIG. 4 is a schematic rear view.

  The resist coating / development processing system includes a carrier block S1 which is a loading / unloading unit for loading / unloading, for example, 25 carriers 20 in which a semiconductor wafer W (hereinafter referred to as a wafer W) as a substrate to be processed is hermetically contained. A coating / development processing block S2 (hereinafter referred to as processing block S2), which is a coating / development processing unit configured by vertically arranging a plurality of unit blocks B1 to B4, for example, and an interface block as an interface unit S3 and an exposure apparatus S4, an etching block S5 which is an etching processing unit disposed between the carrier block S1 and the processing block S2 and disposed on the processing block S2 side, and on the carrier block S1 side. And a measurement block S6 which is a measurement unit to be arranged.

  The carrier block S <b> 1 includes a mounting table 21 on which a plurality of (for example, four) carriers 20 can be mounted, an opening / closing unit 22 provided on a wall surface in front of the mounting table 21, and an opening / closing unit 22. And a transfer arm B for taking out the wafer W from the carrier 20. The transfer arm B is movable in the horizontal X, Y and vertical Z directions and rotates about the vertical axis so as to transfer the wafer W to and from the transfer stage TRS4 provided in the measurement block S6. It is configured to be freely movable.

  A processing block S2 that is connected to the back side of the carrier block S1 via a measurement block S6 and an etching block S5 and is surrounded by a housing 70 is connected. In this example, the processing block S2 includes, from the lower side, a first unit block (CHM) B1 for storing chemical liquid containers such as a resist solution and a developing solution, and a second unit block (DEV layer for performing a developing process). ) B2, the coating film forming unit block for performing the two-stage resist solution coating process and the third and fourth unit blocks (COT layers) B3 and B4 which are the cleaning unit blocks for performing the cleaning process. Yes. In this case, one of the unit blocks for forming the coating film, for example, the third unit block (COT layer) B3 is used as a unit block (BCT) for performing an antireflection film forming process formed on the lower layer side of the resist film. Layer). Further, an antireflection film forming unit block for performing an antireflection film forming process formed on the upper layer side of the resist film may be provided above the fourth unit block (COT layer) B4. .

  The first to fourth unit blocks B1 to B4 are disposed on the front surface side, are disposed on the rear surface side with a liquid processing unit for applying a chemical solution to the wafer W, and are performed by the liquid processing unit. Between various processing units such as various heating units for performing pre-processing and post-processing of the processing to be performed, and the above-described liquid processing units disposed on the front side and processing units such as the heating unit disposed on the back side. Specifically, it is a dedicated substrate transfer means for transferring the wafer W between the processing unit such as the heating unit and the liquid processing unit in which the development processing unit is arranged in the lower stage and the resist processing unit is arranged in the upper stage. Some main arms A1 and A2 are provided.

  In this example, the unit blocks B1 to B4 are formed in the same arrangement layout of the liquid processing unit, the processing unit such as a heating unit, and the conveying means between the unit blocks B1 to B4. Here, the same arrangement layout means that the center of the wafer W in each processing unit, that is, the center of the spin chuck that is a holding means of the wafer W in the liquid processing unit, the heating plate and the cooling plate in the heating unit, and so on. It means that the center is the same.

  As shown in FIG. 1, the DEV layer B2 has an etching block S5 and an interface block S3 on the carrier block S1 side in the length direction of the DEV layer B2 (Y direction in the figure) at the center of the DEV layer B2. A transfer area R1 (horizontal movement area of the main arm A1) for the wafer W for connecting the two is formed. Further, although not shown, the COT layers B3 and B4 are similar to the DEV layer B2 in the center of the COT layers B3 and B4 in the length direction (Y direction in the figure) of the COT layers B3 and B4. A wafer W transfer area R2 (horizontal movement area of the main arm A2) for connecting S1 and the interface block S3 is formed.

  On both sides of the transport region R1 (R2) viewed from the carrier block S1 side, a plurality of units for performing development processing as the liquid processing unit on the right side from the near side (carrier block S1 side) to the back side. For example, a one-stage development unit 31 including three development processing units, a two-stage coating unit 32, and a cleaning unit (not shown) are provided. Each unit block is provided with, for example, four shelf units U1, U2, U3, U4 in which heating units are multi-staged in order from the front side toward the back side, and development is performed in the DEV layer B2. Various units for performing pre-processing and post-processing of processing performed in the unit 31 are stacked in a plurality of stages, for example, three stages. In this way, the developing unit 31 and the shelf units U1 to U4 are partitioned by the transport region R1, and the cleaning air is ejected and exhausted to the transport region R1, thereby suppressing the floating of particles in the region. It has become.

  Among the various units for performing the above pre-processing and post-processing, for example, as shown in FIG. 4, a heating unit (PEB) called a post-exposure baking unit that heat-processes the wafer W after exposure. In addition, a heating unit (POST) or the like called a post-baking unit or the like for performing heat treatment to remove moisture of the wafer W after development processing is included. Each processing unit such as the heating unit (PEB, POST) is accommodated in the processing container 40, and the shelf units U1 to U4 are configured by stacking the processing containers 40 in three stages. A wafer loading / unloading port 41 is formed on the surface facing the transfer region R1 of 40. The heating unit (PEB, POST) is formed so that the heating temperature and the heating time can be adjusted.

  The main arm A1 is provided in the transfer region R1. The main arm A1 transfers wafers to and from all modules (places where the wafers W are placed) in the DEV layer B2, for example, the processing units of the shelf units U1 to U4 and the units of the developing unit 31. For this reason, it is configured to be movable in the horizontal X and Y directions and the vertical Z direction and to be rotatable about the vertical axis.

  The main arm A1 (A2) is configured in the same manner, and the main arm A1 will be described as a representative example. For example, as shown in FIG. The arm main body 50 which has the curved arm piece 51 is provided, and these curved arm pieces 51 are comprised so that advancement / retraction is mutually independent along the base which is not shown in figure. The base is configured to be rotatable about a vertical axis, movable in the Y direction, and movable up and down. Thus, the bending arm piece 51 is configured to be movable back and forth in the X direction, movable in the Y direction, freely movable up and down, and rotatable about the vertical axis, and is arranged on each unit of the shelf units U1 to U4 and on the carrier block S1 side. The wafer W can be transferred between the transfer stage TRS1 of the shelf unit U5 and the liquid processing unit. The driving of the main arm A1 is controlled by a controller (not shown) based on a command from the control unit 60 serving as a control unit. Further, in order to prevent heat storage in the heating unit of the main arm A1 (A2), the order of receiving the wafers W can be arbitrarily controlled by a program.

  Further, the unit blocks B3 and B4 for forming the coating film are configured in the same manner, and are configured in the same manner as the unit block B2 for development processing described above. Specifically, a coating unit 32 for performing a resist solution coating process on the wafer W is provided as a liquid processing unit, and the shelf units U1 to U4 of the COT layers B3 and B4 are provided with wafers after the resist solution coating. A heating unit (CLHP) for heat-treating W and a hydrophobizing unit (ADH) for improving the adhesion between the resist solution and the wafer W are provided and are configured in the same manner as the DEV layer B2. That is, the coating unit, the heating unit (CLHP), and the hydrophobizing unit (ADH) are configured to be partitioned by the transport region R2 of the main arm A2 (horizontal movement region of the main arm A2). In the COT layers B3 and B4, the main arm A2 delivers the wafer W to the delivery stage TRS1 of the shelf unit U5, the coating unit 32, and the processing units of the shelf units U1 to U4. It has come to be. The hydrophobic treatment unit (ADH) performs gas treatment in an HMDS atmosphere, but may be provided in any one of the unit blocks B3 and B4 for forming a coating film.

  The etching block S5 arranged adjacent to the processing block S2 includes a housing 70a connected to the housing 70 of the processing block S2. The dry etching is stacked in multiple stages, for example, four stages in the housing 70a. An etching unit 80, which is an apparatus, is disposed, and a transfer arm C for transferring the wafer W into and out of the etching unit 80 and a delivery stage TRS2 are disposed. In this case, the transfer arm C transfers the wafer W between the transfer stage TRS1 of the shelf unit U5 of the processing block S2 and the transfer stage TRS2 in the etching block S5. In addition, it is movable in the vertical direction and rotatable. The etching unit 80 is formed so that the etching rate can be controlled by adjusting etching process conditions such as applied high frequency, high frequency voltage and gas pressure in a vacuum atmosphere, for example.

  In the etching block S5 configured as described above, a shield for shielding electromagnetic waves is applied to the housing 70a so that electromagnetic waves generated from the etching unit 80 do not affect the outside during the dry etching process. Any shield may be used as long as it is a shielding plate made of conductive metal or synthetic resin. In this embodiment, for example, a shielding plate 81 made of aluminum alloy is used to form the casing 70a. ing.

  As described above, the casing 70a of the etching block S5 is configured by the electromagnetic wave shielding plate 81, whereby electromagnetic waves generated from the etching unit 80 can be blocked from leaking to the outside during the dry etching process.

  The measurement block S6 disposed between the carrier block S1 and the etching block S5 includes a housing 70b connected to the housing 70a of the carrier block S1 and the etching block S5. A line width measuring device 90 which is an apparatus, a transfer arm D for carrying in / out a wafer W to / from the line width measuring device 90, and a delivery stage TRS3 are arranged. In this case, the transfer arm D transfers the wafer W between the transfer stage TRS3 in the measurement block S6, the transfer stage TRS2 of the etching block S5, and the line width measuring device 90. These are formed so as to be movable in the X, Y and vertical directions and to be rotatable.

  As shown in FIG. 5, the line width measuring apparatus 90 includes a mounting table 91 on which the wafer W is mounted horizontally. The mounting table 91 configures, for example, an XY stage, and is formed to be movable in the horizontal X direction and the Y direction. Above the mounting table 91, a light irradiation unit 92 that irradiates light from the oblique direction to the wafer W mounted on the mounting table 91, and light that is irradiated from the light irradiation unit 92 and reflected by the wafer W is detected. A light receiving portion 93 is disposed. Information on the light detected by the light receiving unit 93 can be output to the detection unit 94, and the detection unit 94 reflects reflected light from a predetermined pattern formed on the wafer W based on the acquired light information. The light intensity distribution can be measured. Note that the line width measuring apparatus 90 can detect impurities, particles, and the like attached on the wafer W in addition to measuring the line width of the pattern.

  Information from the detection unit 94 is transmitted to the control unit 60, and for example, information processing for measuring the line width is performed. The control unit 60 includes, for example, a calculation unit 61, a storage unit 62, and an analysis unit 63. The calculation unit 61 calculates each light intensity distribution in the calculation of reflected light reflected from a plurality of virtual patterns having different line widths based on known information such as the optical constant of the resist film, the pattern shape and structure of the resist film, for example. It can be calculated. The storage unit 62 can store each calculation light intensity distribution for the virtual pattern calculated by the calculation unit 61 and create a library thereof.

  The light intensity distribution for the actual pattern on the wafer W measured by the detection unit 94 can be output to the analysis unit 63. The analysis unit 63 collates the light intensity distribution of the actual pattern output from the detection unit 94 with the light intensity distribution of the virtual pattern stored in the library of the storage unit 62, and the virtual pattern with which the light intensity distribution matches. The line width of the virtual pattern can be estimated as the line width of the actual pattern, and the line width can be measured.

  Information on the line width measured as described above is transmitted to the exposure apparatus S4, the heating unit (PEB), and the etching unit 80. In this case, the exposure apparatus S4 has an exposure control unit (not shown) and performs exposure according to exposure conditions such as an exposure position, an exposure amount, and an exposure focus on the optical system wafer W preset by the exposure control unit. The process is configured to be controllable.

  Therefore, by transmitting a control signal from the control unit 60 to the exposure apparatus S4, the heating unit (PEB), and the etching unit 80, in the exposure process of the second and subsequent lithography processes based on the measurement information of the line width of the pattern. Exposure correction such as exposure position, exposure amount and exposure focus, temperature correction such as heating temperature and heating time in the heating processing of the heating unit (PEB) after exposure, high frequency, high frequency voltage and gas pressure applied in the etching process, etc. Etching correction such as an etching rate can be performed by adjusting the etching process conditions.

  Further, as shown in FIG. 1, a shelf unit U6 is provided at a position where the main arm A1 can access the adjacent area of the processing block S2 and the interface block S3. The shelf unit U6 includes a delivery stage TRS4 and a delivery stage (not shown) having a cooling function for delivering the wafer W so as to deliver the wafer W to and from the main arm A1 of the DEV layer B2. ing. In addition, in a region adjacent to the processing block S2 and the interface block S3, as shown in FIGS. 1 and 4, two stages of peripheral edge exposure devices (WEE) are arranged.

  On the other hand, an exposure apparatus S4 is connected to the back side of the shelf unit U6 in the processing block S2 via an interface block S3. The interface block S3 includes an interface arm E for transferring the wafer W to each part of the shelf unit U6 of the DEV layer B2 of the processing block S2 and the exposure apparatus S4. The interface arm E serves as a transfer means for the wafer W interposed between the processing block S2 and the exposure apparatus S4. In this example, the wafer W is transferred to the transfer stage TRS4 and the like of the DEV layer B2. It is configured to be movable in the horizontal X and Y directions and the vertical Z direction and to be rotatable about the vertical axis.

  Next, the processing of the wafer W in the coating / developing processing system configured as described above will be described with reference to the flowchart shown in FIG. Here, the process after the wafer W previously coated with the hard mask is taken out from the carrier 20 and subjected to the hydrophobic treatment by the hydrophobic treatment unit (ADH) will be described.

  The wafer W temporarily stored in the shelf unit U5 after being subjected to the hydrophobic treatment is taken out from the shelf unit U5 by the main arm A2, transferred to the coating unit 32, and a resist film is formed in the coating unit 32 (S−). 1). The wafer W on which the resist film is formed is transferred to the heating unit (CLHP) by the main arm A2, and pre-baked (PAB) for evaporating the solvent from the resist film is performed (S-2). Thereafter, the wafer W is transferred to a peripheral exposure apparatus (WEE), subjected to a peripheral exposure process (S-3), and then subjected to a heating process (S-4). Next, the wafer W is transferred to the exposure apparatus S4 by the interface arm E, where a predetermined exposure process is performed (S-5).

  The wafer W after the exposure processing is transferred to the delivery stage TRS4 of the shelf unit U6 in order to deliver the wafer W to the DEV layer B2 by the interface arm E. The wafer W on the stage TRS4 is transferred to the main part of the DEV layer B2. After being received by the arm A1 and first subjected to post-exposure baking (S-6) in the heating unit (PEB) in the DEV layer B2, the main arm A1 applies a cooling plate (not shown) to the shelf unit U6. It is conveyed and adjusted to a predetermined temperature. Next, the wafer W is taken out from the shelf unit U6 by the main arm A1 and transferred to the developing unit 31, where a developing solution is applied (S-7). Thereafter, the main arm A1 transports the heating unit (POST) to perform a predetermined development process.

  The developed wafer W is transferred to the delivery stage TRS1 of the shelf unit U5. The wafer W on the stage TRS1 is received by the transfer arm C of the etching block S5 and transferred to the etching unit 80 of the etching block S5. Then, an etching process using the pattern after the development process as a mask is performed (S-8).

  The wafer W after the etching process is taken out from the etching unit 80 by the transfer arm C and transferred to the delivery stage TRS2 of the etching block S5. The wafer W on the stage TRS2 is transferred to the transfer arm of the measurement block S6. D is received and transferred to the line width measuring device 90 of the measurement block S6, and the line width of the pattern formed on the wafer W is measured (S-9). The measurement information of the line width is transmitted to the control unit 60 and stored in the control unit 60.

  The wafer W on which the line width has been measured is taken out from the line width measuring device 90 by the transfer arm D, and then transferred to the transfer stage TRS2, the transfer arm C, and the transfer stage TRS1 of the processing block S2 in the etching block S5. The wafer W on the stage TRS1 is received by the main arm A2 of the processing block S2, transferred to the cleaning unit (SCR), and subjected to cleaning processing (S-10). Thereby, a series of lithography processes (processes) and etching processes (processes) are completed. In this state, on the surface of the wafer W, as shown in FIG. 7A, a pattern having a pitch P up to a critical dimension within a range in which the resist PR is not broken by one lithography process is formed. In FIG. 7, symbol CD is a line width, and HM is a hard mask.

  The wafer W that has been subjected to the lithography process (process) and the etching process (process) is subjected to the same lithography process (process) and etching process (process) as described above, so that the pattern formed on the wafer W can be miniaturized. I can plan. That is, the wafer W subjected to the first lithography process (process) and the etching process (process) is subjected to the resist coating process (COT) (S-11) → pre-bake (PAB) (S-12) as described above. → Peripheral exposure process (WEE) (S-13) → Heat process (BAKE) (S-14) → Exposure process (EXP) (S-15) → Post-exposure bake (PEB) (S-16) → Development process ( DEV) (S-17) → etching process (ET) (S-18) is performed, so that a pattern is formed between the pitches P of the pattern formed by one lithography process as shown in FIG. 7B. A pattern with a pitch 1 / P can be formed by additional formation.

  Further, in the second lithography process (processing) and the etching process (processing), measurement information measured by the line width measuring device 90 after the first etching process is sent from the control unit 60 to the exposure apparatus S4, heating unit (PEB). And the etching unit 80, based on the measurement information of the line width of the pattern, the exposure correction in the exposure process of the second and subsequent lithography processes, the exposure correction such as the exposure amount and the exposure focus, the heating unit after exposure ( Etching correction such as an etching rate by adjusting etching process conditions such as a high frequency, a high frequency voltage, and a gas pressure applied in the etching process can be performed. These exposure correction, temperature correction, and etching correction may all be performed, or at least one of them may be performed. Thereby, the pattern formed on the wafer W can be miniaturized.

  The wafer W that has been subjected to the second lithography process (process) and etching process (process) is transferred to the line width measuring device 90 of the measurement block S6, and the line width of the pattern is measured and attached to the surface of the wafer W. Impurities and particles are measured (CDM / MCRO) (S-19). This measurement information is also transmitted to the control unit 60, so that the shape of the line width formed on the wafer W, the pitch 1 / P, the state of impurities, particles, etc. adhering to the wafer W can be confirmed.

  The wafer W that has been subjected to the second lithography process (process) and etching process (process) as described above is returned to the original carrier 20 mounted on the carrier block S1 by the transfer arm B and processed. Ends.

  In the above embodiment, the case where the lithography process (process) and the etching process (process) are performed twice has been described. However, the lithography process (process) and the etching process (process) may be performed three times or more. Of course, a single lithography process (processing) and etching process (processing) can also be performed.

  Moreover, although the case where the antireflection film is not formed has been described in the above embodiment, the substrate processing method (system) according to the present invention is similarly applied to the case where the antireflection film is formed below or above the resist film. Can be applied.

1 is a schematic plan view showing an example of a resist coating / development processing system to which a substrate processing system according to the present invention is applied. It is a schematic perspective view of the said resist application | coating / development processing system. It is a schematic front view of the said resist application | coating / development processing system. It is a schematic rear view of the resist coating / developing system. It is a schematic side view which shows the measuring apparatus in this invention. It is a flowchart which shows the process sequence of the board | substrate by the substrate processing method which concerns on this invention. They are an expanded sectional view (a) which shows pattern formation of the 1st time, and an expanded sectional view (b) which shows pattern formation of the 2nd time.

W Semiconductor wafer (substrate to be processed)
B2 Second unit block (DEV layer)
B3 Third unit block (COT layer)
B4 Fourth unit block (COT layer)
S1 Carrier block S2 Processing block S3 Interface block S4 Exposure apparatus S5 Etching block S6 Measurement block 31 Development unit (processing unit)
32 Coating unit (processing unit)
60 Control part (control means)
80 Etching unit (dry etching equipment)
81 Electromagnetic wave shielding plate 90 Line width measuring device

Claims (5)

A substrate loading / unloading section;
A coating / development processing unit having a resist coating device, a developing device, and a heating device;
An interface unit disposed between the coating / development processing unit and the exposure apparatus, and managing delivery of a substrate to be processed between the coating / development processing unit and the exposure apparatus;
An etching processing unit having an etching apparatus for performing an etching process using a pattern formed on the substrate to be processed after the development process as a mask;
A measuring unit having a measuring device for measuring the line width of the pattern formed on the substrate to be processed;
Information measured by the measuring apparatus is stored, and based on the stored information, exposure correction in the exposure process in the second and subsequent lithography processes, temperature correction in the heating process after exposure, and / or etching correction in the etching process anda control means for become by,
A substrate processing system comprising: the etching processing unit disposed adjacent to the coating / developing processing unit; and the measurement unit disposed adjacent to the loading / unloading unit . A substrate loading / unloading section;
A coating / development processing unit having a resist coating device, a developing device, and a heating device;
An interface unit arranged between the coating / development processing unit and the exposure apparatus, and managing delivery of the substrate to be processed between the coating / development processing unit and the exposure apparatus;
An etching processing unit having an etching apparatus for performing an etching process using a pattern formed on the substrate to be processed after the development process as a mask;
A measuring unit having a measuring device for measuring the line width of the pattern formed on the substrate to be processed;
Information measured by the measuring apparatus is stored, and based on the stored information, exposure correction in the exposure process in the second and subsequent lithography processes, temperature correction in the heating process after exposure, and / or etching correction in the etching process And a control means for performing
Between the carry-in / carry-out unit and the coating / development processing unit, the measurement unit and the etching processing unit are arranged in parallel, and the etching processing unit is arranged on the coating / development processing unit side, and the measurement unit is carried in / out. A substrate processing system, characterized in that it is arranged on the part side. The substrate processing system according to claim 1 or 2,
A substrate processing system, wherein the control means forms a pattern formed by the second and subsequent lithography processes between patterns formed by the previous lithography process. The substrate processing system according to claim 1,
The measuring device irradiates the pattern with light, detects the light intensity distribution of the reflected light, calculates the reflected light intensity distribution for a plurality of virtual patterns having different line widths, and the detected actual light intensity. A substrate processing system characterized in that the line width is measured by collating the light intensity distribution of the pattern and setting the line width of the virtual pattern to which the light intensity distribution is matched as the line width of the actual pattern. The substrate processing system according to any one of claims 1 to 4 ,
A substrate processing system, wherein the etching apparatus is configured by a dry etching apparatus, and a shield capable of blocking electromagnetic waves is provided on a casing forming an etching processing unit.

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