JP4549210B2 - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Description

  The present invention provides an effective laminate portion in which thinned dielectric layers and internal electrode layers are alternately laminated, and an external cover layer that is provided on the upper and lower surfaces of the effective laminate portion and protects the effective laminate portion. And a method for manufacturing the same.

  A multilayer ceramic capacitor is formed by laminating a plurality of ceramic green sheets for dielectric layers having internal electrode patterns formed on the surface, laminating ceramic green sheets for external cover layers so as to sandwich them, and pressing them. It is manufactured by cutting and sintering the laminate in the thickness direction.

  In recent years, with the miniaturization and enhancement of functions of electronic components, multilayer ceramic capacitors have also been reduced in size and capacity, and the thickness of the dielectric layer (distance between internal electrodes) has been reduced to 10 μm or less. The number of stacked layers and internal electrodes has been increased to 100 or more and manufactured.

  With such multi-layering, the ratio of the thicknesses of the internal electrodes is increased (steps are increased), and there are places where the pressing force is insufficient in the pressing process.

In order to solve this problem, by forming the outer cover layer by reducing the degree of polymerization of the binder contained in the ceramic green sheet for the outer cover layer, the deformation of the outer cover layer is increased, and the pressure is insufficient. A technique of eliminating the location is known (see Patent Document 1).
Japanese Patent Laid-Open No. 2003-203824

  However, due to the further thinning of the dielectric layer, the average grain size of the main crystal phase constituting the dielectric layer is also about 1 μm. In order to adjust the sintering temperature to this dielectric layer, an outer cover layer is formed. If the dielectric powder used in the process is to be atomized, the number of contacts between the particles increases, and the frictional force between the particles increases. Then, even if the degree of polymerization of the binder is reduced as described above, the deformation of the green sheet for the outer cover layer is reduced, the step due to the thickness of the internal electrode cannot be reduced, and between the outer cover layer and the effective laminate part, or In the effective laminate portion, delamination is generated during firing or cracks are generated during the solder thermal shock test between the dielectric layer and the internal electrode.

  Even if the dielectric powder used for thin layer / high lamination is made fine, the present invention can prevent cracks or delamination between the outer cover layer and the effective laminate part or between the dielectric layer and the internal electrode in the effective laminate part. An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing lamination and a method for manufacturing the same.

  The present invention comprises an effective laminate portion in which dielectric layers and internal electrode layers are alternately laminated in the vertical direction, and an external cover layer composed of dielectric layers superimposed on the upper and lower surfaces of the effective laminate portion. In the multilayer ceramic capacitor, the occupied area distribution for each particle size of the main crystal particles in the outer cover layer is substantially equal to the occupied area distribution for each particle size of the main crystal particles in the dielectric layer. A monolithic ceramic capacitor having a first occupied area distribution of a diameter region and a second occupied area distribution of a particle size region larger than the first occupied area distribution.

  As a result, the effect of reducing the contact area between the particles is obtained by including the main crystal particles having a large particle size before firing, and the presence of the large area particles after firing increases the porcelain strength. The effect of increasing and suppressing the occurrence of cracks in the element can be obtained.

Here, when the particle diameter of the main crystal particle when showing the peak in the first occupied area distribution is D ₁ and the particle diameter of the main crystal particle when showing the peak in the second occupied area distribution is D ₂ , D _It is preferable that ₁ is 0.1 to 0.5 μm and D ₂ / D ₁ is 1.5 to 4.0. This is because the occurrence of delamination is extremely eliminated.

It is preferable that the relationship of 0.05 ≦ t ₂ / t ₁ ≦ 0.20 is satisfied, where the thickness of the effective laminate portion is t ₁ and the thickness of the outer cover layer is t _2, and the dielectric layer The thickness is preferably 7 μm or less and the number of laminated layers is 100 or more. This is because the present invention exerts its effect at such a thickness and the number of laminated layers.

The present invention also includes a step of forming a laminated body part by interposing an internal electrode pattern between green sheets for a dielectric layer containing dielectric powder to form a laminated part, and a dielectric on the upper and lower surfaces of the laminated part. A method of manufacturing a multilayer ceramic capacitor including a step of superimposing a green sheet for an outer cover layer containing body powder, wherein the occupation area distribution for each particle size of the dielectric powder in the green sheet for the outer cover layer is: A first occupied area distribution of a particle size region substantially equal to an occupied area distribution of each particle size of the dielectric powder in the dielectric layer green sheet, and a particle size region larger than the first occupied area distribution. The dielectric powder has a second occupied area distribution, the particle size of the dielectric powder when showing the peak in the first occupied area distribution is DG ₁ , and the dielectric when showing the peak in the second occupied area distribution the particle size of the powder and DG ₂ That when a DG ₁ is 0.1 to 0.5 [mu] _m, a manufacturing method of a multilayer ceramic capacitor DG 2 / DG ₁ is characterized in that 1.5 to 4.0. By this method, the above multilayer ceramic capacitor can be manufactured.

Here, the weight W ₂ of the dielectric powder occupying the second occupied area distribution is preferably 0.75 to 1.5 times the weight W ₁ of the dielectric powder occupying the first occupied area distribution. This is because within this range, solder heat shock cracks hardly occur.

  Occupied area distribution refers to the occupancy occupied by the main crystal particles of the particle size on the horizontal axis for the main crystal particles included in a predetermined range when the outer cover layer and the dielectric layer are cut in a certain section. The distribution state when graphed with the area as the vertical axis, the particle size of the main crystal particles included in the second occupied area distribution is larger than the particle size of the main crystal particles included in the first occupied area distribution ing. The first occupied area distribution and the second occupied area distribution are mountain-shaped, and each has a peak. The first occupied area distribution and the second occupied area distribution have a valley-like boundary between the first occupied area distribution mountain and the second occupied area distribution mountain. What is necessary is just to distinguish with a boundary. In addition, the boundary is the occupied area between the particle size of the main crystal particle when showing the peak in the first occupied area distribution and the particle size of the main crystal particle when showing the peak in the second occupied area distribution. The area occupancy of the grain size of the main crystal grains at this boundary is preferably 5% or less, and most preferably close to 0%.

  According to the multilayer ceramic capacitor of the present invention, it is possible to maintain the deformability of the outer cover layer even if the dielectric powder of the effective dielectric is atomized, and to reduce the stacking step due to the thickness of the internal electrode. Can be suppressed.

An embodiment of the present invention will be described.
As shown in FIG. 1, the multilayer ceramic capacitor of the present invention is configured by alternately laminating dielectric layers 11 and internal electrode layers 12, and contributes to capacity generation. 1 is composed of an outer cover layer 2 made of a dielectric layer that does not contribute to capacity generation, and an external electrode 3 formed on the end portions (side surfaces) of these effective laminate portion 1 and outer cover layer 2. Has been.

The effective laminate portion 1 includes a dielectric layer 11 and an internal electrode layer 12. The main crystal phase of the dielectric layer 11 is mainly composed of BaTiO ₃ , and BaCaTiO ₃ , BaTiZrO ₃ , BaCaTiZrO _{3, and the} like may be contained therein or substituted for them. The secondary phase (grain boundaries and triple point grain boundaries) is mainly composed of SiO ₂ , and additionally contains B, Ca, Ba, rare earth, and the like. Here, the present invention can be preferably applied to the dielectric layer 11 having a thickness of 7 μm or less and a lamination number of 100 layers or more, but is particularly preferably 5 μm or less, more preferably 3 μm or less. It is desirable that there are more than 200 layers, more preferably more than 200 layers. This is because the present invention exhibits its effect when the multilayer ceramic capacitor is thinned and highly laminated to increase the capacity. The average grain size of the main crystal phase in the dielectric layer is preferably 0.5 μm or less, particularly preferably 0.3 μm or less, and the average grain size of the particles constituting the main crystal phase in the dielectric layer is reduced. In this case, it is possible to make a thin layer and a high layer.

  The occupied area distribution for each grain size of the main crystal particles in the dielectric layer 11 shows a mountain-like distribution having one peak, which is almost the same as the first occupied area distribution in the outer cover layer 2 described later. It matches.

  The internal electrode layer 12 is preferably made of any one of metals such as Ni, Cu, Ag, and Ag-Pd, or an alloy thereof, in order to reduce the cost of a small and high capacity multilayer ceramic capacitor. Ni is particularly desirable. The thickness of the internal electrode layer 12 is 5 μm or less, preferably 3 μm or less, more preferably 2 μm or less for the purpose of reducing the influence of strain stress of the internal electrode layer 12.

The outer cover layer 2 is superposed on the upper and lower surfaces of the effective laminate 1, and the material thereof is the main crystal phase mainly composed of BaTiO ₃ and ₂ composed mainly of SiO ₂ , similar to the dielectric layer. It consists of ceramics containing the next phase. The outer cover layer 2 also has a laminated structure like the dielectric layer 11, and there is no particular limitation on the number of laminated layers and the thickness of one layer, but the protective effect of the outer cover layer 2 and the reduction in thermal shock resistance due to strain are prevented. from the viewpoint of, it is desirable not more than 0.2 times 0.05 times the thickness _{t 1} of the thickness _{t 2} is enabled laminate portion 1 of the outer cover layer 2.

  The main crystal particles in the outer cover layer 2 have an occupation area distribution for each of at least two types of particle sizes. Specifically, a first occupied area distribution of a particle size region substantially equal to the occupied area distribution for each particle size of the main crystal particles in the dielectric layer 11, and a particle size larger than the first occupied area distribution It has a second occupied area distribution of the region.

  Here, the occupied area distribution is a graph with the horizontal axis representing the particle size and the vertical axis representing the occupied area occupied by the main crystal particle within a predetermined range when cut in a certain section. This is the distribution state at the time. Each of the first occupied area distribution and the second occupied area distribution shows a mountain-like distribution having one peak.

  The first occupied area distribution is substantially coincident with the occupied area distribution for each particle size of the main crystal particles in the dielectric layer 11 in terms of particle size and peak. Further, the second occupied area distribution is the occupied area distribution of the particle size region larger than the first occupied area distribution, in other words, the minimum particle size included in the second occupied area distribution is the first occupied area distribution. It is larger than the maximum particle size contained. The first occupied area distribution and the second occupied area distribution have a valley-like boundary between the first occupied area distribution mountain and the second occupied area distribution mountain. What is necessary is to distinguish. The boundary is the area occupation between the main crystal particle diameter when showing the peak in the first occupied area distribution and the main crystal particle diameter when showing the peak in the second occupied area distribution. This means the position showing the lowest point of the rate, and the area occupancy of the grain size of the main crystal particles at this boundary is preferably 5% or less, and most preferably close to 0%. The outer cover layer has the first occupied area distribution and the second occupied area distribution partitioned by such a boundary, so that the deformability of the outer cover layer is maintained and the stacking step due to the thickness of the inner electrode is reduced. The effect that it is possible can be produced. In addition, as a particle diameter measuring method in the present invention, a method of calculating the particle diameter of each particle by an intercept method from a cross-sectional SEM photograph is used.

Here, when the particle diameter of the main crystal particle when showing the peak in the first occupied area distribution is D ₁ and the particle diameter of the main crystal particle when showing the peak in the second occupied area distribution is D ₂ , D _It is preferable that ₁ is 0.1 to 0.5 μm and D ₂ / D ₁ is 1.5 to 4.0. Also, _{P 1} peak heights in the first area occupied by the distribution, the peak height at the second occupied area distribution and _{P 2,} the P 2 / _{P 1} is in the range of 0.5 to 1.5 Is preferred. This is because, within this range, the delamination occurrence rate after firing and the crack occurrence rate after the solder thermal shock test are very low.

The first occupied area distribution and the second occupied area distribution are, for example, the occupied area distribution for each particle size of the dielectric powder in the green sheet for the outer cover layer before firing. A first occupied area distribution of a particle size region approximately equal to an occupied area distribution of each particle size of the dielectric powder in the sheet, and a second occupied area distribution of a particle size region larger than the first occupied area distribution. Have
Particularly, by the average particle 1.5 to 4.0 times the diameter DG ₁ of the dielectric powder occupying an average particle diameter DG ₂ of the dielectric powder occupying the second occupied area distribution in the first occupied area distribution, Can be formed.

Hereafter, the manufacturing method of the multilayer ceramic capacitor of this invention is demonstrated in detail.
First, a ceramic slurry is obtained by dispersing a BaTiO ₃ -based ceramic raw material powder, glass powder containing SiO ₂ as a main component, and various trace amounts of additives in a dispersion medium containing a binder. Next, the obtained slurry is formed into a sheet using a known coater, such as a doctor blade, to obtain a dielectric layer green sheet that becomes a dielectric layer after firing.

  Next, a conductive paste containing at least one metal powder selected from the group of Ni, Cu, Ag, Ag—Pd, etc. is printed on the dielectric layer green sheet, and dried to thereby form an internal electrode pattern. A green sheet for a dielectric formed with is prepared.

  Here, the thickness of the dielectric layer green sheet is preferably 8 μm or less, particularly 6 μm or less, and more preferably 4 μm or less, and the thickness of the internal electrode pattern is 5 μm or less, particularly 3 μm or less, more preferably 2 μm or less. . The number of stacked layers is preferably 100 layers or more, particularly 150 layers or more, and more preferably 200 layers or more.

On the other hand, an external cover layer green sheet that becomes an external cover layer after firing is also produced in the same manner as the dielectric layer green sheet. Here, the raw material powder (dielectric powder) contained in the green sheet for the outer cover layer has a grain size region substantially equal to the occupied area distribution for each grain size of the dielectric powder in the dielectric layer green sheet. The particle size of the dielectric powder having one occupied area distribution and a second occupied area distribution in a particle size region larger than the first occupied area distribution and showing a peak in the first occupied area distribution the DG _1, when the particle diameter of the dielectric powder when a peak in the second occupied area distribution and DG _2, a DG ₁ is _0.1~0.5μm, DG 2 / DG ₁ 1.5 When it is ˜4.0, the multilayer ceramic capacitor of the present invention can be manufactured. At this time, the weight W ₂ of the dielectric powder occupying the second occupied area distribution, is preferably 0.75 to 1.5 times the weight W ₁ of the dielectric powder occupying the first occupied area distribution. This is because the amount of deformation of the green sheet for the outer cover layer before firing becomes extremely good, and does not greatly differ from the firing temperature of the laminate part.

  Then, a plurality of green sheets for dielectric layers provided with internal electrode patterns are laminated to produce a laminated body portion (unfired) that develops a capacitance after firing. A green body for an outer cover layer to be a cover layer is superposed (multiple laminated) to form a laminated body after thermocompression bonding.

  After this laminated body is cut into a desired size, individual green multilayer ceramic capacitor body molded bodies are obtained.

  Next, the unfired multilayer ceramic capacitor body molded body is fired under predetermined conditions to obtain a capacitor body.

  Finally, an external electrode paste is attached and baked on the end surface of the capacitor body from which the internal electrode layer is derived, and a multilayer ceramic capacitor provided with external electrodes is obtained.

Next, examples of the present invention are shown below.
First, BaTiO ₃ powder having an average particle diameter of 0.2 μm is used as a ceramic powder used in a ceramic slurry for producing a dielectric layer green sheet, and SiO having an average particle diameter of 0.3 μm as a sintering aid. _The glass powder which has ₂ as a main component was used. BaTiO ₃ powder and glass powder were adjusted at a ratio of 100: 1 to a binder solution in which polyvinyl butyral and a plasticizer were dissolved in a mixed solvent in which toluene and ethanol were mixed at a weight ratio of 1: 1 as a solvent for ceramic slurry. The ceramic slurry was prepared by dispersing with a ball mill. Using this ceramic slurry, a green sheet for a dielectric layer having a thickness of 3 μm was prepared on a carrier film such as PET by a doctor blade method.

  On the other hand, as a ceramic slurry for producing the green sheet for the cover layer, the dielectric powder contained in the ceramic slurry of the dielectric layer green sheet and the dielectric powder having a larger average particle diameter are shown in Table 1. A ceramic slurry was prepared using glass powder or the like in the same manner as in the above preparation method by mixing so as to obtain the peak particle size ratio shown. Using the produced ceramic slurry, a 10 μm green sheet for an outer cover layer was produced on the carrier film by a doctor blade method.

  The conditions for adjusting the slurry to be pulverized and mixed were the same for both sheets.

  Next, Ni film formed by a thin film method is transferred to the dielectric layer green sheet to form an internal electrode pattern, and the dielectric layer green sheet on which the internal conductor pattern is formed is peeled off from the carrier film. 300 layers were stacked, and 20 sheets of green sheets for external cover layers were stacked on the upper and lower surfaces, respectively, to produce a laminate of the present invention. The thickness of the internal electrode pattern was adjusted to 1.5 μm.

  And this laminated body was cut | disconnected, the laminated ceramic capacitor main body molded object was produced, and it baked at 1170 degreeC in the reducing atmosphere after the degreasing process, and obtained the laminated ceramic capacitor main body.

  Finally, an external electrode paste was applied to both end faces of the capacitor body and baked to form external electrodes, thereby producing a multilayer ceramic capacitor having a size of 3.2 mm long × 2.5 mm wide × 1.5 mm high.

The thicknesses of the outer cover layer, dielectric layer, and internal electrode layer were 160 μm, 2.4 μm, and 1.0 μm.

  For the finished multilayer ceramic capacitor, the occurrence rate (%) of delamination generated in 100 pieces was determined as an evaluation of structural defects. Further, as an evaluation of the reliability of the multilayer ceramic capacitor, a solder thermal shock test at a temperature difference of 280 ° C. was performed to determine the number of cracks generated in 100 pieces.

On the other hand, as a comparative example, the same multilayer ceramic capacitor was manufactured by making the particle diameters of the dielectric powders contained in the dielectric layer green sheet and the outer cover layer green sheet equal, and the same evaluation was performed. The results are shown in Table 1.

  As is apparent from the results in Table 1, the occupied area distribution for each particle size of the main crystal particles in the outer cover layer is substantially equal to the occupied area distribution for each particle size of the main crystal particles in the dielectric layer. Sample No. 1 having a first occupied area distribution of a diameter region and a second occupied area distribution of a particle size region larger than the first occupied area distribution. 1 to 10, peeling due to distortion caused by the deformability of the outer cover layer generated between the outer cover layer and the effective laminate portion or the delamination occurrence rate between the effective laminate portions is 10% or less, after the solder thermal shock test The crack generation rate was 5% or less.

In particular, the particle diameter D ₂ of the main crystal grains when a peak in the second occupied area distribution, the particle size of the main crystal grains 1.5 of D ₁ of the case showing a peak in the first area occupied by the distribution Sample no. In 2 to 10, the delamination occurrence rate was 5% or less.

  On the other hand, as a comparative example, a sample No. 1 in which the peak particle sizes of the dielectric powder in the green sheet for the outer cover layer and the dielectric powder in the dielectric layer were made equal. No. 11, delamination occurs at the interface between the outer cover layer and the dielectric layer of all the multilayer ceramic capacitors after firing, the delamination occurrence rate is 85%, and the solder thermal shock crack occurrence rate is 50%. It was.

  In addition, sample No. shown in Table 1 FIG. 2 shows the occupation area distribution for each grain size of the main crystal grains in the outer cover layer 5. The first occupied area distribution of the grain size region approximately equal to the occupied area distribution of each grain size of the main crystal particles in the dielectric layer, and the second occupied area of the grain size region larger than the first occupied area distribution It can be seen that it has a distribution.

It is a schematic sectional drawing which shows the multilayer ceramic capacitor of this invention. It is a graph which shows the occupation area distribution for every particle size of the main crystal grain in the outer cover layer of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Effective laminated body part 11 Dielectric layer 12 Internal electrode layer 2 External cover layer 3 External electrode

Claims (6)

A laminate comprising an effective laminate portion in which dielectric layers and internal electrode layers are alternately laminated in the vertical direction, and an external cover layer comprising dielectric layers superimposed on the upper and lower surfaces of the effective laminate portion. In ceramic capacitors,
The first occupied area of the particle size region in which the occupied area distribution for each particle size of the main crystal particles in the outer cover layer is substantially equal to the occupied area distribution for each particle size of the main crystal particles in the dielectric layer A monolithic ceramic capacitor having a distribution and a second occupied area distribution of a particle size region larger than the first occupied area distribution. When the particle diameter of the main crystal particle when showing the peak in the first occupied area distribution is D ₁ and the particle diameter of the main crystal particle when showing the peak in the second occupied area distribution is D ₂ , D ₁ is 0. The multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor has a thickness of 0.1 to 0.5 μm and D ₂ / D ₁ of 1.5 to 4.0. The relationship of 0.05 ≦ t ₂ / t ₁ ≦ 0.20 is satisfied, where t _{1 is} the thickness of the effective laminate portion and t ₂ is the thickness of the outer cover layer. 2. The multilayer ceramic capacitor according to 2. The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer has a thickness of 7 μm or less and a stacking number of 100 or more. A step of forming a laminated body part by vertically interposing an internal electrode pattern between dielectric sheet green sheets containing dielectric powder, and an external part containing dielectric powder on the upper and lower surfaces of the laminated part A method of manufacturing a multilayer ceramic capacitor including a step of superimposing a green sheet for a cover layer,
Particle size region in which the occupied area distribution for each particle size of the dielectric powder in the outer cover layer green sheet is substantially equal to the occupied area distribution for each particle size of the dielectric powder in the dielectric layer green sheet Having a second occupied area distribution of a particle size region larger than the first occupied area distribution and the first occupied area distribution,
When the particle size of the dielectric powder when showing the peak in the first occupied area distribution is DG ₁ and the particle size of the dielectric powder when showing the peak in the second occupied area distribution is DG ₂ , DG ₁ There is a 0.1 to 0.5 [mu] _m, a manufacturing method of a multilayer ceramic capacitor DG 2 / DG ₁ is characterized in that 1.5 to 4.0. The weight W ₂ of the dielectric powder occupying the second occupied area distribution is 0.75 to 1.5 times the weight W ₁ of the dielectric powder occupying the first occupied area distribution. 6. A method for producing a multilayer ceramic capacitor according to 5.

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