JP4549366B2 - Multilayer printed wiring board - Google Patents

Description

  The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board containing electronic components such as IC chips.

The IC chip has been electrically connected to the printed wiring board by a mounting method such as wire bonding, TAB, or flip chip.
In wire bonding, an IC chip is die-bonded to a printed wiring board with an adhesive, and the pad of the printed wiring board and the IC chip pad are connected with a wire such as a gold wire, and then the IC chip and the wire are protected. An encapsulating resin such as a thermosetting resin or a thermoplastic resin has been applied.
In TAB, the bumps of the IC chip and the pads of the printed wiring board are collectively connected with wires called leads by solder or the like, and then sealed with resin.
The flip chip is performed by connecting the IC chip and the pad portion of the printed wiring board via bumps and filling a resin in the gap between the bumps.
Japanese Patent Laid-Open No. 11-233678 JP-A-8-293476 Japanese Patent Laid-Open No. 10-261642

  However, in each mounting method, electrical connection is performed between the IC chip and the printed wiring board via connecting lead parts (wires, leads, bumps). Each of these lead parts is likely to be cut and corroded, which may cause the connection with the IC chip to be lost or cause a malfunction.

  The inventor has devised that the IC chip and the multilayer printed wiring board can be electrically connected without using lead parts by incorporating the IC chip in the multilayer printed wiring board. That is, an opening, a through-hole, or a counterbore is provided in a resin insulating substrate, an electronic component such as an IC chip is built in in advance, an interlayer insulating layer is laminated, and a photoetching or laser is applied on the pad of the IC chip. A structure was devised in which a via hole was provided to form a conductive circuit as a conductive layer, and then a multilayer printed wiring board was provided by repeating the interlayer insulating layer and the conductive layer.

  However, it has been clarified that in the structure incorporating the IC chip, the interlayer insulating layer disposed on the upper layer of the IC chip is peeled and cracked, and the reliability is lowered.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer print that can be directly electrically connected to an IC chip without a lead component and has high reliability. The purpose is to propose a wiring board.

  The present inventor has discovered that peeling and cracking of the interlayer insulating layer occur near the corners of the IC chip. For this reason, peeling and cracking have the knowledge that stress is concentrated at the corners of the IC chip, and the endurance test was conducted by chamfering the corners on the four sides of the IC chip. No peeling or cracking occurred in the layer. That is, it was found that high reliability can be obtained by chamfering the IC chip.

  It is preferable to provide a transition layer on the pad of the IC chip. The reason for this is as follows. IC pad pads are generally made of aluminum or the like. When the via hole of the interlayer insulating layer was formed by photoetching with the die pad on which the transition layer was not formed, the resin was likely to remain on the surface layer of the pad after exposure and development if the die pad remained. Moreover, discoloration of the pad was caused by the adhesion of the developer. On the other hand, even when the via hole was formed by the laser, if the die pad was not burned out, a resin residue was generated on the pad. Further, when the substrate was immersed in an acid, an oxidant, or an etchant in the subsequent process, or after various annealing processes, discoloration and dissolution of the IC chip pad occurred. Further, the pads of the IC chip are made with a diameter of about 40 μm, and the via hole is larger than that, and therefore unconnected is likely to occur at the time of displacement.

  On the other hand, by providing a transition layer made of copper or the like on the die pad, it is possible to use a solvent and prevent resin residue on the pad. Further, even when the substrate is immersed in an acid, an oxidant, or an etching solution in the post-process, or through various annealing processes, the pad is not discolored or dissolved. This improves the connectivity and reliability between the pad and the via hole. Furthermore, via holes can be reliably connected by interposing a transition layer having a diameter larger than 40 μm on the pads of the IC chip. Desirably, the transition layer should be equal to or larger than the via hole diameter.

  Each of them may function only with a multilayer printed wiring board, but in some cases, in order to function as a package substrate as a semiconductor device, BGA, solder bump or PGA for connection with a mother board or daughter board as an external substrate (Conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case of connection by the conventional mounting method.

  As a resin-made substrate incorporating an electronic component such as an IC chip used in the present invention, epoxy resin, BT resin, phenol resin or the like impregnated with a reinforcing material such as glass epoxy resin or a core material, or an epoxy resin. A laminate of prepregs or the like is used, and those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate without a metal film, and a resin sheet can be used. However, if a temperature of 350 ° C. or higher is applied, the resin will dissolve and carbonize.

  An electronic component such as a core substrate or the like in which a cavity for accommodating an electronic component such as an IC chip is previously formed in a counterbore, a through hole, and an opening is bonded with an adhesive or the like. Physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate incorporating the IC chip to form a conductive metal film on the entire surface. As the metal, one that forms one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. As thickness, it is good to form between 0.001-2.0 micrometers. In particular, 0.01 to 1.0 μm is desirable. In particular, it is good to form with nickel, chromium, and titanium. This is because moisture does not enter from the interface and the metal adhesion is excellent.

  The metal film is thickened by electroless or electrolytic plating. Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. The thickness is preferably in the range of 1 to 20 μm. If it is thicker, undercutting may occur during etching, and a gap may be generated at the interface between the formed transition layer and via hole. Thereafter, an etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etched to form a transition layer on the pad of the IC chip.

The transition layer defined in the present invention will be described.
The transition layer means an intermediate intermediary layer provided to directly connect an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. A feature is that it is formed of two or more metal layers and is larger than a die pad of an IC chip which is a semiconductor element. This improves electrical connection and alignment, and enables via hole processing by laser or photoetching without damaging the die pad. For this reason, the IC chip can be securely embedded, accommodated, accommodated, and connected to the printed wiring board. Further, it is possible to directly form a metal which is a conductor layer of the printed wiring board on the transition layer. Examples of the conductor layer include a via hole in an interlayer resin insulating layer and a through hole on a substrate.

  In addition to the above method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate, and the portion corresponding to the transition layer is removed and thickened by electrolytic plating. Thereafter, the resist is peeled off, and a transition layer can be similarly formed on the pad of the IC chip by an etching solution.

  As described above, in the multilayer printed wiring board of the present invention, since the corners of the IC chip are chamfered, stress is not concentrated at the corners of the IC chip, and peeling and cracks in the interlayer insulating layer are eliminated, which is high. Reliability can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
First, the configuration of the multilayer printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. 7 showing a cross section of the multilayer printed wiring board 10.

  As shown in FIG. 7, the multilayer printed wiring board 10 includes a core substrate 30 that houses the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.

  The IC chip 20 is covered with a passivation film 24, and a die pad 22 constituting an input / output terminal is disposed in the opening of the passivation film 24. A transition layer 38 mainly made of copper is formed on the pad 22.

  A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board.

  In the multilayer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core substrate 30 in advance, and a transition layer 38 is disposed on the pad 22 of the IC chip 20. For this reason, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using lead parts or sealing resin.

  A plan view of the IC chip 20 incorporated in the multilayer printed wiring board 10 is shown in FIG. The corners 20a on the four sides of the IC chip 20 are chamfered and formed in a semicircular shape. Therefore, even when the multilayer printed wiring board 10 is subjected to a heat cycle, stress does not concentrate at the corner 20a of the IC chip 20. Therefore, in the vicinity of the corner portion 20a, the core substrate 30 and the interlayer resin insulation layer 50, the IC chip and the interlayer resin insulation layer 50 are prevented from peeling off, and the generation of cracks in the interlayer resin insulation layer 50 is prevented. The reliability of the plate 10 can be improved. As shown in FIG. 1B, instead of forming the corner portion 20a of the IC chip 20 in a semicircular shape, the corner portion 20a is cut as shown in FIG. Concentration of stress at the corner 20a can also be prevented by using an octagon.

  In the multilayer printed wiring board of this embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened and the film thickness is increased. Becomes even. Furthermore, the shape stability can be maintained even when the upper via hole 60 is formed by the transition layer.

  Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etchant in the post-process, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.

  Next, a method for manufacturing the multilayer printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) First, the multi-chip IC chip shown in FIG. 1 (A) is cut into individual pieces by dicing as shown in FIG. 1 (B), and the corner portion 20a is chamfered into a semicircular shape by polishing. .
(2) On the other hand, an insulating resin substrate (core substrate) 30 in which a prepreg in which a core material such as glass cloth is impregnated with a resin such as epoxy is laminated is prepared as a starting material (see FIG. 2A). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring (see FIG. 2B). Here, the concave portion is provided by counterbore processing, but a core substrate including an accommodation portion can be formed by bonding an insulating resin substrate provided with an opening and a resin insulating substrate not provided with an opening.

(3) Thereafter, the adhesive material 34 is applied to the recess 32 using a printing machine. At this time, potting or the like may be performed in addition to the application. Next, the IC chip 20 is placed on the adhesive material 34 (see FIG. 2C).

(4) Then, the upper surface of the IC chip 20 is pushed or hit to be completely accommodated in the recess 32 (see FIG. 2D). Thereby, the core substrate 30 can be smoothed.

(5) After that, physical vapor deposition such as vapor deposition and sputtering is performed on the entire surface of the core substrate 30 in which the IC chip 20 is accommodated, and a conductive metal film 33 is formed on the entire surface (FIG. 3A). As the metal, one that forms one or more layers of metals such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferable. The thickness is preferably between 0.0001 and 2.0 μm, particularly preferably between 0.01 and 1.0 μm.

  A plating film 36 may be formed on the metal film 33 by electroless plating (FIG. 3B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a build-up formed later, is mainly copper, it is preferable to use copper. The thickness is preferably in the range of 1 to 20 μm.

(6) Thereafter, a resist is applied, exposed and developed to provide a plating resist 35 so as to provide an opening above the pad of the IC chip, and electroless plating is performed to provide an electroless plating film 37 (FIG. 3 ( C)). After removing the plating resist 35, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed, thereby forming a transition layer 38 on the pad 22 of the IC chip (FIG. 3D). Here, the transition layer is formed of a plating resist. However, after the electrolytic plating film is uniformly formed on the electroless plating film 36, an etching resist is formed, exposed and developed, and the metal other than the transition layer is formed. It is also possible to form a transition layer on the pad of the IC chip by exposing and etching. In this case, the thickness of the electrolytic plating film is preferably in the range of 1 to 15 μm. If it is thicker, undercutting occurs during etching, and a gap may be generated at the interface between the formed transition layer and via hole.

(7) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (see FIG. 4A).

(8) An interlayer resin insulation layer 50 is provided by laminating a thermosetting resin sheet having a thickness of 50 μm on the substrate that has undergone the above-described process at a pressure of kg / cm ² while raising the temperature to 50 to 150 ° C. (FIG. 4). (See (B)). The degree of vacuum at the time of vacuum bonding is 10 mmHg.

(9) Next, with a CO ₂ gas laser with a wavelength of 10.4 μm, an interlayer resin insulation layer under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μs, a mask hole diameter of 0.5 mm, and one shot 50 is provided with a via hole opening 48 having a diameter of 80 μm (see FIG. 4C). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Although the resin residue is removed here using chromic acid, desmear treatment can also be performed using oxygen plasma.

(10) Next, the roughened surface 50α of the interlayer resin insulation layer 50 is provided by dipping in an oxidizing agent such as chromic acid or permanganate (see FIG. 4D). The roughened surface 50α is preferably formed in the range of 0.1 to 5 μm. As an example, a roughened surface 50α of 2 to 3 μm is provided by dipping in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes. In addition to the above, the roughened surface 50α can be formed on the surface of the interlayer resin insulation layer 50 by performing plasma treatment using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.

(9) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 5A). The metal layer 52 is formed by electroless plating. A metal layer 52 that is a plating film is provided in a range of 0.1 to 5 μm by preliminarily applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 and immersing it in an electroless plating solution for 5 to 60 minutes. As an example,
[Electroless plating aqueous solution]
NiSO ₄ 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at the liquid temperature of 34 degreeC.
Other than the above, using the same apparatus as the plasma treatment described above, after replacing the argon gas inside, sputtering with Ni and Cu as targets was performed under the conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes. The Ni / Cu metal layer 52 can also be formed on the surface of the interlayer resin insulation layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2 μm.

(12) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed thereon, exposed at 100 mJ / cm ² , and then developed with 0.8% sodium carbonate. A plating resist 54 having a thickness of 15 μm is provided. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 5B). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.

(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL)
19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm2
Time 65 minutes Temperature 22 ± 2 ° C

(13) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 having a thickness of 16 μm formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 5C). ). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.

(14) Next, the above steps (8) to (13) are repeated to further form the upper interlayer resin insulation layer 150 and the conductor circuit 158 (including the via hole 160) (see FIG. 6A). ).

(15) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 15 parts by weight of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd., trade name: Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured with a B type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3. In addition, a commercially available solder resist can also be used as a solder resist.

(16) Next, the solder resist composition is applied to the substrate 30 at a thickness of 30 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a solder resist resist opening is formed. A photomask having a thickness of 5 mm on which the pattern of 1 is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (FIG. 6). (See (B)).

(17) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphate (2.8 × 10 ^−1). mol / l) and sodium citrate (1.6 × 10 ⁻¹ mol / l) in a pH = 4.5 electroless nickel plating solution for 20 minutes, and the opening 71 is plated with a thickness of 5 μm. Layer 72 is formed. Furthermore, the substrate was made of potassium gold cyanide (7.6 × 10 ⁻³ mol / l), ammonium chloride (1.9 × 10 ⁻¹ mol / l), sodium citrate (1.2 × 10 ⁻¹ mol). / L), immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) for 7.5 minutes at 80 ° C. A solder pad 75 is formed on the conductor circuit 158 by forming a 0.03 μm gold plating layer 74 (see FIG. 6C).

(18) Thereafter, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 76. As a result, it is possible to obtain the multilayer printed wiring board 10 including the IC chip 20 and having the solder bumps 76 (see FIG. 7).

  In the above-described embodiment, thermosetting resin sheets are used for the interlayer resin insulation layers 50 and 150. This thermosetting resin sheet resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.

The thermosetting resin sheet used in the manufacturing method of the first embodiment is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). It is dispersed inside.
Note that the terms “sparingly soluble” and “soluble” used in the first embodiment are “soluble” for the sake of convenience when the solution has a relatively high dissolution rate when immersed in a solution of the same acid or oxidizing agent for the same time. A material having a relatively low dissolution rate is referred to as “slightly soluble” for convenience.

  Examples of the soluble particles include resin particles soluble in acid or oxidizing agent (hereinafter referred to as soluble resin particles), inorganic particles soluble in acid or oxidizing agent (hereinafter referred to as soluble inorganic particles), and metals soluble in acid or oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.

  The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.

  The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the first embodiment, the particle size of the soluble particles is the length of the longest part of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. And it may consist of a mixture of two or more resins.

  Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified and other modified polybutadiene rubbers, carboxyl group-containing (meth) acrylonitrile / butadiene rubbers, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.

  Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.

  Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.

  Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.

  When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted with the hardly soluble resin, and no crack is generated in the interlayer resin insulation layer made of the resin sheet. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.

The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins and the like. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.

  Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.

  In the resin sheet used in the first embodiment, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin sheet, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin sheet which contains a soluble particle only in the surface layer part which forms a roughening surface. Thereby, since the portions other than the surface layer portion of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits through the interlayer resin insulating layer is reliably maintained.

  In the resin sheet, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin sheet. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin sheet is melted to the deep part of the resin sheet, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin sheet cannot be maintained, which may cause a short circuit.

The resin sheet preferably contains a curing agent, other components, etc. in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.

  The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin sheet. If it is less than 0.05% by weight, the resin sheet is not sufficiently cured, so that the degree of penetration of acid or oxidant into the resin sheet increases, and the insulation of the resin sheet may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.

  Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By including these fillers, it is possible to improve the performance of the multilayer printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.

  Moreover, the said resin sheet may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers melt and carbonize when a temperature of 350 ° C. or higher is applied.

  Next, a multilayer printed wiring board according to a first modification of the first embodiment will be described with reference to FIG. In 1st Embodiment mentioned above, the case where BGA was arrange | positioned demonstrated. The first modified example is substantially the same as that of the first embodiment, but is configured in a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.

Next, a multilayer printed wiring board according to a second modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the IC chip is accommodated in the recess 32 provided in the core substrate 30 with counterbore. On the other hand, in the second modified example, the IC chip 20 is accommodated in the through hole 32 formed in the core substrate 30. In the second modified example, since the heat sink can be directly attached to the back side of the IC chip 20, there is an advantage that the IC chip 20 can be efficiently cooled.

Next, a multilayer printed wiring board according to a third modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the transition layer 38 is formed on the pad 22 of the IC chip 20, and the via hole 60 of the interlayer resin insulating layer 50 is connected to the transition layer 38. On the other hand, in the third modified example, the via hole 60 is directly connected to the pad 22 without providing a transition layer. Since this third modified example can reduce the number of steps compared to the first embodiment, there is an advantage that it can be configured at a low cost.

Next, a multilayer printed wiring board according to a fourth modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the IC chip is accommodated in the multilayer printed wiring board. On the other hand, in the fourth modified example, the IC chip 20 is accommodated in the multilayer printed wiring board, and the IC chip 120 is placed on the surface. As the built-in IC chip 20, a cache memory having a relatively small calorific value is used, and as the IC chip 120 on the surface, a CPU for calculation is placed.

  The pads 22 of the IC chip 20 and the pads 124 of the IC chip 120 are connected via a transition layer 38 -via hole 60 -conductor circuit 58 -via hole 160 -conductor circuit 158 -solder bump 76U. On the other hand, the pad 124 of the IC chip 120 and the pad 92 of the daughter board 90 are composed of the solder bump 76U-conductor circuit 158-via hole 160-conductor circuit 58-via hole 60-through hole 136-via hole 60-conductor circuit 58-. Via hole 160 is connected to conductor circuit 158 via solder bump 76U.

  In the fourth modified example, it is possible to arrange the IC chip 120 and the cache memory 20 close to each other while manufacturing the cache memory 20 having a low yield separately from the IC chip 120 for the CPU. Is possible. In the fourth modified example, by incorporating an IC chip and placing it on the surface, it is possible to mount electronic components such as IC chips having different functions, and to obtain a higher-performance multilayer printed wiring board. Can do.

[Second Embodiment]
A multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment described above, the transition layer is provided after the IC chip is mounted on the core substrate. On the other hand, in the second embodiment, a transition layer is provided on the IC chip and then mounted on the core substrate.

  As shown in FIG. 20, the multilayer printed wiring board 10 of the second embodiment includes a core substrate 30 that houses the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.

  A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board.

  FIG. 14A showing a cross section of the semiconductor element 20 and FIG. 15B showing a plan view of the configuration of the semiconductor element (IC chip) accommodated in the multilayer printed wiring board 10 according to the second embodiment. The description will be given with reference.

  As shown in FIG. 14B, a die pad 22 and wiring (not shown) are disposed on the upper surface of the semiconductor element 20, and a passivation film 24 is coated on the die pad 22 and wiring. An opening of a passivation film 24 is formed in the die pad 22. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38 includes a thin film layer 33 and an electrolytic plating film 37.

  In the multilayer printed wiring board 10 of this embodiment, the IC chip 20 is built in the core substrate 30, and the transition layer 38 is disposed on the pad 22 of the IC chip 20. For this reason, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using lead parts or sealing resin. In addition, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened, and the film thickness becomes uniform. Furthermore, the shape stability can be maintained even when the upper via hole 60 is formed by the transition layer.

  Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etchant in the post-process, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.

  As shown in FIG. 15B, the corners 20a of the four sides of the IC chip 20 are chamfered and formed in a semicircular shape. Therefore, even when the multilayer printed wiring board 10 is subjected to a cold heat cycle, the stress does not concentrate at the corner 20a of the IC chip 20. Therefore, in the vicinity of the corner portion 20a, the core substrate 30 and the interlayer resin insulation layer 50, the IC chip and the interlayer resin insulation layer 50 are prevented from peeling off, and the generation of cracks in the interlayer resin insulation layer 50 is prevented. The reliability of the plate 10 can be improved.

Next, a method for manufacturing the multilayer printed wiring board described above with reference to FIG. 20 will be described with reference to FIGS.
First, a method for manufacturing the semiconductor element described above with reference to FIG. 14B will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 22 are formed by a conventional method on the silicon wafer 20A shown in FIG. 12A (see FIG. 15A showing the plan views of FIG. 12B and FIG. 12B). Note that FIG. 12B shows a BB cross section of FIG.
(2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 12C).

(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (FIG. 13A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below that range, a thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As a metal to be formed, a material selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the second embodiment, the thin film layer 33 is formed of chromium.

(4) Thereafter, a resist layer of a liquid resist, a photosensitive resist, or a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and after exposure and development, a non-formation portion 35a is formed in the plating resist 35. Electrolytic plating is performed to provide a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (FIG. 13B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the conductor layer, which is a buildup formed later, is mainly copper, it is preferable to use copper. In the second embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.

(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 under the plating resist 35 is subjected to sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc. Then, the transition layer 38 is formed on the pad 22 of the IC chip (FIG. 13C).

(6) Next, an etching solution is sprayed on the substrate to etch the surface of the transition layer 38, thereby forming a roughened surface 38α (see FIG. 14A). The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like, and the corners 20a on the four sides are chamfered in a semicircular shape to form the semiconductor element 20 (FIG. 14 (B) and FIG. 15 (B) which is a plan view of FIG. 14 (B)). Thereafter, if necessary, operation check and electrical inspection of the divided semiconductor element 20 may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied, and the inspection accuracy is high.

  In the semiconductor device according to the second embodiment described above with reference to FIG. 14B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37. On the other hand, the transition layer can be configured as a three-layer structure including a thin film layer (first thin film layer), an electroless plating film (second thin film layer), and an electrolytic plating film (thickening layer). In the case of a three-layer structure, the second thin film layer is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating. The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver.

  In the above-described example, the transition layer 38 is formed by forming the thickening layer 37 in the resist non-formation portion using a semi-additive process. On the other hand, it is also possible to form the transition layer 38 by forming a thick layer 37 uniformly using a full additive process, then providing a resist, and removing the non-resist forming portion by etching.

Next, a manufacturing process of the multilayer printed wiring board that accommodates the above-described IC chip 20 will be described.
(1) An insulating resin substrate 30A having a thickness of 0.5 mm obtained by laminating and curing a prepreg in which a core material such as glass cloth is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy is used as a starting material. First, a through hole 32 for accommodating an IC chip is formed in the insulating resin substrate 30A (see FIG. 16A). Although the resin substrate 30A in which the core material is impregnated with the resin is used here, a resin substrate that does not include the core material can also be used. Note that it is preferable to provide a taper 32 a at the upper end opening of the through hole 32. By the taper 32a, the groove of the filling resin generated in the cavity edge portion can be eliminated in the laminating process described later. Moreover, it becomes possible to ensure flatness.

(2) Thereafter, the IC chip 20 described above with reference to FIG. 14B is accommodated in the through hole 32 of the insulating resin substrate 30A (see FIG. 16B).

(3) Then, the insulating resin substrate 30A that accommodates the IC chip 20 and, similarly, a core material such as a glass cloth or a prepreg impregnated with a resin such as BT or epoxy is laminated and cured to a thickness of 0.2 mm The insulating resin substrate (core substrate) 30B is laminated with an uncured prepreg 30C (thickness: 0.1 mm) in which a core material such as glass cloth is impregnated with a resin such as epoxy (FIG. 16C). . Although the resin substrate 30B in which the core material is impregnated with the resin is used here, a resin substrate that does not include the core material can also be used. Further, instead of the prepreg, various thermosetting resins or a sheet in which a core material is impregnated with a thermosetting resin and a thermoplastic resin can be used.

(4) The above-described laminate is pressed from above and below with stainless steel (SUS) press plates 100A and 100B. At this time, the epoxy resin 30α oozes out from the prepreg 30C, fills the space between the through hole 32 and the IC chip 20, and covers the upper surface of the IC chip 20. As a result, the upper surfaces of the IC chip 20 and the insulating resin substrate 30A become completely flat. (FIG. 16D). For this reason, when forming a buildup layer at the process mentioned later, a via hole and wiring can be formed appropriately and the reliability of wiring of a multilayer printed wiring board can be improved. The pressurization and / or temporary curing is preferably performed under reduced pressure. By reducing the pressure, air bubbles are not left between the IC chip 20, the insulating resin substrate 30A, the prepreg 30C, the resin substrate 30B, and in the prepreg 30C, and the reliability of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 30 that accommodates the IC chip 20 is formed by heating to cure the uncured epoxy resin 30α (FIG. 16E). This main curing is preferably performed under reduced pressure. By reducing the pressure, no bubbles remain in the prepreg 30C, and the reliability of the multilayer printed wiring board can be improved.

(6) A thermosetting resin sheet similar to that of the first embodiment having a thickness of 50 μm is laminated on the substrate that has undergone the above-mentioned process by vacuum compression bonding at a pressure of 5 kg / cm ² while raising the temperature to 50 to 150 ° C. A layer 50 is provided (see FIG. 17A). The degree of vacuum at the time of vacuum bonding is 10 mmHg.

(7) Next, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulation layer 50 with a CO ₂ gas laser having a wavelength of 10.4 μm (see FIG. 17B). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected.

(8) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid to form a roughened surface 50α (see FIG. 17C).

(9) Next, as in the first embodiment, a metal layer 52 is formed on the surface of the interlayer resin insulation layer 50 (see FIG. 18A).

(10) A commercially available photosensitive dry film is affixed to the substrate 30 after the above processing, a photomask film is placed, exposed at 100 mJ / cm ² and then developed with 0.8% sodium carbonate. A plating resist 54 having a thickness of 20 μm is provided. Next, electrolytic plating is performed under the same conditions as in the first embodiment to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 18B).

(11) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 made of a film 56 having a thickness of 16 μm are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 18C). ). In the present embodiment, as described above with reference to FIG. 16 (E), the upper surface of the core substrate 30 is formed to be completely smooth, so that the via hole 60 can appropriately connect to the transition layer 38. it can. For this reason, it becomes possible to improve the reliability of a multilayer printed wiring board.

(12) Next, by repeating the steps (6) to (11), an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) are further formed (see FIG. 19A). ).

(13) Next, a solder resist composition (organic resin insulating material) is obtained in the same manner as in the first embodiment.

(14) Next, the solder resist composition is applied to the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which the pattern of 1 is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (FIG. 19). (See (B)).

(15) Next, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 of the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed. Further, by forming a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72, a solder pad 75 is formed on the conductor circuit 158 (see FIG. 19C).

(16) Thereafter, a solder paste 76 is formed by printing a solder paste on the opening 71 of the solder resist layer 70 and reflowing at 200 ° C. As a result, the multilayer printed wiring board 10 including the IC chip 20 and having the solder bumps 76 can be obtained (see FIG. 20).

[Third embodiment]
Subsequently, the configuration of the multilayer printed wiring board according to the third embodiment will be described.
As shown in FIG. 26, the multilayer printed wiring board 10 of the third embodiment accommodates the heat sink 30D on which the IC chip 20 of the second embodiment described above with reference to FIG. The core resin 31, the interlayer resin insulation layer 50 on the IC chip 20, and the interlayer resin insulation layer 150. Via hole 60 and conductor circuit 58 are formed in interlayer resin insulation layer 50, and via hole 160 and conductor circuit 158 are formed in interlayer resin insulation layer 150.

  A solder resist layer 70 is disposed on the interlayer resin insulating layer 150. The conductor circuit 158 under the opening 71 of the solder resist layer 70 is provided with solder bumps 76 for connection to an external substrate (not shown) such as a daughter board or a mother board.

  The heat sink 30D is made of a ceramic such as aluminum nitride, alumina, or mullite, or a metal such as an aluminum alloy, copper, or adjacent bronze. Here, it is preferable to use an aluminum alloy having a high thermal conductivity or a copper foil subjected to roughening treatment on both surfaces. In the present embodiment, by attaching a heat sink 30D to the back surface of the IC chip 20 embedded in the core substrate 31, heat generated in the IC chip 20 is released and the core resin 31 and the interlayer resin insulating layer 50 formed on the core substrate are disposed. , 150 is prevented, and disconnection of the via holes 60, 160 and the conductor circuits 58, 158 on the interlayer resin insulation layer is eliminated. This increases the reliability of the wiring.

  The IC chip 20 is attached to the heat sink 30D with a conductive adhesive 29. The conductive adhesive 29 contains a metal powder such as copper, gold, silver, and aluminum in a resin and has high thermal conductivity. Therefore, the heat generated in the IC chip 20 is efficiently released to the heat sink 30D side. be able to. Here, a conductive adhesive is used to attach the IC chip 20, but various materials can be used as long as the adhesive has high thermal conductivity.

  In the multilayer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core substrate 31, and the transition layer 38 is disposed on the pad 22 of the IC chip 20. For this reason, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using lead parts or sealing resin. In addition, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened, and the film thickness becomes uniform. Furthermore, the shape stability can be maintained even when the upper via hole 60 is formed by the transition layer.

  Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent the resin residue on the pad 22 from being immersed in an acid, an oxidant, or an etchant in the post-process, and various annealing. Even after the process, discoloration and dissolution of the pad 22 do not occur. This improves the connectivity and reliability between the IC chip pads and via holes. Furthermore, a via hole having a diameter of 60 μm can be reliably connected by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm.

  Similarly to the second embodiment, the corners 20a on the four sides of the IC chip 20 are chamfered and formed in a semicircular shape. Therefore, even when the multilayer printed wiring board 10 is subjected to a heat cycle, stress does not concentrate at the corner 20a of the IC chip 20. Therefore, in the vicinity of the corner portion 20a, the core substrate 30 and the interlayer resin insulation layer 50, the IC chip and the interlayer resin insulation layer 50 are prevented from peeling off, and the generation of cracks in the interlayer resin insulation layer 50 is prevented. The reliability of the plate 10 can be improved.

  Next, a method for manufacturing the multilayer printed wiring board described above with reference to FIG. 26 will be described with reference to FIGS.

(1) A conductive adhesive 29 is applied to a plate-shaped heat sink 30D (FIG. 21A) made of ceramic such as aluminum nitride, alumina, mullite, aluminum alloy, or adjacent bronze (FIG. 21A). )). As the conductive adhesive, a paste containing copper particles having an average particle diameter of 2 to 5 μm and having a thickness of 10 to 20 μm was used.

(2) The IC chip 20 according to the second embodiment described above is placed (FIG. 21C).

(3) Next, the heat sink 30D to which the IC chip 20 is attached is placed on a stainless steel (SUS) press plate 100A. Then, a prepreg laminate 31α having a thickness of 0.5 mm formed by laminating an uncured prepreg in which a core material such as glass cloth is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy is placed on the heat sink 30D. (FIG. 22 (A)). In the prepreg laminate 31α, a through hole 32 is provided in advance at the position of the IC chip 20. Here, a prepreg in which a core material is impregnated with a resin is used, but a resin substrate without a core material can also be used. Further, instead of the prepreg, various thermosetting resins or a sheet in which a core material is impregnated with a thermosetting resin and a thermoplastic resin can be used.

(4) The above-described laminate is pressed from above and below with stainless steel (SUS) press plates 100A and 100B. At this time, the epoxy resin 31β oozes out from the prepreg 31α, fills the space between the through hole 32 and the IC chip 20, and covers the upper surface of the IC chip 20. Thereby, the upper surfaces of the IC chip 20 and the prepreg laminate 31α are completely flat. (FIG. 22 (B)). For this reason, when forming a buildup layer at the process mentioned later, a via hole and wiring can be formed appropriately and the reliability of wiring of a multilayer printed wiring board can be improved. As in the second embodiment, by reducing the pressure and applying pressure and / or pre-curing, mixing of bubbles can be prevented and the reliability of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 31 that accommodates the IC chip 20 is formed by heating and curing the epoxy resin of the prepreg (FIG. 22C). As in the second embodiment, by performing curing by reducing the pressure, it is possible to prevent mixing of bubbles and improve the reliability of the multilayer printed wiring board.

(6) A thermosetting resin sheet similar to that of the first embodiment having a thickness of 50 μm is vacuum-pressurized and laminated at a pressure of 5 kg / cm ² while being heated to a temperature of 50 to 150 ° C. on the substrate that has undergone the above-described steps. An insulating layer 50 is provided (see FIG. 23A). The degree of vacuum at the time of vacuum bonding is 10 mmHg.

(7) Next, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulation layer 50 with a CO ₂ gas laser having a wavelength of 10.4 μm (see FIG. 23B). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, thereby improving the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing the transition layer 38 having a diameter of 60 μm or more on the 40 μm diameter pad 22, the via hole opening 48 having a diameter of 60 μm can be reliably connected.

(8) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid to form a roughened surface 50α (see FIG. 23C).

(9) Next, as in the first embodiment, a metal layer 52 is formed on the surface of the intermediate resin insulation layer 50 (see FIG. 24A).

(10) A commercially available photosensitive dry film is affixed to the substrate 30 after the above processing, a photomask film is placed, exposed at 100 mJ / cm ² and then developed with 0.8% sodium carbonate. A plating resist 54 having a thickness of 15 μm is provided. Next, electrolytic plating is performed under the same conditions as in the first embodiment to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 24B).

(11) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating are removed. A conductor circuit 58 and a via hole 60 having a thickness of 16 μm formed of the film 56 are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 24C). ). In the present embodiment, as described above with reference to FIG. 22C, the upper surface of the core substrate 31 is formed to be completely smooth, so that the via hole 60 can appropriately connect to the transition layer 38. it can. For this reason, it becomes possible to improve the reliability of a multilayer printed wiring board.

(12) Next, by repeating the steps (6) to (11), an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) are further formed (see FIG. 25A). ).

(13) Next, a solder resist composition (organic resin insulating material) similar to that of the first embodiment is obtained.

(14) Next, the solder resist composition is applied to the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which a pattern of 2 is drawn is brought into close contact with the solder resist layer 70, exposed to ultraviolet light of 1000 mJ / cm ² and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (FIG. 25). (See (B)).

(15) Next, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 of the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed. Further, by forming a gold plating layer 74 on the nickel plating layer 72, solder pads 75 are formed on the conductor circuit 158 (see FIG. 25C).

(16) After that, solder bumps 76 are formed by printing solder paste in the openings 71 of the solder resist layer 70 and reflowing at 200 ° C. Finally, the heat sink 30D is divided into pieces by dicing or the like to obtain the multilayer printed wiring board 10 (see FIG. 26).

[First comparative example]
As a first comparative example, a multilayer printed wiring board was formed in the same manner as in the first embodiment. However, the corners of the IC chip were not chamfered.

[Second comparative example]
As a second comparative example, a multilayer printed wiring board was formed in the same manner as in the second embodiment. However, the corners of the IC chip were not chamfered.

[Third comparative example]
As a third comparative example, a multilayer printed wiring board was formed in the same manner as in the third embodiment. However, the corners of the IC chip were not chamfered.

  Peeling and cracking of the interlayer resin insulation layer after heat cycle of the multilayer printed wiring board of the first, second and third embodiments and the multilayer printed wiring board of the first, second and third comparative examples The result of evaluating the presence or absence of occurrence is shown in the chart of FIG. In the first, second, and third embodiments, no peeling or cracking occurred in the interlayer resin insulating layer, but in the first, second, or third comparative example, peeling or cracking occurred in the interlayer resin insulating layer. .

(A) is a plan view of a multi-chip IC chip before cutting, and (B) and (C) are plan views of the chamfered and separated IC chip. (A), (B), (C), (D) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. (A), (B), (C), (D) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. (A), (B), (C), (D) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. It is sectional drawing of the multilayer printed wiring board which concerns on 1st Embodiment. It is sectional drawing of the multilayer printed wiring board which concerns on the modification of 1st Embodiment of 1st Embodiment. It is sectional drawing of the multilayer printed wiring board which concerns on the 2nd modification of 1st Embodiment. It is sectional drawing of the multilayer printed wiring board which concerns on the 3rd modification of 1st Embodiment. It is sectional drawing of the multilayer printed wiring board which concerns on the 4th modification of 1st Embodiment. (A), (B), (C) is a manufacturing-process figure of the IC chip accommodated in the multilayer printed wiring board concerning 2nd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the IC chip accommodated in the multilayer printed wiring board concerning 2nd Embodiment of this invention. (A), (B) is a manufacturing-process figure of the IC chip accommodated in the multilayer printed wiring board concerning 2nd Embodiment of this invention. (A) is a top view of the silicon wafer which concerns on 2nd Embodiment of this invention, (B) is a top view of the semiconductor element separated into pieces. (A), (B), (C), (D), (E) is a manufacturing process figure of the multilayer printed wiring board concerning a 2nd embodiment of the present invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 2nd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 2nd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 2nd Embodiment of this invention. It is sectional drawing of the multilayer printed wiring board which concerns on 2nd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. (A), (B), (C) is a manufacturing-process figure of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. It is sectional drawing of the multilayer printed wiring board which concerns on 3rd Embodiment of this invention. It is a graph which shows the evaluation result of each embodiment and a comparative example.

Explanation of symbols

20 IC chip 20a Corner 22 Pad 24 Passivation film 30 Core substrate 30D Heat sink 32 Recess 36 Resin layer 38 Transition layer 50 Interlayer resin insulation layer 58 Conductor circuit 60 Via hole 70 Solder resist layer 76 Solder bump 90 Daughter board 96 Conductive connection pin 97 Conductive adhesive 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

Claims (2)

In the multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on the substrate, and the via hole is formed in the interlayer insulating layer,
The substrate has a built-in IC chip having pads and corners of four sides chamfered in an arc shape ,
The via hole and the pad are electrically connected via a mediation layer formed on the pad,
The mediation layer is a multilayer printed wiring board characterized that you have been formed by two or more metal layers. The multilayer printed wiring according to claim 1 , wherein a diameter of the mediating layer is formed larger than a pad diameter of the IC chip.

Images