JP4550685B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A method of manufacturing a semiconductor device using a conventional technique will be described with reference to cross-sectional process diagrams of FIGS. 1 to 9 (see Patent Document 1).

As shown in FIG. 1, a gate insulating film 101a made of a silicon oxide film (SiO ₂ ) is formed on a semiconductor substrate 101 made of silicon (Si). A gate electrode 102a made of polysilicon is formed on the gate insulating film 101a by a CVD method. An upper insulating film 103a made of SiO _{2 is} formed on the gate polysilicon film 102a using the CVD method. An upper polysilicon film 104a is formed on the upper insulating film 103a with a thickness of 500 to 2500 mm by using the CVD method.

  Next, as shown in FIG. 2, the gate polysilicon film 102a and the upper insulating film 103a are patterned by patterning the gate polysilicon film 102a, the upper insulating film 103a, and the upper polysilicon film 104a using photo and etching techniques. Then, a gate electrode structure made of the upper polysilicon film 104a is formed. Impurity regions 102 are formed by ion-implanting impurities into the semiconductor silicon substrate 101 using the gate electrode structure as a mask.

Next, as shown in FIG. 3, a silicon nitride film (SIN) 105a is formed so as to cover the entire surface. A silicon oxide film (SiO ₂ ) 106a is formed so as to cover the silicon nitride film.
Next, as shown in FIG. 4, a polysilicon film 107a is formed to a thickness of 500 to 2500 by using a CVD method so as to cover the silicon oxide film 106a.
Next, as shown in FIG. 5, the sidewall polysilicon film 107a is formed by anisotropically etching the entire polysilicon film 107a. An interlayer insulating film 108a made of SiO ₂ is formed so as to cover the entire surface.

Next, as shown in FIG. 6, a contact hole 109a is formed above the impurity region 102 of the interlayer insulating film 108a by using a photo and etching technique. At this time, if the mask alignment is shifted, the upper polysilicon film 104a, the sidewall polysilicon film 107a, the silicon nitride film 105a, and the silicon above the gate polysilicon film 102a are etched by the formation of the contact hole 109a. A predetermined amount of the oxide film 106a is also removed. However, since the upper polysilicon film 104a and the sidewall polysilicon film 107a have a selectivity (etching rate ratio) 20 to 50 times higher than that of the interlayer insulating film (SiO ₂ ) 108a, the contact hole 109a is completely opened. After that, a predetermined amount remains.

  Next, heat treatment is performed. As a result, as shown in FIG. 7, an oxidized polysilicon film 104b is formed on the upper polysilicon film 104a exposed due to the mask alignment shift, and on the sidewall polysilicon film 107a on the side wall of the gate electrode 111a. A sidewall oxide polysilicon film 107b is formed. An oxide film 107c is also formed in the impurity region 102 in the contact hole 109a when the polysilicon oxide film 104b and the sidewall polysilicon oxide film 107b are formed. The oxidation rate of the upper polysilicon film 104a and the sidewall polysilicon film 107a is 5 to 10 times that of the impurity region 102. The thickness of the polysilicon oxide film 104b and the sidewall oxide polysilicon film 107b is such that the oxide polysilicon film 104b and the sidewall oxide polysilicon film 107b are also removed when the oxide film 107c on the impurity region 102 is removed by etching. After the etching step is completed, the remaining polysilicon oxide film 104b and sidewall oxide polysilicon film 107b should be thick enough to finally establish insulation between the conductive layer 110a and the gate electrode 111a. That's fine. Specifically, when the thickness of the oxide film 107c on the impurity region 102 is about 200 mm, the thickness of the polysilicon oxide film 104b and the side wall oxide polysilicon film 107b may be about 1000 to 1500 mm.

  Next, as shown in FIG. 8, the oxide film 107c formed on the impurity region 102 in the contact hole 109a is removed by etching. By etching the oxide film 107c, the polysilicon oxide film 104b and the sidewall oxide polysilicon film 107b in the contact hole 109a are also removed by a predetermined amount. However, since the polysilicon oxide film 104b and the sidewall oxide polysilicon film 107b are sufficiently thick, they are not completely removed.

  As shown in FIG. 9, the conductive layer is electrically connected to the impurity region 102 in the contact hole 109a and extends along the surfaces of the polysilicon oxide film 104b and the sidewall oxide polysilicon film 107b and the surface of the interlayer insulating film 108a. Layer 110a is formed. Here, even if the upper polysilicon film 104a is temporarily exposed due to the mask alignment deviation at the time of forming the contact hole, at this time, the gate electrode 111a is formed of the polysilicon oxide film 104b and the sidewall oxide polysilicon film. Since it is covered with 107b, the gate electrode 111a and the conductive layer 110a were not short-circuited.

In the prior art, the semiconductor device has been manufactured as described above.
JP-A-5-343669

  In the conventional method of forming a semiconductor device, an oxide film of 1000 to 1500 mm (104b and 107b in FIG. 9) is formed on the gate electrode in order to prevent a short circuit between the gate electrode and the contact when the source or drain contact is misaligned. Therefore, the height including the gate electrode (101a to 107a in FIG. 4) becomes high (about 5000 mm), and there is a problem that the space between the gate electrodes cannot be miniaturized. This is because the relationship between the height h of the gate electrode and the space s between the gate electrodes is such that when the aspect ratio (= h / s) is higher than 0.9, voids are formed in the space between the gate electrodes, and the contact between the contacts. This is because a short circuit is likely to occur (see FIGS. 27 and 28).

On the other hand, when the thickness of the oxide film 1000 Å to 1500 上 の on the gate electrode is reduced, if the contact alignment is shifted, the gate electrode and the contact are short-circuited. It cannot be thinned.
Therefore, in the case of the prior art, since the height including the gate electrode is about 5000 mm, it is impossible to make the space between the gate electrodes 0.56 μm or less, and further miniaturization of the semiconductor integrated circuit, particularly 0.13 Miniaturization after μm was difficult (see FIG. 28 and Table 1).

Also, the drain contact, source contact, and gate contact cannot be formed with a single mask in the conventional method for forming a semiconductor device.
The prior art requires an exposed surface oxidation treatment after opening the contact hole in order to prevent a short circuit between the gate electrode and the contact when the source and / or drain contact is misaligned. Therefore, in one mask, the oxide film is similarly applied to the gate electrode contact surface exposed for the gate contact and the gate electrode surface exposed in the source or drain contact hole due to the mask alignment shift. When the gate contact is made conductive, the gate electrode and the source or drain contact are short-circuited, and if the short-circuit is to be prevented, a conduction failure occurs in the gate contact. Therefore, at least one mask is required for forming the drain contact and one mask is required for forming the gate electrode, which causes a problem that the process becomes complicated and the manufacturing cost increases.

  The present invention has been made in view of such circumstances, and provides a method for manufacturing a semiconductor device that is suitable for further miniaturization of the semiconductor device and is low in cost.

According to the present invention, possess an interlayer insulating film covering the gate electrode structure of a polysilicon film formed on the substrate surface, and a manufacturing method of the aspect ratio is greater than 0.9 the semiconductor device between the gate electrode Forming a gate electrode made of a polysilicon film on the substrate surface through a gate insulating film; forming impurity regions on both sides of the gate electrode to form a source region and a drain region, respectively; A step of laminating a film capable of functioning as an etching stopper layer when a contact hole is opened in contact with the surface of the gate electrode and the surface of the source region and / or the drain region without providing a hard mask; Forming an interlayer insulating film thereon; using one mask, penetrating the interlayer insulating film and etching stopper Opening a contact hole on the layer, and then removing the etching stopper layer to expose the contact surface on the gate electrode and the source and / or drain region; an insulating film on at least the contact hole side wall and the contact surface Including a step of depositing the gate electrode from the sidewall-like insulating film after the etch-back to such a thickness that the gate electrode is not exposed; and a step of forming a sidewall-like insulating film on the side wall of the contact hole by etching back the insulating film. A method of manufacturing a semiconductor device is provided.

According to the manufacturing method of the present invention, the sidewall (spacer) -like insulating film formed in the contact hole is short-circuited between the gate electrode and the source contact and / or the drain contact due to misalignment during contact photo processing and / or Alternatively, since a short circuit between the contacts is prevented, the semiconductor device can be miniaturized.
Further, according to the manufacturing method of the present invention, the drain contact and / or the source contact and the gate contact can be processed with one mask.
As a result, it is possible to obtain a further miniaturized semiconductor device, which is impossible with the prior art, and to reduce the manufacturing cost.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a gate electrode structure made of a polysilicon film formed on a surface of a semiconductor silicon substrate and an interlayer insulating film covering the gate electrode structure. A step of exposing a desired contact surface by opening a contact hole through the insulating film, a step of depositing an insulating film on at least the contact hole side wall and the contact surface, and etching back the insulating film to the side wall of the contact hole A sidewall insulating film is formed.

  In the present invention, the semiconductor device is preferably a semiconductor device having a MOS field effect transistor (MOS FET), and more preferably a flash memory.

  In the method of the present invention, the gate electrode structure may have a single-layer polysilicon gate electrode or a stacked polysilicon gate electrode. The gate electrode structure can be formed by any method, for example, formed according to a method known in the art. The height of the gate electrode structure (distance from the silicon substrate surface to the top surface of the gate electrode structure before the formation of the interlayer insulating film) is preferably lower than 4600 mm, more preferably lower than 3200 mm, and even more preferably from 2400 mm. Low. As the miniaturization technology advances, the height of the gate electrode structure can be further reduced.

  Before forming each element on the semiconductor silicon substrate, the silicon substrate may be separated into a plurality of element formation regions separated from each other. For isolation of the element formation region, a method known in the art such as a LOCOS (or selective oxidation) method, a recessed LOCOS method, or a trench isolation (STI) method is used.

The interlayer insulating film is formed by an arbitrary method, and for example, a CDV method, a plasma CVD method, a coating method (SOD: Spin On Deposition), or the like is used. For the interlayer insulating film, an insulating material known in the art, for example, an oxide film-based material such as silicon oxide (SiO ₂ ) can be used. The silicon oxide may be doped with phosphorus and / or boron like BPSG, PSG or BSG, for example.

  The contact hole is formed by etching so that a desired contact surface is exposed through the interlayer insulating film. “Contact surface” is a surface of an element or a part of an element, and is a surface that is in contact with a conductor for electrical connection with the outside of the semiconductor device or with another element or part, or a surface for contacting Say. The desired contact surface is the surface of the source region and / or drain region and / or gate electrode. In a preferred embodiment, the desired contact surface is two or more surfaces selected from the group consisting of a source region surface, a drain region surface, and a gate electrode surface. In a more preferred embodiment, the desired contact surface is a combination of a gate electrode surface and a source and / or drain region surface.

  Etching can be performed by a method known in the art.For example, a material (for example, silicon) that forms an interlayer insulating film compared to a material (for example, polysilicon) that constitutes an element such as a source / drain or gate electrode structure. The process is performed under such a condition that the selection ratio to the oxide film is sufficiently high.

  When the desired contact surface is a combination of the surface of the gate electrode and the surface of the source region and / or the drain region, the desired contact surface is generally opened using two or more masks. Can be opened using a single mask. When two or more masks are used, the gate contact is less likely to cause a short circuit with other elements or wiring due to contact misalignment. Also good.

  The sidewall-like insulating film can be formed by etching back an insulating film deposited on at least the entire surface inside the hole (that is, the side wall portion and the bottom surface). Here, the contact hole “side wall portion” in this specification means a surface other than the bottom surface (that is, the surface on which a desired contact is formed) among the surfaces defining the contact hole, and is a laminated surface (silicon substrate). It also includes surfaces that are (substantially) parallel to the (main surface). Therefore, for example, when a layer (e.g., polysilicon layer) in the gate electrode structure is exposed substantially parallel to the stacked surface in the contact hole due to contact alignment deviation, the exposed surface is also a `` side wall part ''. include. In general, the insulating film is etched back after being deposited on the entire surface of the substrate including the surface inside the hole.

  The etch back is preferably anisotropic etching, more preferably full surface anisotropic etching. The insulating film may be made of any material as long as it provides electrical insulation, and is preferably a silicon nitride film or a silicon oxide film. The insulating film is preferably deposited using plasma.

  The insulating film is deposited to a thickness that corresponds to or exceeds the distance of the alignment deviation that is assumed or allowed in advance or the contact alignment that has occurred. For example, the insulating film is deposited to a thickness corresponding to the distance of the alignment deviation that is assumed or allowed in advance or the contact alignment that has occurred + the thickness of the contact etch back margin. The presumed or tolerable alignment deviation or the resulting contact alignment deviation is a technique or apparatus or system used to create a contact hole creation mask (e.g., photomask) on a semiconductor device. Depending on the specifications, the degree of integration or miniaturization of the semiconductor to be manufactured, or the generation, and the distance is, for example, 100 nm, 80 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm. The contact etch back margin is determined depending on the film quality of the insulating film and the etching conditions, and is, for example, 300 mm, 200 mm, 150 mm, 100 mm, 80 mm, 50 mm, or 30 mm.

  As one embodiment of the method of the present invention, an etching stopper layer is stacked on the surface of the impurity region where the contact surface is to be formed (on the substrate surface) and the contact hole is opened before forming the interlayer insulating film. Alternatively, the etching stopper layer may be first exposed, and then the contact surface may be exposed. The etching stopper layer is preferably also laminated on the top surface of the gate electrode structure or above or on the top surface or above and on the side. Here, the side part of the gate electrode structure refers to a side wall of the gate electrode structure itself and / or a side surface of a film (for example, a sidewall-like insulating film) provided in contact with a part or the whole of the side wall.

  Any material can be used for the etching stopper layer as long as it can have a sufficient selection ratio with respect to the material used for the interlayer insulating film (for example, silicon oxide-based material) under the etching conditions for the contact hole. (For example, silicon nitride oxide or aluminum oxide) can be used. Preferably, the etching stopper layer is formed of a silicon nitride film.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. 10 to 24 based on embodiments.
This embodiment is an example of a method for manufacturing a semiconductor device according to the present invention, which prevents an insulation failure (occurrence of a short circuit) between the second polysilicon film 10 on the gate electrode and the contact surface 20 due to the occurrence of misalignment during contact formation. An aspect is shown.

FIG. 10 is a plan structural view of a miniaturized flash memory manufactured by the manufacturing method according to the present invention and having a space between gate electrodes of 3400 mm.
11 (a) to 24 (a) show the manufacturing process of the present invention in the cross-sectional structural view taken along line xx-x in FIG. 11 (b) to 24 (b) show cross-sectional structural views taken along the line yy-y in FIG. 10, corresponding to FIGS. 11 (a) to 24 (a), respectively.

First, the main surface of the semiconductor silicon substrate 1 is separated into a plurality of element formation regions by the STI method.
As shown in FIG. 11, a first oxide film 2 is formed on the main surface of a semiconductor silicon substrate 1 made of silicon, and then a first insulating film (for example, silicon) is formed on the surface of the first oxide film 2. Nitride film 3) is formed 1600 mm.

Next, as shown in FIG. 12, a resist pattern 4 is formed on the first insulating film 3 formed on the semiconductor silicon substrate 1 with a predetermined region spaced apart, and the resist pattern 4 is used as a mask to form a first pattern. The insulating film 3 and the first oxide film 2 are sequentially etched.
Subsequently, as shown in FIG. 13, the element isolation region 5 is formed in the semiconductor silicon substrate 1 by etching the semiconductor silicon substrate 1 by about 2000 using the first insulating film 3 formed in FIG. 11 as a mask. To do.

Next, as shown in FIG. 14, a film (for example, silicon oxide film) 6 that can be electrically insulated is deposited on the entire surface of the semiconductor device by, for example, a CVD method to completely embed the element isolation region 5. .
Next, the CMP method, which is a known technique, is used to planarize the CVD silicon oxide film 6 and the first insulating film 3 simultaneously using the first insulating film 3 as a stopper. Then, the entire surface is wet-etched with phosphoric acid to remove it, and then the first oxide film 2 is removed (FIG. 15).
At this point, the main surface of the semiconductor silicon substrate 1 is separated into a plurality of element formation regions.

Thereafter, an element is formed in the separated element formation region to manufacture a semiconductor device.
As shown in FIG. 16, 95 mm of oxide film 7 is formed so as to cover the semiconductor device, 2000 mm of first polysilicon film 8 is formed thereon, and first polysilicon film 8 is polished by CMP. Then, a second insulating film 9 (for example, composed of three layers of a polysilicon oxide film (45 mm), a nitride film (55 mm), and an oxide film (80 mm)) is formed thereon. The second polysilicon film 10 is deposited by 2500 mm.

  Next, as shown in FIG. 17, a resist film is patterned in a predetermined region in the direction orthogonal to the element isolation region portion 5 with an interval (3400 mm), and using this as a mask, the second polysilicon film 10, The control gate 19 is formed by sequentially etching the second insulating film 9 and the first polysilicon film 8.

  Next, as shown in FIG. 18, the resist pattern film 11 is patterned in order to remove the oxide film in the region where the source region portion is to be formed, and the oxide film 7 is etched using this as a mask. The surface of the substrate 1 is exposed, and impurities are ion-implanted therein to form an impurity region portion to be a source region 21. Similarly, etching and impurity implantation are performed to form an impurity region portion to be a drain region 22.

Next, as shown in FIG. 19, a third insulating film 12 (1000 mm) is formed using a CVD method so as to cover the entire surface of the semiconductor device, and both side walls of the control gate 19 are formed by performing anisotropic etching on the entire surface. Then, a sidewall-like third insulating film 12 is formed.
Subsequently, as shown in FIG. 20, a plasma SIN film 13 (500 mm) is deposited using a CVD method so as to cover the entire surface of the semiconductor device.

  Thereafter, 16000 mm of BPSG film 14 is deposited using the CVD method so as to cover the entire surface of the semiconductor device. At this time, since the aspect ratio of the control gate 19 (about 3000 mm) and the space between the gate electrode and the gate electrode (3400 mm) is about 0.9 or less, voids in the BPSG film can be prevented (FIG. 26). , See Table 1). Subsequently, polishing is performed to planarize the BPSG film 14, contact holes 15 are formed by using a photo and etching technique, and the contact surface 20 is exposed. FIG. 21 shows a state in which the third insulating film 12 and the SIN film 13 are completely removed by etching, but depending on the material and etching conditions of these films, only a part of these films 12 and 13 is present. There may be a case where a substantial amount remains after the contact surface 20 is removed.

Next, as shown in FIG. 22, a fourth insulating film (for example, silicon nitride film) 16 is deposited using a 600-cm CVD method so as to cover the entire surface of the semiconductor device. The fourth insulating film 16 finally establishes insulation between the second polysilicon film 10 and the contact surface 20 and prevents a short circuit that may be caused by a void between the contact and the contact. The film thickness of the fourth insulating film 16 is determined by the alignment margin for each generation. Specifically, 600 mm when the alignment margin is 50 nm. Since the fourth insulating film 16 is electrically insulated, for example, a silicon oxide film or the like may be used.
Subsequently, as shown in FIG. 23, the fourth insulating film 16 formed in the contact 15 in FIG. While forming the film 16, the contact surface 20 is exposed on the surface of the impurity region 21.

Next, as shown in FIG. 24, tungsten 17 (4000 mm) is buried in the contact hole 15. At this time, as described above, the sidewall-like fourth insulating film 16 insulates between the second polysilicon film 10 and the tungsten 17, so that no short circuit occurs.
Finally, the METAL wiring 18 (4000 mm) is formed, and conduction with the surface of the semiconductor silicon substrate 1 is formed, so that a semiconductor device suitable for high integration can be manufactured.

  By the way, if the contact alignment shifts, for example, 50 nm during the etching of the contact hole 15 in FIG. 21, a part of the contact hole is formed above the gate electrode and the second polysilicon film may be exposed. is there. However, when the fourth insulating film 16 is deposited to a thickness of, eg, 600 mm in FIG. 22, the fourth insulating film having a thickness (β) extends to the top of the interlayer insulating film 14 on the exposed second polysilicon film. Therefore, the surface of the second polysilicon film 10 is not exposed even by the etch back in FIG. 23 (see FIG. 25). Therefore, a short circuit does not occur with the tungsten 17 embedded in the contact hole 15 (therefore, the contact surface 21 finally).

  As shown in FIG. 25, the film thickness A of the sidewall-like insulating film is determined by the relationship with the maximum penetration amount B (= contact alignment margin C) of the contact hole due to misalignment onto the gate electrode. Insulating film width A> maximum penetration amount B on the gate electrode due to misalignment. Here, if the maximum penetration amount B is estimated to be 0.05 μm, the film width A of the sidewall-like insulating film can be set to about 600 mm, for example. In this case, the space between the gate electrodes can be reduced to 0.22 μm, and a miniaturization process of 0.09 μm or later can be processed by the present invention. The maximum penetration amount B is reduced to 0.04 μm and 0.03 μm as the miniaturization progresses, and the film width A of the sidewall-like insulating film can be reduced in conjunction with it, so that the space between the gate electrodes can be further reduced.

  Further, since the side wall portion of the contact hole is covered with a sidewall-like insulating film, there is no problem of short circuit even if a void is formed between the contact and the contact. Therefore, element design that is not restricted by the aspect ratio (≈0.9) in which voids can be formed is possible, and the semiconductor device can be further miniaturized.

  In the above embodiment, the creation of the drain contact is described. However, the source contact and / or the gate contact may be made subsequently, or the source contact and / or the gate contact may be made simultaneously when the drain contact is made (that is, (With one mask).

  The above embodiments and examples are described as examples for facilitating the understanding of the present invention, and the present invention is limited to the specific configurations and arrangements described in this specification or the accompanying drawings. It should be noted that it is not limited. Those skilled in the art will recognize that the specific configurations, means, methods, and apparatus described herein can be replaced with many others known in the art without departing from the spirit and scope of the present invention. Should be understood and easily recognized.

It is a schematic sectional drawing explaining 1 process of the conventional semiconductor manufacturing method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing explaining 1 process of the conventional method. It is a schematic sectional drawing of the semiconductor device manufactured by the conventional method. It is a top view of the semiconductor device manufactured by the manufacturing method of the present invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing explaining 1 process in one form of the method of this invention. It is a schematic sectional drawing of the semiconductor device manufactured by one form of the method of this invention. It is a schematic sectional drawing of the semiconductor device manufactured when contact misalignment arises in one form of the method of this invention. It is a schematic sectional drawing of the semiconductor device manufactured by the method of this invention. It is a schematic sectional drawing of the semiconductor device before the interlayer insulation film lamination in the conventional method. It is a schematic sectional drawing of the semiconductor device after interlayer insulation film lamination in the conventional method.

Explanation of symbols

1: semiconductor silicon substrate 2: first oxide film 3: first insulating film 4: resist pattern 5: element isolation region 6: CVD silicon oxide film 7: oxide film 8: first polysilicon film (floating gate) film)
9: Second insulating film
10: Second polysilicon film
11: Resist pattern
12: Third insulation film
13: Plasma SIN film
14: BPSG film
15: Contact
16: Fourth insulation film
17: Tungsten
18: METAL wiring
19: Control gate
20: Contact surface
21: Source area
22: Drain region
101: Semiconductor silicon substrate
101a: Gate insulation film
102: Impurity region
102a: Gate polysilicon film
103a: Upper insulating film
104a: Upper polysilicon film
104b: Polysilicon oxide film
105a: Silicon nitride film (SIN)
106a: Silicon oxide film (SiO ₂ )
107a: Side wall polysilicon film
107b: Sidewall oxidized polysilicon film
107c: Oxide film
108a: Interlayer insulation film
109a: Contact hole
110a: Conductive layer
111a: Gate electrode

Claims (5)

Possess an interlayer insulating film covering a gate electrode structure consisting of a polysilicon film formed on the substrate surface this, and an aspect ratio between the gate electrode structure in the manufacturing method of greater than 0.9 the semiconductor device,
Forming a gate electrode made of a polysilicon film via a gate insulating film on the substrate surface;
Forming impurity regions on both sides of the gate electrode to form a source region and a drain region, respectively;
Laminating a film that can function as an etching stopper layer when opening a contact hole in contact with the surface of the gate electrode and the surface of the source region and / or the drain region without providing a hard mask on the gate electrode;
Forming an interlayer insulating film on the etching stopper layer;
Using one mask, a contact hole is opened on the etching stopper layer through the interlayer insulating film, and then the etching stopper layer is removed to expose the contact surface on the gate electrode and the source region and / or the drain region. The process of
Depositing an insulating film on at least the contact hole side wall and the contact surface to a thickness such that the gate electrode is not exposed from the sidewall-like insulating film after the etch back;
A method of manufacturing a semiconductor device comprising a step of forming a sidewall-like insulating film on a sidewall portion of a contact hole by etching back the insulating film. The method according to claim 1, wherein the height of the gate electrode structure is lower than 4600 mm, and the space between the gate electrode structures is 0.27 to 0.51 µm. The method according to claim 1 or 2 deposited insulating film is performed using the plasma. The method according to any one of claims 1 to 3 , wherein the insulating film is a silicon nitride film or a silicon oxide film. The method according to any one of claims 1 to 4, the gate electrode structure possesses single-poly gate electrode or stacked polysilicon gate electrode.

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