JP4556385B2 - Method for manufacturing magnetic memory device - Google Patents

Description

【０１２８】
表１に示したように、本実施例と比較例１，２とでは、ＭＲ変化率においては大差が見られなかったものの、スイッチング電流および隣接セル反転電流については、明らかな性能の向上が認められる。
【０１２９】
スイッチング電流とは、書込対象の記憶セルにおける磁化方向の反転をおこなうために必要な最小限の電流値である。このスイッチング電流については、本実施例が、比較例１の６．８ｍＡに対して５分の１未満の１．２ｍＡという小さな値を示した。これは、書込ワード線６およびビット線５によって貫かれるように環状磁性層４ａ，４ｂを設けたことにより、感磁層としての接続部分１４ａ，１４ｂの磁化反転を効率的に行うことができたので、小さな電流であっても書き込み操作が可能となったことを示す。比較例２と比較した場合にも、本実施例のほうが比較的小さなスイッチング電流となっていることから、環状磁性層４ａ，４ｂによって積層体Ｓ２０ａ，Ｓ２０ｂを取り囲むようにしたことによって、より効率的に接続部分１４ａ，１４ｂの磁化反転を行うことができ、より小さな電流であっても書き込み操作が可能となったことを示す。
【０１３０】
隣接セル反転電流とは、書込対象の記憶セルと隣接した記憶セルに印加された電流によって、本来、書込がなされるべきでない記憶セルの磁化方向が反転してしまう電流値を表す。表１に示したように、本実施例では、従来例よりも大きな書込電流を印加しても、隣接する記憶セルにおける磁化方向は反転しないことがわかった。これは、閉じた磁路を形成し、隣接する記憶セルに悪影響を及ぼす磁界の発生を抑制することができたことを示す。特に、比較例２と比べた場合にも本実施例のほうが比較的大きな隣接セル反転電流を示したことから、環状磁性層４ａ，４ｂによって積層体Ｓ２０ａ，Ｓ２０ｂを取り囲むようにしたことによって、隣接する記憶セルに悪影響を及ぼす磁界の発生をより確実に抑制することができたことを示す。
【０１３１】
以上説明したように、本実施例によれば、ＴＭＲ素子１２０ａ，１２０ｂが、積層面に沿った方向を軸方向とするように積層体Ｓ２０ａ，Ｓ２０ｂを取り囲むと共にビット線５および書込ワード線６によって軸方向に沿って貫かれるように構成された環状磁性層４ａ，４ｂ、を含むようにしたので、ビット線５と書込ワード線６の双方に電流を流すことによって閉じた磁路を形成することができ、ＴＭＲ素子１２０ａ，１２０ｂの接続部分１４ａ，１４ｂの磁化の反転をより効率よく行うことができると共に、書込対象とする記憶セルに隣接した記憶セルに対して、磁気的な影響を低減することができることがわかった。
【０１３２】
以上、いくつかの実施の形態を挙げて本発明を説明したが、本発明は、これらの実施の形態および変形例に限定されず、種々変形可能である。例えば、本実施の形態および各変形例では、逆流防止用の整流素子としてショットキーダイオードを用いるようにしたが、同じく整流作用を有する素子であるバイポーラトランジスタに置き換えることができる。
【０１３３】
図３１は、ＴＭＲ素子１２０ａ，１２０ｂと読出ワード線１２ａ，１２ｂとの間にバイポーラトランジスタ７６ａ，７６ｂを設けた場合の回路の要部構成を表している。図３２に、バイポーラトランジスタ７６ａ，７６ｂの断面構造を示す。バイポーラトランジスタ７６ａ，７６ｂのベースＢは、ワードデコード線７２に接続されている。各コレクタＣが接続層２８を介してそれぞれ環状磁性層４ａ，４ｂに接続されており、各エミッタＥが接続層２７を介していずれも読出ワード線１２に接続されている。
【０１３４】
図３３は、このバイポーラトランジスタ７６ａ，７６ｂを設けた場合における読出回路の全体を示したものである。この場合、Ｙ方向アドレスデコーダ回路５６Ａからの制御信号が例えば単位読出回路８０ｎのセンスアンプ回路５６Ｂに伝達されると、センスアンプ回路５６Ｂがビット線５ａ，５ｂを通るように読出電流を発する。Ｙ方向アドレスデコーダ回路５６Ａからの制御信号は同時に読出スイッチ８３ｎにも伝達され、この読出スイッチ８３ｎが導通状態となる。一方、Ｘ方向アドレスデコーダ回路５８Ａが記憶セル１ｍを選択し、ワードデコード線７２ｍを通るように制御信号を発する。バイポーラトランジスタ７６ａ，７６ｂのそれぞれのベースＢにＸ方向アドレスデコーダ回路５８Ａからの制御信号が伝達されると、コレクタＣとエミッタＥとの間がそれぞれ導通状態となる。この結果、読出電流が、記憶セル１ｍのＴＭＲ素子１２０ａ，１２０ｂを通過し、読出スイッチ８３ｎを経由して最終的に定電流回路５８Ｂへ流入する。ダイオード７５ａ，７５ｂと同様にバイポーラトランジスタ７６ａ，７６ｂも、一方向に電流を通過するように機能するので、図３７に示したような読出電流の回り込みを回避することが可能である。
【０１３５】
また、逆流防止用の整流素子として、図３４に示したように、ＭＯＳトランジスタ７７ａ，７７ｂを用いることができる。この場合、各ソースＳがそれぞれＴＭＲ素子１２０ａ，１２０ｂに接続し、各ドレインＤがいずれも読出ワード線１２に接続しており、ワードデコード線７２に接続されたゲートＧが閉じることにより導通状態とすることができる。図３５は、ＭＯＳトランジスタ７７ａ，７７ｂを設けた場合における読出回路の全体を示したものである。ゲートＧを閉じることによって導通状態とする点を除き、図３５に示した読出回路における読出動作は上記バイポーラトランジスタ７６ａ，７６ｂを用いた回路（図３３）と同様である。
【０１３６】
また、本実施の形態では、ビット線と書込ワード線とが互いに平行部分をなす場合について説明したが、これに限定されず、互いに例えば９０°をなすような場合であってもよい。ただし、平行部分を取り囲むように環状磁性層を形成する場合のほうが、感磁層の磁化反転がより効率的に行われるのでより好ましい。
【０１３７】
また、本実施の形態では、各記憶セルの情報の読み出しを、一対のＴＭＲ素子それぞれに流す読出電流の差分値を出力として行うようにしたが、これに限定されない。例えば、ある１つのＴＭＲ素子を通過する読出電流の値をそのまま出力させ、高抵抗状態にあるか低抵抗状態にあるかの検出をおこなうようにしてもよい。
【０１３８】
また、本実施の形態では、図７に示したように、各ＴＭＲ素子における積層体が上側（整流素子とは反対側）に配置されるようにしたが、これに限定されない。例えば、図３６に示したように、各ＴＭＲ素子において、積層体を下側（整流素子に近い側）に配置するようにしてもよい。
【０１４３】
【発明の効果】
本発明の磁気メモリデバイスの製造方法によれば、基体の上に、環状磁性層の一部をなす下部磁性層を形成する工程と、下部磁性層の上に、第１の絶縁膜を介して書込専用線を形成する工程と、書込専用線の上に、第２の絶縁膜を介して書込読出兼用線を、書込専用線および書込読出兼用線が互いに平行に延在する部分を含むように形成する工程と、書込読出兼用線と、第２の絶縁膜と、書込専用線とを順次エッチングしてパターニングすることにより、書込専用線および書込読出兼用線が第２の絶縁膜を挟んで互いに平行に延在する部分を含む積層パターンを形成する積層パターン形成工程と、積層パターンの側面を少なくとも覆うと共に下部磁性層と接するように環状磁性層の一部をなす一対の中間磁性層を形成する工程と、積層パターンの上面を露出させたのち、その上面の上に強磁性層と非磁性層とを順に積層することにより積層部分を形成する工程と、その積層部分における書込読出兼用線とは反対側の積層面と接し、かつ、一対の中間磁性層における上端と接するように第１の感磁層としての上部磁性層を設けることにより、積層体を形成すると共に積層部分および積層パターンを取り囲む環状磁性層を形成する工程とを含むようにしたので、積層部分における書込読出兼用線とは反対側の積層面のみと電気的に接するように、積層部分および積層パターンを取り囲むように設けられた環状磁性層が得られる。このため、書込読出兼用線に書込電流を流すことによって各感磁層の効率的な磁化反転に寄与する閉磁路を形成でき、感磁層の磁化反転に必要な書込電流をより小さくすることができるうえ、書込読出兼用線を介して各積層体に読出電流を供給することもできる。これにより、よりコンパクトな構成とすることができ、高密度化に有利となる。
【０１４４】
さらに、積層パターン形成工程において、書込読出兼用線をマスクとして第２の絶縁膜および書込専用線を選択的にエッチングすることにより、積層パターンを自己整合的に形成するようにしたので、アライメント精度の高い加工が可能となり、製造工程全体としていっそうの簡略化を図ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る磁気メモリデバイスの全体構成を示すブロック図である。
【図２】図１に示した磁気メモリデバイスの書込線の構成を示す平面図である。
【図３】図１に示した磁気メモリデバイスの記憶セル群の要部構成を示す部分平面図である。
【図４】図１に示した磁気メモリデバイスの記憶セル群の要部構成を示す要部斜視図である。
【図５】図３に示した記憶セルのＶ−Ｖ線に沿った切断面の構成を示す断面図である。
【図６】図１に示した磁気メモリデバイスの記憶セル群の要部構成を示す他の部分平面図である。
【図７】図６に示した記憶セルのＶII−ＶII線に沿った切断面の構成を示す断面図である。
【図８】図１に示した磁気メモリデバイスの回路構成を示す回路図である。
【図９】図８に示した回路構成における部分拡大図である。
【図１０】 図１に示した磁気メモリデバイスの製造方法における一工程を表す拡大断面図である。
【図１１】図１０に続く一工程を表す拡大断面図である。
【図１２】図１１に続く一工程を表す拡大断面図である。
【図１３】図１２に続く一工程を表す拡大断面図である。
【図１４】図１３に続く一工程を表す拡大断面図である。
【図１５】図１４に続く一工程を表す拡大断面図である。
【図１６】図１５に続く一工程を表す拡大断面図である。
【図１７】図１６に続く一工程を表す拡大断面図である。
【図１８】図１７に続く一工程を表す拡大断面図である。
【図１９】図１８に続く一工程を表す拡大断面図である。
【図２０】図１９に続く一工程を表す拡大断面図である。
【図２１】図２０に続く一工程を表す拡大断面図である。
【図２２】図２１に続く一工程を表す拡大断面図である。
【図２３】図２２に続く一工程を表す拡大断面図である。
【図２４】図２３に続く一工程を表す拡大断面図である。
【図２５】図２４に続く一工程を表す拡大断面図である。
【図２６】図２５に続く一工程を表す拡大断面図である。
【図２７】本発明の第２の実施の形態に係る磁気メモリデバイスにおける磁気抵抗効果素子の断面構成を示す断面図である。
【図２８】図２７に示した磁気抵抗効果素子の断面構成における書込電流方向と還流磁界方向（磁化方向）との関係を表す説明図である。
【図２９】本発明の第３の実施の形態に係る磁気メモリデバイスにおける磁気抵抗効果素子の断面構成を示す断面図である。
【図３０】図２９に示した磁気抵抗効果素子の断面構成における書込電流方向と還流磁界方向（磁化方向）との関係を表す説明図である。
【図３１】図８に示した回路構成における整流素子の変形例を表す部分拡大図である。
【図３２】図３１に示した整流素子の変形例における断面構成を示す部分断面図である。
【図３３】図３１に示した整流素子の変形例における全体の回路構成を示す回路図である。
【図３４】図８に示した回路構成における整流素子の他の変形例を表す部分拡大図である。
【図３５】図３４に示した整流素子の他の変形例における全体の回路構成を示す回路図である。
【図３６】図１に示した磁気メモリデバイスにおける変形例としての記憶セルの断面構成を示す断面図である。
【図３７】図８に示した回路構成に対応する比較例としての回路構成を示す回路図である。
【図３８】従来例としての磁気メモリデバイスの構成を説明するための平面図である。
【図３９】従来例としての磁気メモリデバイスの要部構成を説明するための断面図である。
【図４０】比較例としての磁気メモリデバイスの要部構成を説明するための断面図である。
【図４１】他の比較例としての磁気メモリデバイスの要部構成を説明するための断面図である。
【符号の説明】
１…記憶セル、２…第１磁性層、３…トンネルバリア層、４…環状磁性層、５…ビット線、６…書込ワード線、７…絶縁膜、８…第２磁性層、９…非磁性導電層、１０…平行部分、１２…読出ワード線、１４…接続部分、１９…積層パターン、Ｓ２０，Ｓ２１，Ｓ２２…積層体、４１…書込ワード線引出電極、４２…ビット線引出電極、４３…読出ワード線引出電極、１２０ａ，１２０ｂ…磁気抵抗効果（ＴＭＲ）素子。[0001]
BACKGROUND OF THE INVENTION
  The present invention provides an external magnetic fieldDepending on the magnetosensitive layerMagnetic memory device that records and reads information using changes in magnetization directionOfIt relates to a manufacturing method.
[0002]
[Prior art]
Conventionally, volatile memories such as DRAM (Dynamic Rabdom Access Memory) and SRAM (Static RAM) have been used as general-purpose memories used in information processing apparatuses such as computers and communication devices. In these volatile memories, it is necessary to constantly supply current and perform refresh in order to retain the memory. Further, since all information is lost when the power is turned off, it is necessary to provide a non-volatile memory as a means for recording information in addition to these volatile memories. For example, a flash EEPROM or a magnetic hard disk device is used. It is done.
[0003]
In these nonvolatile memories, speeding up access is an important issue as information processing speeds up. Further, along with the rapid spread and high performance of portable information devices, development of information devices aiming at so-called ubiquitous computing that can perform information processing anywhere and anytime is rapidly progressing. As a key device that plays a central role in the development of such information equipment, there is a strong demand for the development of a nonvolatile memory that supports high-speed processing.
[0004]
As an effective technique for increasing the speed of the nonvolatile memory, a magnetic random access memory (hereinafter referred to as MRAM; Magnetic) in which magnetic memory elements for storing information according to the magnetization direction along the easy axis of the ferromagnetic layer are arranged in a matrix form. known as random access memory). In the MRAM, information is stored using a combination of magnetization directions in two ferromagnetic materials. On the other hand, reading of stored information is performed by detecting a resistance change (that is, a change in current or voltage) that occurs depending on whether the magnetization direction is parallel or antiparallel to a certain reference direction. In order to perform stable writing and reading in the MRAM, it is important that the rate of change in resistance is as large as possible because of the operation based on such a principle.
[0005]
The MRAM that is currently in practical use utilizes a giant magneto-resistive (GMR) effect. The GMR effect means that when two magnetic layers are arranged so that the easy magnetization directions of the respective layers are parallel to each other, the resistance value is minimum when the magnetization directions of the respective layers are parallel to the easy magnetization axis. This is a phenomenon that is maximum when antiparallel. As an MRAM using a GMR element that can obtain such a GMR effect (hereinafter referred to as GMR-MRAM), for example, a technique disclosed in Patent Document 1 is known.
[0006]
The GMR-MRAM includes a coercive force difference type (pseudo spin valve type) and an exchange bias type (spin valve type). In the coercive force difference type MRAM, a GMR element has two ferromagnetic layers and a nonmagnetic layer sandwiched between them, and information writing and writing are performed using the coercive force difference between the two ferromagnetic layers. Reading is performed. Here, when the GMR element has a configuration of “nickel iron alloy (NiFe) / copper (Cu) / cobalt (Co)”, for example, the resistance change rate is a small value of about 6 to 8%. On the other hand, in an exchange bias type MRAM, a GMR element includes a fixed layer whose magnetization direction is fixed by antiferromagnetic coupling with an antiferromagnetic layer, a free layer whose magnetization direction is changed by an external magnetic field, and a gap between them. The non-magnetic layer is sandwiched, and information is written and read using the difference in magnetization direction between the fixed layer and the free layer. For example, when the configuration of the GMR element is “platinum manganese (PtMn) / cobalt iron (CoFe) / copper (Cu) / CoFe”, the resistance change rate is about 10%, which is larger than the coercivity difference type. However, it was insufficient to achieve further improvement in storage speed and access speed.
[0007]
In order to solve these points, an MRAM having a TMR element using a tunneling magneto-resistive (TMR) (hereinafter referred to as TMR-MRAM) has been proposed. The TMR effect is an effect that a tunnel current flowing through an insulating layer changes depending on a relative angle of a magnetization direction between two ferromagnetic layers sandwiching an extremely thin insulating layer (tunnel barrier layer). The resistance value is minimum when the magnetization directions of the two ferromagnetic layers are parallel to each other, and is maximum when the magnetization directions are antiparallel to each other. In the TMR-MRAM, when the TMR element has a configuration of “CoFe / aluminum oxide / CoFe”, for example, when the resistance change rate is as high as about 40% and the resistance value is large, it is combined with a semiconductor device such as a MOSFET. Easy to match. Therefore, a higher output can be easily obtained as compared with GMR-MRAM, and an improvement in storage capacity and access speed is expected. In TMR-MRAM, a method is known in which information is stored by changing the magnetization direction of a magnetic film of a TMR element in a predetermined direction by a current magnetic field generated by passing a current through a conducting wire. As a method of reading stored information, a method of detecting a change in resistance of a TMR element by flowing a current in a direction perpendicular to the tunnel barrier layer is known. As for TMR-MRAM, the technique disclosed in Patent Document 2 or Patent Document 3 is known.
[0008]
[Patent Document 1]
US Pat. No. 5,343,422
[Patent Document 2]
US Pat. No. 5,629,922
[Patent Document 3]
Japanese Patent Laid-Open No. 9-91949
[0009]
[Problems to be solved by the invention]
As described above, the MRAM using the TMR effect can achieve higher output than the MRAM using the GMR effect. However, even an MRAM using a TMR element exhibiting a resistance change rate of about 40% as described above has an output voltage of about several tens of mV, which is inconvenient for realizing a higher-density magnetic memory device. It is enough.
[0010]
FIG. 38 is a plan view for explaining a configuration of a conventional magnetic memory device using the TMR effect, and FIG. 39 shows a cross-sectional configuration of a main part of the conventional magnetic memory device corresponding to FIG. The write bit line 105 is orthogonal to the read word line 112 and the write word line 106 extending in parallel to each other, and the first magnetic layer 102, the tunnel barrier layer 103, and the region sandwiched in the Z direction at the orthogonal portion A TMR element 120 made of the second magnetic layer 104 is provided. In such a type of MRAM in which the write bit line 105 and the write word line 106 are orthogonal to each other, the magnetization direction in the second magnetic layer 104 functioning as a free layer cannot be sufficiently aligned, It was difficult to perform sufficiently stable writing.
[0011]
Further, in the MRAM using the TMR effect, information is stored in each memory cell by changing the magnetization direction of the magnetic film by the induced magnetic field caused by the current flowing through the orthogonally arranged conducting wires, that is, the current magnetic field. However, since this current magnetic field is an open magnetic field (not magnetically confined in a specific region), the current magnetic field is low in efficiency, and there is a concern about an adverse effect on an adjacent storage cell.
[0012]
Furthermore, when the memory cells are further integrated to further increase the density of the magnetic memory device, the TMR element must be miniaturized, but the following problems are concerned. That is, the demagnetizing field increases as the aspect ratio (thickness / width in the in-plane direction) of each magnetic layer in the TMR element increases, and the magnetic field strength for changing the magnetization direction of the free layer increases. It is considered that a write current is required.
[0013]
  SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and a first object of the present invention is to achieve stable writing by efficiently using a magnetic field formed by currents flowing through a plurality of conductors, while having a compact configuration. Magnetoresistive effect elementMethod of manufacturing a magnetic memory device having a childIs to provide. The second purpose is to provide a magnetoresistive element that hardly adversely affects adjacent magnetoresistive elements.Method of manufacturing a magnetic memory device having a childIs to provide.
[0014]
[Means for Solving the Problems]
  A method of manufacturing a magnetic memory device according to the present invention includes a plurality of write-only lines, a plurality of write / read lines extending so as to intersect with the plurality of write-only lines, and a ferromagnetic layer having a fixed magnetization direction A non-magnetic layer and a non-magnetic layer configured to allow current to flow in a direction perpendicular to the stacking surface, and to surround the stacking portion so that the direction along the stacking surface is the axial direction, A plurality of annular magnetic layers including a first magnetosensitive layer that is configured to be penetrated along the axial direction by a write-only line, and whose magnetization direction is changed by an external magnetic field to form a stacked body together with the stacked portion This method includes the following steps (A) to (G).
(A) A step of forming a lower magnetic layer forming a part of the annular magnetic layer on the substrate.
(B) A step of forming a write-only line on the lower magnetic layer extending in a direction along the laminated surface via the first insulating film.
(C) A write / read line is formed on the write-only line through the second insulating film so as to include a portion in which the write-only line and the write / read line are extended in parallel to each other. Process.
(D) The write / read line, the second insulating film, and the write-only line are sequentially etched and patterned, so that the write-only line and the write / read line sandwich the second insulating film. A laminated pattern forming step of forming a laminated pattern including portions extending in parallel with each other.
(E) A step of forming a pair of intermediate magnetic layers forming a part of the annular magnetic layer so as to cover at least the side surface of the laminated pattern and be in contact with the lower magnetic layer.
(F) A step of forming a laminated portion by exposing the upper surface of the laminated pattern and then laminating a ferromagnetic layer and a nonmagnetic layer in that order on the upper surface.
(G) By providing the upper magnetic layer as the first magnetosensitive layer in contact with the laminated surface opposite to the write / read line in the laminated portion and in contact with the upper ends of the pair of intermediate magnetic layers, Forming a laminated body and forming an annular magnetic layer surrounding a laminated portion and a laminated pattern;
  In the laminated pattern formation step, the laminated pattern is formed in a self-aligned manner by selectively etching the second insulating film and the write-only line using the write / read line as a mask.
  Here, “external magnetic field” in the present invention means a magnetic field generated by a current flowing through a plurality of conductive wires, or a reflux magnetic field generated in an annular magnetic layer. Also, the “annular” of the “annular magnetic layer” penetrates the inside.Write-read shared line and write-only lineWhen entangled, the surroundings of each are completely and continuously taken in magnetically and electrically,Write-read shared line and write-only lineThe cross section of the direction which crosses is shown in the closed state. Therefore, the annular magnetic layer allows an insulator to be contained as long as it is magnetically and electrically continuous. That is, an insulator that does not flow current is not included, but an oxide film that is generated in the manufacturing process may be included. The “axial direction” refers to the opening direction when attention is paid to the annular magnetic layer alone, that is, the extending direction of a plurality of conductors penetrating the inside.The Also, “Write / read line and write-only line”`` To be penetrated by '' means a region or space surrounded by an annular magnetic layer.Write / read shared line and write dedicated lineShows the state of penetrating.Furthermore, “the write-only line and the write / read line are parallel to each other across the second insulating film” includes a manufacturing error range of ± 10 °.
[0019]
  In the method for manufacturing a magnetic memory device of the present invention, the above steps are provided so as to surround the laminated portion and the laminated pattern so as to be in electrical contact with only the laminated surface on the opposite side to the write / read line in the laminated portion. An annular magnetic layer is obtained. Therefore, when a write current flows through the write / read line, a closed magnetic path that contributes to efficient magnetization reversal of each magnetosensitive layer is formed, and each stacked body is connected via the write / read line. A read current is supplied.
  In addition, in the stacked pattern forming step, the stacked pattern is formed in a self-aligned manner by selectively etching the second insulating film and the write-only line using the write / read shared line as a mask. While processing with high alignment accuracy can be performed, a resist pattern forming process and a removing process thereof can be omitted, and the entire manufacturing process can be simplified.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
[First Embodiment]
First, the configuration of the magnetic memory device according to the first embodiment will be described with reference to FIGS.
[0022]
FIG. 1 is a conceptual diagram showing the overall configuration of a magnetic memory device according to the present embodiment. The magnetic memory device includes an address buffer 51, a data buffer 52, a control logic unit 53, a memory cell group 54, a first drive control circuit unit 56, a second drive control circuit unit 58, and an external address input. Terminals A0 to A20 and external data terminals D0 to D7 are provided.
[0023]
The memory cell group 54 includes a large number of memory cells 1 each having a pair of tunnel magnetoresistive elements (hereinafter referred to as TMR elements) in a word line direction (X direction) and a bit line direction (Y direction) orthogonal to each other. It has an arrayed matrix structure. The memory cell 1 is a minimum unit for storing data in the magnetic memory device. The memory cell 1 will be described in detail later.
[0024]
The first drive control circuit unit 56 includes an address decoder circuit 56A, a sense amplifier circuit 56B, and a current drive circuit 56C in the Y direction, and the second drive control circuit unit 58 includes an address decoder circuit 58A in the X direction, and a constant drive circuit 56C. The circuit has a current circuit 58B and a current drive circuit 58C.
[0025]
The address decoder circuits 56A and 58A select the subsequent word decode line 72 and bit decode line 71 in accordance with the input address signal. The sense amplifier circuit 56B and the constant current circuit 58B are circuits that are driven when a read operation is performed, and the current drive circuits 56C and 58C are circuits that are driven when a write operation is performed.
[0026]
Sense amplifier circuit 56B and memory cell group 54 are connected by a plurality of bit decode lines 71 (described later) through which a sense current flows during a read operation. Similarly, the constant current circuit 58B and the memory cell group 54 are connected by a plurality of word decode lines 72 (described later) through which a sense current flows during a read operation.
[0027]
The current drive circuit 56C and the memory cell group 54 are connected to each other via a write word line 6 (described later) necessary for the write operation. Similarly, the current drive circuit 58C and the memory cell group 54 are connected via a write word line 6 (described later) that is necessary for the write operation.
[0028]
The address buffer 51 includes external address input terminals A0 to A20, a Y-direction address decoder circuit 56A in the first drive control circuit unit 56, a second-direction address line 57, and an X-direction address line 55. The X-direction address decoder circuit 58A in the drive control circuit unit 58 is connected. The address buffer 51 receives external address signals from external address input terminals A0 to A20, and is required in the Y-direction address decoder circuit 56A and the X-direction address decoder circuit 58B by an internal buffer amplifier (not shown). Is amplified to a voltage level of Further, the address buffer 51 divides the amplified address signal into two and outputs the divided address signal to the Y-direction address decoder circuit 56A via the Y-direction address line 57 and also to the X-direction address decoder circuit via the X-direction address line 55. It functions to output to 58A.
[0029]
The data buffer 52 includes an input buffer 52A and an output buffer 52B, includes external data terminals D0 to D7, is connected to the control logic unit 53, and operates according to an output control signal 53A from the control logic unit 53. It has become. The input buffer 52A is connected to the Y-direction current drive circuit 56C in the first drive control circuit unit 56 and the X in the second drive control circuit unit 58 via the Y-direction and X-direction write data buses 61 and 60, respectively. When the write operation to the memory cell group 54 is performed, the signal voltage of the external data terminals D0 to D7 is taken in and is required by an internal buffer amplifier (not shown). After the voltage level is amplified to a predetermined voltage level, the data is transmitted to the X-direction current drive circuit 58C and the Y-direction current drive circuit 56C via the X-direction write data bus 60 and the Y-direction write data bus 61. The output buffer 52B is connected to the sense amplifier circuit 56B via the Y-direction read data bus 62. When reading the information signal stored in the memory cell group 54, an output buffer 52B (not shown) is provided. 2), after amplifying the information signal input from the sense amplifier circuit 56B, it functions to output to the external data terminals D0 to D7 with low impedance.
[0030]
The control logic unit 53 includes a chip select terminal CS and a write enable terminal WE, and is connected to the data buffer 52. The control logic unit 53 functions to output a signal voltage from a chip select terminal CS for selecting a memory cell group 54 to be read and written, and a write enable signal. It functions to take in the signal voltage from the terminal WE and output the output control signal 53A to the data buffer 52.
[0031]
Next, the configuration related to the information writing operation in the magnetic memory device of the present embodiment will be described.
[0032]
FIG. 2 is a conceptual diagram showing a main part plane configuration related to the write operation in the memory cell group 54. As shown in FIG. 2, the magnetic memory device of the present embodiment has a plurality of bit lines 5a and 5b for both writing and reading, and a plurality of bit lines 5a and 5b extending so as to intersect with each other. In each region where the bit lines 5a and 5b and the write word line 6 intersect, a parallel portion 10 in which the bit line 5 and the write word line 6 extend in parallel to each other is included. It is comprised so that it may have. Specifically, as shown in FIG. 2, while the write word line 6 extends in a rectangular wave shape along the X direction, the bit lines 5a and the bit lines 5b are alternately arranged in a straight line. Extends along the direction. The rising and falling portions of the rectangular wave shape in the write word line 6 form a plurality of parallel portions 10 together with the bit lines 5a and 5b. The TMR elements 120 a and 120 b constituting the memory cell 1 are provided in each region where the bit lines 5 a and 5 b intersect with the write word line 6 so as to surround at least a part of each parallel portion 10. Specifically, the TMR element 120a is provided in the intersection region between the bit line 5a and the write word line 6, and the TMR element 120b is provided in the intersection region between the bit line 5b and the write word line 6. . Here, the fact that the TMR elements 120a and 120b are provided in the intersecting region includes the case where the TMR elements 120a and 120b are provided next to the intersection. The TMR element 120a and the TMR element 120b are both specific examples corresponding to the “magnetoresistance effect element” of the present invention.
[0033]
Currents from the Y-direction current drive circuit 58C and the X-direction current drive circuit 56C flow through the bit lines 5a and 5b and the write word line 6, respectively. Here, the current flowing through the bit line 5a and the current flowing through the bit line 5b are always opposite to each other. For example, as shown by the arrows in FIG. In the case of (from bottom to top), the current direction of the bit line 5b is the -Y direction (from the top to the bottom of the page). Therefore, in this case, assuming that the direction of the current flowing through the write word line 6 is the + X direction as a whole (from left to right in the drawing), the current direction of the bit line 5a and the write word line 6 passing through the inside of the TMR element 120a. Are parallel to each other (in the same direction). On the other hand, the current directions of the bit line 5b and the write word line 6 passing through the inside of the TMR element 120b are also parallel to each other. In the following description, the bit lines 5a and 5b are simply referred to as the bit line 5 when it is not necessary to distinguish the current direction.
[0034]
FIG. 3 more specifically shows the planar configuration of the main part of the memory cell group 54. The bit lines 5a and 5b, the write word line 6, and the memory cell 1 shown in FIG. 3 correspond to FIG. The memory cell 1 includes a TMR element 120a and a TMR element 120b, and is arranged in a parallel portion 10 between the bit lines 5a and 5b and the write word line 6 along the Y direction. Each of the TMR elements 120a and 120b includes a stacked body S20 (S20a and S20b) including a magnetosensitive layer and an annular magnetic layer 4 (4a and 4b). The bit lines 5a and 5b and the write word in the parallel portion 10 are provided. The magnetization direction of the magnetosensitive layer is changed by a magnetic field (that is, an external magnetic field in the annular magnetic layer 4) generated by a current flowing through both lines 6. In this case, the bit lines 5a and 5b and the write word line 6 in the parallel portion 10 are provided at substantially coincident positions in the XY plane, but are arranged so as to have a constant interval in the Z direction. They are electrically isolated from each other.
[0035]
Bit line lead electrodes 42 are provided at both ends of each bit line 5. Each bit line lead electrode 42 is connected such that one is connected to the Y-direction current drive circuit 56C and the other is finally grounded. Similarly, write word line lead electrodes 41 are provided at both ends of each write word line 6. Each write word line lead electrode 41 is connected such that one is connected to the X direction current drive circuit 58C and the other is finally grounded.
[0036]
FIG. 4 is an enlarged perspective view of the memory cell 1. The write word line 6 that is a write-only line and the bit lines 5a and 5b that are write / read lines extend parallel to each other and penetrate the annular magnetic layers 4a and 4b. The write word line 6, the bit lines 5a and 5b, and the annular magnetic layers 4a and 4b are electrically insulated from each other through insulating films 7a and 7b. The stacked portions 20a and 20b forming part of the stacked bodies S20a and S20b have one surface electrically connected to the inner walls of the annular magnetic layers 4a and 4b and the other surface electrically connected to the bit lines 5a and 5b. The annular magnetic layers 4a and 4b and the bit lines 5a and 5b are disposed so as to be connected. Further, the annular magnetic layers 4a and 4b are electrically connected to the read word line 12 extending in the X direction via Schottky diodes 75a and 75b (described later) not shown in FIG. The read word line 12 is directly connected to the annular magnetic layer 4, the bit lines 5a, 5b or the write word line 6 except that it is connected to the annular magnetic layers 4a, 4b via Schottky diodes 75a, 75b. It is electrically insulated without contact. With such a structure, the current supplied from the bit lines 5a and 5b to the stacked portions 20a and 20b can be guided to the read word line 12 via the annular magnetic layers 4a and 4b and the Schottky diodes 75a and 75b. it can.
[0037]
FIG. 5 illustrates a cross-sectional configuration of the TMR elements 120a and 120b in the memory cell 1 illustrated in FIG.
[0038]
As shown in FIG. 5, the TMR elements 120a and 120b include stacked bodies S20a and S20b each including a magnetosensitive layer whose magnetization direction is changed by an external magnetic field and configured to allow current to flow in a direction perpendicular to the stacked surface. The annular magnetic layer is configured to surround the stacked bodies S20a and S20b so that the direction along the stacked surface is the axial direction and to be penetrated along the axial direction by the bit lines 5a and 5b and the write word line 6 4a and 4b.
[0039]
The stacked bodies S20a and S20b are configured by stacked portions 20a and 20b and connection portions 14a and 14b that face the stacked portions 20a and 20b and form part of the annular magnetic layers 4a and 4b. These connection portions 14a and 14b correspond to a specific example of the “magnetic layer” in the present invention. Further, the stacked bodies S20a and S20b are formed of aluminum oxide (Al₂O_Three) And the like, and the first magnetic layers 2a and 2b made of a ferromagnetic material and having a fixed magnetization direction so that a current flows in a direction perpendicular to the laminated surface. It is configured. Here, the tunnel barrier layers 3a and 3b are one specific example corresponding to the “nonmagnetic layer” in the present invention. In FIG. 5A, in order to clarify the configuration of the stacked bodies S20a and S20b, the dimensions are exaggerated relatively larger than the surroundings.
[0040]
When a voltage in the vertical direction is applied to the stacked surface between the first magnetic layers 2a, 2b and the connection portions 14a, 14b of the annular magnetic layers 4a, 4b, the stacked bodies S20a, S20b, for example, the first magnetic layers 2a, 2b Electrons pass through the tunnel barrier layers 3a and 3b and move to the connection portions 14a and 14b so that a tunnel current flows. This tunnel current varies depending on the relative angle between the spins of the first magnetic layers 2a and 2b and the spins of the connection portions 14a and 14b at the interface with the tunnel barrier layers 3a and 3b. That is, the resistance value is minimized when the spins of the first magnetic layers 2a and 2b and the spins of the connection portions 14a and 14b are parallel to each other, and the resistance value is maximized when the spins are antiparallel. Using these resistance values, the magnetoresistance change rate (MR ratio) is defined as in equation (1).
[0041]
(MR ratio) = dR / R (1)
[0042]
Here, “dR” is the difference in resistance value between when the spins are parallel to each other and anti-parallel, and “R” is the resistance value when the spins are parallel to each other.
[0043]
The resistance value against the tunnel current (hereinafter referred to as tunnel resistance Rt) strongly depends on the film thickness T of the tunnel barrier layers 3a and 3b. In the low voltage region, the tunnel resistance Rt increases exponentially with respect to the film thickness T of the tunnel barrier layers 3a and 3b as shown in the equation (2).
[0044]
Rt∝exp (2χ^T), Χ = {8π²m^*(Φ ・ Ef)^0.5} / H (2)
[0045]
Where “φ” is the barrier height, “m”^*"Represents the effective mass of electrons," Ef "represents Fermi energy, and h represents Planck's constant. In general, in a memory element using a TMR element, a tunnel resistance Rt is several tens kΩ · (μm) in order to match with a semiconductor device such as a transistor.²Degree is appropriate. However, in order to increase the density and increase the operation speed in the magnetic memory device, the tunnel resistance Rt is 10 kΩ · (μm).²Or less, more preferably 1 kΩ · (μm)²The following is preferable. Therefore, in order to realize the tunnel resistance Rt, it is desirable that the thickness T of the tunnel barrier layers 3a and 3b is 2 nm or less, more preferably 1.5 nm or less.
[0046]
By reducing the thickness T of the tunnel barrier layers 3a and 3b, the tunnel resistance Rt can be reduced, while leakage due to unevenness at the junction interface between the first magnetic layers 2a and 2b and the connection portions 14a and 14b. Since current is generated, the MR ratio is lowered. In order to prevent this, the thickness T of the tunnel barrier layers 3a and 3b needs to have such a thickness that leakage current does not flow. Specifically, the thickness T is preferably 0.3 nm or more.
[0047]
The stacked bodies S20a and S20b shown in FIG. 5 have a coercivity difference structure, and are configured such that the coercivity of the first magnetic layers 2a and 2b is larger than the coercivity of the connection portions 14a and 14b. It is desirable that Specifically, the coercive force of the first magnetic layers 2a and 2b is (50 / 4π) × 10.^ThreeIt is desirable to be larger than A / m, in particular, (100 / 4π) × 10^ThreeA / m or more is desirable. By doing so, it is possible to prevent the magnetization directions in the first magnetic layers 2a and 2b from being influenced by an unnecessary magnetic field such as an external disturbing magnetic field. The first magnetic layers 2a and 2b are made of, for example, a cobalt iron alloy (CoFe) having a thickness of 5 nm. In addition, single cobalt (Co), cobalt platinum alloy (CoPt), nickel iron cobalt alloy (NiFeCo), or the like can be applied to the first magnetic layers 2a and 2b. Moreover, it is desirable that the easy magnetization axes of the first magnetic layers 2a and 2b and the easy magnetization axes of the connection portions 14a and 14b are parallel to each other. By doing so, the respective magnetization directions are stabilized in a state of being parallel or antiparallel to each other.
[0048]
The annular magnetic layers 4 a and 4 b extend so as to annularly surround at least a part of the parallel portion 10 in the bit lines 5 a and 5 b and the write word line 6, and the annular magnetic layer is generated by a current flowing through the parallel portion 10. 4a and 4b are configured to generate a reflux magnetic field. Of the annular magnetic layers 4a and 4b, the connection portions 14a and 14b adjacent to the stacked portions 20a and 20b function as a storage layer for storing information. The annular magnetic layers 4a and 4b are made of, for example, a nickel iron alloy (NiFe), and the thickness of the connection portions 14a and 14b is about 20 nm. Further, the coercive force of the connecting portions 14a and 14b is (50 / 4π) × 10.^ThreeA / m or more (100 / 4π) × 10^ThreeIt is desirable to be within a range of A / m or less and to be smaller than the coercive force of the first magnetic layers 2a and 2b. (50 / 4π) × 10^ThreeThis is because with the coercive force of less than A / m, the magnetization direction in the connection portions 14a and 14b may be disturbed by an unnecessary magnetic field such as an external disturbing magnetic field. On the other hand, (100 / 4π) × 10^ThreeThis is because with a coercive force exceeding A / m, the TMR elements 120a and 120b themselves may be deteriorated due to heat generated by an increase in write current. Furthermore, when the coercivity of the connection portions 14a and 14b is equal to or greater than the coercivity of the first magnetic layers 2a and 2b, the write current increases and the magnetization direction of the first magnetic layers 2a and 2b as the magnetization fixed layers This is because the function of the TMR elements 120a and 120b as memory elements is deteriorated. Further, in order to concentrate the current magnetic field generated by the bit lines 5a and 5b and the write word line 6 on the annular magnetic layers 4a and 4b, it is preferable that the magnetic permeability of the annular magnetic layers 4a and 4b is larger. Specifically, it is 2000 or more, more preferably 6000 or more.
[0049]
Each of the bit lines 5a and 5b and the write word line 6 has a structure in which, for example, 10 nm thick titanium (Ti), 10 nm thick titanium nitride (TiN), and 500 nm thick aluminum (Al) are sequentially stacked. And are electrically insulated from each other by the insulating films 7a and 7b. The bit lines 5a and 5b and the write word line 6 may be made of at least one of aluminum (Al), copper (Cu), and tungsten (W), for example. A more specific writing operation for the TMR elements 120a and 120b using the bit lines 5a and 5b and the write word line 6 will be described later.
[0050]
Next, a configuration related to the information reading operation will be described. FIG. 6 shows a plan configuration of a main part related to a read operation in the memory cell group 54, and corresponds to FIG.
[0051]
As shown in FIG. 6, each memory cell 1 is disposed in the vicinity of each intersection of the plurality of read word lines 12 and the plurality of bit lines 5a and 5b in the XY plane. Here, the read word line 12 is electrically connected to the stacked bodies S20a and S20b in the TMR elements 120a and 120b of each memory cell 1 through Schottky diodes 75a and 75b. The pair of bit lines 5a and 5b supplies a read current to each of the TMR elements 120a and 120b, and one read word line 12 supplies the read current flowing in each of the TMR elements 120a and 120b to the ground. It is a guide. Bit line extraction electrodes 43 are provided at both ends of each read word line 12. Here, the read word line 12 is a specific example corresponding to the “read-only line” of the present invention.
[0052]
7 (FIGS. 7A and 7B) shows a cross-sectional configuration of the memory cell 1 shown in FIG. 6 in the direction of the arrow along the VII-VII cutting line. As shown in FIG. 7, the memory cell 1 includes a pair of base cells 11 provided with a pair of Schottky diodes 75a and 75b (hereinafter simply referred to as diodes 75a and 75b) functioning as rectifying elements. TMR elements 120a and 120b. The pair of TMR elements 120a and 120b are formed in regions corresponding to the diodes 75a and 75b, respectively. Here, the “rectifying element” refers to an element that allows current to pass only in one direction and prevents passage of current in the reverse direction.
[0053]
The pair of diodes 75a and 75b includes conductive layers 24a and 24b, an epitaxial layer 25, and a substrate 26 in this order from the TMR elements 120a and 120b, and each of the pair of diodes 75a and 75b is shot between the conductive layers 24a and 24b and the epitaxial layer 25. It forms a key barrier. The diode 75a and the diode 75b are connected to the annular magnetic layer 4a and the annular magnetic layer 4b, respectively. The substrate 26 is an n-type silicon wafer. In general, an impurity diffusion of phosphorus (P) is performed on an n-type silicon wafer.⁺⁺Use a mold. On the other hand, in the epitaxial layer 25, phosphorus is diffused at a low concentration so that n^-Make it a mold. This n^-By bringing the epitaxial layer 25, which is a type semiconductor, into contact with the conductive layers 24a and 24b made of metal, a band gap is generated and a Schottky barrier is formed. Further, the pair of diodes 75a and 75b are connected to the read word line 12 via the connection layer 12T.
[0054]
Next, with reference to FIG. 8, a circuit configuration related to the read operation in the magnetic memory device of the present embodiment will be described.
[0055]
FIG. 8 is a configuration diagram of a circuit system including the memory cell group 54 and its readout circuit. This readout circuit system is a differential amplification type in which the memory cell 1 is composed of a pair of TMR elements 120a and 120b. Here, reading of information in each memory cell 1 flows into each of the stacked bodies S20a and S20b in the TMR elements 120a and 120b (flows from the bit lines 5a and 5b into the stacked bodies S20a and S20b, respectively) The difference value of the current flowing into the word line 12 is output as an output.
[0056]
In FIG. 8, unit cell read circuit 80 (..., 80 n, 80 n + 1,. Are arranged in parallel in the bit string direction. Each of unit read circuits 80n is connected to Y direction address decoder circuit 56A via bit decode lines 71 (..., 71n, 71n + 1,...), And connected to output buffer 52B via Y direction read data bus 62. ing.
[0057]
In the memory cell group 54, a matrix-like wiring is formed by read word lines 12 (..., 12m, 12m + 1,...) Extending in the X direction and a pair of bit lines 5a and 5b extending in the Y direction. Each memory cell 1 is disposed at a crossing position with the read word line 12 in a region sandwiched between the pair of bit lines 5a and 5b. One end of each of the stacked bodies S20a and S20b in each memory cell 1 is connected to the bit lines 5a and 5b, and the other end is connected to the common read word line 12 via the diodes 75a and 75b.
[0058]
One end of each read word line 12 is connected to each read switch 83 (..., 83m, 83m + 1,...) Via a read word line lead electrode 43, and is further connected to a common constant current circuit 58B. Each read switch 83 is connected to an X-direction address decoder circuit 58A via a word decode line 72 (..., 72m, 72m + 1,...), And when a selection signal is input from the X-direction address decoder circuit 58A. It is configured to conduct. The constant current circuit 58B functions to make the current flowing through the read word line 12 constant.
[0059]
One end of each bit line 5a, 5b is connected to the sense amplifier circuit 56B via the bit line lead electrodes 42a, 42b, respectively, and the other end is finally grounded. One sense amplifier circuit 56B is provided for each unit readout circuit 80. Each unit readout circuit 80 has a function of capturing a potential difference between the pair of bit lines 5a and 5b and amplifying the potential difference. Each sense amplifier circuit 56B is connected to an output line 82 (..., 82n, 82n + 1,...), And finally connected to an output buffer 52B via a Y-direction read data bus 62.
[0060]
Next, the operation in the magnetic memory device of the present embodiment will be described.
[0061]
First, the write operation in the memory cell 1 will be described with reference to FIGS. FIG. 7 shows the relationship between the write current direction and the return magnetic field direction (magnetization direction) in the cross section of the TMR elements 120a and 120b. In FIG. 7, the arrows shown for each magnetic layer indicate the magnetization direction in the magnetic layer. However, the magnetic field directions are also shown for the annular magnetic layers 4a and 4b. Here, the magnetizations of the first magnetic layers 2a and 2b are fixed in the + X direction.
[0062]
FIGS. 7A and 7B show the case where the write currents flow in the same direction through the bit lines 5a and 5b and the write word line 6 passing through the TMR elements 120a and 120b. Indicates the state. In particular, FIG. 7A corresponds to the write current direction shown in FIG. Here, in the TMR element 120a, a write current flows from the front to the back (in the + Y direction) in the direction perpendicular to the paper surface, and the return magnetic field 34a is generated in the clockwise direction in the annular magnetic layer 4a. Show. In this case, the magnetization direction of the connection portion 14a as the magnetosensitive layer is the + X direction. On the other hand, TMR element 120b corresponds to the case where the direction of the write current flowing through bit line 5 and write word line 6 is completely opposite to that of TMR element 120a. That is, in the TMR element 120b, when a write current flows from the back to the front (in the −Y direction) in a direction perpendicular to the paper surface, a return magnetic field 34b is generated counterclockwise in the annular magnetic layer 4b. Is shown. In this case, the magnetization direction of the connection portion 14b is the -X direction.
[0063]
As described above, when currents in the same direction flow through both the bit lines 5a and 5b and the write word line 6 passing through the annular magnetic layers 4a and 4b, free-flow magnetic fields 34a and 34b in a predetermined direction are generated, and accordingly TMR is generated. The magnetization directions of the connection portions 14a and 14b in the elements 120a and 120b change, and the state is parallel (same direction) to the magnetization direction of the first magnetic layers 2a and 2b, and is antiparallel (opposite direction). Show either one. By utilizing this, binary information “0” or “1” can be stored in the memory cell 1. In the present invention, the “magnetization directions are antiparallel to each other” means that the relative directions formed by the mutual magnetization directions, that is, the average magnetization directions in the respective magnetic layers are strictly 180 degrees, and errors that occur in manufacturing. In addition, it includes a case where the angle deviates from 180 degrees by a predetermined angle due to an error or the like that occurs because the axis is not completely uniaxial. In addition, “information” generally refers to binary information represented by “0”, “1” or “High”, “Low”, etc. according to current value or voltage value in an input / output signal to the magnetic memory device.
[0064]
For example, “0” is set to the state shown in FIG. 7A, that is, the connection portion 14a of the TMR element 120a is magnetized in the + X direction and the connection portion 14b of the other TMR element 120b is magnetized in the −X direction. In the case of correspondence, the state of FIG. 7B opposite to FIG. 7A, that is, the connecting portion 14a of the TMR element 120a is magnetized in the −X direction, and the connecting portion 14b of the other TMR element 120b is used. Can be stored in association with “1” in the state of magnetization in the + X direction. Here, the + X direction is a specific example corresponding to the “first direction” in the present invention, and the −X direction is a specific example corresponding to the “second direction” in the present invention. Therefore, the state in FIG. 7A is one specific example corresponding to the “first state” in the present invention, and the state in FIG. 7B corresponds to the “second state” in the present invention. It is one specific example.
[0065]
In this case, in the TMR elements 120a and 120b, if the magnetization directions of the first magnetic layers 2a and 2b and the connection portions 14a and 14b are parallel to each other, a low resistance state in which a large tunnel current flows is obtained. It becomes a high resistance state in which only current flows. That is, the TMR element 120a and the TMR element 120b that make a pair always store information with one having a low resistance and the other having a high resistance. When a write current flows in the opposite direction between the bit lines 5a and 5b and the write word line 6, or when only one of the write currents flows, the connection portions 14a and 14b The magnetization direction is not reversed, and data is not rewritten.
[0066]
As described above, according to the TMR elements 120a and 120b in the magnetic memory device of the present embodiment, the current in the same direction is supplied to both the bit lines 5a and 5b and the write word line 6 to thereby cause the bit line 5a. , 5b and the current magnetic field generated by the write word line 6 are in the same direction inside the annular magnetic layers 4a, 4b, and a combined magnetic field can be formed. For this reason, a large magnetic flux density can be obtained as compared with the case where no annular magnetic layer is provided or the case where the bit line and the write word line are orthogonal to each other. The minimum current required for reversing the magnetization of the connecting portions 14a and 14b of the magnetic layers 4a and 4b can be further reduced.
[0067]
Further, the write current direction of bit line 5a and write word line 6 in TMR element 120a is opposite to the write current direction of bit line 5b and write word line 6 in TMR element 120b. The magnetization direction of the connection portion 14a and the magnetization direction of the connection portion 14b are antiparallel to each other. Therefore, by using this, binary information “0” or “1” can be stored.
[0068]
In addition, in the TMR elements 120a and 120b, annular magnetic layers 4a and 4b configured to penetrate along the axial direction by the bit lines 5a and 5b and the write word line 6 surround the stacked bodies S20a and S20b. The stacked bodies S20a and S20b are electrically connected to the annular magnetic layers 4a and 4b on one surface side, and are electrically connected to the bit lines 5a and 5b on the other surface side. I made it. Thereby, the bit lines 5a and 5b can be used as both lines for writing and reading. Therefore, the formation area of the TMR elements 120a and 120b can be reduced, and the formation area of the memory cell 1 can be reduced, which is advantageous for increasing the capacity of stored information.
[0069]
Next, a read operation in the magnetic memory device will be described with reference to FIGS.
[0070]
First, one of the plurality of bit decode lines 71 is selected by the address decoder circuit 56A in the first drive control circuit unit 56, and a control signal is transmitted to the corresponding sense amplifier circuit 56B. As a result, a read current flows through the bit lines 5a and 5b, and a positive potential is applied to the stacked bodies S20a and S20b in the TMR elements 120a and 120b. Similarly, one of the plurality of word decode lines 72 is selected by the X-direction address decoder circuit 58A in the second drive control circuit unit 58, and the read switch 83 at the corresponding location is driven. The selected read switch 83 is energized, a read current flows through the corresponding read word line 12, and a negative potential is applied to the opposite side of the stacked bodies S20a and S20b in the TMR elements 120a and 120b. Therefore, a read current necessary for reading can be supplied to one memory cell 1 selected by Y direction address decoder circuit 56A and X direction address decoder circuit 58A. Based on this read current, the magnetization direction of the connection portions 14a and 14b as the magnetosensitive layer can be detected, and the stored information can be read.
[0071]
FIG. 9A and FIG. 9B are circuit diagrams showing the peripheral portion of the memory cell 1. The magnetization directions of the first magnetic layers 2a and 2b of the stacked bodies S20a and S20b are indicated by white arrows, and the magnetization directions of the connection portions 14a and 14b are indicated by black arrows. The magnetization directions of the first magnetic layers 2a and 2b are both fixed in the left direction, for example. In FIG. 9A, in the stacked body S20a, the first magnetic layer 2a and the connecting portion 14a have parallel magnetization directions, and in the stacked body S20b, the first magnetic layers 2a, 2b and the connecting portion 14b are antiparallel. The magnetization direction. In this case, the stacked body S20a is in a low resistance state, and the stacked body S20b is in a high resistance state, which corresponds to “0”, for example. On the other hand, in the case of FIG. 9B, the stacked body S20a is in a high resistance state and the stacked body S20b is in a low resistance state, as opposed to the case of FIG. It corresponds. Such binary information can be read by using the magnitude of the resistance values of the stacked body S20a and the stacked body S20b and detecting the difference between the current values flowing through them.
[0072]
Here, the operation during the read operation of the magnetic memory device of the present embodiment will be described in comparison with a comparative example. FIG. 37 is a configuration diagram of a circuit system including a memory cell group including a memory cell 501 as a comparative example of the present embodiment and a read circuit thereof.
[0073]
The comparative example shown in FIG. 37 is an example in which a rectifying element such as a diode is not provided on the current path from the bit lines 5a and 5b to the read word line 12 through the TMR elements 120a and 120b. . Here, the readout switch 83_mSelect memory cell 501_mWhen an attempt is made to read the information stored in, a read current that follows the current path R indicated by the solid line flows. This current path R is a regular current path. However, at the same time, in this comparative example, for example, the memory cell 501_{m + 1}As a result, the read current wraps around the path L passing through. Specifically, for example, the read current that has flowed into the bit line 5a from the sense amplifier circuit 56B is not originally selected as a read target._{m + 1}Into the TMR element 120a of the read word line 12_{m + 1}Passes through the TMR element 120b. After that, the memory cell 501 is flowed backward through the bit line 5b toward the sense amplifier circuit 56B._mTherefore, the read current flowing toward the TMR element 120b is merged.
[0074]
On the other hand, in the magnetic memory device of the present embodiment, it is arranged on each current path of the read current supplied to the TMR elements 120a and 120b. More specifically, diodes 75a and 75b are arranged between the TMR elements 120a and 120b and the read word line 12, respectively. Here, the “current path” refers to the entire path that the read current follows to flow into the stacked bodies S20a and S20b, passes through the stacked bodies S20a and S20b, and flows out. Specifically, as shown in FIG. 8, it starts from the sense amplifier circuit 56B, flows into the stacked bodies S20a and S20b of the TMR elements 120a and 120b through the bit lines 5a and 5b, and further joins through the diodes 75a and 75b. After that, it indicates the current path R that finally reaches the constant current circuit 58B. In the vicinity of the memory cell 1, as shown in FIG. 5, the current path R is formed from the bit lines 5a, 5b to the first magnetic layers 2a, 2b, the tunnel barrier layers 3a, 3b, and the connection portions 14a, 14b (annular magnetic The layers 4a and 4b), the conductive layers 24a and 24b, the epitaxial layer 25, the connection layer 12T, and the read word line 12 are sequentially traced. The diodes 75a and 75b as rectifying elements have a rectifying action for flowing a current on the current path R so as to go only in the ground direction (read word line 12 side). Therefore, unnecessary current wraparound from a memory cell that is not a read target can be blocked. That is, noise with respect to the read signal can be reduced, and stable magnetic information can be read. Further, for example, it is possible to prevent a read current from one bit line 5a from passing from one stacked body S20a to the other stacked body S20b in the magnetic memory cell to be read and reaching the other bit line 5b. .
[0075]
Furthermore, in the magnetic memory device of the present embodiment, a read current is supplied from each of the pair of bit lines 5a and 5b to each of the stacked bodies S20a and S20b, and the magnetic memory cell is based on the difference between the pair of read current values. Information can be read from Thereby, since the read current is differentially output, the noise generated in each bit line 5 and the offset component included in the output value of each TMR element 120a, 120b are canceled out and removed.
[0076]
Next, a method for manufacturing the magnetic memory device of the present embodiment having the above configuration will be described.
[0077]
The method of manufacturing the magnetic memory device according to the present embodiment includes a step of forming lower magnetic layers 4Ba and 4Bb forming part of the annular magnetic layers 4a and 4b on the base 11 provided with the diodes 75a and 75b, A step of forming a write word line 6 on the lower magnetic layers 4Ba and 4Bb via an insulating film 7A, and a bit line 5a and 5b on the write word line 6 via an insulating film 7B. The step of forming the write word line 6 and the bit lines 5a and 5b to include portions extending in parallel to each other, the bit lines 5a and 5b, the insulating film 7B, and the write word line 6 are sequentially etched. Then, patterning is performed to form a stacked pattern 19a, 19b including portions where the write word line 6 and the bit lines 5a, 5b extend in parallel with the insulating films 7Ba, 7Bb interposed therebetween. The steps of forming the stacked portions 20a and 20b forming part of the stacked bodies S20a and S20b on the stacked patterns 19a and 19b, and the stacked layers on the opposite sides of the stacked portions 20a and 20b from the bit lines 5a and 5b. Forming an annular magnetic layer 4a, 4b by providing an upper magnetic layer surrounding the laminated portions 20a, 20b and the laminated patterns 19a, 19b so as to be in electrical contact with only the surface. This will be specifically described below.
[0078]
With reference to FIGS. 10 to 26, a method for manufacturing TMR elements 120a and 120b in the magnetic memory device will be mainly described in detail. 10 to 26 are cross-sectional views corresponding to FIG. 7 and show the formation process.
[0079]
First, as shown in FIG. 10, a substrate 11 in which diodes 75a and 75b are embedded is prepared, and lower magnetic layers 4Ba and 4Bb are selectively formed on the conductive layers 24a and 24b in the diodes 75a and 75b. Specifically, first, a resist pattern (not shown) is selectively formed by an i-line stepper or the like so as to cover a region other than a region where the lower magnetic layers 4Ba and 4Bb are formed. Using this resist pattern, for example, iron sulfide (FeSO_Four) And nickel sulfate (NiSO)_Four) To form a plating film made of a nickel iron alloy (NiFe; atomic ratio is Ni: Fe = 80: 20) by energizing, and by lifting off the resist pattern, the lower magnetic layer 4Ba, Complete the formation of 4Bb.
[0080]
After forming the lower magnetic layers 4Ba and 4Bb, as shown in FIG. 11, for example, TEOS (normal tetraethyl silicate; Si (OC₂H_Five)_Four), For example, silicon oxide (SiO 2) so as to cover the whole with a CVD (Chemical Vapor Deposition) apparatus.₂7A is formed. This insulating film 7A is a specific example corresponding to the “first insulating film” of the present invention.
[0081]
Subsequently, a plating base film (not shown) made of, for example, titanium (Ti) is formed on the insulating film 7A by sputtering or the like. After that, as shown in FIG. 12, the write word line 6 is selectively formed on the plating base film so as to be narrower than the width of the lower magnetic layers 4Ba and 4Bb in the formation region of the lower magnetic layers 4Ba and 4Bb. Respectively. Specifically, after a resist pattern (not shown) having a predetermined shape is formed on the plating base film on the insulating film 7A, the resist pattern (not shown) is immersed in a plating layer and subjected to plating using the plating base film as an electrode. A write word line 6 made of copper (Cu) is formed. After removing the resist pattern, an unnecessary plating base film exposed on the insulating film 7A is removed by ion milling.
[0082]
Next, as shown in FIG. 13, for example, SiO is covered so as to cover the whole using a CVD apparatus.₂After the insulating film 7B is formed, the insulating film 7B is polished by a CMP apparatus, and the surface of the insulating film 7B is planarized. Here, the insulating film 7B is a specific example corresponding to the “second insulating film” of the present invention.
[0083]
Subsequently, a plating base film made of, for example, titanium is formed on the insulating film 7B by sputtering or the like. Thereafter, as shown in FIG. 14, bit lines 5a and 5b are selectively formed so as to cover a region corresponding to the write word line 6 of the plating base film. Specifically, after a resist pattern (not shown) having a predetermined shape is formed on the insulating film 7B, the resist pattern (not shown) is immersed in a plating layer and subjected to plating using the plating base film as an electrode. Line 5 is formed. After removing the resist pattern, the unnecessary plating base film exposed on the insulating film 7B is removed by ion milling.
[0084]
Next, as shown in FIG. 15, stacked patterns 19a and 19b are formed in a self-aligning manner using the bit lines 5a and 5b as a mask. Specifically, C as a reactive gas_FourF₈By removing the insulating film 7B, the write word line 6 and the insulating film 7A in the region not protected by the bit lines 5a and 5b by RIE (RIE: Reactive Ion Etching) using RIE and ion milling, the stacked pattern 19a, 19b is formed. Here, it is important to remove the insulating film 7A until the lower magnetic layers 4Ba and 4Bb are exposed.
[0085]
Thus, by forming the stacked patterns 19a and 19b in a self-aligning manner using the bit lines 5a and 5b as a mask, the write word line 6 having the same width as the bit lines 5a and 5b can be formed with high accuracy. Can do. Furthermore, the resist pattern forming step and the removing step thereof can be omitted, and the manufacturing process can be simplified.
[0086]
After the stacked patterns 19a and 19b in the parallel portions 10 of the bit lines 5a and 5b and the write word line 6 are formed, as shown in FIG.₂An insulating film 7C made of or the like is formed.
[0087]
Next, as shown in FIG. 17, the insulating films 7 </ b> C and 7 </ b> Cb are formed by completely removing the insulating film 7 </ b> C except for the portions formed so as to be in contact with the side surfaces of the stacked patterns 19 a and 19 b by ion milling or the like. After that, a plating base film made of, for example, NiFe is thinly formed over the entire surface by sputtering or the like. Thereafter, as shown in FIG. 18, a photoresist layer 31A is formed by photolithography or the like on the plating base film corresponding to the region where the lower magnetic layers 4Ba and 4Bb are not formed.
[0088]
After the photoresist layer 31A is formed, it is immersed in a plating layer and subjected to plating using the plating base film as an electrode, thereby forming intermediate magnetic layers 4Sa and 4Sb made of, for example, NiFe as shown in FIG. Next, after removing the photoresist layer 31A, the exposed unnecessary plating base film is removed by ion milling. In addition, as shown in FIG.₂An insulating film 17A made of is formed.
[0089]
After that, as shown in FIG. 21, polishing is performed using a CMP apparatus until the bit lines 5a and 5b are finally exposed, and a flat surface including the bit lines 5a and 5b is formed. Further, the first magnetic layers 2a and 2b and the aluminum (Al) layer are sequentially formed on the flat surface by sputtering or the like, and the tunnel barrier layer 3 is formed by oxidizing the Al layer with oxygen plasma or the like. obtain. Further, for example, a NiFe layer is formed on the tunnel barrier layer 3 by sputtering or the like, and then a photoresist layer 31B is left on the NiFe layer so as to leave a partial region corresponding to the bit lines 5a and 5b. Form. By using this photoresist layer 31B as a mask and selectively etching by ion milling or the like, stacked portions 20a and 20b are formed.
[0090]
Next, as shown in FIG. 22, using a CVD apparatus or the like, silicon oxide (SiO 2₂) Etc. are formed over the entire surface, and then the photoresist layer 31B is removed. Further, as shown in FIG. 23, after selectively forming a photoresist layer 31C so as to cover a region other than the region corresponding to the intermediate magnetic layers 4Sa and 4Sb, C_FourF₈The insulating film 7D in the region corresponding to the intermediate magnetic layers 4Sa and 4Sb is removed by reactive ion etching using. Here, the insulating film 7D separated from the insulating films 7Da and 7Db in contact with the stacked portions 20a and 20b by etching is hereinafter referred to as an insulating film 17B for convenience.
[0091]
Next, after removing the photoresist layer 31C, as shown in FIG. 24, a photoresist layer 31D is selectively formed so as to cover the insulating film 17B by photolithography or the like.
[0092]
After forming the photoresist layer 31D, the NiFe layer covering the stacked portions 20a and 20b is removed by reverse sputtering, and then the upper magnetic layer 4U made of NiFe, for example, as shown in FIG. Form. Thereby, the formation of the annular magnetic layers 4a and 4b including the lower magnetic layers 4Ba and 4Bb, the intermediate magnetic layers 4Sa and 4Sb, and the upper magnetic layers 4Ua and 4Ub is completed. Here, the intermediate magnetic layers 4Sa and 4Sb and the upper magnetic layers 4Ua and 4Ub are one specific example corresponding to the “upper magnetic layer” of the present invention.
[0093]
After the formation of the annular magnetic layers 4a and 4b is completed, the photoresist layer 31D is removed, and an unnecessary plating base film exposed on the insulating film 17B is removed by ion milling or the like. Finally, as shown in FIG. 26, for example, SiO2 is covered so as to cover the whole with a CVD apparatus or the like.₂An insulating film 17C made of is formed. This completes the formation of the TMR elements 120a and 120b.
[0094]
Thereafter, write word line lead electrodes 41 are formed at both terminals of the write word line 6, bit line lead electrodes 42 are formed at both terminals of the bit lines 5 a and 5 b, and each of the read word lines 12 is further formed. Read word line lead electrodes 43 are formed at both terminals.
[0095]
Thus, the formation of the memory cell group 54 including the memory cell 1 including the pair of TMR elements 120a and 120b is temporarily completed.
[0096]
Thereafter, SiO 2 is further sputtered or CVD equipment.₂Or aluminum oxide (Al₂O_ThreeThe manufacturing of the magnetic memory device is completed through a step of forming a protective film such as) and a step of polishing the protective film to expose the extraction electrodes 41 to 43.
[0097]
As described above, according to the manufacturing method of the present embodiment, since the annular magnetic layers 4a and 4b are formed so as to surround the laminated portions 20a and 20b and the laminated patterns 19a and 19b, the bit lines 5a and 5b are formed. It is possible to provide a write / read line capable of passing both a write current and a read current. As a result, a compact configuration can be achieved as compared with the case where the writing bit line and the reading bit line are provided separately, which is advantageous for high density.
[0098]
In addition, according to the manufacturing method of the present embodiment, since the stacked patterns 19a and 19b are formed in a self-aligning manner using the bit lines 5a and 5b as masks, processing with high alignment accuracy can be performed, and the resist The pattern formation process, the removal process, and the like can be omitted, and the entire manufacturing process can be simplified.
[0099]
[Second Embodiment]
Next, a magnetic memory device according to a second embodiment of the present invention will be described with reference to FIGS.
[0100]
FIG. 27 shows a cross-sectional configuration of the TMR element 121a in the magnetic memory device of the present embodiment, and corresponds to the TMR element 120a of FIG. 5 in the first embodiment. In FIG. 27, substantially the same parts as those shown in FIG. The TMR element 121b has a cross-sectional configuration similar to that of the TMR element 121a, and thus description thereof is omitted here.
[0101]
In the following description, the configuration of the magnetic memory device according to the present embodiment will be described mainly with respect to differences from the first embodiment, and other descriptions will be omitted as appropriate.
[0102]
In the TMR element 120a of the first embodiment, the connection portion 14a constituting a part of the annular magnetic layer 4a functions as a magnetosensitive layer. On the other hand, the TMR element 121a of the present embodiment includes a magnetosensitive layer including a connection portion 14a and a second magnetic layer 8a that are configured to be magnetically exchange-coupled to each other, and the connection portion 14a has an annular magnetic property. A part of the layer 4a is formed.
[0103]
Specifically, as shown in FIG. 27, the TMR element 121a has a stacked body S21a composed of a stacked portion 21a and a connecting portion 14a, and the stacked portion 21a is arranged in order from the connecting portion 14a side in the second magnetic layer. 8a, a tunnel barrier layer 3a, and a first magnetic layer 2a. The magnetization direction of the second magnetic layer 8a is changed by an external magnetic field, and functions as a magnetosensitive layer together with the connecting portion 14a as described above. The second magnetic layer 8a is made of, for example, a single cobalt (Co), a cobalt iron alloy (CoFe), a cobalt platinum alloy (CoPt), or a nickel iron cobalt alloy (NiFeCo). Here, the connecting portion 14a is a specific example corresponding to the “first magnetic sensitive portion” in the present invention, and the second magnetic layer 8a is a specific example corresponding to the “second magnetic sensitive portion” in the present invention. It is.
[0104]
In the TMR element 121a, the magnetosensitive layer is composed of two parts, that is, the connection part 14a that is the first magnetosensitive part and the second magnetic layer 8a that is the second magnetosensitive part. The magnetization direction of the two magnetic layer 8a can be stabilized. In particular, it is desirable that the second magnetic layer 8a has a coercive force larger than that of the connection portion 14a. This is because the magnetization direction of the second magnetic layer 8a is further stabilized. Therefore, in this case, the coercive force of the connection portion 14a is smaller than that of the first embodiment, for example, (50 / 4π) × 10.^ThreeIt can also be less than A / m.
[0105]
The stacked body S21a having the coercive force difference type structure is desirably configured such that the coercive force of the first magnetic layer 2a is larger than the coercive force of the second magnetic layer 8a. In that case, the coercive force of the first magnetic layer 2a is (50 / 4π) × 10.^ThreeIt is desirable to be larger than A / m, in particular, (100 / 4π) × 10^ThreeA / m or more is desirable. By doing so, it is possible to prevent the magnetization direction in the first magnetic layer 2a from being influenced by an unnecessary magnetic field such as an external disturbing magnetic field.
[0106]
Similar to the first embodiment, the coercivity of the connection portion 14a is (100 / 4π) × 10.^ThreeIt is desirable to be configured to be smaller than the coercive force of the first magnetic layer 2a within a range of A / m or less. (100 / 4π) × 10^ThreeThis is because, with a coercive force exceeding A / m, the TMR element 121a itself may be deteriorated due to heat generated due to an increase in write current. Furthermore, when the coercivity of the connection portion 14a is equal to or greater than the coercivity of the first magnetic layer 2a, the write current increases and changes the magnetization direction of the first magnetic layer 2a as the magnetization fixed layer, This is because the function of the TMR element 121a as a memory element is deteriorated.
[0107]
Next, with reference to FIGS. 28A and 28B, a write operation in the TMR elements 121a and 121b constituting the memory cell 1 will be specifically described. FIGS. 28A and 28B show the relationship between the write current direction and the return magnetic field direction (magnetization direction) in the cross-sectional configuration of the TMR elements 121a and 121b, and are diagrams in the first embodiment. 7 (A) and (B). In the TMR elements 121a and 121b, the connection portions 14a and 14b and the second magnetic layers 8a and 8b function as a storage layer for storing information. That is, the magnetization directions of the connection portions 14a and 14b and the second magnetic layers 8a and 8b are reversed by the return magnetic field 34 generated by the write current flowing through the bit lines 5a and 5b and the write word line 6, and information is stored. The
[0108]
FIGS. 28A and 28B show a case where write currents flow in the same direction through mutually parallel bit lines 5a and 5b and write word line 6 passing through TMR elements 121a and 121b. Here, the magnetization directions of the first magnetic layers 2a and 2b are both fixed in the + X direction. In FIG. 28A, in the TMR element 121a, a write current flows from the front to the back (in the + Y direction) in a direction perpendicular to the paper surface, and a reflux magnetic field 34a is generated in the clockwise direction in the annular magnetic layer 4a. At the same time, in the TMR element 121b, a write current flows from the back to the front (in the −Y direction) in the direction perpendicular to the paper surface, and the return magnetic field 34b is generated counterclockwise in the annular magnetic layer 4b. Is shown. In this case, the magnetization direction of the connection portion 14a and the second magnetic layer 8a is the + X direction, and the magnetization direction of the connection portion 14b and the second magnetic layer 8b is the -X direction. On the other hand, FIG. 28B corresponds to the case where the direction of current flowing through the bit lines 5a and 5b and the write word line 6 is completely opposite to the state shown in FIG. That is, in FIG. 28B, in the TMR element 121a, a write current flows from the back to the front (in the -Y direction) in the direction perpendicular to the paper surface, and the inside of the annular magnetic layer 4a is returned in the counterclockwise direction. In addition to the generation of the magnetic field 34a, a write current flows from the front to the back (in the + Y direction) in the direction perpendicular to the paper surface in the TMR element 121b, and the return magnetic field 34b is generated in the clockwise direction in the annular magnetic layer 4b. Shows when to do. In this case, the magnetization direction of the connection portion 14a and the second magnetic layer 8a is the -X direction, and the magnetization direction of the connection portion 14b and the second magnetic layer 8b is the + X direction.
[0109]
As apparent from FIGS. 28A and 28B, when a write current in the same direction flows through both the bit lines 5a and 5b and the write word line 6 passing through the annular magnetic layers 4a and 4b, the connecting portion 14a. , 14b and the magnetization directions of the second magnetic layers 8a, 8b are reversed, and binary information is recorded. For example, when the state of FIG. 28A is “0”, the state of FIG. 28B is identified by being “1”.
[0110]
When manufacturing the magnetic memory device in the present embodiment, a flat surface including the bit lines 5a and 5b is formed as shown in FIG. 21 through the steps described in the first embodiment. After that, the stacked portions 21a and 21b are formed on the bit lines 5a and 5b as follows. First, as in the first embodiment, an i-line stepper or the like is used to selectively form a resist pattern so as to cover regions other than the regions where the stacked portions 21a and 21b (first magnetic layers 2a and 2b) are to be formed. Form. Thereafter, first magnetic layers 2a and 2b made of, for example, a CoFe layer are formed by sputtering or the like. Subsequently, an aluminum layer is formed on the first magnetic layers 2a and 2b, and this is oxidized to obtain tunnel barrier layers 3a and 3b. Further, the second magnetic layers 8a and 8b are formed on the tunnel barrier layers 3a and 3b by sputtering or the like using, for example, CoFe, thereby completing the formation of the stacked portions 21a and 21b. After that, through the same process as in the first embodiment, a magnetic memory device including the TMR elements 121a and 121b including the stacked bodies S21a and S21b is completed.
[0111]
As described above, according to the TMR elements 121a and 121b in the magnetic memory device of the present embodiment, in addition to the configuration in the first embodiment, between the tunnel barrier layers 3a and 3b and the connection portions 14a and 14b. The second magnetic layers 8a and 8b are provided. For this reason, the connection portions 14a and 14b and the second magnetic layers 8a and 8b form exchange coupling, and the magnetization directions in the second magnetic layers 8a and 8b as the magnetosensitive layers are more stable. More improved. Further, since the coercive force of the connection portions 14a and 14b can be further reduced, the amount of heat generated can be reduced by reducing the current value during the write operation, and the function as a magnetic memory device can be sufficiently exhibited. it can.
[0112]
[Third Embodiment]
Next, with reference to FIG. 29, a magnetic memory device according to the third embodiment of the present invention will be described.
[0113]
FIG. 29 shows a cross-sectional configuration of the TMR element 122a in the magnetic memory device of the present embodiment, and corresponds to FIG. 5 and FIG. In FIG. 29, substantially the same components as those shown in FIGS. 5 and 27 are denoted by the same reference numerals.
[0114]
In the following description, the configuration of the magnetic memory device according to the present embodiment and the method for manufacturing the magnetic memory device will be described mainly with respect to differences from the second embodiment, and other descriptions will be omitted as appropriate. Further, since the TMR element 122b has the same configuration as the TMR element 122a, description thereof is omitted here.
[0115]
The TMR element 121a in the magnetic memory device according to the second embodiment includes the connection portions 14a and 14b in which the magnetosensitive layer constitutes a part of the annular magnetic layer 4, and the second magnetic layers 8a and 8b. The connection portions 14a and 14b and the second magnetic layers 8a and 8b are configured to be magnetically exchange-coupled to each other.
[0116]
In contrast, as shown in FIG. 29, the TMR element 122a in the magnetic memory device according to the present embodiment includes, in addition to the configuration of the TMR element 121a, between the connection portion 14a and the second magnetic layer 8a. A nonmagnetic conductive layer 9a for antiferromagnetic coupling between the connection portion 14a and the second magnetic layer 8a is provided. The TMR element 122a includes a stacked body S22a including a stacked portion 22a and a connecting portion 14a. The laminated portion 22a includes a nonmagnetic conductive layer 9a, a second magnetic layer 8a, a tunnel barrier layer 3a, and a first magnetic layer 2a in this order from the connection portion 14a side. The nonmagnetic conductive layer 9a is made of, for example, ruthenium (Ru) or copper (Cu). Here, the nonmagnetic conductive layer 9a is a specific example corresponding to the “nonmagnetic conductive layer” of the present invention.
[0117]
In the TMR element 122a in the magnetic memory device of the present embodiment, the connection portion 14a and the second magnetic layer 8a are antiferromagnetically coupled, so that the coercivity of the connection portion 14a is (50 / 4π) × 10.^ThreeEven if it is less than A / m, the problem that the magnetization direction in the connection portion 14a is disturbed by an unnecessary magnetic field such as an external disturbing magnetic field does not occur. For example, iron (Fe), NiFe, CoFe, NiFeCo and cobalt ( Co) or the like can form the annular magnetic layers 4a and 4b.
[0118]
The second magnetic layer 8a serves as a part for holding recording, and is stabilized by an anisotropic magnetic field due to antiferromagnetic coupling. The coercive force of the second magnetic layer 8a is (100 / 4π) × 10.^ThreeIt is desirable that the range be A / m or less and be smaller than the coercive force of the first magnetic layer 2a.
[0119]
Next, with reference to FIGS. 30A and 30B, a write operation in the TMR elements 122a and 122b constituting the memory cell 1 will be specifically described. FIGS. 30A and 30B show the relationship between the write current direction and the return magnetic field direction (magnetization direction) in the cross-sectional configuration of the TMR elements 122a and 122b, and are diagrams in the first embodiment. 7 (A) and (B). In the TMR elements 122a and 122b, the connection portions 14a and 14b and the second magnetic layers 8a and 8b function as a storage layer for storing information.
[0120]
30A and 30B show a case where write currents flow in the same direction in mutually parallel bit lines 5a and 5b and write word line 6 passing through TMR elements 122a, 122ba and 122b. . Here, the magnetization directions of the first magnetic layers 2a and 2b are both fixed in the + X direction. In FIG. 30A, a write current flows from the front to the back (in the + Y direction) in the direction perpendicular to the paper surface in the TMR element 122a, and the inside of the annular magnetic layer 4a surrounding the bit line 5a is rotated clockwise. In the TMR element 122b, a write current flows from the back to the front (in the −Y direction) in the direction perpendicular to the paper surface, and the portion of the annular magnetic layer 4 surrounding the bit line 5b is generated. The case where the return magnetic field 34 is generated in the counterclockwise direction inside is shown. In this case, the magnetization direction of the second magnetic layer 8a is the -X direction, and the magnetization direction of the second magnetic layer 8b is the + X direction. On the other hand, FIG. 30B corresponds to the case where the direction of current flowing through bit lines 5a and 5b and write word line 6 is completely opposite to the state shown in FIG. That is, FIG. 30B shows a case where the write current flows from the back to the front (in the −Y direction) in the direction perpendicular to the paper surface in the TMR element 122a and the inside of the annular magnetic layer 4a surrounding the bit line 5a. Is generated in a counterclockwise direction, and a write current flows from the front to the back (in the + Y direction) in the direction perpendicular to the paper surface in the TMR element 122b, and the annular magnetism in the portion surrounding the bit line 5b The case where the return magnetic field 34b is generated in the clockwise direction inside the layer 4b is shown. In this case, the magnetization direction of the second magnetic layer 8a is the + X direction, and the magnetization direction of the second magnetic layer 8b is the -X direction.
[0121]
When current flows in the same direction through the bit lines 5a and 5b and the write word line 6 in this way, the magnetization directions of the second magnetic layers 8a and 8b are reversed and 0 or 1 is recorded. For example, when the state of FIG. 30A is 0, the state of FIG. Here, when the write current flows in the opposite directions, or when the write current flows in only one of them, the magnetization directions of the second magnetic layers 8a and 8b are not reversed, and the data rewrite is performed. It is not done.
[0122]
When manufacturing the magnetic memory device in the present embodiment, a flat surface including the bit lines 5a and 5b is formed as shown in FIG. 21 through the steps described in the first embodiment. After that, the stacked portions 22a and 22b are formed on the bit lines 5a and 5b as follows. First, as in the first and second embodiments, an i-line stepper or the like is used to selectively cover a region other than the region where the stacked portions 22a and 22b (first magnetic layers 2a and 2b) are formed. A resist pattern is formed. Thereafter, first magnetic layers 2a and 2b made of, for example, a CoFe layer are formed by sputtering or the like. Subsequently, an aluminum layer is formed on the first magnetic layers 2a and 2b, and this is oxidized to obtain tunnel barrier layers 3a and 3b. Further, on the tunnel barrier layers 3a and 3b, second magnetic layers 8a and 8b made of, for example, CoFe and nonmagnetic conductive layers 9a and 9b made of a nonmagnetic metal material such as ruthenium (Ru) are formed by sputtering or the like. By forming in order, the formation of the stacked portions 22a and 22b is completed. Thereafter, a magnetic memory device including the TMR elements 122a and 122b is completed through steps similar to those in the first and second embodiments.
[0123]
As described above, in the magnetic memory device according to the present embodiment, in addition to the configuration of the second embodiment, the connection portions 14a and 14b of the annular magnetic layers 4a and 4b and the second magnetic layers 8a and 8b The nonmagnetic conductive layers 9a and 9b are provided between them. By doing so, since the connection portions 14a and 14b and the second magnetic layers 8a and 8b can form strong antiferromagnetic coupling, the connection as the magnetosensitive layer is caused by an unnecessary magnetic field due to an external disturbing magnetic field or the like. The magnetization directions of the portions 14a and 14b and the second magnetic layers 8a and 8b are more stable without being disturbed. In addition to this, the coercivity of the connecting portions 14a and 14b can be further reduced by the above configuration. Therefore, it is possible to reduce the amount of heat generated by reducing the current value during the write operation, and the metal elements and the like contained in the connection portions 14a and 14b are diffused and moved to the second magnetic layers 8a and 8b. Since this can be shielded by providing the nonmagnetic conductive layers 9a and 9b, the thermal stability is improved. As a result, more stable writing is possible.
[0124]
【Example】
Further, specific examples in this embodiment will be described.
[0125]
In this example, based on the manufacturing method described in the first embodiment, a magnetic memory device in which a plurality of memory cells 1 having the cross-sectional structure shown in FIG. This is designated as Sample 1.
[0126]
With respect to the TMR element 120a in the magnetic memory device of Sample 1, the MR ratio (MR ratio), switching current, and adjacent cell inversion current were measured. The results are shown in Table 1 as examples. Here, in order to compare the numerical values, the same measurement was performed for the magnetic memory device including the memory cell 101 having a structure without the continuous annular magnetic layer as shown in FIG. It is written together. Further, the same applies to the magnetic memory device including the memory cell 201 having the stacked body S20a in the region outside the annular magnetic layer 4a, that is, the region not surrounded by the annular magnetic layer 4a, as shown in FIG. Measurements are made and are shown in Table 1 as Comparative Example 2. Comparative Example 1 includes a connection layer 113a that serves as a current path during a read operation and electrically connects the bit line 5a and the conductive layer 24a. Comparative Example 2 is configured to include a write-only write bit line 115 a and a read-only read bit line 13. Note that the current values of the switching current and the adjacent cell inversion current are measured by causing the same write current to simultaneously flow through the bit line 5a (write bit line 115a) and the write word line 6. did. Applied magnetic field during measurement is (500 / 4π) × 10^ThreeA / m.
[0127]
[Table 1]

[0128]
As shown in Table 1, although there was no significant difference in MR change rate between this example and Comparative Examples 1 and 2, there was a clear improvement in performance with respect to switching current and adjacent cell inversion current. It is done.
[0129]
The switching current is a minimum current value necessary for reversing the magnetization direction in the memory cell to be written. Regarding this switching current, this example showed a small value of 1.2 mA, which is less than one fifth with respect to 6.8 mA of Comparative Example 1. This is because, by providing the annular magnetic layers 4a and 4b so as to be penetrated by the write word line 6 and the bit line 5, the magnetization reversal of the connection portions 14a and 14b as the magnetosensitive layers can be efficiently performed. Therefore, it shows that the writing operation is possible even with a small current. Even when compared with Comparative Example 2, since the switching current of this example is relatively small, it is more efficient by surrounding the stacked bodies S20a and S20b with the annular magnetic layers 4a and 4b. This shows that the magnetization reversal of the connection portions 14a and 14b can be performed, and the writing operation can be performed even with a smaller current.
[0130]
The adjacent cell inversion current represents a current value at which the magnetization direction of the memory cell that should not be written is reversed by the current applied to the memory cell adjacent to the memory cell to be written. As shown in Table 1, it was found that in this example, the magnetization direction in the adjacent memory cell was not reversed even when a larger write current was applied than in the conventional example. This indicates that a closed magnetic path is formed, and generation of a magnetic field that adversely affects adjacent memory cells can be suppressed. In particular, when compared with Comparative Example 2, the present example also showed a relatively large adjacent cell reversal current, so that the annular magnetic layers 4a and 4b surrounded the stacked bodies S20a and S20b, thereby providing adjacent This shows that the generation of a magnetic field that adversely affects the memory cell can be more reliably suppressed.
[0131]
As described above, according to the present embodiment, the TMR elements 120a and 120b surround the stacked bodies S20a and S20b so that the direction along the stacked surface is the axial direction, and the bit line 5 and the write word line 6 Since the annular magnetic layers 4a and 4b configured to penetrate along the axial direction are included, a closed magnetic path is formed by supplying current to both the bit line 5 and the write word line 6. In addition, the magnetization of the connection portions 14a and 14b of the TMR elements 120a and 120b can be reversed more efficiently, and the magnetic effect on the memory cell adjacent to the memory cell to be written can be increased. It was found that can be reduced.
[0132]
Although the present invention has been described with reference to some embodiments, the present invention is not limited to these embodiments and modifications, and various modifications can be made. For example, in this embodiment and each modification, a Schottky diode is used as a rectifying element for preventing backflow, but it can be replaced with a bipolar transistor that is also an element having a rectifying action.
[0133]
FIG. 31 shows a main configuration of a circuit when bipolar transistors 76a and 76b are provided between the TMR elements 120a and 120b and the read word lines 12a and 12b. FIG. 32 shows a cross-sectional structure of the bipolar transistors 76a and 76b. The bases B of the bipolar transistors 76a and 76b are connected to the word decode line 72. Each collector C is connected to the annular magnetic layers 4 a and 4 b via the connection layer 28, and each emitter E is connected to the read word line 12 via the connection layer 27.
[0134]
FIG. 33 shows the entire readout circuit when the bipolar transistors 76a and 76b are provided. In this case, when the control signal from the Y-direction address decoder circuit 56A is transmitted to, for example, the sense amplifier circuit 56B of the unit read circuit 80n, the sense amplifier circuit 56B generates a read current through the bit lines 5a and 5b. The control signal from Y-direction address decoder circuit 56A is simultaneously transmitted to read switch 83n, and read switch 83n is turned on. On the other hand, the X-direction address decoder circuit 58A selects the memory cell 1m and issues a control signal so as to pass through the word decode line 72m. When the control signal from the X-direction address decoder circuit 58A is transmitted to the bases B of the bipolar transistors 76a and 76b, the collector C and the emitter E are brought into conduction. As a result, the read current passes through the TMR elements 120a and 120b of the memory cell 1m, and finally flows into the constant current circuit 58B via the read switch 83n. Similarly to the diodes 75a and 75b, the bipolar transistors 76a and 76b function so as to pass current in one direction, so that it is possible to avoid the read current wraparound as shown in FIG.
[0135]
Further, as shown in FIG. 34, MOS transistors 77a and 77b can be used as rectifying elements for preventing backflow. In this case, the sources S are connected to the TMR elements 120a and 120b, the drains D are connected to the read word line 12, and the gate G connected to the word decode line 72 is closed, so that the conductive state is established. can do. FIG. 35 shows the entire readout circuit when MOS transistors 77a and 77b are provided. Except for the point that the conductive state is established by closing the gate G, the read operation in the read circuit shown in FIG. 35 is the same as the circuit using the bipolar transistors 76a and 76b (FIG. 33).
[0136]
In this embodiment, the case where the bit line and the write word line are parallel to each other has been described. However, the present invention is not limited to this. For example, the bit line and the write word line may be 90 ° to each other. However, the case where the annular magnetic layer is formed so as to surround the parallel portion is more preferable because the magnetization reversal of the magnetosensitive layer is more efficiently performed.
[0137]
Further, in the present embodiment, the reading of information in each memory cell is performed by using the difference value of the reading current passed through each of the pair of TMR elements as an output, but the present invention is not limited to this. For example, the value of the read current passing through a certain TMR element may be output as it is to detect whether it is in a high resistance state or a low resistance state.
[0138]
Further, in the present embodiment, as shown in FIG. 7, the laminated body in each TMR element is arranged on the upper side (the side opposite to the rectifying element), but the present invention is not limited to this. For example, as shown in FIG. 36, in each TMR element, the stacked body may be disposed on the lower side (side closer to the rectifying element).
[0143]
【The invention's effect】
  According to the method of manufacturing a magnetic memory device of the present invention, a step of forming a lower magnetic layer that forms a part of an annular magnetic layer on a base, and a first insulating film on the lower magnetic layer A process for forming a write-only line, and a write / read line extending on the write-only line via a second insulating film, and the write-only line and the write / read line extending in parallel with each other The write-only line and the write / read line are formed by sequentially etching and patterning the step of forming the portion, the write / read line, the second insulating film, and the write-only line. A laminated pattern forming step of forming a laminated pattern including portions extending in parallel with each other across the second insulating film;Forming a pair of intermediate magnetic layers forming at least a part of the annular magnetic layer so as to cover at least the side surface of the laminated pattern and in contact with the lower magnetic layer; and exposing the upper surface of the laminated pattern; A step of forming a laminated portion by sequentially laminating a magnetic layer and a nonmagnetic layer; and a top surface of a pair of intermediate magnetic layers in contact with a laminated surface opposite to the write / read line in the laminated portion. Providing an upper magnetic layer as a first magnetosensitive layer so as to be in contact with each other, thereby forming a laminated body and forming an annular magnetic layer surrounding the laminated portion and the laminated pattern;Therefore, an annular magnetic layer provided so as to surround the laminated portion and the laminated pattern so as to be in electrical contact with only the laminated surface on the opposite side to the read / write line in the laminated portion is obtained. Therefore, a closed magnetic path that contributes to efficient magnetization reversal of each magnetosensitive layer can be formed by flowing a write current through the read / write line, and the write current required for magnetization reversal of the magnetosensitive layer can be made smaller. In addition, a read current can be supplied to each stacked body via the write / read line. Thereby, it can be set as a more compact structure and it becomes advantageous to densification.
[0144]
  further,In the laminated pattern forming step, the laminated pattern is formed in a self-aligned manner by selectively etching the second insulating film and the write-only line using the write / read line as a mask.BecauseEnables processing with high alignment accuracyMadeAs a whole manufacturing processMoreSimplification can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a magnetic memory device according to a first embodiment of the invention.
2 is a plan view showing a configuration of a write line of the magnetic memory device shown in FIG. 1; FIG.
3 is a partial plan view showing the main configuration of a storage cell group of the magnetic memory device shown in FIG. 1;
4 is a main part perspective view showing a main part configuration of a memory cell group of the magnetic memory device shown in FIG. 1; FIG.
5 is a cross-sectional view showing a configuration of a cut surface along the line VV of the memory cell shown in FIG. 3;
6 is another partial plan view showing the main configuration of the memory cell group of the magnetic memory device shown in FIG. 1; FIG.
7 is a cross-sectional view showing a configuration of a cut surface along the line VII-VII of the memory cell shown in FIG. 6;
8 is a circuit diagram showing a circuit configuration of the magnetic memory device shown in FIG. 1. FIG.
9 is a partially enlarged view of the circuit configuration shown in FIG.
10 is an enlarged cross-sectional view showing a step in the method of manufacturing the magnetic memory device shown in FIG. 1. FIG.
FIG. 11 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
12 is an enlarged cross-sectional view illustrating a process following FIG. 11. FIG.
13 is an enlarged cross-sectional view illustrating a process subsequent to FIG. 12. FIG.
14 is an enlarged cross-sectional view illustrating a process subsequent to FIG. 13. FIG.
15 is an enlarged cross-sectional view illustrating a process following FIG.
16 is an enlarged cross-sectional view illustrating a process following FIG.
FIG. 17 is an enlarged cross-sectional view illustrating a process following FIG.
FIG. 18 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
FIG. 19 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
20 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
FIG. 21 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
22 is an enlarged cross-sectional view illustrating a process subsequent to FIG. 21. FIG.
FIG. 23 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
24 is an enlarged cross-sectional view illustrating a process subsequent to FIG. 23. FIG.
25 is an enlarged cross-sectional view illustrating a process subsequent to FIG. 24. FIG.
FIG. 26 is an enlarged cross-sectional view illustrating a process subsequent to FIG.
FIG. 27 is a cross-sectional view showing a cross-sectional structure of a magnetoresistive effect element in a magnetic memory device according to a second embodiment of the present invention.
28 is an explanatory diagram showing the relationship between the write current direction and the return magnetic field direction (magnetization direction) in the cross-sectional configuration of the magnetoresistive effect element shown in FIG. 27. FIG.
FIG. 29 is a cross-sectional view showing a cross-sectional configuration of a magnetoresistive effect element in a magnetic memory device according to a third embodiment of the present invention.
30 is an explanatory diagram showing the relationship between the write current direction and the return magnetic field direction (magnetization direction) in the cross-sectional configuration of the magnetoresistive effect element shown in FIG. 29;
31 is a partially enlarged view showing a modification of the rectifying element in the circuit configuration shown in FIG.
32 is a partial cross-sectional view showing a cross-sectional configuration in a modified example of the rectifying device shown in FIG. 31;
33 is a circuit diagram showing an overall circuit configuration in a modified example of the rectifying element shown in FIG. 31. FIG.
34 is a partially enlarged view showing another modification of the rectifying element in the circuit configuration shown in FIG.
35 is a circuit diagram showing an overall circuit configuration in another modification of the rectifying element shown in FIG. 34. FIG.
36 is a cross-sectional view showing a cross-sectional configuration of a memory cell as a modification of the magnetic memory device shown in FIG. 1;
FIG. 37 is a circuit diagram showing a circuit configuration as a comparative example corresponding to the circuit configuration shown in FIG. 8;
FIG. 38 is a plan view for explaining the configuration of a conventional magnetic memory device.
FIG. 39 is a cross-sectional view for explaining a main part configuration of a conventional magnetic memory device.
FIG. 40 is a cross-sectional view for explaining a main configuration of a magnetic memory device as a comparative example.
FIG. 41 is a cross-sectional view for explaining a main configuration of a magnetic memory device as another comparative example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell, 2 ... 1st magnetic layer, 3 ... Tunnel barrier layer, 4 ... Annular magnetic layer, 5 ... Bit line, 6 ... Write word line, 7 ... Insulating film, 8 ... 2nd magnetic layer, 9 ... Nonmagnetic conductive layer, 10 ... parallel portion, 12 ... read word line, 14 ... connection portion, 19 ... laminated pattern, S20, S21, S22 ... laminated body, 41 ... write word line lead electrode, 42 ... bit line lead electrode 43, read word line lead electrodes, 120a, 120b, magnetoresistive effect (TMR) elements.

Claims (5)

A plurality of write-only lines and a plurality of write / read lines extending so as to intersect the plurality of write-only lines;
A laminated portion including a ferromagnetic layer and a nonmagnetic layer whose magnetization directions are fixed and configured to allow a current to flow in a direction perpendicular to the laminated surface, and a direction along the laminated surface as an axial direction Surrounding the laminated portion and configured to be penetrated along the axial direction by the writing / reading line and the write-only line , and the magnetization direction is changed by an external magnetic field to form a laminated body together with the laminated portion A plurality of magnetoresistive elements having an annular magnetic layer including a first magnetosensitive layer, and a method for manufacturing a magnetic memory device comprising:
Forming a lower magnetic layer forming a part of the annular magnetic layer on a substrate;
Forming the write-only line on the lower magnetic layer , extending in a direction along the laminated surface via a first insulating film;
The write / read line is formed on the write-only line through a second insulating film so as to include a portion where the write-only line and the write / read line are extended in parallel to each other. Process,
By sequentially etching and patterning the write / read line, the second insulating film, and the write-only line, the write-only line and the write / read line are converted into the second insulating film. A laminated pattern forming step of forming a laminated pattern including portions extending in parallel with each other,
Forming a pair of intermediate magnetic layers forming a part of the annular magnetic layer so as to cover at least a side surface of the laminated pattern and be in contact with the lower magnetic layer;
Forming the laminated portion by exposing the upper surface of the laminated pattern and then laminating the ferromagnetic layer and the nonmagnetic layer in order on the upper surface ;
By providing an upper magnetic layer as the first magnetosensitive layer in contact with the laminated surface opposite to the write / read line in the laminated portion and in contact with the upper ends of the pair of intermediate magnetic layers , it looks including the step of forming the annular magnetic layer surrounding the laminated portion and the laminate pattern so as to form the laminate,
In the laminated pattern forming step, the laminated pattern is formed in a self-aligned manner by selectively etching the second insulating film and the write-only line using the write / read line as a mask. A method for manufacturing a magnetic memory device. In the step of forming the laminated portion, a second magnetosensitive layer whose magnetization direction is changed by an external magnetic field is laminated on the nonmagnetic layer.
The method of manufacturing a magnetic memory device according to claim 1. In the step of forming the laminated portion, a nonmagnetic conductive layer is laminated on the second magnetosensitive layer.
The method of manufacturing a magnetic memory device according to claim 2. The second magnetosensitive layer is formed of a material having a coercive force larger than that of the first magnetosensitive layer.
The method of manufacturing a magnetic memory device according to claim 2 or 3, After forming a metal layer on the ferromagnetic layer, the metal layer is oxidized to form a tunnel barrier layer as the nonmagnetic layer.
The method of manufacturing a magnetic memory device according to claim 1, wherein the magnetic memory device is manufactured as described above.

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