JP4557155B2 - Step-down DC / DC converter and step-up DC / DC converter - Google Patents

Description

  The present invention relates to a step-down DC / DC converter and a step-up DC / DC converter, and more particularly to a step-down synchronous rectification DC / DC converter and a step-up synchronous rectification DC / DC converter.

As is well known in this technical field, a DC / DC converter refers to a power converter that converts a DC voltage (DC input voltage) at a certain voltage level into a DC voltage (DC output voltage) at another voltage level. . The DC / DC converter is also called a switching regulator. Here, a DC / DC converter in which the voltage level of the DC output voltage is higher than the voltage level of the DC input voltage is called a step-up DC / DC converter, and the voltage level of the DC output voltage is lower than the voltage level of the DC input voltage. The DC / DC converter is called a step-down DC / DC converter. The present invention relates to a step-down DC / DC converter and a step-up DC / DC converter. First, descending describes pressure-type DC / DC converter will be described step-up DC / DC converter thereafter.

  In a step-down DC / DC converter, a transistor is used as a switch, which is switched, and a direct current input voltage is changed to an alternating current voltage. After the voltage is stepped down by a transformer, the voltage is rectified and converted into a direct current output voltage.

  As this step-down DC / DC converter, there is a step-down synchronous rectification DC / DC converter.

A general step-down synchronous rectification DC / DC converter 10 will be described with reference to FIG. Here, the terminals and voltages are denoted by the same reference numerals. The step-down synchronous rectification DC / DC converter 10 has a power input terminal V _DD , a switch terminal SW, a power output terminal Vout, and a ground terminal. The ground terminal is held at the ground potential. An anode (cathode) of the input power supply 25 is connected to the power input terminal V _DD . As a result, the DC input voltage V _DD is applied from the input power supply 25 between the ground terminal and the power input terminal V _DD .

  An inductor L is connected between the switch terminal SW and the power output terminal Vout. That is, one end of the inductor L is connected to the switch terminal SW, and the other end of the inductor L is connected to the power output terminal Vout.

A series circuit of a resistor Ro and a capacitor Co and a load Rout are connected between the power output terminal Vout and the ground terminal. Low DC output voltage Vout than the DC input voltage V _DD is generated between the power supply output terminal Vout and the ground terminal. That is, the series circuit of the resistor Ro and the capacitor Co serves as an output circuit that generates a DC output voltage Vout lower than the DC input voltage V _DD between the power supply output terminal Vout and the ground terminal.

The step-down synchronous rectification DC / DC converter 10 includes a first transistor Q1 connected between the power input terminal V _DD and the switch terminal SW, and a second transistor connected between the switch terminal SW and the ground terminal. A transistor Q2. The first transistor Q1 has first and second main electrode terminals and a first control terminal. The second transistor Q2 has third and fourth main electrode terminals and a second control terminal.

More specifically, the illustrated first transistor Q1 is a P-channel field effect transistor having a source, a drain, and a gate as a first main electrode terminal, a second main electrode terminal, and a first control terminal, respectively. It is composed of The illustrated second transistor Q2 is composed of an N-channel field effect transistor having a drain, a source, and a gate as a third main electrode terminal, a fourth main electrode terminal, and a second control terminal, respectively. Has been. In the P-channel field effect transistor Q1, its source is connected to the power supply input terminal V _DD and its drain is connected to the switch terminal SW. In the N-channel field effect transistor Q2, its drain is connected to the switch terminal SW and its source is connected to the ground terminal.

  A first parasitic diode D1 is connected between the drain and source of the P-channel field effect transistor Q1, and a second parasitic diode D2 is connected between the source and drain of the N-channel field effect transistor Q2. Specifically, the anode of the first parasitic diode D1 is connected to the drain of the P-channel field effect transistor Q1, and the cathode of the first parasitic diode D1 is connected to the source of the P-channel field effect transistor Q1. The anode of the second parasitic diode D2 is connected to the source of the N-channel field effect transistor Q2, and the cathode of the second parasitic diode D2 is connected to the drain of the N-channel field effect transistor Q2.

  These P-channel field effect transistor Q1 and N-channel field effect transistor Q2 are driven by a drive unit to be described later.

  Specifically, the drive unit includes a reference voltage generation circuit (not shown), an error amplifier 12, a pulse width modulation (PWM) comparator 13, an oscillator 14, a pulse frequency modulation (PFM) comparator 15, It has an AND gate AND, a drive circuit 17, and a zero detection amplifier 18.

Reference voltage generating circuit is connected between the ground terminal power input terminal V _DD, it generates a reference voltage Vref. The power output terminal Vout is grounded through resistors R1 and R2 connected in series. A capacitor C1 is connected in parallel to the resistor R1. The connection point between the resistors R 1 and R 2 is connected to the inverting input terminal − of the error amplifier 12. A reference voltage Vref is supplied to the non-inverting input terminal + of the error amplifier 12. The error amplifier 12 compares the voltage obtained by dividing the power supply output voltage Vout with the reference voltage Vref, and outputs an error amplification signal A.

  The output terminal of the error amplifier 12 is connected to the non-inverting input terminal + of the PWM comparator 13. The oscillator 14 oscillates a triangular wave (sawtooth wave) B. The output terminal of the oscillator 14 is connected to the inverting input terminal − of the PWM comparator 13. The PWM comparator 13 compares the triangular wave B with the error amplification signal A and outputs a pulse width modulation signal D.

  The output terminal of the error amplifier 12 is also connected to the non-inverting input terminal + of the PFM comparator 15. The reference voltage Vref is divided by resistors R3 and R4, and the divided reference voltage C is connected to the inverting input terminal − of the PFM comparator 15. The PFM comparator 15 compares the divided reference voltage C with the error amplification signal A and outputs a pulse frequency modulation signal E.

  The output terminal of the PWM comparator 13 and the output terminal of the PFM comparator 15 are connected to the AND gate AND. The logical product gate AND calculates the logical product of the pulse width modulation signal D and the pulse frequency modulation signal E and outputs a logical product output signal F.

  The output terminal of the AND gate AND is connected to the drive circuit 17. Based on the AND output signal F supplied from the AND gate AND, the driving circuit 17 prevents the P-channel field effect transistor Q1 and the N-channel field effect transistor Q2 from being turned on at the same time. The channel field effect transistor Q2 is driven.

  In any case, the drive unit drives the P-channel field effect transistor Q1 and the N-channel field effect transistor Q2 so that the P-channel field effect transistor Q1 and the N-channel field effect transistor Q2 are not turned on at the same time.

  FIG. 2 shows waveforms of respective parts of the step-down synchronous rectification DC / DC converter 10 shown in FIG. 2A shows the waveforms of the error amplification signal A, the triangular wave B, and the divided reference voltage C, FIG. 2B shows the waveform of the pulse width modulation signal D, and FIG. 2C shows the pulse frequency modulation. The waveform of the signal E is shown, and (d) shows the waveform of the logical product output signal F.

  On the other hand, the switch terminal SW is connected to the non-inverting input terminal + of the zero detection amplifier 18. The inverting input terminal − of the zero detection amplifier 18 is connected to the ground terminal. The zero detection amplifier 18 supplies a zero detection signal to the drive circuit 17 when detecting that the current flowing through the N-channel field effect transistor Q2 has become zero due to the voltage at the switch terminal SW being zero. In response to the zero detection signal, the drive circuit 17 turns off the N-channel field effect transistor Q2.

  Thus, in order to prevent the reverse current due to the N-channel field effect transistor Q2 being turned on, the zero detection amplifier 18 is prepared. Such a reverse current phenomenon occurs when the load current flowing through the load Rout is small.

  As an actual circuit, a one-pulse circuit is inserted between the zero detection amplifier 18 and the drive circuit 17.

  FIG. 3 shows a conventional step-down synchronous rectification DC / DC converter 10A. In FIG. 3, a circuit portion preceding the drive circuit 17 in the drive unit is omitted.

As shown in FIG. 3, the one-pulse circuit 20 is connected to the switch terminal SW and the output terminal of the zero detection amplifier 18. One pulse circuit 20 shown includes a set input terminal 20 _S, having a reset input terminal 20 _R, and an output terminal 20 _Q, composed of SR flip-flop, circuit consisting of first and second NOR gates G1, G2 Has been.

That is, the reset input terminal 20 _R of the one-pulse circuit 20 voltage G of the switch terminal SW is supplied. A zero detection signal is supplied to the set input terminal 20 _S of the one-pulse circuit 20 from the output terminal of the zero detection amplifier 18. The output terminal 20 _Q of the one pulse circuit 20 is connected to the drive circuit 17. One input terminal of the first NOR gate G1 is connected to the reset input terminal 20 _R, an output terminal of the first NOR gate G1 output terminal 20 _Q and the second one of the inputs of the NOR gate G2 of the one-pulse circuit 20 Connected to the terminal. The other input terminal of the second NOR gate G2 is connected to the set input terminal 20 _S, an output terminal of the second NOR gate G2 is connected to the other input terminal of the first NOR gate G1.

  FIG. 4 shows waveforms of respective parts of the conventional step-down synchronous rectification DC / DC converter 10A shown in FIG. 4A shows the waveform of the voltage G at the switch terminal SW, FIG. 4B shows the waveform of the output signal (zero detection signal) H of the zero detection amplifier 18, and FIG. 4C shows the waveform of the one-pulse circuit 20. The waveform of the output signal (one pulse) I is shown.

Until time t reaches the time t _1, the drive circuit 17 maintains the P-channel field effect transistor Q1 in the on state, and maintains the N-channel field effect transistor Q2 off. As a result, the voltage G of the switch terminal SW has a DC input voltage V _DD.

When the time t has reached the time t _1, the driving circuit 17 is a P-channel field effect transistor Q1 in the OFF state, the N-channel field effect transistor Q2 is turned on. As a result, the voltage G at the switch terminal SW becomes a negative voltage, and a current flows from the ground terminal to the switch terminal SW via the N-channel field effect transistor Q2 and the second parasitic diode D2. Since the voltage G at the switch terminal SW becomes a negative voltage, the zero detection amplifier 18 changes its output signal H from the logic “1” level to the logic “0” level after its own response time t _d elapses from the time t _1. Transition. This response time t _d is, for example, several tens of nanoseconds.

On the other hand, the one-pulse circuit 20 changes its output signal I from the logic “0” level to the logic “1” level at time t ₁ .

When the time t is the time t ₂ and the voltage G at the switch terminal SW becomes zero, the zero detection amplifier 18 changes the output signal from the logic “0” level to the logic “1” level. That is, the zero detection amplifier 18 outputs a zero detection signal.

At time t the time t _3, the drive circuit 17, a P-channel field effect transistor Q1 in the on state, to turn off the N-channel field effect transistor Q2. As a result, the voltage G at the switch terminal SW becomes the DC input voltage V _DD again. Since the voltage G at the switch terminal SW is the DC input voltage V _DD and the output signal H of the zero detection amplifier 18 is at the logic “1” level, the output signal I of the one-pulse circuit 20 is changed from the logic “1” level to the logic “0” level. Transition to.

As a result, the output signal I of the _one- pulse circuit 20 is at a logic “1” level during a time T ₁ from time t ₁ to time t ₃ . The drive circuit 17 turns off the N-channel field effect transistor Q2 while the output signal I of the one-pulse circuit 20 is at the logic “1” level.

  Next, the step-up DC / DC converter will be described. In a step-up DC / DC converter, a transistor is used as a switch, which is switched, and a DC input voltage is once changed to an AC voltage. After the voltage is boosted by a transformer, the voltage is rectified and converted to a DC output voltage.

  As this step-up DC / DC converter, there is a step-up synchronous rectification DC / DC converter.

A general boost synchronous rectification DC / DC converter 30 will be described with reference to FIG. Again, terminals and voltages are represented by the same reference numerals. The step-up type synchronous rectification DC / DC converter 30 is different in configuration and operation of a drive circuit and a zero detection amplifier as will be described later, and is connected to a power input terminal V _DD , a switch terminal SW, and a power output terminal Vout. However, except for the differences described later, it has the same configuration as the step-down synchronous rectification DC / DC converter 10 shown in FIG. Accordingly, reference numerals 17A and 18A are assigned to the drive circuit and the zero detection amplifier, respectively. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted for the sake of simplicity. Hereinafter, differences from FIG. 1 will be described.

An inductor L is connected between the switch terminal SW and the power input terminal V _DD . That is, one end of the inductor L is connected to the switch terminal SW, and the other end of the inductor L is connected to the power input terminal V _DD .

A DC output voltage Vout higher than the DC input voltage V _DD is generated between the power supply output terminal Vout and the ground terminal. That is, the series circuit of the resistor Ro and the capacitor Co serves as an output circuit that generates a DC output voltage Vout higher than the DC input voltage V _DD between the power supply output terminal Vout and the ground terminal.

  The source of the P-channel field effect transistor Q1 is connected to the power supply output terminal Vout.

  The drive circuit 17A, based on the AND output signal F supplied from the AND gate AND, prevents the P-channel field effect transistor Q1 and the N-channel field effect transistor Q2 from being turned on at the same time. The channel field effect transistor Q2 is driven. However, the drive circuit 17A is opposite to the drive circuit 17 shown in FIG. 1 in the field effect transistor that is turned on / off based on the logical product output signal F.

  The inverting input terminal − of the zero detection amplifier 18A is connected to the power supply output terminal Vout. When the zero detection amplifier 18A detects that the current flowing through the P-channel field effect transistor Q1 is zero by the fact that the voltage at the switch terminal SW has become the power supply output voltage Vout, the zero detection amplifier 18A supplies the zero detection signal to the drive circuit 17A. To do. In response to the zero detection signal, the drive circuit 17A turns off the P-channel field effect transistor Q1.

  Thus, in order to prevent the reverse current due to the P-channel field effect transistor Q1 being turned on, the zero detection amplifier 18A is prepared. Such a reverse current phenomenon occurs when the load current flowing through the load Rout is small.

  As an actual circuit, an inverter and a one-pulse circuit are inserted between the zero detection amplifier 18A and the drive circuit 17A.

  FIG. 6 shows a conventional step-up synchronous rectification DC / DC converter 30A. In FIG. 6, the circuit portion of the drive unit prior to the drive circuit 17A is omitted.

As shown in FIG. 6, the zero detection signal output from the output terminal of the zero detection amplifier 18A is supplied to a set input terminal 20 _S of the one pulse circuit 20 via an inverter IV.

  FIG. 7 shows waveforms of respective parts of the conventional step-up synchronous rectification DC / DC converter 30A shown in FIG. 7A shows the waveform of the voltage G ′ at the switch terminal SW, FIG. 7B shows the waveform of the output signal (zero detection signal) H ′ of the zero detection amplifier 18A, and FIG. 7C shows the one-pulse circuit. The waveform of 20 output signals (one pulse) I ′ is shown.

Until time t reaches the time t _1, the drive circuit 17A maintains the N-channel field effect transistor Q2 in the ON state, maintains the P-channel field effect transistor Q1 in the off state. As a result, the voltage G ′ at the switch terminal SW is zero.

When the time t has reached the time t _1, the drive circuit 17A is an N-channel field effect transistor Q2 off, the P-channel field effect transistor Q1 is turned on. As a result, the voltage G ′ at the switch terminal SW becomes higher than the power supply output voltage Vout, and a current flows from the switch terminal SW to the power supply output terminal Vout through the first parasitic diode D1. 'Because becomes higher than the power supply output voltage Vout, after its own response time t _d has elapsed zero detection amplifier 18A from time t _1, the output signal H' voltage G on the switch terminal SW logic from the logic "0" level Transition to the “1” level. This response time t _d is, for example, several tens of nanoseconds.

On the other hand, the one-pulse circuit 20 changes its output signal I ′ from the logic “0” level to the logic “1” level at time t ₁ .

At time t is time t _2, the when the voltage G of the switch terminal SW is equal to the power supply output voltage Vout, the zero detection amplifier 18A shifts the output signal from the logic "1" level to logic "0" level. That is, the zero detection amplifier 18A outputs a zero detection signal.

At time t the time t _3, the drive circuit 17A is a N-channel field effect transistor Q2 in the on state, to turn off the P-channel field effect transistor Q1. As a result, the voltage G ′ at the switch terminal SW becomes zero again. Since the voltage G ′ at the switch terminal SW is zero and the output signal H ′ of the zero detection amplifier 18A is at the logic “0” level, the output signal I ′ of the one-pulse circuit 20 is changed from the logic “1” level to the logic “0” level. Transition.

As a result, the output signal I ′ of the _one- pulse circuit 20 is at a logic “1” level during a time T ₁ from time t ₁ to time t ₃ . The drive circuit 17A turns off the P-channel field effect transistor Q1 while the output signal I ′ of the one-pulse circuit 20 is at the logic “1” level.

  As a prior art document related to the present invention, a DC / DC converter is known in which high efficiency is maintained and output ripple is reduced even when a current required by a load is small (Patent Document). 1).

JP-A-10-225105

  As described above, the zero detection amplifier 18 is prepared in the step-down DC / DC converter 10A in order to prevent a reverse current due to the N-channel field effect transistor Q2 being turned on. That is, the on-resistance of the N-channel field effect transistor Q2 is used as a detection resistor to detect that the current flowing therethrough becomes zero and to turn off the N-channel field effect transistor Q2.

However, in the conventional step-down synchronous rectification DC / DC converter 10A, because of the response time _{t d} to zero detection amplifier 18 itself, as shown in FIG. 4 (c), the set terminal 20 _S of the one pulse circuit 20 The timing of the signal on the side shifts, and the one-pulse circuit 20 outputs an incorrect output signal I. That is, the one-pulse circuit 20 must output a logic “1” level output signal I during time T ₂ from time t ₂ to time t ₃ as shown in FIG. despite, as shown in FIG. 4 (c), between time t ₁ of time T ₁ of the until time t _3, resulting in an output signal I of the logic "1" level.

  Similarly, the reason why the zero detection amplifier 18A is prepared in the step-up DC / DC converter 30A is to prevent a reverse current caused by turning on the P-channel field effect transistor Q1. That is, the on-resistance of the P-channel field effect transistor Q1 is used as a detection resistor to detect that the current flowing therethrough becomes zero and to turn off the P-channel field effect transistor Q1.

However, in the conventional step-up synchronous rectification DC / DC converter 30A, because of the response time _{t d} to zero detection amplifier 18A itself, as shown in FIG. 7 (c), the set terminal 20 _S of the one pulse circuit 20 The one-pulse circuit 20 outputs an incorrect output signal I ′ because the timing of the side signal is shifted. In other words, the one-pulse circuit 20 originally does not output a logic “1” level output signal I ′ during a time T ₂ from time t ₂ to time t ₃ as shown in FIG. In spite of this, as shown in FIG. 7C, the output signal I ′ at the logic “1” level is output during the time T ₁ from the time t ₁ to the time t ₃ .

  Accordingly, an object of the present invention is to provide a step-down DC / DC converter that can prevent erroneous output of a one-pulse circuit.

  Another object of the present invention is to provide a step-up DC / DC converter that can prevent erroneous output of a one-pulse circuit.

The step-down DC / DC converter according to the first embodiment to which the present invention is applied has a ground terminal having a ground potential and a power input terminal (V _DD ), and a DC input is provided between the ground terminal and the power input terminal. An input power supply (25) for applying a voltage (V _DD ), a first main electrode terminal connected to the power supply input terminal, a second main electrode terminal connected to a switch terminal (SW), and a first control A first transistor (Q1) having a first control terminal to which a voltage is supplied; a third main electrode terminal connected to the switch terminal; a fourth main electrode terminal connected to the ground terminal; A second transistor (Q2) having a second control terminal to which a control voltage of 2 is supplied, an inductor (L) connected between the switch terminal and a power output terminal (Vout), and the power output Connected between the terminal and the ground terminal, An output circuit (Ro, Co) that generates a DC output voltage lower than the DC input voltage between these terminals and the first and second transistors so that the first and second transistors are not turned on simultaneously. Drive unit (12, 13, 14, 15, AND, 17, 18, 20, 22; 22A) for driving the transistors.

According to the step-down DC / DC converter according to the first aspect of the present invention, the drive unit has a response time (t _d ), is connected to the switch terminal, and a current flowing through the second transistor is Zero detection means (18) that detects zero and outputs a zero detection signal, and is connected to the switch terminal, and the voltage at the switch terminal has a delay time (t _c ) longer than the response time. Delay means (22, 22A) for delaying and outputting a delayed voltage, a reset input terminal (20 _R ) for receiving the delayed voltage, and a set input terminal (20 _S ) for receiving the zero detection signal A one-pulse circuit (20) for outputting one pulse in response to the zero detection signal, and means (17) for turning off the second transistor (Q2) in response to the one pulse. To.

In the step-down DC / DC converter, the first transistor has a source, a drain, and a gate as the first main electrode terminal, the second main electrode terminal, and the first control terminal, respectively. The second transistor includes a drain, a source, and a third main electrode terminal, a fourth main electrode terminal, and a second control terminal, respectively. , And an N-channel field effect transistor (Q2) having a gate. The one-pulse circuit (20) is composed of, for example, an SR flip-flop circuit composed of two NOR gates (G1, G2). Said delay means (22) is connected to the switch terminal, amplifies the voltage at the switch terminals, a buffer (B1) for outputting the amplified voltage has a gate receiving the voltage the amplifier, the source A grounded N-channel field effect transistor (Q3); a current source (IO) connected between the drain of the N-channel field effect transistor and the power input terminal; a drain of the N-channel field effect transistor; An input terminal is connected to the capacitor (C2) connected between the ground terminal and the drain of the N-channel field effect transistor, the voltage across the capacitor is inverted, and the inverted voltage is reduced to the delayed voltage. As an inverter (I2). Instead, the delay means (22A) may be composed of a delay circuit in which an even number of inverters are cascade-connected.

A step-up DC / DC converter according to a second embodiment to which the present invention is applied has a ground terminal having a ground potential and a power input terminal (V _DD ), and a DC input is provided between the ground terminal and the power input terminal. The first main electrode terminal is connected to the input power supply (25) for applying the voltage (V _DD ), the power supply output terminal (Vout), the second main electrode terminal is connected to the switch terminal (SW), and the first A first transistor (Q1) having a first control terminal to which the control voltage is supplied, a third main electrode terminal connected to the switch terminal, and a fourth main electrode terminal connected to the ground terminal. A second transistor (Q2) having a second control terminal to which a second control voltage is supplied, and an inductor (L) connected between the switch terminal and the power input terminal (V _DD ), , The power output terminal and the ground terminal And the first circuit and the second transistor are not turned on at the same time, and an output circuit (Ro, Co) that generates a DC output voltage higher than the DC input voltage between the terminals. And a drive unit (12, 13, 14, 15, AND, 17A, 18A, 20, 22 ' ; 22B) for driving the second transistor.

According to the step-up DC / DC converter according to the second aspect of the present invention, the drive unit has a response time (t _d ), is connected to the switch terminal, and a current flowing through the first transistor is Zero detection means (18A) for detecting zero and outputting a zero detection signal, and connected to the switch terminal, the voltage at the switch terminal is set to a delay time (t _c ) longer than the response time. A delay means ( 22 ' ; 22B) for outputting a delayed voltage with a delay by a delay, a reset input terminal (20R) for receiving the delayed voltage, and a set for receiving the zero detection signal via an inverter (IV). A one-pulse circuit (20) having an input terminal (20S) and outputting a one-pulse in response to the zero detection signal; and in response to the one-pulse, the first transistor (Q1). Means for turning off.

In the step-up DC / DC converter, the first transistor has a source, a drain, and a gate as the first main electrode terminal, the second main electrode terminal, and the first control terminal, respectively. The second transistor includes a drain, a source, and a third main electrode terminal, a fourth main electrode terminal, and a second control terminal, respectively. , And an N-channel field effect transistor (Q2) having a gate. The one-pulse circuit (20) is composed of, for example, an SR flip-flop circuit composed of two NOR gates (G1, G2). The delay means ( 22 ′ ) is connected to the switch terminal, inverts the voltage at the switch terminal, and outputs a first inversion voltage, and the first inversion voltage. An N-channel field effect transistor (Q3) having a gate for receiving the source and a grounded source; a current source (IO) connected between a drain of the N-channel field effect transistor and the power input terminal; A capacitor (C2) connected between the drain of the channel field-effect transistor and the ground terminal; and an input terminal connected to the drain of the N-channel field-effect transistor, inverting the voltage across the capacitor; A second inverter (I2) that outputs a second inverted voltage as the delayed voltage may be included. Instead, the delay means (22B) may be composed of a delay circuit in which an odd number of inverters are cascaded.

  In addition, the code | symbol in the said parenthesis is attached | subjected in order to make an understanding of this invention easy, and it is only an example, and of course is not limited to these.

  In the present invention, since the delay time of the delay means is longer than the response time of the zero detection means, there is an effect that an erroneous output of the one-pulse circuit can be prevented.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A step-down synchronous rectification DC / DC converter 10B according to the first embodiment of the present invention will be described with reference to FIG. The illustrated step-down synchronous rectification DC / DC converter 10B has the same configuration as the conventional step-down synchronous rectification DC / DC converter 10A illustrated in FIG. 3 except that a delay circuit 22 is added. The same operation is performed. Accordingly, components having the same functions as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted for the sake of simplicity.

The delay circuit 22 is inserted between the switch terminal SW and the reset input terminal 20 _R of the one-pulse circuit 20. The delay circuit 22 delays the voltage G at the switch terminal SW by a delay time t _c and outputs a delayed voltage J.

The illustrated delay circuit 22 includes a current source IO, a buffer B1, an inverter I2, an N-channel field effect transistor Q3, and a capacitor C2.

The input terminal of the buffer B1 is connected to the switch terminal SW. The buffer B1 amplifies the voltage G at the switch terminal SW and outputs the amplified voltage. The output terminal of the buffer B1 is connected to the gate of the N-channel field effect transistor Q3. That is, the amplified voltage is supplied from the buffer B1 to the gate of the N-channel field effect transistor Q3. The source of the N-channel field effect transistor Q3 is grounded, and the drain is connected to the power input terminal V _DD via the current source IO. That is, the current source IO is connected between the drain of the N-channel field effect transistor Q3 and the power input terminal V _DD .

The drain of the N-channel field effect transistor Q3 is grounded through the capacitor C2. In other words, the capacitor C2 is connected between the drain of the N-channel field effect transistor Q3 and the ground terminal. Further, the drain of the N-channel field effect transistor Q3 is also connected to the input terminal of the second inverter I2. The inverter I2 inverts the voltage across the capacitor C2 and outputs the inverted voltage as a delayed voltage. An output terminal of the inverter I2 is connected to the reset input terminal 20 _R of the one-pulse circuit 20.

Such a configuration of the delay circuit 22 has an N-channel field-effect transistors Q3, and a current source IO, the delay time t _c which is set by the capacitor C2. This delay time t _c is longer than the response time t _d of the zero detection amplifier 18 (t _c > t _d ).

The one-pulse circuit 20 has a reset input terminal 20 _R that receives the delayed voltage J and a set input terminal 20 _S that receives the zero detection signal H. The one pulse circuit 20 outputs a one pulse in response to the zero detection signal. In response to the one pulse, the drive circuit 17 turns off the N-channel field effect transistor Q2.

  FIG. 9 shows waveforms of respective parts of the step-down synchronous rectification DC / DC converter 10B shown in FIG. 9A shows the waveform of the voltage G at the switch terminal SW, FIG. 9B shows the waveform of the output signal (zero detection signal) H of the zero detection amplifier 18, and FIG. 9C shows the waveform of the delay circuit 22. The waveform of the output signal (delayed voltage) J is shown, and (d) shows the waveform of the output signal (one pulse) I of the one-pulse circuit 20.

Until time t reaches the time t _1, the drive circuit 17 maintains the P-channel field effect transistor Q1 in the on state, and maintains the N-channel field effect transistor Q2 off. As a result, the voltage G at the switch terminal SW is the DC input voltage V _DD .

When the time t has reached the time t _1, the driving circuit 17 is a P-channel field effect transistor Q1 in the OFF state, the N-channel field effect transistor Q2 is turned on. As a result, the voltage G at the switch terminal SW becomes a negative voltage, and a current flows from the ground terminal to the switch terminal SW via the second parasitic diode D2. Since the voltage G of the switch terminal SW becomes negative voltage, when the zero detection amplifier 18 has passed its own response time t _d from the time t _1, the logic and the output signal H "1" logic level to the "0" Transition to level.

On the other hand, the delay circuit 22 transitions the output signal J from the logic “1” level to the logic “0” level when the delay time t _c elapses from the time t ₁ .

Since the delay time t _c of the delay circuit 22 is longer than the response time t _d of the zero detection amplifier 18, the one-pulse circuit 20 does not transition the level of the output signal I.

When the time t is the time t ₂ and the voltage G at the switch terminal SW becomes zero, the zero detection amplifier 18 changes the output signal H from the logic “0” level to the logic “1” level. That is, the zero detection amplifier 18 outputs a zero detection signal. Since the output signal J of the delay circuit 22 is the logic “0” level and the output signal H of the zero detection amplifier 18 is the logic “1” level, the one-pulse circuit 20 changes the output signal I from the logic “0” level to the logic “1” level. Transition to. That is, the one pulse circuit 20 outputs a one pulse in response to the zero detection signal.

At time t the time t _3, the drive circuit 17, a P-channel field effect transistor Q1 in the on state, to turn off the N-channel field effect transistor Q2. As a result, the voltage G at the switch terminal SW becomes the power input voltage V _DD again. At the same time, the delay circuit 22 changes its output signal J from the logic “0” level to the logic “1” level at time t ₃ . Therefore, the output signal I of the one-pulse circuit 20 also becomes a logic "0" level at this time _{t 3.}

As a result, the output signal I of the one-pulse circuit 20 is at the logic “1” level during the time T ₂ from the time t ₂ to the time t ₃ .

As described above, the driving circuit 17, since the time t ₃ has a N-channel field effect transistor Q2 off, the drive circuit 17, in addition, from time t ₂ at time t ₃ of the time T ₂ In the meantime, the N-channel field effect transistor Q2 is turned off.

Thus, according to the present embodiment, since the delay time t _c of the delay circuit 22 is set longer than the response time t _d of the zero detection amplifier 18, an erroneous output of the one-pulse circuit 20 can be prevented.

  With reference to FIG. 10, a step-down synchronous rectification DC / DC converter 10C according to a second embodiment of the present invention will be described. The illustrated step-down synchronous rectification DC / DC converter 10C has the same configuration as the step-down synchronous rectification DC / DC converter 10B illustrated in FIG. 8 except that the configuration of the delay circuit is different. To work. Therefore, the reference numeral 22A is assigned to the delay circuit, and the same reference numerals are assigned to components having the same functions as those shown in FIG. 8, and the description thereof is omitted for the sake of simplicity. To do.

  The delay circuit 22A is composed of a delay circuit in which four inverters are connected in cascade.

Such a configuration of the delay circuit 22A, having a delay time t _c which is defined by the inverter stages. This delay time t _c is longer than the response time t _d of the zero detection amplifier 18 (t _c > t _d ).

  FIG. 11 shows waveforms of respective parts of the step-down synchronous rectification DC / DC converter 10C shown in FIG. 11A shows the waveform of the voltage G at the switch terminal SW, FIG. 11B shows the waveform of the output signal (zero detection signal) H of the zero detection amplifier 18, and FIG. 11C shows the waveform of the delay circuit 22A. The waveform of the output signal (delayed voltage) Ja is shown, and (d) shows the waveform of the output signal (one pulse) Ia of the one-pulse circuit 20.

Until time t reaches the time t _1, the drive circuit 17 maintains the P-channel field effect transistor Q1 in the on state, and maintains the N-channel field effect transistor Q2 off. As a result, the voltage G at the switch terminal SW is the DC input voltage V _DD .

When the time t has reached the time t _1, the driving circuit 17 is a P-channel field effect transistor Q1 in the OFF state, the N-channel field effect transistor Q2 is turned on. As a result, the voltage G at the switch terminal SW becomes a negative voltage, and a current flows from the ground terminal to the switch terminal SW via the second parasitic diode D2. Since the voltage G at the switch terminal SW becomes a negative voltage, the zero detection amplifier 18 changes its output signal H from the logic “1” level to the logic “0” when its own response time t _d elapses from the time t _1. Transition to level.

On the other hand, the delay circuit 22A, at the time of the lapse of the delay time _{t c} from the time _{t 1,} a transition the output signal Ja from the logic "1" level to logic "0" level.

Since long delay time t _c of the delay circuit 22A than the response time of the zero detection amplifier 18 t _d, the one pulse circuit 20 does not shift the level of the output signal Ia.

When the time t is the time t ₂ and the voltage G at the switch terminal SW becomes zero, the zero detection amplifier 18 changes the output signal H from the logic “0” level to the logic “1” level. That is, the zero detection amplifier 18 outputs a zero detection signal. Since the output signal Ja of the delay circuit 22A is the logic “0” level and the output signal H of the zero detection amplifier 18 is the logic “1” level, the one-pulse circuit 20 changes the output signal Ia from the logic “0” level to the logic “1” level. Transition to. That is, the one pulse circuit 20 outputs a one pulse in response to the zero detection signal.

At time t the time t _3, the drive circuit 17, a P-channel field effect transistor Q1 in the on state, to turn off the N-channel field effect transistor Q2. As a result, the voltage G at the switch terminal SW becomes the power input voltage V _DD again.

Delay circuit 22A at the time _{t 4} when the delay time _{t c} has elapsed from time _{t 3,} the transition and the output signal Ja from the logic "0" level to logic "1" level. Therefore, the output signal Ia of the one-pulse circuit 20 also becomes a logic “0” level at this time t4.

As a result, the output signal Ia of the one-pulse circuit 20 from the time _{t 2} of time T3 at time _{t 4,} a logic "1" level.

As described above, the driving circuit 17, since the time t ₃ has a N-channel field effect transistor Q2 off, the drive circuit 17, in addition, from time t ₂ at time t ₃ of the time T ₂ In the meantime, the N-channel field effect transistor Q2 is turned off.

Thus, according to the present embodiment, since the delay time t _c of the delay circuit 22A is made longer than the response time t _d of the zero detection amplifier 18, an erroneous output of the one-pulse circuit 20 can be prevented.

With reference to FIG. 12, a step-up synchronous rectification DC / DC converter 30B according to a third embodiment of the present invention will be described. The step-down synchronous rectification DC / DC converter 30B shown has the same configuration as the conventional step-down synchronous rectification DC / DC converter 30A shown in FIG. 6 except that a delay circuit 22 ′ is added. , Do the same. Accordingly, components having the same functions as those shown in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted for the sake of simplicity.

Delay circuit 22 ', except for using an inverter I1 instead of the buffer B1, has the same configuration as the delay circuit 22 shown in FIG.

The delay circuit 22 ′ having such a configuration has a delay time t _c set by the N-channel field effect transistor Q3, the current source IO, and the capacitor C2. This delay time t _c is longer than the response time t _d of the zero detection amplifier 18A (t _c > t _d ).

The one pulse circuit 20 has 'a reset input terminal 20 _R for receiving a zero detection signal H' voltage J delayed a set input terminal 20 _S for receiving a signal obtained by inverting the inverter IV. The one pulse circuit 20 outputs a one pulse in response to the inverted zero detection signal. In response to the one pulse, the drive circuit 17A turns off the P-channel field effect transistor Q1.

FIG. 13 shows waveforms of respective parts of the step-up type synchronous rectification DC / DC converter 30B shown in FIG. 13A shows the waveform of the voltage G ′ at the switch terminal SW, FIG. 13B shows the waveform of the output signal (zero detection signal) H ′ of the zero detection amplifier 18A, and FIG. 13C shows the delay circuit. The waveform of the output signal (delayed voltage) J ′ of 22 ′ is shown, and (d) shows the waveform of the output signal (one pulse) I ′ of the one-pulse circuit 20.

Until time t reaches the time t _1, the drive circuit 17A maintains the N-channel field effect transistor Q2 in the ON state, maintains the P-channel field effect transistor Q1 in the off state. As a result, the voltage G at the switch terminal SW is zero.

When the time t has reached the time t _1, the drive circuit 17A is an N-channel field effect transistor Q2 off, the P-channel field effect transistor Q1 is turned on. As a result, the voltage G ′ at the switch terminal SW becomes higher than the power supply output voltage Vout, and a current flows from the switch terminal SW to the power supply output terminal Vout via the first parasitic diode D1. Since the voltage G of the switch terminals SW 'is higher than the power supply output voltage Vout, at zero detection amplifier 18A is a lapse its own response time t _d from the time t _1, the output signal H from the logic "0" level Transition to logic “1” level.

On the other hand, the delay circuit 22 ', at the time of the lapse of the delay time _{t c} from the time _{t 1,} the output signal J' transitions from a logic "1" level to logic "0" level.

Since the delay time t _c of the delay circuit 22 ′ is longer than the response time t _d of the zero detection amplifier 18A, the one-pulse circuit 20 does not transition the level of the output signal I ′.

At time t is time t _2, the when the voltage G 'of the switch terminal SW becomes the power supply output voltage Vout, the zero detection amplifier 18A shifts the output signal H to a logic "0" level from a logic "1" level. That is, the zero detection amplifier 18A outputs a zero detection signal. Since the output signal J ′ of the delay circuit 22 ′ is the logic “0” level and the output signal H ′ of the zero detection amplifier 18A is the logic “1” level, the one-pulse circuit 20 changes the output signal I ′ from the logic “0” level to the logic “0” level. Transition to the “1” level. That is, the one pulse circuit 20 outputs a one pulse in response to the zero detection signal.

At time t the time t _3, the drive circuit 17A is a N-channel field effect transistor Q2 in the on state, to turn off the P-channel field effect transistor Q1. As a result, the voltage G ′ at the switch terminal SW becomes zero again. At the same time, the delay circuit 22 ', at time _{t 3,} the output signal J' transitions from a logic "0" level to logic "1" level. Therefore, the output signal I 'is also the one-pulse circuit 20, a logic "0" level at this time _{t 3.}

As a result, the output signal I ′ of the one-pulse circuit 20 is at the logic “1” level during the time T ₂ from the time t ₂ to the time t ₃ .

As described above, the drive circuit 17A, since the time _{t 3} has a P-channel field effect transistor Q1 in the off state, the drive circuit 17A includes, in addition to this, from the time _{t 2} at time _{t 3} of the time _{T 2} In the meantime, the P-channel field effect transistor Q1 is turned off.

Thus, according to the present embodiment, since the delay time t _c of the delay circuit 22 ′ is set longer than the response time t _d of the zero detection amplifier 18A, an erroneous output of the one-pulse circuit 20 can be prevented.

  With reference to FIG. 14, a step-up synchronous rectification DC / DC converter 30C according to a fourth embodiment of the present invention will be described. The illustrated step-up type synchronous rectification DC / DC converter 30C has the same configuration as the step-up type synchronous rectification DC / DC converter 30B illustrated in FIG. 12 except that the configuration of the delay circuit is different. To work. Therefore, the reference numeral 22B is attached to the delay circuit, and the same reference numerals are attached to the components having the same functions as those shown in FIG. 12, and the description thereof is omitted for the sake of simplicity. To do.

  The delay circuit 22B is composed of a delay circuit in which five inverters are connected in cascade.

The delay circuit 22B having such a configuration has a delay time t _c defined by the number of inverter stages. This delay time t _c is longer than the response time t _d of the zero detection amplifier 18A (t _c > t _d ).

  FIG. 15 shows waveforms of respective parts of the step-up type synchronous rectification DC / DC converter 30C shown in FIG. 15A shows the waveform of the voltage G ′ at the switch terminal SW, FIG. 15B shows the waveform of the output signal (zero detection signal) H ′ of the zero detection amplifier 18A, and FIG. 15C shows the delay circuit. 22B shows the waveform of the output signal (delayed voltage) Ja ′ of 22B, and (d) shows the waveform of the output signal (one pulse) Ia ′ of the one-pulse circuit 20.

Until time t reaches the time t _1, the drive circuit 17A maintains the N-channel field effect transistor Q2 in the ON state, maintains the P-channel field effect transistor Q1 in the off state. As a result, the voltage G ′ at the switch terminal SW is zero.

When the time t has reached the time t _1, the drive circuit 17A is an N-channel field effect transistor Q2 off, the P-channel field effect transistor Q1 is turned on. As a result, the voltage G ′ at the switch terminal SW becomes higher than the power supply output voltage Vout, and a current flows from the switch terminal Sw to the power supply output terminal Vout through the first parasitic diode D1. Since the voltage G 'of the switch terminal SW is higher than the power supply output voltage Vout, at zero detection amplifier 18A is a lapse its own response time t _d from the time t _1, the output signal H from the logic "0" level Transition to logic “1” level.

On the other hand, the delay circuit 22B is at the time of the lapse of the delay time _{t c} from the time _{t 1,} a transition the output signal Ja 'from the logic "1" level to logic "0" level.

Since long delay time _{t c} of the delay circuit 22B than the response time of the zero detection amplifier 18A _{t d,} the one pulse circuit 20 does not shift the level of the output signal Ia '.

At time t the time t _2, 'when is the power supply output voltage Vout, the zero detection amplifier 18A outputs signal H' voltage G of the switch terminal SW transitions to a logic "0" level from a logic "1" level. That is, the zero detection amplifier 18A outputs a zero detection signal. Since the output signal Ja ′ of the delay circuit 22B is the logic “0” level and the output signal H ′ of the zero detection amplifier 18A is the logic “0” level, the one-pulse circuit 20 changes the output signal Ia ′ from the logic “0” level to the logic “0”. Transition to 1 "level. That is, the one pulse circuit 20 outputs a one pulse in response to the zero detection signal.

At time t the time t _3, the drive circuit 17A is a N-channel field effect transistor Q2 in the on state, to turn off the P-channel field effect transistor Q1. As a result, the voltage G ′ at the switch terminal SW becomes zero again.

The delay circuit 22B is the time _{t 4} when the delay time _{t c} has elapsed from time _{t 3,} the transition and the output signal Ja 'from the logic "0" level to logic "1" level. Therefore, the output signal Ia 'also one-pulse circuit 20, a logic "0" level at this time _{t 4.}

As a result, the output signal Ia ′ of the one-pulse circuit 20 is at the logic “1” level during the time T ₃ from time t ₂ to time t ₄ .

As described above, the drive circuit 17A, since the time _{t 3} has a P-channel field effect transistor Q1 in the off state, the drive circuit 17A includes, in addition to this, from the time _{t 2} at time _{t 3} of the time _{T 2} In the meantime, the P-channel field effect transistor Q1 is turned off.

Thus, according to the present embodiment, since the delay time t _c of the delay circuit 22B is set longer than the response time t _d of the zero detection amplifier 18A, an erroneous output of the one-pulse circuit 20 can be prevented.

  Although the present invention has been described above with reference to preferred embodiments, it is needless to say that the present invention is not limited to the above-described embodiments. For example, the delay circuit is not limited to that of the above-described embodiment, and various types can be used. For example, in the case of a step-down synchronous rectification DC / DC converter, an even number of inverters connected in cascade can be used as a delay circuit. In the case of a step-up synchronous rectification DC / DC converter, a delay circuit can be used. An odd number of inverters connected in cascade can be used.

It is a block diagram which shows the structure of the pressure | voltage fall type synchronous rectification DC / DC converter to which this invention is applied. 2 is a time chart showing waveforms of respective parts of the step-down synchronous rectification DC / DC converter shown in FIG. 1. It is a block diagram which shows the structure of the conventional pressure | voltage fall type synchronous rectification DC / DC converter. 4 is a time chart showing waveforms of respective parts of the conventional step-down synchronous rectification DC / DC converter shown in FIG. 3. It is a block diagram which shows the structure of the step-up type synchronous rectification DC / DC converter to which this invention is applied. It is a block diagram which shows the structure of the conventional step-up type synchronous rectification DC / DC converter. It is a time chart which shows the waveform of each part of the conventional step-up type synchronous rectification DC / DC converter shown in FIG. 1 is a block diagram showing a configuration of a step-down synchronous rectification DC / DC converter according to a first embodiment of the present invention. It is a time chart which shows the waveform of each part of the pressure | voltage fall type synchronous rectification DC / DC converter shown in FIG. It is a block diagram which shows the structure of the pressure | voltage fall type synchronous rectification DC / DC converter by the 2nd Embodiment of this invention. 11 is a time chart showing waveforms of respective parts of the step-down synchronous rectification DC / DC converter shown in FIG. 10. It is a block diagram which shows the structure of the step-up type synchronous rectification DC / DC converter by the 3rd Embodiment of this invention. 13 is a time chart showing waveforms of respective parts of the step-up type synchronous rectification DC / DC converter shown in FIG. 12. It is a block diagram which shows the structure of the step-up type synchronous rectification DC / DC converter by the 4th Embodiment of this invention. It is a time chart which shows the waveform of each part of the step-up type synchronous rectification DC / DC converter shown in FIG.

Explanation of symbols

10B, 10C step-down synchronous rectification DC / DC converter Q1 first transistor (P-channel field effect transistor)
Q2 Second transistor (N-channel field effect transistor)
L Inductor 25 Input power supply Co Capacitor Ro Resistor Rout Load V _DD Power supply input terminal (DC input voltage)
Vout Power supply output terminal (DC output voltage)
17, 17A Drive circuit 18, 18A Zero detection amplifier 20 One pulse circuit 22, 22 ', 22A, 22B Delay circuit 30B, 30C Boost type synchronous rectification DC / DC converter

Claims (10)

An input power source having a ground terminal of a ground potential and a power input terminal, and applying a DC input voltage between the ground terminal and the power input terminal;
A first transistor having a first control terminal to which a first main electrode terminal is connected to the power input terminal, a second main electrode terminal is connected to a switch terminal, and a first control voltage is supplied;
A second transistor having a second control terminal to which a third main electrode terminal is connected to the switch terminal, a fourth main electrode terminal is connected to the ground terminal, and a second control voltage is supplied;
An inductor connected between the switch terminal and the power output terminal;
An output circuit connected between the power output terminal and the ground terminal, and generating a DC output voltage lower than the DC input voltage between the terminals;
In a step-down DC / DC converter including a drive unit that drives the first and second transistors so that the first and second transistors do not turn on at the same time.
The drive unit is
Zero detection means having a response time, connected to the switch terminal, detecting that the current flowing through the second transistor is zero, and outputting a zero detection signal;
Delay means connected to the switch terminal, delaying the voltage at the switch terminal by a delay time longer than the response time, and outputting a delayed voltage;
A one-pulse circuit having a reset input terminal for receiving the delayed voltage and a set input terminal for receiving the zero detection signal, and outputting a one pulse in response to the zero detection signal;
And a means for turning off the second transistor in response to the one pulse. The first transistor comprises a P-channel field effect transistor having a source, a drain, and a gate as the first main electrode terminal, the second main electrode terminal, and the first control terminal,
The second transistor is an N-channel field effect transistor having a drain, a source, and a gate as the third main electrode terminal, the fourth main electrode terminal, and the second control terminal, respectively. The step-down DC / DC converter according to claim 1.   2. The step-down DC / DC converter according to claim 1, wherein the one-pulse circuit is constituted by an SR flip-flop circuit composed of two NOR gates. The delay means is
A buffer connected to the switch terminal, amplifying the voltage at the switch terminal, and outputting the amplified voltage;
An N-channel field effect transistor having a gate for receiving the amplified voltage and having a source grounded;
A current source connected between the drain of the N-channel field effect transistor and the power input terminal;
A capacitor connected between a drain of the N-channel field effect transistor and the ground terminal;
2. The step-down type according to claim 1, further comprising: an inverter having an input terminal connected to a drain of the N-channel field effect transistor, inverting a voltage across the capacitor, and outputting an inverted voltage as the delayed voltage. DC / DC converter.   2. The step-down DC / DC converter according to claim 1, wherein the delay means is composed of a delay circuit in which an even number of inverters are cascade-connected. An input power source having a ground terminal of a ground potential and a power input terminal, and applying a DC input voltage between the ground terminal and the power input terminal;
A first transistor having a first control terminal to which a first main electrode terminal is connected to a power output terminal, a second main electrode terminal is connected to a switch terminal, and a first control voltage is supplied;
A second transistor having a second control terminal to which a third main electrode terminal is connected to the switch terminal, a fourth main electrode terminal is connected to the ground terminal, and a second control voltage is supplied;
An inductor connected between the switch terminal and the power input terminal;
An output circuit connected between the power supply output terminal and the ground terminal and generating a DC output voltage higher than the DC input voltage between the terminals;
In a step-up DC / DC converter provided with a drive unit that drives the first and second transistors so that the first and second transistors are not turned on simultaneously,
The drive unit is
Zero detection means having a response time, connected to the switch terminal, detecting that the current flowing through the first transistor is zero, and outputting a zero detection signal;
Delay means connected to the switch terminal, delaying the voltage at the switch terminal by a delay time longer than the response time, and outputting a delayed voltage;
A one-pulse circuit having a reset input terminal for receiving the delayed voltage and a set input terminal for receiving the zero detection signal via an inverter, and outputting a one pulse in response to the zero detection signal;
And a means for turning off the first transistor in response to the one pulse. The first transistor comprises a P-channel field effect transistor having a source, a drain, and a gate as the first main electrode terminal, the second main electrode terminal, and the first control terminal,
The second transistor is an N-channel field effect transistor having a drain, a source, and a gate as the third main electrode terminal, the fourth main electrode terminal, and the second control terminal, respectively. The step-up DC / DC converter according to claim 6.   The step-up DC / DC converter according to claim 6, wherein the one-pulse circuit is configured by an SR flip-flop circuit including two NOR gates. The delay means is
A first inverter connected to the switch terminal and inverting a voltage at the switch terminal to output a first inverted voltage;
An N-channel field effect transistor having a gate receiving the first inversion voltage and having a source grounded;
A current source connected between the drain of the N-channel field effect transistor and the power input terminal;
A capacitor connected between the drain of the N-channel field effect transistor and the ground terminal;
2. An inverter having an input terminal connected to the drain of the N-channel field effect transistor, inverting the voltage across the capacitor, and outputting a second inverted voltage as the delayed voltage. 6. The step-up DC / DC converter according to 6.   The step-up DC / DC converter according to claim 6, wherein the delay unit includes a delay circuit in which an odd number of inverters are cascade-connected.

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