JP4557382B2 - Wiring board and manufacturing method thereof - Google Patents

Description

上記ガラスに対して、表１に示す組成物をプレス成形してドクターブレード法によって成形体を作製し、この成形体を７００℃のＮ₂＋Ｈ₂Ｏ中で脱バインダー処理した後、窒素雰囲気中で表１の条件で焼成して絶縁基板用のセラミックスを作製した。
【００４３】
このセラミックスについて、アルキメデス法に基づき開気孔率を測定し、また、誘電率、誘電損失、抗折強度、熱膨張係数を以下の方法で評価した。
【００４４】
誘電率、誘電損失については、直径２〜７ｍｍ、厚み２〜２．５ｍｍの形状に切り出し、６０ＧＨｚにてネットワークアナライザー、シンセサイズドスイーパーを用いて誘電体円柱共振器法により行った。測定では、ＮＲＤガイド（非放射性誘電体線路）で、誘電体共振器の励起を行い、ＴＥ₀₂₁またはＴＥ₀₃₁モードの共振特性より、誘電率、誘電損失を算出した。
【００４５】
また、試料を幅４ｍｍ×厚さ３ｍｍ×長さ７０ｍｍの形状に切り出し、ＪＩＳＣ−２１４１の規定に基づいて３点曲げ試験を行った。さらに、室温から４００℃における熱膨張曲線をとり、熱膨張係数を算出した。また、磁器の焼肌面の表面粗さ（Ｒａ）を表面粗さ計にて測定し、表１に示した。
【００４６】
【表１】

【００４７】
また、表１における各原料組成物を用いて、ドクターブレード法により厚み５００μｍのグリーンシートを作製し、このシートにビアホールを形成し、Ｃｕメタライズペーストをスクリーン印刷法に充填し、さらにメタライズパッドのパターンをスクリーン印刷で塗布した。
【００４８】
そして、メタライズペーストが塗布、充填されたグリーンシートをスルーホールの位置合わせを行いながら６枚積層し圧着した。この積層体を７００℃でＮ₂＋Ｈ₂Ｏ中で脱バインダー後、表１と同じ条件で焼成して配線基板を作製した。
【００４９】
また、上記配線基板の絶縁基板表面に、真空蒸着法によって、Ｔｉ層を０．２μｍの厚さで形成した後、種々のＴｉＷ，ＴｉＭｏ，Ｎｉ，Ｃｒ，Ｔａの種々の金属層を厚み１０μｍで形成した後、Ｃｕ層を３μｍの厚みで形成した。なお、ＴｉＷおよびＴｉＭｏの合金層中のＷ、Ｍｏ含有量は９０重量％である。
【００５０】
その後、この薄膜金属層に感光性フォトレジストを一面に塗布し、フォトリソグラフィー技術によりエッチングマスクを作成し、薄膜層の一部を酸性エッチング液により不要部の薄膜を除去して、大きさが１×１ｍｍの評価用パッドを形成した。
【００５１】
そして、このパッドに対して、Ｃｕからなるピンを半田付けして、−４０℃と１２５℃の各温度に制御した恒温槽に配線基板を１５分／１５分の保持を１サイクルとして１００サイクルの熱サイクルを施した後に、このピンを垂直に引き上げ、半田もしくは薄膜金属層が離れた時の強度を薄膜金属層の接着強度として評価し、その結果を表２に示した。
【００５２】
また、上述と同様の方法により、絶縁基板表面に長さ３０．０ｍｍ、幅３．０ｍｍ、厚さ２０μｍの評価用パッドを２０個形成して各パッドのシート抵抗を測定し、その平均値をシート抵抗として算出した。
【００５３】
さらに、表１のガラスセラミックスの下面全面に銅ペーストを用いてガラスセラミックスとの同時焼成により形成したグランド層を設けるとともに、上述と同様にして、ガラスセラミックスの上面に厚み１５０μｍの上面に配線幅２６０μｍ、厚み１０μｍ、長さ１０、２０、３０μｍの薄膜配線層（インピーダンス５０Ω）を形成したマイクロストリップ線路３種を形成し、入力端子から１１０ＧＨｚの信号を入力し、透過した伝送信号強度をネットワークアナライザによって測定し、配線層の長さと信号強度の関係から最小二乗法によって薄膜配線層の伝送損失Ｓ₂₁を評価した。
【００５４】
【表２】

【００５５】
表１、２の結果から明らかなように、本発明に従い、所定のガラスとディオプサイド型酸化物結晶相と所定のフィラーとを含有するガラスセラミックスを絶縁基板として用いた試料Ｎｏ．２〜５、８〜１０、１２、１３、１５〜１８では、磁器の誘電損失が低くなり、また、薄膜配線層の伝送損失が−１．５ｄＢ／ｃｍより小さくなった。
さらに、接着強度が２２．５ＭＰａ以上と高い強度が得られた。
【００５６】
これに対して、フィラーを添加しない試料Ｎｏ．１、ガラス量が４０重量％より少ない試料Ｎｏ．７、ガラスセラミックスの焼成時間が０．２時間より短い試料Ｎｏ．１１、５時間より長い試料Ｎｏ．１４では、いずれも磁器の開気孔率が０．３％を越え、信号の伝送損失が−２ｄＢ／ｃｍ以上悪くなった。
【００５７】
また、ディオプサイド型酸化物結晶相を析出しないガラスを用いた試料Ｎｏ．１９、ディオプサイド型酸化物結晶相を析出するもののＳｒＯを含まないガラスを用いた試料Ｎｏ．２０では、開気孔率が２％よりも多く伝送損失の大きなものであった。
【００５８】
【発明の効果】
以上詳述したように、本発明によれば、絶縁基板の誘電損失を小さくできるとともに、絶縁基板表面のボイド率を低下させることができることから、微細で、低抵抗で、良好なインピーダンス特性を有し、高周波信号の導体損失を低減することができるとともに、絶縁基板に対して接着強度の高い薄膜配線層を有する配線基板を得ることができる。
【図面の簡単な説明】
【図１】本発明の多層配線基板の応用の一例である半導体素子収納用パッケージの多層配線層の構造を説明するための一部拡大断面図である。
【図２】図１のパッケージを外部回路基板への実装構造の一実施例を示した概略断面図である。
【符号の説明】
Ａ・・パッケージ
Ｂ・・外部回路基板
Ｘ 配線基板
Ｙ 多層配線層
１ａ，１ｂ，１ｃ 薄膜金属層
２ 絶縁膜
３ 絶縁基板
４ 半導体素子
５ 電極端子
６ 接続端子
７ メタライズパッド
８ ビアホール導体[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board having a thin film wiring layer formed on the surface of an insulating substrate, and more particularly to a wiring board including an insulating substrate having a smooth surface on which a thin film wiring layer can be satisfactorily formed and a method for manufacturing the same. is there.
[0002]
[Prior art]
Conventionally, a wiring board has, for example, an insulating substrate formed of alumina ceramics and the like, and a surface of the insulating substrate and / or a metallized wiring layer co-fired on the surface, and the insulating substrate surface has a low resistance. In order to form a thin film wiring layer capable of fine pattern wiring, for example, after polishing and smoothing the surface of the insulating substrate, the thin film is formed on the surface of the insulating substrate by chromium, titanium, tantalum, copper, etc. It is formed by laminating a thin film wiring layer made of the above metal and an insulating film made of an organic polymer material such as polyimide.
[0003]
Here, since the insulating substrate constituting the wiring substrate has a high firing temperature of about 1600 ° C., a refractory metal such as tungsten or molybdenum is used as the metallized wiring layer formed inside the insulating substrate.
[0004]
Alumina ceramics constituting the conventional insulating substrate as described above have a high dielectric constant and cannot transmit signals at high speed. Further, since the refractory metal constituting the metallized wiring layer has a high electric resistance, similarly, it is not possible to propagate a signal at high speed. Thus, it has been proposed to use glass ceramics having a low dielectric constant and a firing temperature of 1000 ° C. or lower, which can be fired at a low temperature, and using Cu or Ag having a low electrical resistance as a conductor.
[0005]
For example, in Japanese Patent Application Laid-Open No. 10-212136, the present applicant forms a Cu conductor wiring layer on the surface of a green sheet containing a mixture of glass such as lithium silicate and SiO ₂ filler, and fires it at 1000 ° C. or less. And proposed to make a wiring board.
[0006]
[Problems to be solved by the invention]
However, in the case where the insulating substrate is composed of glass ceramics including the above lithium silicate glass and SiO ₂ filler, a large amount of voids are present in the insulating substrate, and the smoothness of the substrate surface is impaired. The position accuracy of the thin film wiring layer formed on the surface is lowered, so that it is impossible to make a fine wiring, and the thin film wiring layer with a uniform thickness cannot be formed, and the impedance characteristic of the signal transmitted through the wiring layer As a result, the reflection of the high-frequency signal is increased and the signal cannot be transmitted satisfactorily.
[0007]
In addition, since the smoothness of the substrate is impaired by the voids, the unevenness at the interface of the thin film wiring layer through which high-frequency signals mainly pass increases, increasing the wiring resistance in the high-frequency band, increasing the conductor loss and increasing the high-frequency signals. There was also a problem that the transmission characteristics of the system deteriorated.
[0008]
Accordingly, the present invention provides a wiring board having an insulating substrate on which a thin-film wiring having a fine and uniform thickness is deposited on the surface, and in particular, can reduce the conductor loss of high-frequency signals, and a method for manufacturing the same. It is intended.
[0009]
[Means for Solving the Problems]
As a result of various investigations on the above problems, the present inventor has found that glass capable of precipitating a diopside oxide crystal phase containing SiO ₂ , Al ₂ O ₃ , MgO, SrO and CaO, and a filler By forming a thin film wiring layer on the surface of an insulating substrate having few voids after forming a mixture of at least one selected from the group consisting of at least Al ₂ O ₃ , MgSiO ₃ , AlN, and MgTiO ₃ , It has been found that a wiring board having a wiring layer having a low resistance, good impedance characteristics, and capable of reducing a conductor loss of a high-frequency signal can be manufactured.
[0010]
That is, the wiring board of the present invention includes a glass phase and a diopside oxide crystal phase containing SiO ₂ , Al ₂ O ₃ , MgO, SrO and CaO, and at least Al ₂ O ₃ , MgSiO ₃ , AlN and MgTiO _3. Including a Ti layer, a metal layer containing W or Mo, and a Cu layer on the surface of an insulating substrate made of a ceramic having an open porosity of 0.3% or less . and it has a thin-film wiring layer laminated in this order, in which the adhesive strength of the thin film wiring layer, characterized in der Rukoto least 22.5 MPa.
[0011]
In the wiring board, the surface roughness (Ra) of the surface of the insulating substrate on which the thin film wiring layer is formed is preferably 0.1 μm or less, and 60 to 77 GHz of the insulating substrate. in dielectric loss 50 × ^{10 -4} or less, the transmission characteristic _{S 21} in the following 110GHz of the thin-film wiring layer formed on the surface of the insulating substrate is preferably not more than -1.5 dB / cm.
[0013]
A method of manufacturing a wiring board of the present _{invention, SiO 2, Al 2 O 3} , MgO, SrO and CaO glass capable precipitate unrealized diopside-type oxide crystal phase 6 0-9 0% by weight, even without least by molding the _Al 2 _O 3, MgSiO _3, AlN and MgTiO mixture containing a ratio of from 10 to 4 0% by weight of at least one filler selected from the group consisting of ₃ to prepare a green sheet, 800 1000 and calcined by heating from 0.2 to 5 hours at ° C., a process of forming an insulating substrate open porosity is 0.3% or less of the ceramic, the surface of the insulating substrate, the thin film forming method, Ti layer, a metal layer and a Cu layer containing W or Mo, is characterized in that it comprises a step of forming a thin film wiring layer formed in this order, the.
[0014]
In the wiring board manufacturing method, the glass is SiO ₂ 30 to 55 wt%, Al ₂ O ₃ 4 to 15 wt%, MgO 14 to 30 wt%, CaO 5 to 20 wt%, and SrO 10 to 25 wt%. It is desirable to use what consists of%.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings showing embodiments. FIG. 1 is a partially enlarged cross-sectional view for explaining the structure of a multilayer wiring layer formed on the surface of a package for housing a semiconductor element composed of a multilayer wiring board as an example of application of the wiring board of the present invention.
[0017]
This configuration will be described in more detail. As shown in FIG. 1, the package A includes a wiring board X and a multilayer wiring layer Y having a laminated structure of a thin metal layer 1 and an insulating film 2 formed on the surface of the wiring board X. The multilayer wiring layer Y is formed by alternately laminating thin film metal layers and insulating films on the surface of the insulating substrate 3 of the wiring board X in the order of thin film metal layer-insulating film -...- insulating film-thin film metal layer. According to FIG. 1, the thin film metal layers 1a, 1b and 1c are formed, and the thin film metal layers 1a-1b, 1b-1c and Are electrically connected. The electrode terminal 5 of the semiconductor element 4 is mounted and connected to the thin film metal layer 1a on the outermost surface of the multilayer wiring layer Y.
[0018]
According to the present invention, in the multilayer wiring board constituting the package A having the above structure, the insulating substrate 3 includes glass containing SiO ₂ , Al ₂ O ₃ , MgO, SrO and CaO, and a diopside oxide crystal phase. , as a _{filler, Al 2 O 3, MgSiO 3} , AlN, containing at least one selected from the group consisting of MgTiO _3, a significant feature that consists of an open porosity of 0.3% or less of the glass ceramics.
[0019]
According to the present invention, a glass containing SiO ₂ , Al ₂ O ₃ , MgO, CaO and capable of precipitating a diopside oxide crystal phase of Ca (Mg, Al) (Si, Al) ₂ O _6. By combining SrO and at least one selected from the group consisting of Al ₂ O ₃ , MgSiO ₃ , AlN, and MgTiO ₃ as a filler and firing under predetermined conditions, the open porosity of the ceramic is reduced to 0. As a result of reducing the surface of the glass ceramic to 3% or less, particularly 0.2% or less, and containing at least one low resistance metal selected from the group of Cu, Ag and Au on the surface, for example, A fine and low-resistance thin-film wiring layer having a wiring width of 75 μm or less and an interval between wirings of 75 μm or less can be formed with a uniform thickness with high accuracy. That is, when the open porosity of the insulating substrate 3 exceeds 0.3%, the positional accuracy of the thin film wiring layer containing Cu, Ag or Au is lowered, fine wiring is not possible, and the thickness of the wiring layer varies. Impedance characteristics of signals transmitted through the wiring layer deteriorate, and transmission characteristics of high-frequency signals deteriorate.
[0020]
Further, in order to improve the productivity by omitting the ceramic polishing process and simplify the process, the surface roughness (Ra) of the surface of the glass ceramic is 0.1 μm or less, particularly 0.05 μm or less. desirable.
[0021]
In order to reduce the voids in the glass ceramic and reduce the open porosity, in order to reduce the dielectric loss in the high frequency band, the content of alkali metal, BaO, B ₂ O ₃ in the glass is an oxide. In terms of conversion, it is desirable that the amount be 5% by weight or less, particularly 1% by weight or less.
[0022]
The addition according to the present invention, with respect to the glass, at _{least for Al} 2 _O 3 _filler, MgSiO 3, AlN, in a ratio of at least one kind of 1 0-4 0% by weight selected from the group consisting of MgTiO _3, Although it is dispersed, the average particle size is 2 to 10 μm, particularly 3 to 3 in terms of enhancing wettability with glass and improving sinterability, suppressing void generation, increasing strength of ceramics, and reducing dielectric loss. The shape is preferably 7 μm, and the shape thereof may be spherical, but it may be an anisotropic particle having a needle-like or plate-like aspect ratio of 3 or more in terms of high strength and low dielectric loss.
[0023]
If the filler is not included, there is a problem that the void generation rate increases and the ceramic strength of the ceramic decreases.
[0024]
Further, the thin film metal layer 1 in the multilayer wiring layer Y includes at least one low-resistance metal selected from the group of Cu, Ag, and Au, and the group of Ti, W, Mo, Cr, Ni, Ta as other components It is desirable to have a structure in which a plurality of at least one metal layer selected from is laminated. In addition, in order to raise adhesive strength in the thin film metal layer 1c directly formed in the surface of the wiring board X among said thin film metal layers 1, it is 0.1-3 micrometers, especially 0.3-1.5 micrometers in thickness. It is desirable to form a metal layer containing W or Mo, whereby the adhesion strength of the thin film metal layer to the wiring board can be increased.
[0025]
Further, the W, Mo-containing layer preferably contains W and / or Mo in an amount of 50% by weight or more, particularly 70% by weight or more, and particularly preferably an alloy layer with Ti.
[0026]
Further, the thin metal layer 1c may be a laminate of a Cu layer and a W, Mo-containing layer. However, in order to increase the adhesive force between the wiring substrate X and the insulating substrate 3, a thickness of 0.05 on the surface of the wiring substrate X is provided. A W, Mo-containing layer is laminated through a Ti layer having a thickness of ˜0.5 μm, and a Cu-containing layer having a thickness of 1 to 10 μm is formed as the main conductor layer, so that the thickness is 1.5 to 15 μm as a whole. desirable. Further, a Cr layer may be formed on the surface in contact with the insulating film in order to improve the adhesion with the insulating film 2.
[0027]
Further, the thin metal layers 1a and 1b include at least one metal layer selected from the group of Cu, Ag and Au of at least 1 to 10 μm, and further from the group of Ti, W, Mo, Cr, Ni and Ta. It is desirable to include at least one selected metal layer, and in particular, by interposing a Cr layer between the Cu layer and the insulating film 2, the adhesive force with the insulating film can be increased. Similarly, the thickness of the thin metal layers 1a and 1b is suitably 1.5 to 15 μm.
[0028]
Further, as the insulating film 2 in the multilayer wiring layer Y, a polyimide-based or epoxy-based organic polymer material can be used. In particular, by using a polyimide-based organic polymer material, a polyimide-based organic polymer material is used. Since the linear thermal expansion coefficient of the material is about 20 ppm / ° C., the difference in linear thermal expansion coefficient between the insulating substrate 3 and the insulating film 2 is reduced, so that the linear thermal expansion coefficient is compared with the case where the insulating substrate 3 is made of alumina ceramics. The warp of the wiring board caused by the difference can be reduced. The thickness of the insulating film 2 is suitably 1 to 10 μm.
[0029]
The semiconductor element storage package A in FIG. 1 is composed of a wiring board X composed of at least one insulating substrate 3 and a multilayer wiring layer Y formed on the surface thereof. A semiconductor element 4 is mounted on the surface of the package A, and the semiconductor element 4 is electrically connected to an electrode terminal 5 formed on the lower surface thereof and a wiring layer on the surface of the package A. Further, as shown in FIG. 2, a connection terminal 6 for electrical connection to the external circuit board B is provided on the lower surface of the package A, and is electrically connected to the wiring conductor on the surface of the external circuit board B. As a result, the package A is mounted on the external circuit board B.
[0030]
In general, the electrode terminals 5 and the connection terminals 6 are preferably formed of a brazing material such as solder. When the package A is a BGA type package as shown in FIG. 1, the connection terminals 6 are solder balls. Formed by.
[0031]
The external circuit board B is made of, for example, an insulating material containing at least an organic resin, specifically, a glass-epoxy composite material, and generally a printed board having a linear thermal expansion coefficient of 13 to 16 ppm / ° C. Wiring made of a metal conductor such as Cu, Au, Al, Ni, Pb—Sn is formed on the surface of the insulating substrate.
[0032]
Further, a metallized pad 7 for connection to the external circuit board B is formed on the back surface of the package A. The thin film metal layer 1a on the outermost surface of the multilayer wiring layer Y is a thin film metal layer in the multilayer wiring layer Y. They are electrically connected through via-hole conductors 8 formed so as to penetrate 1b and 1c and the insulating substrate 3.
[0033]
(Manufacturing method of a wiring board) In order to produce the wiring board which has the via-hole conductor 8 and the metallization pad 7 using said glass ceramic, first, for example, said glass component with an average particle diameter of 1-10 micrometers is 60-00. 9 0% by weight, after the addition of the average particle 10 to the filler component of the size 2 to 10 [mu] m 4 0 wt% suitable mixture in a mixing ratio of the molding of the organic resin binder, a desired forming means, for example, gold It is molded into an arbitrary shape by a die press, cold isostatic press, injection molding, extrusion molding, doctor blade method, calendar roll method, rolling method or the like.
In particular, a doctor blade method is suitable for producing a green sheet.
[0034]
Next, a through-hole for forming the via-hole conductor 8 is formed in the ceramic green sheet, and a conductive paste mainly containing copper or silver is filled in the through-hole, and the conductive paste is screen printed. Thus, the pattern of the metallized pad 7 is formed. Then, if necessary, a green sheet on which a metallized wiring layer and a via-hole conductor are formed is laminated in the same manner as described above.
[0035]
Further, the method for forming the metallized wiring layer is not limited to the above printing method, and it may be formed by transferring a transfer film formed with a metal foil of a predetermined wiring pattern formed on the surface to the surface of the green sheet. it can.
[0036]
Next, in firing the above-mentioned molded body, first, the binder component blended for molding is removed. The removal of the binder is performed in an air atmosphere at around 700 ° C. However, for example, when Cu is used as the conductor material, it is performed in a nitrogen atmosphere containing water vapor at 100 to 700 ° C. At this time, the shrinkage start temperature of the molded body is preferably about 700 to 850 ° C., and if the shrinkage start temperature is lower than this, it becomes difficult to remove the binder. It is necessary to control the yield point as described above.
[0037]
And by baking for 0.2 to 5 hours, especially 0.5 to 2 hours in an oxidizing atmosphere or non-oxidizing atmosphere at 800 to 1000 ° C., the open porosity of the fired glass ceramic is 0.3% or less. In particular, it is 0.2% or less, and the porosity inside the glass ceramic is 3% or less, particularly 1% or less. That is, if the firing temperature is lower than 800 ° C. or the firing time is shorter than 0.2 hours, the glass ceramic cannot be densified and the open porosity increases, and conversely the firing temperature exceeds 1000 ° C. This is because if the firing time is longer than 5 hours, the number of voids in the glass ceramic increases again.
[0038]
In addition, about the said baking, when co-firing with conductor materials, such as Cu, it calcinates in non-oxidizing atmospheres, such as nitrogen and nitrogen / hydrogen mixed atmosphere where a conductor material is not oxidized. Thereby, the wiring board X having the metallized pad 7 and the via-hole conductor 8 is obtained.
[0039]
In the glass ceramics produced as described above, the crystal phase generated from the glass component, the crystal phase generated by the reaction between the glass component and the filler component, the filler component, or the filler component is decomposed and generated. The crystal phase is present, and a glass phase is present at the grain boundary of these crystal phases.
(Multilayer wiring layer)
According to the present invention, the multilayer wiring layer Y is formed on the surface of the insulating substrate 3. The multilayer wiring layer Y is formed by the following process.
(1) A thin film metal layer made of a plurality of metal layers using a different deposition source by a thin film method such as a sputtering method, an ion plating method, or a vacuum deposition method on the entire upper surface of the wiring board X. The layer is formed to a thickness of 1.5 to 15 μm. Next, a photosensitive photoresist is applied on the entire surface of the thin film. Then, an etching mask is prepared by a well-known photolithography technique, and an unnecessary portion of the thin film metal layer is removed by reactive ion dry etching using an acidic etchant or a reactive gas (CCl4, BCl3). Thus, a thin film metal layer 1c having a predetermined pattern is obtained. Thereafter, the etching mask is removed by peeling.
(2) Next, the insulating film 2 made of an organic polymer insulating material such as polyimide is formed on the thin metal layer 1c. For example, a polymer solution of an organic polymer material is uniformly applied to the upper surface of the wiring board X by a spin coating method or the like, and heated to a temperature at which the organic polymer material is cured.
(3) Next, through holes for connection for connecting the upper and lower thin film metal layers are formed using a conventionally well-known photolithography technique.
[0040]
By repeatedly performing the above steps (1), (2), and (3), a predetermined plurality of thin-film metal layers and insulating films can be formed, thereby producing the multilayer wiring board of the present invention. Can do.
[0041]
In addition, a connection terminal for electrical connection with an external circuit board is appropriately attached to the multilayer wiring board, and a semiconductor element such as silicon is prepared for the multilayer wiring board, and is provided on the upper surface of the multilayer wiring board. Positioning is performed so that the electrode terminals of the semiconductor element are connected to the provided connection pads, and mounting is performed by solder or the like by a known flip-chip connection method.
[0042]
【Example】
In order to confirm the effect of the multilayer wiring board of the present invention, a multilayer wiring board for evaluation was produced as follows. First, a glass having the following composition was prepared.

The composition shown in Table 1 was press-molded with respect to the glass, and a molded body was prepared by a doctor blade method. The molded body was debindered in N ₂ + H ₂ O at 700 ° C., and then in a nitrogen atmosphere. Then, firing was performed under the conditions in Table 1 to produce ceramics for an insulating substrate.
[0043]
About this ceramic, the open porosity was measured based on the Archimedes method, and dielectric constant, dielectric loss, bending strength, and thermal expansion coefficient were evaluated by the following methods.
[0044]
The dielectric constant and dielectric loss were cut into a shape having a diameter of 2 to 7 mm and a thickness of 2 to 2.5 mm, and the dielectric cylinder resonator method was performed using a network analyzer and a synthesized sweeper at 60 GHz. In the measurement, the dielectric resonator was excited with an NRD guide (non-radiative dielectric line), and the dielectric constant and dielectric loss were calculated from the resonance characteristics of the TE ₀₂₁ or TE ₀₃₁ mode.
[0045]
Further, the sample was cut into a shape of width 4 mm × thickness 3 mm × length 70 mm, and a three-point bending test was performed based on the provisions of JISC-2141. Furthermore, the thermal expansion coefficient from room temperature to 400 ° C. was taken, and the thermal expansion coefficient was calculated. Further, the surface roughness (Ra) of the porcelain skin surface was measured with a surface roughness meter and shown in Table 1.
[0046]
[Table 1]

[0047]
Further, using each raw material composition in Table 1, a green sheet having a thickness of 500 μm was prepared by a doctor blade method, via holes were formed in the sheet, Cu metallized paste was filled in a screen printing method, and a metallized pad pattern was further formed. Was applied by screen printing.
[0048]
Then, six green sheets coated and filled with metallized paste were stacked and pressure-bonded while aligning the through holes. After debinding of the laminate at 700 ° C. in N ₂ + H ₂ O in, to prepare a wiring substrate was fired under the same conditions as in Table 1.
[0049]
Further, after forming a Ti layer with a thickness of 0.2 μm on the insulating substrate surface of the wiring board by vacuum deposition, various metal layers of various TiW, TiMo, Ni, Cr, and Ta are formed with a thickness of 10 μm. After the formation, a Cu layer was formed with a thickness of 3 μm. The contents of W and Mo in the alloy layer of TiW and TiMo are 90% by weight.
[0050]
Thereafter, a photosensitive photoresist is applied to the entire surface of the thin film metal layer, an etching mask is formed by photolithography technique, and an unnecessary portion of the thin film is removed from the thin film layer with an acidic etching solution. A 1 mm evaluation pad was formed.
[0051]
Then, a pin made of Cu is soldered to the pad, and 100 cycles of holding the wiring board in a constant temperature bath controlled at -40 ° C. and 125 ° C. for 15 minutes / 15 minutes. After the thermal cycle, this pin was pulled up vertically, and the strength when the solder or thin film metal layer was separated was evaluated as the adhesive strength of the thin film metal layer. The results are shown in Table 2.
[0052]
Further, by the same method as described above, 20 evaluation pads having a length of 30.0 mm, a width of 3.0 mm, and a thickness of 20 μm were formed on the surface of the insulating substrate, and the sheet resistance of each pad was measured. Calculated as sheet resistance.
[0053]
Further, a ground layer formed by co-firing with glass ceramic using copper paste is provided on the entire lower surface of the glass ceramic shown in Table 1, and in the same manner as described above, a wiring width of 260 μm is formed on the upper surface of the glass ceramic with a thickness of 150 μm. Three types of microstrip lines with a 10 μm thick, 10, 20, and 30 μm long thin film wiring layer (impedance 50 Ω) are formed, a 110 GHz signal is input from the input terminal, and the transmitted transmission signal intensity is measured by a network analyzer. The transmission loss S ₂₁ of the thin film wiring layer was evaluated by the least square method from the relationship between the length of the wiring layer and the signal intensity.
[0054]
[Table 2]

[0055]
As is apparent from the results of Tables 1 and 2, according to the present invention, sample No. 1 using a glass ceramic containing a predetermined glass, a diopside oxide crystal phase and a predetermined filler as an insulating substrate was used. 2-5, the 8～10,12,13,15～18, dielectric loss porcelain becomes low, and the transmission loss of the thin-film wiring layer is smaller than -1.5 dB / cm.
Furthermore, the adhesive strength was as high as 22.5 MPa or higher.
[0056]
On the other hand, sample no. 1. Sample No. whose glass amount is less than 40% by weight. 7. Sample No. 7 with a glass ceramic firing time shorter than 0.2 hours. 11, Sample No. longer than 5 hours No. 14, the open porosity of the porcelain exceeded 0.3%, and the signal transmission loss deteriorated by -2 dB / cm or more.
[0057]
Sample No. using glass that does not precipitate a diopside oxide crystal phase. 19, Sample No. using a glass that precipitates a diopside-type oxide crystal phase but does not contain SrO. In No. 20, the open porosity was more than 2% and the transmission loss was large.
[0058]
【The invention's effect】
As described above in detail, according to the present invention, together with small Kudekiru the dielectric loss of the insulating substrate, since it is possible to reduce the void ratio of the insulating substrate surface, a fine, low-resistance, a good impedance characteristic a, it is possible to reduce the conductor loss of the high frequency signal, it is possible to obtain a wiring board which have a high adhesive strength thin-film wiring layer on the insulating substrate.
[Brief description of the drawings]
FIG. 1 is a partially enlarged cross-sectional view for explaining the structure of a multilayer wiring layer of a package for housing a semiconductor element, which is an example of application of the multilayer wiring board of the present invention.
2 is a schematic cross-sectional view showing an embodiment of a structure for mounting the package of FIG. 1 on an external circuit board.
[Explanation of symbols]
A. Package B. External circuit board X Wiring board Y Multilayer wiring layers 1a, 1b, 1c Thin film metal layer 2 Insulating film 3 Insulating substrate 4 Semiconductor element 5 Electrode terminal 6 Connection terminal 7 Metallized pad 8 Via hole conductor

Claims (6)

At least one selected from the group consisting of SiO ₂ , Al ₂ O ₃ , MgO, SrO and CaO and a diopside oxide crystal phase and at least Al ₂ O ₃ , MgSiO ₃ , AlN and MgTiO ₃ contains a crystalline phase, on the surface of an insulating substrate made of an open porosity of 0.3% or less of ceramic, Ti layer, a metal layer and a Cu layer containing W or Mo is, the thin-film wiring layer laminated in this order together with the wiring board adhesion strength of the thin film wiring layer, characterized in der Rukoto least 22.5 MPa. Wiring board according to claim 1, wherein a surface roughness of at burn the skin surface of the thin-film wiring layer is formed the insulating surface (Ra) of the substrate is 0.1μm or less. The wiring board according to claim 1, wherein a dielectric loss at 60 to 77 GHz of the insulating substrate is 50 × 10 ⁻⁴ or less. 4. The wiring board according to claim 1, wherein a transmission characteristic S ₂₁ at 110 GHz or less of the thin film wiring layer formed on the surface of the insulating substrate is −1.5 dB / cm or less. 5. _{SiO 2, Al 2 O 3,} MgO, glass can be deposited unrealized diopside-type oxide crystal phase of SrO and CaO 6 0 to 9 0% by weight, even without least _{Al 2 O 3, MgSiO 3,} AlN And a mixture containing at least one filler selected from the group of MgTiO ₃ at a ratio of 10 to 40 % by weight to form a green sheet and heated at 800 to 1000 ° C. for 0.2 to 5 hours. and fired Te, a process of forming an insulating substrate open porosity is 0.3% or less of the ceramic, the surface of the insulating substrate, the thin film forming method, a metal layer containing Ti layer, W, or Mo and the Cu layer, method for manufacturing a wiring substrate, characterized by comprising a step of forming a thin film wiring layer formed in this order, the. As the glass, using the _SiO 2 30 to 55 _wt%, and Al ₂ O 3 4 to 15 wt%, and MgO14~30 wt%, and CaO5~20 wt%, those consisting of SrO10~25 wt% The method for manufacturing a wiring board according to claim 5 .

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