JP4559938B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a highly reliable semiconductor device capable of improving a change in threshold voltage and a decrease in drain saturation current in a p-channel MIS transistor (p-type MISFET) during long-term use. It is.

In recent years, semiconductor integrated circuits have been miniaturized and densified, and in generations where the design rule is deep sub-micron or less, n ⁺ gate electrodes are used for n-type MISFETs and p ^{+ for} p-type MISFETs. A so-called dual gate structure using a gate electrode has become the mainstream. However, in the CMISLSI having this dual gate structure, boron introduced into the polycrystalline polysilicon film to form the p ⁺ gate electrode of the p-type MISFET penetrates the gate insulating film by a heat treatment in a later process, and passes through the p-type MISFET. This causes a phenomenon called boron penetration, which is diffused to the channel region. It is known that when a phenomenon called boron penetration occurs, transistor characteristics fluctuate and the reliability of the gate insulating film is impaired.

  Therefore, a technique is known in which fluorine is implanted into the gate electrode to improve the reliability of the gate insulating film and to prevent fluctuations in transistor characteristics of the p-type MISFET (see, for example, Patent Document 1). .

  Hereinafter, a method for manufacturing a conventional semiconductor device having a dual gate structure will be described with reference to the drawings.

  7A to 7E are cross-sectional views showing the manufacturing process of the conventional semiconductor device. In the drawing, an n-type MISFET formation region Rn is shown on the left side, and a p-type MISFET formation region Rp is shown on the right side.

  In the conventional method for manufacturing a semiconductor device, first, in the step shown in FIG. 7A, an n-well 101A is formed in a p-type MISFET formation region Rp and a p-well 101B is formed in an n-type MISFET formation region Rn. After that, an element isolation region 102 surrounding each active region is formed.

  Next, in the step shown in FIG. 7B, after forming the oxide film 103 on the silicon substrate 101, the non-doped polycrystalline silicon film 104 is formed on the oxide film 103.

  Next, in the step shown in FIG. 7C, the polycrystalline silicon film 104 and the oxide film 103 are patterned, and the p-type MISFET gate electrode 104A and the gate insulating film are formed on the active region of the p-type MISFET formation region Rp. 103A is formed, and the gate electrode 104B and the gate insulating film 103B of the n-type MISFET are formed on the active region of the n-type MISFET formation region Rn.

Next, in the step shown in FIG. 7D, fluorine ions 108 are implanted into the exposed regions of the gate electrodes 104A and 104B and the silicon substrate 101 with an implantation energy of 10 keV and an implantation dose of 2 × 10 ¹³ to 2 × 2. The injection is performed from a direction substantially perpendicular to the substrate surface under the condition of × 10 ¹⁵ ions / cm ² .

  Next, in the step shown in FIG. 7E, sidewalls 105 made of a silicon oxide film are formed on the side surfaces of the gate electrodes 104A and 104B. Thereafter, arsenic, which is an n-type impurity, is ion-implanted in the n-type MISFET formation region Rn to form an n-type impurity diffusion layer 106 that becomes a source / drain region of the n-type MISFET, and the p-type MISFET formation region Rp Then, boron, which is a p-type impurity, is ion-implanted to form a p-type impurity diffusion layer 107 to be a source / drain region of the p-type MISFET. Thereafter, a rapid heat treatment for activating the ion-implanted impurities is performed to complete the p-type MISFET and the n-type MISFET. At this time, fluorine is diffused from the gate electrodes 104A and 104B into the gate insulating films 103A and 103B by this rapid heating treatment.

According to this manufacturing method, in the p-type MISFET, since fluorine is introduced into the gate insulating film 103A, the physical property to the gate insulating film due to the difference in thermal expansion coefficient between the gate electrode 104A and the gate insulating film 103A. Stress is alleviated and the reliability of the transistor is improved. Further, p ⁺ the gate electrodes in the 104A fluorine is introduced at a dose of ^{2 × 10 13 ~2 × 10 15} ions / cm 2, the gate of the boron introduced into the p ⁺ gate electrode 104A by the action of the fluorine Intrusion into the insulating film 103A and the semiconductor substrate 101 is suppressed, and fluctuations in transistor characteristics and deterioration in reliability can be prevented.
JP-A-11-163345

  However, in the conventional method for manufacturing a semiconductor device as shown in FIGS. 7A to 7E, there is a problem that the threshold voltage changes and the drain current amount decreases with time.

  In view of the above, the present invention provides a semiconductor device capable of suppressing changes over time in threshold voltage and drain current by optimizing the amount of fluorine injected into the gate electrode and the amount of fluorine injected into the source / drain regions. An object is to provide a production method that can be obtained.

  The first method for manufacturing a semiconductor device according to the present invention includes a step (a) of implanting fluorine ions into a semiconductor substrate, and a step (b) of forming a gate insulating film on the semiconductor substrate after the step (a). And (c) a step of forming a gate electrode on the gate insulating film, and a step of forming a p-type source / drain extension region in a region of the semiconductor substrate located laterally below the gate electrode. (D) and after the step (c), a step (e) of ion implantation of fluorine into a region of the semiconductor substrate located laterally below the gate electrode, the step (d), and the step After step (e), a step (f) of forming a sidewall on the side surface of the gate electrode and a p-type source / drain region are formed in a region of the semiconductor substrate located below the sidewall. The And a step (g).

  According to the first manufacturing method of the present invention, after fluorine is injected only into the semiconductor substrate, fluorine is injected into the semiconductor substrate and the gate electrode, so that the fluorine ion concentration (dose amount) in the semiconductor substrate is higher than that in the gate electrode. Can be high. Thereby, the dangling bond of silicon can be terminated by fluorine in the channel region of the p-type MISFET. Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed. In addition, since it is possible to avoid an excessive amount of fluorine being injected into the gate electrode, boron does not penetrate, and a large number of trap levels are generated in the gate insulating film. There is no problem that the performance is lowered.

  In the first manufacturing method of the present invention, the total dose amount of fluorine implanted into the region of the semiconductor substrate located under the sidewall is greater than the total dose amount of fluorine implanted into the gate electrode. Will also increase.

  In the first manufacturing method of the present invention, in the step (e), the fluorine ion may be implanted in a state where the gate electrode is covered with a protective film. In this case, the amount of fluorine injected into the gate electrode can be adjusted more reliably.

  The second manufacturing method of the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a gate electrode forming film on the gate insulating film, and the gate Forming a gate electrode on the gate insulating film by patterning the gate electrode forming film after the step (c) of implanting fluorine ions into the electrode forming film and the step (c) After the step (d), a step (e) of forming a p-type source / drain extension region in a region of the semiconductor substrate located below the side of the gate electrode, and the step (d), A step (f) of implanting fluorine into a region of the semiconductor substrate located laterally below the gate electrode while the gate electrode is covered with a protective film; and the step (e) and the step After (f) A step (g) of forming a sidewall on the side surface of the gate electrode, and a step (h) of forming a p-type source / drain region in a region of the semiconductor substrate located below the side wall of the sidewall. With.

  In the second manufacturing method of the present invention, the amount of fluorine contained in the gate electrode can be adjusted by adjusting the dose when fluorine is injected into the gate electrode forming film. As a result, excessive fluorine is injected into the gate electrode and boron penetrates, and a large number of trap levels are generated in the gate insulating film, thereby reducing the reliability of the gate insulating film. . On the other hand, since fluorine is injected into the semiconductor substrate with the gate electrode covered with a protective film, the amount of fluorine injected into the semiconductor substrate and the gate electrode can be adjusted. Thereby, the dangling bond of silicon in the channel region of the p-type MISFET can be terminated. Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed.

  In the second manufacturing method of the present invention, the total dose of fluorine injected into the region of the semiconductor substrate located below the sidewall is greater than the total dose of fluorine injected into the gate electrode. Will also increase.

  A third manufacturing method according to the present invention includes a step (a) of forming a gate insulating film on a semiconductor substrate, a step (b) of forming a gate electrode on the gate insulating film, and the semiconductor substrate A step (c) of forming a p-type source / drain extension region in a region located laterally below the gate electrode; and the gate electrode in a region located laterally below the gate electrode in the semiconductor substrate. And a step of forming a sidewall on the side surface of the gate electrode after the step (d) of ion implantation of fluorine with the protective film covered with a protective film, and the step (c) and the step (d) ( e) and a step (f) of forming a p-type source / drain region in a region of the semiconductor substrate located below the side wall of the sidewall.

  In the third manufacturing method of the present invention, when fluorine is injected, the gate electrode is covered with a protective film, so that the amount of fluorine injected into the gate electrode can be adjusted. As a result, it is possible to avoid an excessive amount of fluorine being injected into the gate electrode, resulting in boron penetration, or a large number of trap levels in the gate insulating film. There is no problem that the reliability of the system is lowered. On the other hand, since a sufficient amount of fluorine can be implanted into the silicon substrate, dangling bonds of silicon in the channel region of the p-type MISFET can be terminated. Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed.

  In the third manufacturing method of the present invention, in the step (d), a part of the fluorine implanted into the protective film reaches the gate electrode and is positioned below the sidewall of the semiconductor substrate. The total dose of fluorine implanted into the region to be implanted is larger than the total dose of fluorine implanted into the gate electrode.

  In the present invention, it is possible to prevent boron from penetrating, to prevent deterioration of the reliability of the gate insulating film due to the generation of a large number of trap levels in the gate insulating film, and to prevent the threshold voltage from aging. The change can be suppressed, and the deterioration of the drain saturation current can be suppressed.

(Inventor's consideration)
Below, the result which the present inventors considered is demonstrated.

  Conventionally, as described in the section “Problems to be Solved by the Invention”, the threshold voltage changes with time, and the drain saturation current decreases. These causes are considered to be because the terminal portion of the silicon atom located at the outermost surface of the channel region in the silicon substrate 101 remains as an unbonded dangling bond. That is, carriers are trapped in this dangling bond and the function of the channel region is lowered, so that the threshold voltage is changed and the drain saturation current is reduced. Even if silicon atoms are bonded to hydrogen in order to prevent this, since Si—H bonds are relatively weak, hydrogen is released with the passage of time, and dangling bonds are likely to occur.

  In order to suppress the formation of dangling bonds, it is considered that a Si—F bond stronger than the Si—H bond may be formed. However, if a sufficient amount of fluorine is injected into the gate electrode to suppress the formation of dangling bonds, a large amount of fluorine segregates at the interface between the gate electrode and the gate insulating film, and boron contained in the gate electrode It has been found that there is a problem that the penetration of the gate insulating film is promoted. It was also found that a large number of trap levels are generated in the gate insulating film, and the reliability of the gate insulating film is lowered.

  Therefore, in the present invention, the necessary amount of fluorine is implanted into each of the gate electrode and the silicon substrate.

(First embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 1A to 1F are cross-sectional views showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. In the drawing, an n-type MISFET (nMIS transistor) formation region Rn is shown on the left side, and a p-type MISFET (pMIS transistor) formation region Rp is shown on the right side.

  In the method of manufacturing a semiconductor device according to the present embodiment, first, in a step shown in FIG. 1A, an element isolation region 11 made of STI (Shallow Trench Isolation) is formed on a semiconductor substrate 10 made of silicon so as to surround an active region. Form. Thereafter, an n-well 10A is formed in the p-type MISFET formation region Rp of the semiconductor substrate 10, and a p-well 10B is formed in the n-type MISFET formation region Rn. Thereafter, ion implantation for adjusting the threshold voltage is performed in the p-type MISFET formation region Rp and the n-type MISFET formation region Rn, and a threshold voltage adjustment diffusion layer (none of which is shown) is formed in each region. To do.

Next, in the step shown in FIG. 1B, a resist 12 is formed on the semiconductor substrate 10 so as to cover the n-type MISFET formation region Rn and have an opening in the p-type MISFET formation region Rp. Thereafter, using the resist 12 as a mask, fluorine ions 13A are implanted into a region of the semiconductor substrate 10 which becomes an active region of the p-type MISFET formation region Rp under conditions of an implantation energy of ¹⁵ keV and an implantation dose of 2 × 10 ¹⁵ ions / cm ^2. The fluorine implantation layer 40 is formed by ion implantation. When ions are implanted under these implantation conditions, the range of fluorine exists in the vicinity of the surface of the semiconductor substrate 10.

  Next, after removing the resist 12 in the step shown in FIG. 1C, a silicon oxide film 14 having a thickness of 2 nm is formed on the semiconductor substrate 10. Thereafter, a polycrystalline silicon film 15 having a thickness of 180 nm is formed on the silicon oxide film 14. Subsequently, a silicon oxide film 16 having a thickness of 100 nm is formed on the polycrystalline silicon film 15.

  Next, in the step shown in FIG. 1D, a gate electrode formation mask (not shown) is formed on the silicon oxide film 16, and the silicon oxide film 16 is selectively etched. Thereby, protective insulating films 16A and 16B made of silicon oxide are formed. Thereafter, the gate electrode forming mask is removed, and the polycrystalline silicon film 15 and the silicon oxide film 14 are selectively etched using the protective insulating films 16A and 16B as hard masks. Thereby, the gate electrode portion 20A including the gate insulating film 14A, the gate electrode 15A, and the protective insulating film 16A is formed on the active region of the p-type MISFET forming region Rp, and on the active region of the n-type MISFET forming region Rn. A gate electrode portion 20B composed of the gate insulating film 14B, the gate electrode 15B, and the protective insulating film 16B is formed. By this etching, the thickness of the protective insulating films 16A and 16B used as the hard mask is reduced to about 40 nm.

Thereafter, a resist 17 is formed on the semiconductor substrate 10 so as to cover the n-type MISFET formation region Rn and to have an opening in the p-type MISFET formation region Rp. Thereafter, using the resist 17 and the gate electrode portion 20A as a mask, boron ions, which are p-type impurities, are implanted into a region to be an active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of 0.5 keV and an implantation dose amount. Ions are implanted under conditions of 4 × 10 ¹⁴ ions / cm ² to form p-type source / drain extension regions 18.

Next, using the resist 17 and the gate electrode portion 20A as a mask, arsenic ions, which are n-type impurities, are implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of 70 keV and an implantation dose of 3. Ions are implanted under the condition of 2 × 10 ¹³ ions / cm ² to form the n-type pocket region 19. At this time, ion implantation of arsenic ions is performed by a rotational implantation method in which an implantation angle is 25 °. Further, using the resist 17 and the gate electrode portion 20A as a mask, fluorine ions 13B are implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of ¹⁵ keV and an implantation dose of 1 × 10 ¹⁵ ions / Ion implantation is performed under conditions of cm ² . As a result, the fluorine concentration of the fluorine injection layer 40 in the semiconductor substrate 10 is increased.

  At this time, since the protective insulating film 16A having a thickness larger than the fluorine implantation depth is formed on the gate electrode 15A, fluorine is not implanted into the gate electrode 15A, and fluorine is introduced only into the semiconductor substrate 10. Injected. When ions are implanted under these implantation conditions, the range of fluorine exists in the vicinity of the surface of the semiconductor substrate 10. Note that the amount of fluorine injected into the gate electrode 15A can be adjusted by making adjustments such as reducing the thickness of the protective insulating film 16A.

Next, after removing the resist 17 in the step shown in FIG. 1E, a resist 21 is formed on the semiconductor substrate 10 so as to cover the p-type MISFET formation region Rp and have an opening in the n-type MISFET formation region Rn. To do. Thereafter, using the resist 21 and the gate electrode portion 20B as a mask, arsenic ions, which are n-type impurities, are implanted into the active region of the n-type MISFET formation region Rn in the semiconductor substrate 10 at an implantation energy of 4 keV and an implantation dose of 6 ×. Ions are implanted under the condition of 10 ¹⁴ ions / cm ² to form n-type source / drain extension regions 22. Next, the resist 21 and the gate electrode portion 20B are masked, and boron ions, which are p-type impurities, are implanted into the semiconductor substrate 10 serving as an active region of the n-type MISFET formation region Rn with an implantation energy of 12 keV and an implantation dose of 3.6 × 10. Ions are implanted under the condition of ¹³ ions / cm ² to form the p-type pocket region 23. At this time, boron ions are implanted by a rotational implantation method in which the implantation angle is 25 °.

  Next, after removing the resist 21 in the step shown in FIG. 1F, an insulating film (not shown) covering the semiconductor substrate 10 and the gate electrode portions 20A and 20B is formed, and anisotropic etching is performed. Thus, the sidewall 24A and the sidewall 24B are formed on the side surfaces of the gate electrode 15A and the gate electrode 15B. At this time, the protective insulating films 16A and 16B formed on the gate electrodes 15A and 15B are etched by over-etching when forming the sidewalls 24A and 24B, and the upper surfaces of the gate electrodes 15A and 15B are exposed. To do.

Thereafter, a mask (not shown) having an opening is formed on the p-type MISFET Rp so as to cover the n-type MISFET formation region Rn in the semiconductor substrate 10, and the activation of the p-type MISFET formation region Rp in the semiconductor substrate 10 is performed. Boron ions, which are p-type impurities, are ion-implanted into a region to be a region under the conditions of an implantation energy of 3 keV and an implantation dose of 3.6 × 10 ¹⁵ ions / cm ² , and a high concentration p-type source / drain region 25 Are selectively formed. At this time, simultaneously with the formation of the p-type source / drain region 25, boron ions are ion-implanted into the gate electrode 15A to form the p ⁺ gate electrode 27.

On the other hand, a mask (not shown) covering the p-type MISFET formation region Rp of the semiconductor substrate 10 and having an opening is formed on the n-type MISFET Rn, and the activation of the n-type MISFET formation region Rn of the semiconductor substrate 10 is performed. Arsenic ions, which are n-type impurities, are ion-implanted into the region under conditions of an implantation energy of 50 keV and an implantation dose amount of 4.0 × 10 ¹⁵ ions / cm ² , thereby forming high-concentration n-type source / drain regions 26. . At this time, simultaneously with the formation of the n-type source / drain region 26, arsenic ions are implanted into the gate electrode 15B to form the n ⁺ gate electrode 28.

  Thereafter, spike RTA treatment at a heat treatment temperature of 1075 ° C. is performed on the semiconductor substrate 10 in a nitrogen atmosphere to activate impurities implanted in the source / drain regions and the gate electrode.

  In the present embodiment, the dangling bond of silicon can be terminated by fluorine in the channel region of the p-type MISFET by making the concentration (dose amount) of fluorine ions in the semiconductor substrate 10 higher than that of the gate electrode 15A. . Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed. In addition, since it is possible to avoid an excessive amount of fluorine being injected into the gate electrode 15A, boron penetration can be prevented. In addition, since the generation of a large number of trap levels in the gate insulating film 14A can be suppressed, a decrease in reliability of the gate insulating film 14A can also be prevented.

  In the above description, when fluorine ions 13B are implanted in the step shown in FIG. 1D, the amount of fluorine implanted into the gate electrode 15A is covered by covering the gate electrode 15A with the protective insulating film 16A. Can be adjusted more reliably. However, in the present invention, the gate electrode 15A may not necessarily be covered with the protective insulating film 16A.

  In this embodiment, fluorine ions are implanted in the step shown in FIG. 1D after being implanted in the step shown in FIG. Thereby, even when most of the fluorine implantation layer 40 is removed when patterning the polycrystalline silicon film 15 in the step shown in FIG. 1D, the fluorine concentration of the fluorine implantation layer 40 is increased thereafter. be able to.

  In this embodiment, fluorine is implanted only into the p-type MISFET formation region Rp, but fluorine may be implanted into the n-type MISFET formation region Rn.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings.

  2A to 2F are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention. In the drawing, an n-type MISFET (nMIS transistor) formation region Rn is shown on the left side, and a p-type MISFET (pMIS transistor) formation region Rp is shown on the right side.

  In the method of manufacturing a semiconductor device according to the present embodiment, first, in a step shown in FIG. 2A, an element isolation region 11 made of STI (Shallow Trench Isolation) is formed on a semiconductor substrate 10 made of silicon so as to surround an active region. Form. Thereafter, an n-well 10A is formed in the p-type MISFET formation region Rp of the semiconductor substrate 10, and a p-well 10B is formed in the n-type MISFET formation region Rn. Thereafter, ion implantation for adjusting the threshold voltage is performed in the p-type MISFET formation region Rp and the n-type MISFET formation region Rn, and a threshold voltage adjustment diffusion layer (none of which is shown) is formed in each region. To do.

Next, in the step shown in FIG. 2B, a silicon oxide film 14 having a thickness of 2 nm is formed on the semiconductor substrate 10. Thereafter, a polycrystalline silicon film 15 having a thickness of 180 nm is formed on the silicon oxide film 14. Thereafter, a resist 29 is formed on the polycrystalline silicon film 15 so as to cover the n-type MISFET formation region Rn and to have an opening in the p-type MISFET formation region Rp. Thereafter, using the resist 29 as a mask, fluorine ions 13C are implanted into a region of the polycrystalline silicon film 15 located in the p-type MISFET formation region Rp under conditions of an implantation energy of ¹⁵ keV and an implantation dose of 1 × 10 ¹⁵ ions / cm ^2. Ions are implanted to form a fluorine implantation layer 41 in the gate electrode formation film 15. When ions are implanted under these implantation conditions, the range of fluorine exists in the vicinity of the surface of the polycrystalline silicon film 15.

  Next, after removing the resist 29 in the step shown in FIG. 2C, a silicon oxide film 16 having a thickness of 100 nm is formed on the polycrystalline silicon film 15.

  Next, in the step shown in FIG. 2D, the silicon oxide film 16 is selectively etched using a gate electrode formation mask (not shown) to thereby form protective insulating films 16A and 16B made of silicon oxide films. Form. Thereafter, the gate electrode forming mask is removed, and the polycrystalline silicon film 15 and the silicon oxide film 14 are selectively etched using the protective insulating films 16A and 16B as hard masks. As a result, the gate electrode portion 20A composed of the gate insulating film 14A, the gate electrode 15A, and the protective insulating film 16A of the p-type MISFET is formed on the portion of the semiconductor substrate 10 that is located in the p-type MISFET formation region Rp. On the portion of the substrate 10 located in the n-type MISFET formation region Rn, the gate electrode portion 20B including the gate insulating film 14B, the gate electrode 15B, and the protective insulating film 16B of the n-type MISFET is formed. By this etching, the thickness of the protective insulating films 16A and 16B used as the hard mask is reduced to about 40 nm.

Thereafter, a resist 17 is formed on the semiconductor substrate 10 so as to cover the n-type MISFET formation region Rn and to have an opening in the p-type MISFET formation region Rp. Thereafter, using the resist 17 and the gate electrode portion 20A as a mask, boron ions, which are p-type impurities, are implanted into a region to be an active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of 0.5 keV and an implantation dose amount. Ions are implanted under conditions of 4 × 10 ¹⁴ ions / cm ² to form p-type source / drain extension regions 18. Next, using the resist 17 and the gate electrode portion 20A as a mask, an arsenic ion as an n-type impurity is implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of 70 keV and an implantation dose of 3.2. Ions are implanted under the conditions of × 10 ¹³ ions / cm ² to form the n-type pocket region 19. At this time, ion implantation of arsenic ions was performed by a rotational implantation method in which the implantation angle was 25 °. Further, using the resist 17 and the gate electrode portion 20A as a mask, fluorine ions 13B are implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of ¹⁵ keV and an implantation dose of 1 × 10 ¹⁵ ions / Ion implantation is performed under conditions of cm ² . Thereby, the fluorine implantation layer 42 is formed in the source / drain formation region. At this time, since the protective insulating film 16A having a thickness larger than the fluorine implantation depth is formed on the gate electrode 15A, fluorine is not implanted into the gate electrode 15A, and fluorine is introduced only into the semiconductor substrate 10. Injected. When ions are implanted under these implantation conditions, the range of fluorine exists in the vicinity of the surface of the semiconductor substrate 10.

2E, after removing the resist 17, a resist 21 is formed on the semiconductor substrate 10 so as to cover the p-type MISFET formation region Rp and have an opening in the n-type MISFET formation region Rn. . Thereafter, using the resist 21 and the gate electrode portion 20B as a mask, arsenic ions, which are n-type impurities, are implanted into the active region of the n-type MISFET formation region Rn in the semiconductor substrate 10 at an implantation energy of 4 keV and an implantation dose of 6 ×. Ions are implanted under the condition of 10 ¹⁴ ions / cm ² to form n-type source / drain extension regions 22. Next, using the resist 21 and the gate electrode portion 20B as they are as masks, boron ions, which are p-type impurities, are implanted into a region to be an active region of the n-type MISFET formation region Rn in the semiconductor substrate 10 with an implantation energy of 12 keV and an implantation dose of 3 The ions are implanted under the condition of 6 × 10 ¹³ ions / cm ² to form the p-type pocket region 23. At this time, boron ions are implanted by a rotational implantation method in which the implantation angle is 25 °.

  Next, after removing the resist 21 in the step shown in FIG. 2F, an insulating film (not shown) covering the semiconductor substrate 10 and the gate electrode portions 20A and 20B is formed, and anisotropic etching is performed. Thus, the sidewall 24A and the sidewall 24B are formed on the side surfaces of the gate electrode 15A and the gate electrode 15B. At this time, the protective insulating films 16A and 16B formed on the gate electrodes 15A and 15B are etched by over-etching when forming the sidewalls 24A and 24B, and the upper surfaces of the gate electrodes 15A and 15B are exposed. To do.

Thereafter, a mask (not shown) that covers the n-type MISFET formation region Rn in the semiconductor substrate 10 and has an opening on the p-type MISFET formation region Rp is formed, and the p-type MISFET formation region in the semiconductor substrate 10 Boron ions, which are p-type impurities, are ion-implanted into a region that becomes an active region of Rp under the conditions of an implantation energy of 3 keV and an implantation dose of 3.6 × 10 ¹⁵ ions / cm ² , and a high-concentration p-type source A drain region 25 is selectively formed. At this time, simultaneously with the formation of the p-type source / drain region 25, boron ions are ion-implanted into the gate electrode 15A to form the p ⁺ gate electrode 27.

On the other hand, a mask (not shown) that covers the p-type MISFET formation region Rp in the semiconductor substrate 10 and has an opening on the n-type MISFET formation region Rn is formed, and the n-type MISFET formation region in the semiconductor substrate 10 Arsenic ions, which are n-type impurities, are ion-implanted into the active region of Rn under the conditions of an implantation energy of 50 keV and an implantation dose of 4.0 × 10 ¹⁵ ions / cm ^2. Form. At this time, simultaneously with the formation of the n-type source / drain region 26, arsenic ions are implanted into the gate electrode 15B to form the n ⁺ gate electrode 28.

  Thereafter, spike RTA treatment at a heat treatment temperature of 1075 ° C. is performed on the semiconductor substrate 10 in a nitrogen atmosphere to activate impurities implanted in the source / drain regions and the gate electrode. At this time, fluorine in the gate electrode 15A diffuses in the interface direction between the gate insulating film 14A and the semiconductor substrate 10 by this spike RTA process.

  In the present embodiment, fluorine is implanted into the polycrystalline silicon film 15 in the step shown in FIG. Since the gate electrode 15A is formed from the polycrystalline silicon film 15, the amount of fluorine contained in the gate electrode 15A can be adjusted by adjusting the dose at this time. Thereby, since it is possible to avoid excessive injection of fluorine into the gate electrode 15A, it is possible to prevent boron from penetrating. In addition, since the generation of a large number of trap levels in the gate insulating film 14A can be suppressed, a decrease in reliability of the gate insulating film 14A can also be prevented.

  On the other hand, in the step shown in FIG. 2D, fluorine is implanted into the silicon substrate 10 with the gate electrode 15A covered with the protective insulating film 16A. Therefore, the amount of fluorine injected into the semiconductor substrate 10 and the gate electrode 15A can be adjusted, respectively, and the dangling bonds of silicon in the channel region of the p-type MISFET can be terminated. Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed.

(Third embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings.

  3A to 3E are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment of the present invention. In the drawing, an n-type MISFET (nMIS transistor) formation region Rn is shown on the left side, and a p-type MISFET (pMIS transistor) formation region Rp is shown on the right side.

  In the method of manufacturing a semiconductor device according to the present embodiment, first, in a step shown in FIG. 3A, an element isolation region 11 made of STI (Shallow Trench Isolation) is formed on a semiconductor substrate 10 made of silicon so as to surround an active region. Form. Thereafter, an n-well 10A is formed in the p-type MISFET formation region Rp of the semiconductor substrate 10, and a p-well 10B is formed in the n-type MISFET formation region Rn. Thereafter, ion implantation for adjusting the threshold voltage is performed in the p-type MISFET formation region Rp and the n-type MISFET formation region Rn, and a threshold voltage adjustment diffusion layer (none of which is shown) is formed in each region. To do.

  Next, in the step shown in FIG. 3B, a silicon oxide film 14 having a thickness of 2 nm is formed on the semiconductor substrate 10. Thereafter, a polycrystalline silicon film 15 having a thickness of 180 nm is formed on the silicon oxide film 14. Subsequently, a silicon oxide film 30 having a thickness of 80 nm is formed on the polycrystalline silicon film 15.

  Next, in the step shown in FIG. 3C, the protective insulating films 30A and 30B are formed by selectively etching the silicon oxide film 30 using a gate electrode forming mask (not shown). Thereafter, the gate electrode forming mask is removed, and the gate electrode forming film 15 and the gate insulating film forming film 14 are selectively etched using the protective insulating films 30A and 30B as hard masks. As a result, the gate electrode portion 31A composed of the gate insulating film 14A, the gate electrode 15A, and the protective insulating film 30A of the p-type MISFET is formed on the active region of the p-type MISFET forming region Rp, and the n-type MISFET forming region Rn is activated. On the region, a gate electrode portion 31B composed of the gate insulating film 14B, the gate electrode 15B, and the protective insulating film 30B of the n-type MISFET is formed. By etching at this time, the thickness of the protective insulating films 30A and 30B used as the hard mask is reduced to about 20 nm. The remaining films of the protective insulating films 30A and 30B are desirably 20 ± 10 nm thick.

Thereafter, a resist 17 is formed on the semiconductor substrate 10 so as to cover the n-type MISFET formation region Rn and to have an opening in the p-type MISFET formation region Rp. Thereafter, the resist 17 and the gate electrode portion 31A are masked, and boron ions, which are p-type impurities, are implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 at an implantation energy of 0.5 keV and an implantation dose of 4 ×. Ions are implanted under the condition of 10 ¹⁴ ions / cm ² to form p-type source / drain extension regions 18. Next, using the resist 17 and the gate electrode portion 20A as a mask, an arsenic ion as an n-type impurity is implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of 70 keV and an implantation dose of 3.2. Ions are implanted under the conditions of × 10 ¹³ ions / cm ² to form the n-type pocket region 19. At this time, ion implantation of arsenic ions was performed by a rotational implantation method in which the implantation angle was 25 °. Further, using the resist 17 and the gate electrode portion 20A as a mask, fluorine ions 13B are implanted into the active region of the p-type MISFET formation region Rp in the semiconductor substrate 10 with an implantation energy of ¹⁵ keV and an implantation dose of 1 × 10 ¹⁵ ions / cm ^2. The fluorine implantation layer 43 is formed in the source / drain formation region by ion implantation under the conditions described above. At this time, since the protective insulating film 30A having a thickness smaller than the fluorine implantation depth is formed on the gate electrode 15A, the gate electrode 15A has a smaller amount of fluorine than the amount of fluorine implanted into the semiconductor substrate 10. Will be injected. When ions are implanted under these implantation conditions, the range of fluorine exists in the vicinity of the surfaces of the gate electrode 15A and the semiconductor substrate 10.

Next, after removing the resist 17 in the step shown in FIG. 3D, a resist 21 is formed on the semiconductor substrate 10 so as to cover the p-type MISFET formation region Rp and have an opening in the n-type MISFET formation region Rn. To do. Thereafter, using the resist 21 and the gate electrode portion 31B as a mask, arsenic ions, which are n-type impurities, are implanted into the semiconductor substrate 10 serving as an active region of the n-type MISFET formation region Rn with an implantation energy of 4 keV and an implantation dose of 6 × 10. Ions are implanted under the condition of ¹⁴ ions / cm ² to form n-type source / drain extension regions 22. Next, using the resist 21 and the gate electrode portion 31B as they are as masks, boron ions, which are p-type impurities, are implanted into the active region of the n-type MISFET formation region Rn in the semiconductor substrate 10 with an implantation energy of 12 keV and an implantation dose of 3.6. Ions are implanted under the condition of × 10 ¹³ ions / cm ² to form the p-type pocket region 23. At this time, ion implantation of boron ions was performed by a rotational implantation method in which the implantation angle was 25 °.

  Next, after removing the resist 21 in the step shown in FIG. 3E, an insulating film (not shown) covering the semiconductor substrate 10 and the gate electrode portions 31A and 31B is formed, and anisotropic etching is performed. Thus, the sidewalls 24A and 24B are formed on the side surfaces of the gate electrode 15A and the gate electrode 15B. At this time, the protective insulating films 30A and 30B formed on the gate electrodes 15A and 15B are etched by over-etching when forming the sidewalls 24A and 24B, and the upper surfaces of the gate electrodes 15A and 15B are exposed. To do.

Thereafter, a mask (not shown) having an opening is formed on the p-type MISFET formation region Rp, and boron ions, which are p-type impurities, are formed in the region of the semiconductor substrate 10 which becomes the active region of the p-type MISFET formation region Rp. Are implanted under the conditions of an implantation energy of 3 keV and an implantation dose of 3.6 × 10 ¹⁵ ions / cm ² to selectively form a high-concentration p-type source / drain region 25. At this time, simultaneously with the formation of the p-type source / drain region 25, boron ions are ion-implanted into the gate electrode 15A to form the p ⁺ gate electrode 27.

On the other hand, a mask (not shown) that covers the p-type MISFET formation region Rp in the semiconductor substrate 10 and has an opening on the n-type MISFET formation region Rn is formed, and the n-type MISFET formation region in the semiconductor substrate 10 Arsenic ions, which are n-type impurities, are ion-implanted into the active region of Rn under the conditions of an implantation energy of 50 keV and an implantation dose of 4.0 × 10 ¹⁵ ions / cm ^2. Form. At this time, simultaneously with the formation of the n-type source / drain region 26, arsenic ions are implanted into the gate electrode 15B to form the n ⁺ gate electrode 28.

  Thereafter, spike RTA treatment at a heat treatment temperature of 1075 ° C. is performed on the semiconductor substrate 10 in a nitrogen atmosphere to activate impurities implanted in the source / drain regions and the gate electrode. At this time, fluorine in the gate electrode 15A diffuses in the interface direction between the gate insulating film 14A and the semiconductor substrate 10 by this spike RTA process.

  In the present embodiment, when fluorine ions 13B are implanted in the step shown in FIG. 3C, the gate electrode 15A is covered with the protective insulating film 30A, so the amount of fluorine implanted into the gate electrode 15A. Can be adjusted. Thereby, since it is possible to avoid an excessive amount of fluorine being injected into the gate electrode 15A, it is possible to prevent boron from penetrating. In addition, since a large number of trap levels can be prevented from being generated without the gate insulating film 14A, a decrease in the reliability of the gate insulating film 14A can also be prevented.

  On the other hand, in the step shown in FIG. 3C, since a sufficient amount of fluorine ions can be implanted into the silicon substrate 10, the dangling bond of silicon in the channel region of the p-type MISFET can be terminated. it can. Thereby, a change with time of the threshold voltage can be suppressed, and deterioration of the drain saturation current can be suppressed.

  FIG. 4 is a graph showing the change over time of the threshold voltage in the p-type MISFET. In FIG. 4, the horizontal axis indicates the elapsed time, and the vertical axis indicates the amount of change in the threshold voltage. Profile (a) shows the measurement result in the conventional p-type MISFET in which fluorine is not implanted into the channel region, and profile (b) shows the measurement result in the p-type MISFET formed by the method of this embodiment. This evaluation was performed by measuring the fluctuation amount of the threshold voltage in a state where a gate voltage was applied to the gate electrode at a temperature of 150 ° C. (stress application state).

  As shown in FIG. 4, in the sample of this embodiment in which an appropriate amount of fluorine is introduced into the channel region, it can be seen that the variation amount of the threshold voltage is remarkably suppressed as compared with the conventional sample.

FIG. 5 is a graph showing the impurity concentration in the gate electrode in the p-type MISFET of the third embodiment. The result shown in FIG. 5 is the result of measuring the impurity concentration in the sample prepared by the method of the third embodiment by the backside SIMS method. In this sample, fluorine ions are implanted under the conditions of an implantation energy of ¹⁵ keV and an implantation dose of 1.0 × 10 ¹⁵ ions / cm ² . In FIG. 5, the horizontal axis indicates the distance from the interface between the gate insulating film and the gate electrode, and the vertical axis indicates the impurity concentration. The horizontal axis is the gate insulating film on the left side and the gate electrode on the right side across the interface.

From the results shown in FIG. 5, it can be seen that the fluorine concentration at the interface portion between the gate insulating film and the gate electrode is about 1 × 10 ^{18 to} 5 × 10 ¹⁸ ions / cm ³ .

FIG. 6 is a graph showing the impurity concentration in the source / drain extension region of the p-type MISFET in the third embodiment. The results shown in FIG. 6 are obtained by measuring the impurity concentration of the sample prepared by the method of the third embodiment by the SIMS method. In this sample, fluorine ions are implanted with an implantation energy of 15 keV and an implantation dose of 1.0. It is injected under the condition of × 10 ¹⁵ ions / cm ² . In FIG. 6, the horizontal axis indicates the distance in the depth direction from the surface of the semiconductor substrate, and the vertical axis indicates the impurity concentration.

As shown in FIG. 6, the fluorine concentration at the semiconductor substrate interface at the channel end under the sidewall is 4 × 10 ¹⁷ to 1 × 10 ¹⁸ ions / cm ³ . As a result of detailed investigations, the concentration of fluorine for suppressing the change over time of the threshold voltage and drain saturation current of the p-type MISFET is 5 × 10 ¹⁷ to 1 × 10 ¹⁹ ions / cm in the channel region immediately below the gate insulating film. ³ It was found that 2 × 10 ¹⁷ to 2 × 10 ¹⁸ ions / cm ³ is effective at the end of the channel region located under the sidewall.

  As described above, the embodiments of the present invention have been described in detail. However, the specific configuration of the present invention is not limited to these embodiments, and design changes and the like can be made without departing from the scope of the present invention. Even if it exists, it is included in this invention. For example, instead of the gate oxide film, a gate oxynitride film or a gate oxide film whose surface is plasma nitrided can be used as the gate insulating film. In each of the embodiments, the silicon oxide film having a thickness of 2.0 nm is used as the gate insulating film. However, the present invention also applies to a gate insulating film made of a silicon oxide film, an oxynitride film, or the like having a larger thickness. Can be applied.

  In each embodiment, the process for forming a semiconductor device having a CMIS structure has been described as an example. However, it goes without saying that the present invention can also be applied to pMIS transistor formation in DRAMs and other devices.

  In the p-type MISFET, the change of the threshold voltage with time can be suppressed and the deterioration of the drain saturation current can be suppressed without reducing the boron penetration and the reliability of the gate insulating film. Industrial applicability is high.

(A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(e) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a graph which shows the time-dependent change of the threshold voltage in p-type MISFET. It is a graph which shows the impurity concentration in the gate electrode in p-type MISFET of 3rd Embodiment. It is a graph which shows the impurity concentration in the source / drain extension area | region of p-type MISFET in 3rd Embodiment. (A)-(e) is sectional drawing which shows the manufacturing process of the conventional semiconductor device.

Explanation of symbols

10 Semiconductor substrate
10A n-well
10B p-well
11 Device isolation region
12 resist
13A Fluorine
13A Fluorine ion
13B Fluorine ion
13C Fluorine ion
14 Gate insulating film formation film
14 Silicon oxide film
14A Gate insulation film
14A, 14B Gate insulation film
14B Gate insulation film
15 Gate electrode forming film
15 Polycrystalline silicon film
15A Gate electrode
15A, 15B Gate electrode
15B Gate electrode
16 Silicon oxide film
16A protective insulation film
16A, 16B Protective insulating film
16B protective insulation film
17 resist
18 p-type source / drain extension regions
19 n-type pocket region
20A Gate electrode
20A Gate electrode part
20A, 20B Gate electrode part
20B Gate electrode part
21 resist
22 n-type source / drain extension regions
23 p-type pocket region
24A sidewall
24B sidewall
25 p-type source / drain regions
26 n-type source / drain regions
27 Gate electrode
28 Gate electrode
29 resist
30 Silicon oxide film
30A protective insulation film
30A, 30B Protective insulating film
30B Protective insulating film
31A Gate electrode part
31B Gate electrode part
40, 41, 42, 43 Fluorine injection layer

Claims (5)

In a manufacturing method of a semiconductor device in which a dangling bond of silicon is terminated by fluorine in a channel formation region of a p-type MISFET,
A step (a) of implanting fluorine ions into the semiconductor substrate;
A step (b) of forming a gate insulating film forming film on the semiconductor substrate after the step (a);
Forming a gate electrode forming film on the gate insulating film forming film (c);
Forming a patterned protective film on the gate electrode forming film (d);
Forming a gate electrode on the gate insulating film and the gate insulating film by patterning the gate electrode forming film and the gate insulating film forming film using the protective film as a mask (e) )When,
Forming a p-type source / drain extension region in a region of the semiconductor substrate located below the side of the gate electrode ( f );
After the step ( f ), a step ( g ) of ion-implanting fluorine into a region of the semiconductor substrate located laterally below the gate electrode;
After the step ( f ) and the step ( g ), a step ( h ) of forming a sidewall on the side surface of the gate electrode;
A step ( i ) of forming a p-type source / drain region in a region of the semiconductor substrate located below the side wall of the sidewall;
In the step (g), an ion implantation of the fluorine on the gate electrode while covering with the protective film, a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1 ,
In the step ( g ), the protective film is thicker than the fluorine implantation depth, and the gate electrode is not implanted with the fluorine. In a manufacturing method of a semiconductor device in which a dangling bond of silicon is terminated by fluorine in a channel formation region of a p-type MISFET,
A step (a) of forming a gate insulating film forming film on the semiconductor substrate;
Forming a gate electrode forming film on the gate insulating film forming film (b);
A step (c) of implanting fluorine ions into the gate electrode forming film;
Forming a patterned protective film on the gate electrode forming film (d);
After the step ( d ) , by patterning the gate insulating film forming film and the gate electrode forming film using the protective film as a mask , the gate insulating film and the gate insulating film are formed on the gate insulating film and the gate insulating film. Forming a gate electrode ( e );
Forming a p-type source / drain extension region in a region of the semiconductor substrate located below the side of the gate electrode ( f );
After the step (f), wherein in a state where the top of the gate electrode covered with the protective film, the in to be adjacent to the gate electrode of the semiconductor substrate, fluorine step of ion implantation (g) When,
After the step ( f ) and the step ( g ), a step ( h ) of forming a sidewall on the side surface of the gate electrode;
And ( i ) forming a p-type source / drain region in a region of the semiconductor substrate located below the side wall of the sidewall. In a manufacturing method of a semiconductor device in which a dangling bond of silicon is terminated by fluorine in a channel formation region of a p-type MISFET,
A step (a) of forming a gate insulating film forming film on the semiconductor substrate;
Forming a gate electrode forming film on the gate insulating film forming film (b);
Forming a patterned protective film on the gate electrode forming film (c);
Forming a gate electrode on the gate insulating film and the gate insulating film by patterning the gate electrode forming film and the gate insulating film forming film using the protective film as a mask (d) )When,
Forming a p-type source / drain extension region in a region of the semiconductor substrate located below the side of the gate electrode ( e );
In to be adjacent to the gate electrode of said semiconductor substrate, while covering with the protective film on the gate electrode, and the fluorine process of ion implantation (f),
After the step ( e ) and the step ( f ), a step ( g ) of forming a sidewall on the side surface of the gate electrode;
Forming a p-type source / drain region in a region of the semiconductor substrate located below the side wall of the sidewall ( h ),
In the step ( f ), the gate electrode is implanted with a smaller amount of fluorine than the amount of fluorine implanted into the semiconductor substrate. A method of manufacturing a semiconductor device according to claim 4 ,
In the step ( f ), the thickness of the protective film is thinner than the fluorine implantation depth, and a part of the fluorine implanted into the protective film reaches the gate electrode.

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