JP4564192B2 - Variable speed controller - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a variable speed control device for controlling a variable speed system in which a primary side of a winding induction machine axially coupled to a prime mover is connected to a system and a frequency converter is connected to a secondary side.
[0002]
[Prior art]
As a conventional control device for a variable speed power generation system, there is a configuration example as shown in FIG.
[0003]
In FIG. 56, reference numeral 1 denotes a winding induction machine directly connected to the rotating shaft of the prime mover 5. The primary side of the winding induction machine 1 is a system not shown via a generator-side circuit breaker 2 and a main transformer 3. The secondary side of the winding induction machine 1 is connected to the output side circuit of the generator side circuit breaker 2 via the frequency converter 4.
[0004]
Here, the frequency converter 4 is a converter using a semiconductor such as a cycloconverter or an inverter, and the prime mover 5 is a water turbine, a pump turbine, a turbine, a windmill, or the like.
[0005]
The main transformer 3 is provided with a voltage adjusting tap and is controlled by a tap switching control device (not shown). The prime mover 5 is controlled by the prime mover control device 6. It has become.
[0006]
On the other hand, 16 is a frequency detector to which the voltage detected by the voltage detector 12 connected to the output-side circuit of the generator-side circuit breaker 2 is input, and 17 is also connected to the output-side circuit of the generator-side circuit breaker 2 The active power detector 10 receives the active power detected by the active power detector 17 and the frequency detected by the frequency detector 16, and inputs the output signal to the prime mover controller 6. It is.
[0007]
Reference numeral 8 denotes a speed controller to which a speed signal output from a speed detector 15 attached to the rotating shaft of the winding induction machine 1 and an output signal from the active power controller 10 are input, and 11 denotes a voltage detector 12. The voltage controller to which the voltage detected by is input.
[0008]
Further, 7 is an output signal of the speed controller 8 and the voltage controller 11, and a current detection signal and voltage from the current detector 14 provided in the electric circuit connecting the frequency converter 4 and the secondary side of the winding induction machine 1. A frequency converter current control for inputting a voltage detection signal from the detector 12 and a phase detection signal from a phase detector 13 attached to the rotary shaft of the winding induction machine 1 and giving the output signal to the frequency converter 4. Device.
[0009]
As shown in FIG. 57, the frequency converter current controller 7 includes a phase reference calculator 71, valid / invalid calculator 72, subtractors 73 and 75, controllers 74 and 76, an output voltage calculator 77, a triangular wave. It comprises a generator 78, a gate pulse generator 79, and an AND circuit 7A.
[0010]
Here, the phase reference calculator 71 receives the system voltage v from the voltage detector 12._LAnd rotational phase θ from the phase detector 13_RAnd converter current phase reference θ_I0Is calculated.
The valid / invalid calculator 72 is used to calculate the current from the current detector 14 and the converter current phase reference θ._I0From these, the effective current Iq and the reactive current Id are calculated. The subtractor 73 is an effective current command value Iq from the speed controller 8.^*And the effective component current Iq are obtained, and the deviation is input to the controller 74. Similarly, the subtractor 75 receives the reactive current command value Id from the voltage controller 11.^*And the reactive current Id are obtained, and the deviation is input to the controller 76. The output voltage calculator 77 is an effective output voltage Vq that is an output of the controller 74.^*And the reactive component output voltage Vd which is the output of the controller 76^*And converter current phase reference θ_I0To output voltage v_IIs calculated. The triangular wave generator 78 generates a triangular wave CRY based on the oscillation frequency OSC. The gate pulse generator 79 outputs the output voltage v_IThe gate pulse is output to the frequency converter 4 through the AND circuit 7A at a timing determined from the intersection of the triangular wave CRY and the triangular wave CRY. When a gate block (GB) signal is input, the AND circuit 7A blocks the gate pulse and stops the converter.
[0011]
The speed controller 8 includes a subtractor 81 and a controller 82 as shown in FIG.
[0012]
Here, the subtractor 81 is the speed target value ω from the active power controller 10.₀ ^*The speed command value ω^*The deviation from the speed ω from the speed detector 15 is obtained and input to the controller 82. When the deviation obtained by the subtracter 81 is input, the controller 82 outputs the output 8a to the effective current command value Iq.^*Is output to the frequency converter current control device 7 as follows.
[0013]
As shown in FIG. 59, the active power controller 10 includes a subtractor 101, a settling rate calculator 102, a limiter 103, an adder 104 and a subtractor 105, a controller 106, and an optimum opening calculator 107. The
[0014]
Here, the subtractor 101 has a reference frequency f.₀And the system frequency f detected by the frequency detector 16_LFrom this, the system frequency fluctuation Δf is obtained. The settling rate calculator 102 determines the ratio between the system frequency fluctuation Δf and the active power 10a to be changed accordingly. The limiter 103 receives an automatic frequency control (AFC) signal P from a central power station (not shown)._AFCTo limit the signal range and rate of change. The adder 104 includes an active power 10a to be changed and an AFC signal P._AFCAnd active power setting value P_SFrom this, the active power target value 10d is obtained. The controller 106 receives the active power target value 10d that is the output of the subtractor 105 and the deviation 10e between the active power P and the speed target value ω so that the deviation 10e becomes zero.₀ ^*Is output to the speed controller 8. Further, the optimum opening calculator 104 determines the control valve opening target value CV that determines the mechanical input / output of the prime mover from the head H and the active power target value 10d.₀ ^*Is output to the prime mover control device 6.
[0015]
The voltage controller 11 includes a subtractor 111 and a controller 112 as shown in FIG.
[0016]
Here, the subtractor 111 is a voltage command value V_SAnd the system voltage v from the voltage detector 12_LAnd is input to the controller 112. Further, when the deviation is input from the subtractor 111, the controller 112 outputs an invalid current command value Id as an output signal.^*Is output to the frequency converter current control device 7.
[0017]
With the above configuration, the active power setting value P_SActive power is exchanged with the grid.
For this purpose, the primary frequency of the winding induction machine 1 must be synchronized with the system frequency. Therefore, the frequency of the frequency converter 4 is controlled according to the difference between the system frequency and the speed of the winding induction machine 1.
[0018]
In this system, the speed ω and the frequency f have a one-to-one relationship determined by the number of poles of the winding induction machine 1 and are the same value when expressed in the pu value. Therefore, the following treats the frequency and speed as the same quantity, and the system frequency f_LAnd synchronous speed ω_SYNAre treated as the same amount.
[0019]
The slip frequency S is defined as follows.
[0020]
S = ω-ω_SYN= Ω-f_L
By the way, the reference synchronization speed ω determined from the reference frequency_SYN0Speed difference from (ω−ω_SYN0) May be tentatively referred to as slip speed or slip frequency._SYN0) Is tentatively referred to as an approximate slip frequency S ′ and distinguished from the slip frequency S.
[0021]
[Problems to be solved by the invention]
The speed ω of the winding induction machine 1 is synchronized at a constant rate ω._SYN61, the current flowing through the frequency converter (hereinafter referred to as converter current) is as shown in FIG. However, this is an example in which the current amplitude is constant and the current for one phase is shown. (Hereinafter described as R-phase current.)
As shown in FIG. 61, the frequency f of the converter current_IIs the speed ω and system frequency f_L, That is, the slip frequency S, and the current phase is a value obtained by integrating the slip frequency.
[0022]
By the way, since the elements constituting the frequency converter can pass a current only in one direction, the element that flows the R-phase positive current (referred to as the R-phase positive element) is a positive half-wave indicated by hatching in FIG. Will flow. In the R-phase positive side element, the duration of continuous energization varies depending on the slip frequency, and the conduction time becomes longer near the synchronous speed.
[0023]
Therefore, the frequency converter used in the variable speed pumped storage power generation system that passes the synchronous speed needs to be designed so that the rated current can be continuously supplied, and there is a problem that the current capacity increases.
[0024]
Therefore, in order not to increase the converter capacity more than necessary from the viewpoint of installation space and economy, the frequency f of the converter current_IThe lower limit frequency f_BNDAnd the lower limit frequency f_BNDIt is devised to avoid driving in the following. That is, -f_BNDTo f_BNDIs the forbidden band and the frequency f of the converter current_IAvoids driving in a prohibited zone. In the following, f_BNDIs also referred to as a forbidden bandwidth.
[0025]
Conventionally, the frequency f of the converter current_IThe above is realized by replacing the forbidden band with a speed forbidden band. That is, the forbidden band lower limit speed ω ′_LAnd forbidden band upper limit speed ω '_UReference sync speed ω_SYN0And forbidden band width f_BNDTo the formula (1)_LTo ω´_UThe speed range up to is the speed prohibition zone.
[0026]
ω´_L= Ω_SYN0-F_BND,  ω´_U= Ω_SYN0+ F_BND(1)
The frequency f of the converter current can be reduced by not operating in the speed prohibition zone._IDoes not fall within the forbidden band. As a result, the frequency converter has a lower limit frequency f._BNDTherefore, it is possible to reduce the current capacity of the frequency converter (see Japanese Patent No. 2851490, Japanese Patent Laid-Open No. 9-37596).
[0027]
A conventional system is shown in FIG. FIG. 62 is the same as the configuration of FIG. 56 except that a speed prohibition band avoidance controller 9 is added between the active power controller 10 and the speed controller 8 with respect to the configuration shown in FIG. .
[0028]
The speed forbidden band avoidance controller 9 includes a hysteresis function means 91 and a change rate limiter 92 as shown in FIG.
[0029]
Here, the hysteresis function means 91 is the speed target value ω from the active power controller 10.₀ ^*Is input, the output 9a of the hysteresis function means 91 is input to the change rate limiter 92. The change rate limiter 92 outputs the output 9b to the speed command value ω.^*Is output to the speed controller 8. Incidentally, the input ω of the hysteresis function means 91₀ ^*64 and the output 91a are shown in FIG. That is, ω₀ ^*If increases
ω₀ ^*<Ω´_LOr ω´_U<Ω₀ ^*  Then ω^*= Ω₀ ^*,
ω´_L≦ ω₀ ^*≦ ω´_U  Then ω^*= Ω´_L
Also, ω₀ ^*Is reduced,
ω₀ ^*<Ω´_LOr ω´_U<Ω₀ ^*  Then ω^*= Ω₀ ^*,
ω´_L≦ ω₀ ^*≦ ω´_U  Then ω^*= Ω´_U
FIG. 65 shows the characteristics of the speed command value according to the conventional method. Speed target value ω₀ ^*Even if the vehicle passes through the speed prohibition zone from time t1 to time t2, the speed command value ω^*Waits at a deceleration under the prohibited zone until time t2, and passes through the prohibited zone in a short time from time t2 to time t3.
[0030]
As described above, the frequency f of the converter current is conventionally prevented by preventing the speed target value from entering the speed forbidden band._IHad avoided driving into the prohibited zone. However, even though the speed target value is not in the speed prohibition band, the frequency f_IIs the lower limit frequency f_BNDThis could cause damage to the transducer elements. For example, speed target value ω₀ ^*And speed command value ω^*When the system frequency fluctuates and Δf decreases from the reference frequency, that is, the reference synchronization speed, when the control is performed as shown in FIG. 65, the approximate slip S ′ is f_BNDThe slip S is-(f_BND−Δf). Converter frequency f_IIs equal to the slip S, so the lower limit frequency f_BNDThere is a risk of destroying the device.
[0031]
In addition, it has been proposed to reduce the load on the element when passing through the forbidden band by narrowing down the converter current when passing through the forbidden band (Japanese Patent Publication No. 2851490). On the contrary, there is a risk of damaging the device by increasing the load on the device.
[0032]
The present invention has been made in view of the circumstances as described above, and has a first object to reduce the load on the element when the element is in a severe operating state, and the capacity of the frequency converter is increased. The second object is to make it possible to avoid damage to the elements of the converter even if the system frequency fluctuates, and the third object to reduce the burden on the elements when passing through the forbidden band. Is to provide a variable speed control device.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, the present invention constitutes a variable speed control device by the following means.
[0034]
  In the invention corresponding to claim 1, the primary side of the winding induction machine that is axially coupled to the prime mover is connected to the system via the main transformer and the generator-side circuit breaker, and the secondary side is controlled by the current control device. In a variable speed control device for controlling a variable speed system formed by connecting a frequency converter, a stop signal is output to stop the frequency converter upon detecting that the element of the frequency converter is in a thermally severe state. Element abnormality detection meansThe element abnormality detecting means includes a temperature detector for detecting the temperature of the heat radiation fin of each element, a temperature detector for cooling water for cooling the frequency converter, a temperature of the heat radiation fin of the element, and a temperature of the cooling water. A temperature estimator that estimates the temperature of each element from the above, a comparator that compares the estimated temperature value of each element with a specified value, and the frequency converter when the estimated temperature value of any element exceeds a specified value And an OR circuit that outputs a stop signal.
[0035]
Here, the element abnormality detection means can detect an element abnormality on the condition that the temperature of the element of the frequency converter exceeds a predetermined value.
[0040]
  Claim2The self-excited frequency controlled by the current control device on the secondary side is connected to the system via the main transformer and the generator-side circuit breaker. In a variable speed control device for controlling a variable speed system formed by connecting a converter, a self-excited frequency conversion is performed by outputting a stop signal when detecting that the element of the self-excited frequency converter is in a thermally severe state. An element abnormality detecting means for stopping the converter, the element abnormality detecting means being output from the converter current control device, and a gate pulse when the converter current is positive and a converter current when the converter current is negative A positive-side and negative-side gate pulse number counter that counts each gate pulse, detects the element abnormality by an integrated value of the number of gate pulses for each half wave, and outputs a stop signal to the self-excited frequency converter; Constructed.
[0058]
Here, the control state changing means of the frequency converter can be constituted by a gate pulse number reducing means for reducing the gate pulse when passing through the forbidden band. In this case, the gate pulse number reduction means may be constituted by a frequency divider and a carrier frequency selection circuit, or by an output voltage correction means for correcting the output voltage of the frequency converter as follows. Also good. In other words, the output voltage correction means of the frequency converter may have a dead band inserted between the output voltage calculator of the frequency converter current control device and the gate pulse generator, and the gate pulse of the maximum phase of the converter current may be inserted. A bias may be applied so as to reduce.
[0059]
Furthermore, the control state changing means of the frequency converter comprises DC link voltage correcting means for increasing the DC link voltage of the self-excited frequency converter, and reduces the converter current when passing through the forbidden band, thereby reducing the frequency converter. The damage of the element can be avoided.
[0071]
  Claim3The frequency converter controlled by the current control device on the secondary side is connected to the system via the main transformer and the generator-side circuit breaker. A speed target value correcting means for correcting a speed target value so that the speed target value does not fall within a speed prohibition band determined from a system frequency and a prohibition band, A speed forbidden band avoidance controller comprising means for calculating a speed command value from the speed target value corrected by the speed target value correcting means, and suppresses fluctuations in the speed target value when the speed target value enters the speed forbidden band. Fluctuation suppression means.
[0072]
Here, the fluctuation suppression means is constituted by a governor-free lock means, and when the speed target value enters the speed prohibition zone, the fluctuation due to the governor-free control component included in the speed target value is removed, whereby the speed target value becomes the speed. The frequency of entering the prohibited zone can be reduced.
[0073]
Further, the fluctuation target is constituted by an AFC lock means, and when the speed target value enters the speed forbidden band, the fluctuation due to the AFC control component included in the speed target value is removed, so that the speed target value is within the speed forbidden band. Can reduce the frequency of entering.
[0074]
Furthermore, it is composed of a low-pass filter as a fluctuation suppression means, and when the speed target value enters the speed prohibition band, the fast fluctuation included in the speed target value is removed, thereby reducing the frequency of the speed target value entering the speed prohibition band. it can.
[0079]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0080]
FIG. 1 is a circuit configuration diagram showing a first embodiment of a variable speed control apparatus according to the present invention. The same parts as those in FIG. 56 are denoted by the same reference numerals and the description thereof is omitted, and different parts will be described here.
[0081]
In the first embodiment, as shown in FIG. 1, an element abnormality detecting means 21 for detecting that an element of the frequency converter 4 is in a thermally severe state is provided, and the frequency converter is operated by the element abnormality detecting means 21. When an abnormality of the element 4 is detected, a converter stop signal (GB) is input to the frequency converter current control device 7 as the element abnormality detection signal 21a.
[0082]
In the variable speed control device having such a configuration, when the element abnormality detecting unit 21 detects that the element of the frequency converter 4 is in a thermally severe state, the element abnormality detecting unit 21 detects the element abnormality detecting signal 21a. Is input to the frequency converter current control device 7 as a converter stop signal GB to stop the frequency converter 4.
[0083]
Therefore, when the element abnormality detecting means 21 detects that the element of the frequency converter 4 is in a thermally severe state, the frequency converter 4 is stopped, so that damage to the element of the frequency converter 4 is avoided. Can do.
[0084]
Here, a specific example in the case where an element temperature abnormality detection device is used as the element abnormality detection means 21 will be described.
[0085]
FIG. 2 is a circuit configuration diagram showing a first specific example of the element temperature abnormality detection device.
[0086]
In the element temperature abnormality detection device 23 shown in FIG. 2, 231-1 to 231-n are n temperature detectors embedded in heat dissipation fins of n elements, 232 is a cooling water temperature detector, 233-1. ˜233-n are n temperature estimators for estimating the temperature of the element junction from the fin temperature and the temperature of the cooling water, 234-1 to 234-n are n comparators, and 235 is an OR circuit.
[0087]
In the element temperature abnormality detection device 23 having such a configuration, the temperature estimator 233-1 is No. 1 fin temperature T_F-1 and cooling water temperature T_WTo (2) in accordance with No. Junction temperature T of element 1_J-1 is estimated.
[0088]
T_J-1 = T_F-1 + R_JF(T_F-1-T_W) / R_F          (2)
However, R_JFIs the thermal resistance from the element junction to the fin, R_FIs the thermal resistance of the fin.
[0089]
The comparator 234-1 has a junction temperature T_JWhen -1 exceeds a specified value, a temperature abnormality signal 23a is output.
[0090]
Although the above has described the temperature detection of No. 1, the same applies to other temperature detections. When one of the temperature detection signals exceeds a specified value, the OR circuit 235 inputs the converter stop signal 23b to the frequency converter current control device 7 to stop the frequency converter 4. The specified value of the temperature of the junction is an upper limit temperature that can be used without leaving any deterioration in the element, and a value of 125 ° C. is generally used.
[0091]
Therefore, according to the variable speed control device including the element temperature abnormality detection device 23 having such a configuration, when the junction temperature of any element of the frequency converter exceeds a specified value, the converter stops. Damage to the frequency converter element can be avoided.
[0092]
FIG. 3 is a circuit configuration diagram showing a second specific example of the element temperature abnormality detection device.
[0093]
In the element temperature abnormality detection device 24 shown in FIG. 3, 241 -R to 241 -T are element loss estimators for each phase, and these loss estimators 241 -R to 241 -T are the converter current detectors 14. Three-phase instantaneous current i detected at_I-R ~ i_I-T and the output voltage v of the frequency converter current control device 7_I-R ~ v_I-T is input respectively, and the estimated loss value P_L-R ~ P_L-T is output to the junction temperature estimators 242-R to 242-T.
243 -R to 243 -T are estimated loss values P input from the junction temperature estimators 242 -R to 242 -T._L-R ~ P_LA comparator 244 for comparing -T with a specified value is an OR circuit to which the outputs of these comparators 243 -R to 243 -T are inputted.
[0094]
In the element temperature abnormality detection device 24 having such a configuration, the loss estimator 241 -R includes the estimated loss value p of the element that flows the R-phase current._LRIs the instantaneous current i of the R-phase circuit of the frequency converter_I-R and output voltage v_IEstimate as a function of -R. However, the estimated loss value p_LRAnd current i_I-R and output voltage v_IThe relationship of -R is obtained in advance from element characteristics and power supply voltage. The junction temperature estimator 242-R_LRAnd thermal resistance R from joint to cooling water_JWAnd the temperature T of the junction from the heat capacity C of the element_JRIs estimated at regular intervals using equation (3).
[0095]
T_JR'= T_JRO'+ (P_LR-T_JRO'/ R_JW) / C
T_JR= T_JR'+ T_W                                      (3)
T_JR', T_JRO′ Is the previous junction temperature rise value, the cooling water temperature T_WIt is an increase from In addition, the temperature T of the cooling water_WIs approximated by a constant value determined by the state of use.
[0096]
The R phase junction temperature estimation has been described above, but the same applies to the other phases. The operations of the comparators 243 -R to 243 -T and the OR circuit 244 are the same as those of the OR circuit 235 shown in FIG.
[0097]
According to the variable speed control device including the element temperature abnormality detection device 24 having such a configuration, the loss of the device is estimated from the output voltage and the converter current of the frequency converter current control device 7, and the junction is determined from the estimated loss value. Since the temperature is estimated and the abnormal temperature of the frequency converter element is detected from the estimated temperature and the converter is stopped, damage to the frequency converter element can be avoided. In addition, since the temperature is not directly measured, the accuracy of the temperature estimation value is lower than that of the first specific example, but there is no practical problem if the specified value of the abnormal temperature high is determined in consideration of the estimation error. Since the measurement of temperature and cooling water temperature can be omitted, it is simple and highly reliable.
[0098]
FIG. 4 is a circuit configuration diagram showing a third specific example of the element temperature abnormality detection device.
[0099]
In the element temperature abnormality detection device 25 shown in FIG. 4, 251 -R to 251 -T are three-phase instantaneous value currents i detected by the converter current detector 14._I-R ~ i_I-T is a comparator for each phase to which the current polarity signals 25a-R to 25a-T, which are the outputs of the comparators 251-R to 251-T, are converted into signal inverters 252-R to 252-T. Output to on-delay timers 253 -R to 253 -T. Output signals 25b-R to 25b-T of the signal inverters 252-R to 252-T are input to on-delay timers 254-R to 254-T. The OR circuit 255 receives the output signals of the on-delay timers 253 -R to 253 -T and 254 -R to 254 -T, and uses the element temperature signal 25 e that is the output signal as a converter stop signal as a frequency converter current control device. 7 is output.
[0100]
In this case, the comparator 251 -R has an instantaneous value current i of the R-phase circuit._IOutput signal 25a-R is set to logic level 1 when -R is positive, and logic level 0 when negative. The on-delay timer 253 -R sets the output signal 25 c -R to the logic level 1 when the signal 25 a -R is at the logic level 1 for the specified time. The on-delay timer 254 -R sets the output signal 25 d -R to the logic level 1 when the signal 25 b -R is at the logic level 1 for the specified time.
[0101]
From the above, it can be seen that the output signal of the on-delay timer becomes logic level 1 when the time during which the R-phase current is continuously positive or negative exceeds the specified time.
The same applies to the other phases. The operation of the OR circuit 255 is the same as that of the OR circuit 235 in FIG.
[0102]
The specified time of the on-delay timer is the longest time that can be used without leaving any deterioration in the element even if a direct current having the maximum current amplitude when passing through the forbidden band continues to flow.
[0103]
According to the variable speed control device including the element temperature abnormality detection device 25 having such a configuration, the converter can be stopped when the current of any phase continues to have the same polarity for a specified time or more. By the way, the element of the frequency converter is in a thermally severe situation when the current flows continuously through the same element, thereby increasing the junction temperature of the element.
[0104]
Therefore, it is possible to avoid damage to the elements of the frequency converter without estimating the temperature of the elements. Since the temperature is not estimated, the thermal margin of the element is less accurate than the second specific example, but there is no practical problem if the specified time is determined in consideration of the estimation error. In addition, since complicated temperature estimation calculation can be omitted, it is simple and highly reliable.
[0105]
In addition, the circuit shown in FIG._I-R ~ i_IBy adding an arithmetic unit that calculates the amplitude of the converter current from -T and an arithmetic unit that determines the specified time of the on-delay timer from the amplitude of the converter current, the specified time of the on-delay timer depends on the amplitude of the converter current. Therefore, the accuracy of estimating the thermal margin of the element can be improved.
[0106]
FIG. 5 is a circuit configuration diagram showing a fourth specific example of the element temperature abnormality detection device.
[0107]
In the element temperature abnormality detection device 26 shown in FIG. 5, 261 -R to 261 -T are three-phase instantaneous value currents i detected by the converter current detector 14._I-R ~ i_IThese zero detectors 261-R to 261-T output reset signals 26a-R to 26a-T to integrators 262-R to 262-T. These integrators 262 -R to 262 -T have a three-phase instantaneous current i._I-R ~ i_I-T and reset signals 26a-R to 26a-T are input, and the output signals are input to the comparators 263-R to 263-T. The OR circuit 264 receives comparators 263-R to 263-T output signals 26c-R to 26c-T, and outputs an element temperature signal 26d as an output signal to the frequency converter current control device 7 as a converter stop signal. To do.
[0108]
In the element temperature abnormality detection device 26 having such a configuration, the zero detector 261-R includes the instantaneous value current i of the R-phase circuit._IWhen -R is zero, output signal 26a-R is set to logic level 1, and the output of integrator 262-R is reset to zero. The integrator 262-R has a current i_I-R is integrated, but the current i_ISince it is reset when -R is zero, its output 26b-R becomes a value obtained by integrating only a positive current or only a negative current. Comparator 263-R sets output signal 26c-R to logic level 1 when output 26b-R of integrator 262-R exceeds a specified value.
[0109]
Therefore, the output signal 26c-R of the comparator 263-R has the same meaning as 25c-R and 25d-R in FIG. Although the R phase has been described above, the same applies to the other phases. The operation of the OR circuit 264 is the same as that of the OR circuit 235 in FIG.
[0110]
The specified value is determined by the product of the maximum time that can be used without causing deterioration of the element even if a direct current having the amplitude of the rated current continues to flow and the amplitude of the rated current.
[0111]
According to the variable speed control device provided with the element temperature abnormality detection device 26 having such a configuration, the converter can be stopped when the integral value of the current having the same polarity becomes a specified value or more. Further, similarly to the case of FIG. 4, it is possible to avoid damage to the elements of the frequency converter without estimating the temperature of the elements.
[0112]
FIG. 6 is a circuit configuration diagram showing a fifth specific example of the element temperature abnormality detection device.
[0113]
However, the frequency converter 4 in this case is a self-excited frequency converter.
[0114]
In the element temperature abnormality detection device 27 shown in FIG. 6, gate pulses PP-R to PP-T, which are gate signals given from the frequency converter current control device 7 to the element for passing the positive current of the frequency converter 4, are gated. It is input to the count terminals of the pulse number counters 271 -R to 271 -T and the reset terminals of the gate pulse number counters 272 -R to 272 -T, respectively. Similarly, gate pulses PN-R to PN-T, which are gate signals of elements that flow negative-side current, correspond to the count terminals of the gate pulse number counters 272-R to 272-T and the gate pulse number counters 271-R to 271-. Each is input to a reset terminal of T.
[0115]
The count high signals 27a-R to 27a-T which are the outputs of these gate pulse number counters 271-R to 271-T and the count high signals 27b-R to which are the outputs of the gate pulse number counters 272-R to 272-T. 27b-T is input to the OR circuit 273, and this OR circuit 273 outputs the element temperature high signal 27c, which is an output signal, to the frequency converter current control device 7 as the converter stop signal 27c.
[0116]
In the element temperature abnormality detection device 27 having such a configuration, the gate pulse PP-R is output when the R-phase converter current is positive, and the gate pulse PN-R is output when the R-phase converter current is negative. Since it is output, the gate pulse number counter 271 -R counts pulses during a period when the converter current is continuously positive. In general, since the gate pulses are output at a constant period, the count high signal 27a-R output from the gate pulse number counter 271-R has the same meaning as the on-delay timer 25c-R in FIG. Similarly, the count high signal 27b-R output from the gate pulse number counter 272-R has the same meaning as the on-delay timer 25d-R in FIG. The other phases also have the same action as in FIG.
[0117]
The operation of the OR circuit 273 is the same as that of the OR circuit 255 in FIG.
[0118]
According to the variable speed control device including the element temperature abnormality detection device 27 having such a configuration, the integrated value of the number of gate pulses for each half wave is obtained, and the temperature rise of the element due to the long conduction time is obtained from the integrated value. 4 can be detected, so that the same effect as in FIG. 4 can be obtained, and the circuit configuration can be simplified as compared with FIG.
[0119]
The specific example of the element temperature abnormality detection device as the element abnormality detection means 21 in FIG. 1 has been described above. Next, another specific example of the element abnormality detection device other than the element temperature abnormality detection device will be described.
[0120]
FIG. 7 is a circuit configuration diagram showing a first specific example of the element abnormality detection device.
[0121]
In FIG. 7, the speed ω detected by the speed detector 15 and the system frequency f detected by the frequency detector 16._LIs input to the subtracter 281, and the output S of the subtracter 281 is input to the comparator 282. The output 28a of the comparator 282 is input to the on-delay timer 284, and an output signal 28b is output to the frequency converter current control device 7 as a converter stop signal. Note that the subtractor 281 and the comparator 282 constitute a forbidden band retention detector 283.
[0122]
In the element abnormality detection device 28 having such a configuration, the subtracter 281 includes the speed ω and the system frequency f._LThe slip frequency S which is the difference between the two is detected. The comparator 282 sets the output signal 28a to logic level 1 when the slip frequency S is in the frequency forbidden band.
When the signal 28 a is at the logic level 1 for a predetermined time or longer, the on-delay timer 284 sets the output signal 28 b to the logic level 1 and stops the frequency converter 4 via the frequency converter current control device 7.
[0123]
In this case, the specified time of the on-delay timer is set to the longest time that can be used without deteriorating the element even when the maximum current during passage through the forbidden band continues to flow in the forbidden band.
[0124]
According to the variable speed control device provided with the element abnormality detection device 28 having such a configuration, the temperature rise of the element having a long conduction time can be obtained by obtaining the time within the slip frequency prohibition band when the slip frequency is small. Since it is detected that the current is excessive and the current of any phase continues to have the same polarity for a specified time or longer from the slip frequency, the converter is stopped, so the same effect as in FIG. 4 can be obtained. At the same time, there is an effect that the circuit is simplified as compared with FIG.
[0125]
FIG. 8 is a circuit configuration diagram showing a second specific example of the element abnormality detection device.
[0126]
In FIG. 8, instead of the on-delay timer 284 shown in FIG. Is output to the frequency converter current control device 7 as a converter stop signal.
[0127]
In this case, in the element abnormality detection device 29, when disturbance occurs in the converter current control while the forbidden band is retained, the AND circuit 292 sets the output signal 29b to the logic level 1 and the frequency via the frequency converter current control device 7. The converter 4 is stopped.
[0128]
According to the variable speed control device provided with the element abnormality detecting means having such a configuration, if a disturbance that increases the converter current occurs while the forbidden band stays, it is a severe condition that causes the temperature of the conducting element to rise. Although the operation may continue, the element abnormality detection device of the present example can stop the converter even in such a state. Further, the same effect as in FIG. 7 can be obtained, and the circuit can be simplified as compared with FIG.
[0129]
FIG. 9 is a circuit configuration diagram showing a third specific example of the element abnormality detection device.
[0130]
In FIG. 9, the control disturbance detecting means 291 in FIG. 8 is replaced with a water level detector 301 and a comparator 302. The comparator 302 outputs the control disturbance detection signal 30a to the frequency converter current control device 7 as a converter stop signal.
[0131]
In the element abnormality detection device having such a configuration, when the output 30a of the surge tank water level detector 301 exceeds the specified value, the comparator 302 sets the output signal 30b to the logic level 1 through the frequency converter current control device 7. The frequency converter 4 is stopped.
[0132]
According to the variable speed control device including the element abnormality detection device having such a configuration, when the prime mover is a pump turbine, when the surge tank water level rises, the torque of the pump turbine increases. For this reason, the speed changes, but the speed controller 8 increases the converter current so as to suppress the speed change.
[0133]
Therefore, if the surge tank water level rises while the forbidden band stays, there is a risk that severe operation will continue for the elements of the converter. In such a state, the converter can be stopped, and the same effect as in the case of FIG. 8 can be obtained.
[0134]
The same effect can be obtained by using the water pressure applied to the control valve, the flow rate of the pump turbine, and the guide vane opening instead of the surge tank water level.
[0135]
Although the above description has been made on the case where the prime mover is a pump turbine, when the prime mover is a steam turbine, the same effect can be obtained by using the turbine inlet steam pressure, the first stage steam pressure, and the turbine steam flow rate. In the case of a windmill, the same effect can be obtained by using the wind speed and the blade angle.
[0136]
FIG. 10 is a circuit configuration diagram showing a fourth specific example of the device abnormality detecting apparatus.
[0137]
10, the control disturbance detection means 291 of FIG. 8 is configured by a voltage converter 311 and a comparator 312.
[0138]
In the element abnormality detection device having such a configuration, the output v of the voltage detector 12_LIs input to the comparator 312 via the voltage converter 311. The comparator 312 outputs the output signal 31a to the frequency converter current control device 7 as a converter stop signal.
[0139]
Further, the output v of the voltage detector 12_LIs converted to a DC voltage signal 31a by a voltage converter 321. The comparator 312 sets the output signal 31b to logic level 1 when the input signal 31a becomes equal to or less than the specified value, and stops the frequency converter 4 via the frequency converter current control device 7.
[0140]
According to the variable speed control device including the element abnormality detection device having such a configuration, when a system failure or a failure of an adjacent machine occurs, the voltage of the winding induction machine decreases and the converter current rapidly increases. The temperature of the conducting element rises. Therefore, since the voltage converter can be stopped by detecting the voltage drop of the winding induction machine, the same effect as in the case of FIG. 8 can be obtained.
[0141]
FIG. 11 is a circuit configuration diagram showing a fifth specific example of the element abnormality detection device.
[0142]
In FIG. 11, the control disturbance detecting means 291 in FIG. 8 is replaced with a system protection relay contact 321 and a single pulse generator 322 separately installed.
[0143]
In the element abnormality detection device 32 having such a configuration, when a system failure occurs and the contact 321 of the system protection relay is closed, the single pulse generator 322 controls the frequency converter current using the output 32a as a converter stop signal for a certain period of time. Output to the device 7 and stop the frequency converter 4. In this case, the fixed time is determined from the time when the influence of the system failure occurs.
[0144]
In the variable speed control device including the element abnormality detection device 32 having such a configuration, when a system failure occurs, the converter current increases rapidly, and the temperature of the conducting element rises.
However, according to the above circuit configuration, the frequency converter can be stopped at the time of a system failure, so that the same effect as in the case of FIG. 8 can be obtained. Moreover, after the system failure is removed, the operation can be resumed.
[0145]
FIG. 12 is a circuit configuration diagram showing a sixth specific example of the element abnormality detection device.
[0146]
In FIG. 12, the control disturbance detection means 291 of FIG. 8 is replaced with a trip contact 331 and a single pulse generator 332 of an adjacent machine installed separately.
[0147]
That is, in FIG. 12, when the adjacent machine trips and the contact 331 is closed, the single pulse generator 332 outputs the output 33a as a converter stop signal to the frequency converter current control device 7 for a certain period of time, and the frequency converter 4 To stop. In this case, the fixed time is determined from the time when the influence of the trip of the adjacent aircraft is exerted.
[0148]
In the element abnormality detection device having such a configuration, when the adjacent machine trips, an increase in the current of the frequency converter may occur through the prime mover or due to a change in power flow. For example, when an adjacent machine sharing a water channel with a variable speed machine trips, the effective drop of the prime mover increases due to a sudden change in the flow rate of the adjacent machine, causing a sudden increase in the prime mover torque of the variable speed machine. Even in such a case, the temperature rise of the element due to an increase in current can be predicted in advance.
[0149]
According to the variable speed control device including the element abnormality detection device having such a configuration, when the adjacent machine trips, the converter current increases rapidly, and the temperature of the conductive element rises. Since the converter can be stopped, the same effect as in FIG. 8 can be obtained. The operation can be resumed after the adjacent aircraft is no longer affected by the trip.
[0150]
FIG. 13 is a circuit configuration diagram showing a second embodiment of the variable speed control device according to the present invention, and an operating point between the element abnormality detecting means 21 and the frequency converter current controller 7 with respect to the configuration of FIG. The changing unit 140 is provided, and the other configuration is the same as that in FIG. 1, and thus the description thereof is omitted here.
[0151]
In FIG. 13, the operating point changing means 140 does not need to immediately stop the frequency converter 4 by the element abnormality detecting means 21 but detects that the element is in a severe operating state. Is input, the correction result of various command values for changing the operating point is output.
[0152]
In the variable speed control device having such a configuration, when the element abnormality detecting means 21 does not need to immediately stop the converter, but detects that the element is in a severe operating state, the operating point changing ability 140 determines the operating point. The determined command value is changed, and as a result, the operation state is changed to an easy operation state for the element.
[0153]
Therefore, since the operation is changed to an easy operation for the element, the temperature rise is suppressed without damaging the element, and the operation can be continued.
[0154]
Here, a specific example when a speed changing device is used as the operating point changing means 140 will be described.
[0155]
FIG. 14 is a circuit configuration diagram showing a first specific example of the speed changing device.
[0156]
In FIG. 14, the speed changing device 35 is composed of a speed deviation amount calculating means 351 and a speed command value correcting means 352.
[0157]
The speed deviation amount calculation means 351 includes a speed ω from the speed detector 15 and a system frequency f from the frequency detector 16._LIs input, and the speed deviation amount 35 a is output to the speed command value correcting means 352. The speed command value correcting means 352 is a speed target value ω from the active power controller 10.₀ ^*Then, the element abnormality detection signal 21b from the element abnormality detecting means 21 and the speed deviation amount 35a are input, and the output 35b is converted into the speed command value ω.^*Is output to the speed controller 8.
[0158]
In such a speed change device 35, the speed deviation amount calculation means 351 includes the speed ω and the system frequency f._LAnd the speed command value correcting means 352 detects that the element abnormality detecting means 21 does not need to immediately stop the converter, but detects that the element is in a severe operating state.₀ ^*Is corrected based on the speed deviation amount 35a and the command value ω is determined^*Is changed. As a result, the speed ω is changed to change to an easy driving state for the element.
[0159]
According to the variable speed control device provided with the speed change device having such a configuration, it is not necessary to stop the converter immediately, but if it is detected that the element is in a severe operating state, the speed and the system frequency are used in a prohibited band. The amount of speed deviation necessary for avoiding the operation is obtained, and the speed command value is corrected by the amount of speed deviation. For this reason, since the operation is surely shifted away from the prohibited zone and the temperature rise of the element is suppressed, the operation can be continued without damaging the element.
[0160]
FIG. 15 is a circuit configuration diagram showing a second specific example of the speed changing device.
[0161]
In FIG. 15, the speed changing device 36 includes a comparator 361 and analog switches 362, 363, 364, 365.
[0162]
The comparator 361 includes the speed ω from the speed detector 15 and the system frequency f from the frequency detector 16._LIs input and the size is compared. The analog switches 362 and 363 are connected in series, and when the analog switch 362 is turned on by a switching command from the comparator 361, the corrected speed set value ω₀₁When the analog switch 362 is turned on, the corrected speed setting value ω₀₂Is output to the output circuit derived from the connection between the analog switches 362 and 363. This output circuit is provided with an analog switch 364, and on the output side of this analog switch 364, the speed target value ω from the active power controller 10 is provided.₀ ^*Is connected to the analog switch 365.
[0163]
Here, the output signal 36b is the corrected speed set value ω when the analog switch 362 is on.₀₁When the analog switch 363 is on, the corrected speed setting value ω₀₂It becomes. The output signal 36c becomes the output signal 36b when the analog switch 364 is on, and the speed target value ω from the active power controller 10 when the analog switch 365 is on.₀ ^*It becomes. The output signal 36c is output to the speed controller 8 as a corrected speed command value.
[0164]
In such speed changing means 36, the comparator 361 has ω> f_LTo turn on the analog switch 362 and ω ≦ f_LThe analog switch 363 is turned on. When the element abnormality detection signal 21b is at logic level 1, the analog switch 364 is turned on, and when the element abnormality detection signal 21b is at logic level 0, the analog switch 365 is turned on.
[0165]
Corrected speed setting value ω₀₁Is determined to be a speed at which the element can be operated comfortably at a speed higher than the upper limit speed of the prohibited band. Also, the correction speed setting value ω₀₂Is determined to be a speed at which the device can be operated easily at a speed lower than the forbidden band lower limit speed.
[0166]
According to the variable speed control device including the speed change device having such a configuration, when it is detected that the element is in a severe operating state, the speed is changed to an easy speed for the element, so that the operation can be continued. .
[0167]
FIG. 16 is a circuit configuration diagram showing a third specific example of the speed changing device.
[0168]
In FIG. 16, the speed changing device 37 is constituted by the speed deviation amount calculating means 351 and the speed command value correcting means 352 shown in FIG.
[0169]
The speed deviation amount calculation means 351 includes a subtractor 371, a comparator 372, analog switches 373 and 374, an adder 375, and an analog switch 376.
[0170]
The speed command value correcting means 352 includes a coefficient unit 377 and an adder 378.
[0171]
Further, the subtractor 371 includes the speed ω from the speed detector 15 and the system frequency f from the frequency detector 16._LAnd the subtraction output signal 37 a is output to the comparator 372. The subtractor 375 generates a forbidden bandwidth f when the analog switch 373 is turned on by an output signal 37a of the adder 371 and a switching command of the comparator 372._BNDIs the forbidden bandwidth −f when the analog switch 374 is on._BNDAre respectively input as output signals 37b, and the subtraction output 37c is converted into a speed deviation amount ω._BIASIs output to the coefficient multiplier 377 via the analog switch 376. The adder 378 outputs the output signal 37d of the coefficient unit 377 and the speed degree target value ω.₀ ^*And the output signal 37e is converted into the speed command value ω.^*Is output to the speed controller 8.
[0172]
In the speed change device 37 having such a configuration, the output signal 37a of the subtractor 371 is the speed ω and the system frequency f._LDifference, that is, the slip frequency S. The comparator 372 turns on the analog switch 373 when the slip frequency S is positive, and turns on the analog switch 374 when the slip frequency S is negative. Therefore, the output signal 37c of the subtractor 375 is a speed deviation amount ω expressed by the equation (4)._BIASWill be seeking.
[0173]
When S <0 …… ω_BIAS= K (-f_BND-S) = k (ω_L−ω)
When S ≧ 0 …… ω_BIAS= K (f_BND-S) = k (ω_U-Ω) (4)
Where ω_{L '}Is the lower limit band speed, ω_UIs the forbidden band upper limit speed and is expressed by equation (5). Conventional forbidden band lower limit speed ω ′ represented by equation (1)_L, Forbidden band upper limit speed ω '_UUnlike ω_L, Ω_UVaries depending on the system frequency.
[0174]
ω_L= F_L-F_BND, ΩU = f_L+ F_BND                  (5)
Next, the speed ω is equal to or lower than the synchronous speed within the speed prohibition zone_XThe operation of the speed changing means 37 will be described by taking as an example a case where an element abnormality is detected by staying in step S2. For simplicity, speed command value ω^*, Speed target value ω₀ ^*Both speed ω_XSuppose that
[0175]
When an element abnormality is detected, the speed command value ω^*Is ω_X+ K (ω_L−ω), the speed ω is ω_L+ (Ω_X−ω_L) / (K + 1). Therefore, if k is sufficiently large, the speed target value ω₀ ^*Is ω_XThe speed ω is the forbidden band lower limit speed ω_LControlled.
[0176]
Similarly, the speed ω is equal to or higher than the synchronous speed within the speed prohibition zone._YForbidden band upper limit speed ω_UControlled.
[0177]
According to the variable speed control device including the speed change device having such a configuration, it is not necessary to immediately stop the converter, but if the element is detected to be in a severe operating state, the speed command value, that is, the speed is prohibited. Band upper speed limit or prohibited band lower limit speed. In addition, the forbidden band upper limit speed or the forbidden band lower limit speed varies depending on the system frequency, so that the speed forbidden band and the slip frequency forbidden band coincide with each other, and the operation is surely out of the forbidden band. Therefore, the operation is easy for the element, and the operation can be continued.
[0178]
FIG. 17 is a circuit diagram showing another configuration example of the speed deviation amount calculation means 351 in FIG.
[0179]
In FIG. 17, the speed deviation amount calculation means 38 includes a comparator 381, analog switches 382, 383, 384, 385, an integrator 386 and a coefficient unit 387.
[0180]
The comparator 381 includes the speed ω from the speed detector 15 and the system frequency f from the frequency detector 16._LIs entered. Further, the integrator 386 receives the acceleration bias ω as an input signal 38b when the analog switch 382 is turned on by an element abnormality signal and the analog switch 383 is turned on.⁺When the analog switch 384 is on, the deceleration bias ω^-Is entered.
[0181]
When the analog switch 382 is off, the analog switch 385 is turned on, and the output 38 c of the integrator 386 becomes the input signal 38 b of the integrator 386 via the coefficient unit 387. The output signal 38c of the integrator 386 is a speed deviation amount ω._BIASIs output to the speed command value correcting means 352 of FIG.
[0182]
In the speed deviation amount calculation means 38 having such a configuration, the analog switch 382 is turned on when the element abnormality detection signal 21b is at the logic level 1, and the analog switch 385 is turned on when the element is at the logic level 0. Further, the comparator 381 has ω> ω_SYNTo turn on the analog switch 383 and ω ≦ f_LThe analog switch 384 is turned on. This integrator 386 has an input 38b of ω⁺Acceleration bias ω⁺The output is increased at the rate of change determined by^-Deceleration bias ω^-When the analog switch 385 is turned on at a rate of change determined by the above, the value changes toward zero at a speed determined by the coefficient of the integrator coefficient unit 387.
[0183]
Next, the speed ω is equal to or lower than the synchronous speed within the forbidden band._XThe operation of the speed deviation calculating means 38 will be described by taking as an example a case where an element abnormality is detected by staying in step S2. For simplicity, speed command value ω^*, Speed target value ω₀ ^*Both speed ω_XSuppose that
[0184]
Until the speed ω enters the forbidden band, the analog switch 385 is on, so the integrator output 38c is zero. When the element abnormality signal 21b becomes logic level 1, the analog switch 382 is turned on. However, since the speed is equal to or lower than the system frequency, the input signal 38b of the integrator 386 is ω^-It becomes. Accordingly, the integrator 386 outputs the output 38c, that is, the speed deviation amount ω._BIASIs reduced to the speed command value ω^*Correct in the downward direction. This operation continues until the element abnormality detection is reset and the analog switch 385 is turned on.
[0185]
Therefore, the operation is surely continued down to a speed that is easy for the element. When the element abnormality detection signal is reset, the integrator 386 slowly adjusts the speed deviation amount ω._BIASBy returning to zero, when the element abnormality factor is removed, the original operation state is restored. When the cause of the abnormality continues, the element abnormality detection signal and the analog switch 385 are repeatedly turned on and off, and the operation is continued at the limit point of the element abnormality detection signal.
[0186]
According to the variable speed control device provided with the speed change device having such a configuration, when detecting that the element is in a severe operating state, the amount of speed deviation increases or decreases until it goes out of the prohibited band. Even if the system frequency fluctuates, it is possible to reliably move to an operation away from the prohibited zone. Accordingly, the speed command value, that is, the speed becomes an easy operation for the element, and the operation can be continued. Further, the abnormality factor recovers only when the speed deviates from the speed prohibition band, and even when there is no abnormality factor, the element can be changed to a comfortable state.
[0187]
FIG. 18 is a circuit diagram showing a configuration example when a speed target value follower 39 is added to the speed changer 35 shown in FIG. 14 as the operating point changer 140 of FIG.
[0188]
In FIG. 18, the speed target value follower 39 includes a subtracter 391 and a changeover switch 392. This subtracter 391 is a speed command value ω corrected from the speed changing device 35.^*And the speed target value ω from the controller 106 of the active power controller 10 shown in FIG.₀ ^*, And its output 39a is given to the changeover switch 392.
[0189]
The changeover switch 392 selects either the deviation signal 10e from the active power controller 10 or the output 39a of the subtractor 391, and uses the output 39b as an input to the controller 106 of the active power controller 10.
[0190]
In the speed target value tracking device 39 having such a configuration, when the element abnormality detection signal 21b is at the logic level 1, the output signal 39b = 39a. In this state, the controller 106 sets the speed target value ω so that the output signal 39a of the subtracter 391 becomes zero.₀ ^*To correct. As the speed target value is corrected, the speed deviation amount ω, which is the output of the speed deviation amount calculating means 351 of the speed changing device 35._BIASWill decrease. That is, the speed deviation ω_BIASChanges from correction of the speed target value to correction of the speed target value.
[0191]
As described above, according to the variable speed control device including the operation point changing device 140 including the speed changing device 35 and the speed target value tracking device 39, when the speed is changed while ignoring the speed target value, the active power becomes the power set value. Therefore, the active power controller may change the speed target value to approach the speed prohibition band, but even in such a case, the speed target value does not approach the speed prohibition band. Can shift to remote driving. Accordingly, when it is detected that the element is in a severe operating state, not only the speed command value but also the speed target value is changed to an operation value that is easy for the element, so that the operation can be continued more stably.
[0192]
FIG. 19 is a circuit diagram showing a configuration example of a speed changing device in which the speed command value correcting means 352 of FIG.
[0193]
In FIG. 19, the active power set value correcting means 40 includes an active power deviation amount calculator 401 and an adder 402.
[0194]
The active power deviation amount calculator 401 is a first-order lag calculator with gain. The effective power deviation amount calculator 401 is a speed deviation amount ω that is an output of the speed deviation amount computing means 351._BIASAnd the output signal 40 a is given to the adder 402. The adder 402 has an active power set value P_SAnd the output signal 40a are added, and the active power set value P in which the output signal 40b is corrected is added._S1Is output to the active power controller 10.
[0195]
In the active power set value correction device 40 having such a configuration, the active power deviation amount calculator 401 is configured to output the speed deviation amount ω._BIASIs converted into an active power deviation amount. Gain is determined by the ratio of change in speed and change in active power. The first-order lag time constant is determined from the delay time from when the active power set value is changed to when the speed is changed.
[0196]
According to the variable speed control device including the speed change device having such a configuration, when it is detected that the element is in a severe operating state, the active power set value is corrected, and the speed target value is set in response to the active power control. Since the change is made, the operation can be changed to an easy operation for the element without losing the balance with the prime mover, and more stable operation can be continued.
[0197]
FIG. 20 is a circuit diagram showing a configuration example in which the operating point changing unit 140 in FIG. 13 is replaced with a reactive current command value correcting unit 41.
[0198]
In FIG. 20, the reactive current command value correcting means 41 includes a changeover switch 411, and the changeover switch 411 includes a reactive current command value 11 b (Id) from the voltage controller 11.^*) And modified reactive current set value Id₀₁And the output signal 41b is output to the frequency converter 7 as a modified reactive current command value.
In the reactive current command value correcting means 41 having such a configuration, the output signal 21b of the element abnormality detector 21 is 41b = 41a at the logic level 1. In this state, the reactive current of the converter is the modified reactive current set value Id.₀₁Controlled.
[0199]
This modified reactive current set value Id₀₁Is selected as the reactive current at zero or no-load rated excitation. In this case, Id₀₁Is a smaller value than the reactive current during normal operation, the converter current decreases.
[0200]
According to the variable speed control device provided with the reactive current command value correcting means 41 having such a configuration, when it is detected that the converter is not in a severe operating state without stopping the converter, the frequency converter current control is performed. The reactive current command value of the device is corrected, and as a result, the converter current decreases, so that the temperature rise of the element is suppressed and the operation can be continued.
[0201]
FIG. 21 is a circuit diagram showing a configuration example when a voltage set value tracking means 42 is added to the active power set value correcting means 40 shown in FIG.
[0202]
In FIG. 21, the voltage set value follow-up means 42 includes a subtracter 421 and a changeover switch 422.
[0203]
The subtractor 421 has a reactive current command value Id corrected from the reactive current correcting means 35.^*And reactive current target value Id which is output 11b of controller 112₀ ^*And the output 42 a is output to the changeover switch 422. The changeover switch 422 selects either the deviation signal 11 a from the voltage controller 11 or the output signal 42 a of the subtractor 421, and uses the output 42 b as an input to the controller 112 of the voltage controller 11.
[0204]
In the voltage setting value tracking means 42 having such a configuration, when the element abnormality detection signal 21b is at the logic level 1, 42b = 42a. In this state, the controller 112 causes the reactive current target value Id so that the input signal 42a becomes zero.₀ ^*To correct.
[0205]
Therefore, the reactive current target value Id₀ ^*Also, the reactive current command value is corrected to be zero.
[0206]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the converter, but if it is detected that the element is in a severe operating state, the voltage controller is set to the corrected reactive current command value for the reactive component. Therefore, it is possible to prevent the voltage controller from increasing the reactive current command value. Therefore, since the reactive current is surely reduced, the temperature rise of the element is suppressed and the operation can be continued stably.
[0207]
FIG. 22 is a circuit diagram showing a configuration example in which the speed command value correcting means 352 of FIG. 14 is replaced with a control valve opening command value correcting means 43.
[0208]
In FIG. 22, the control valve opening command value correcting means 43 includes a control valve opening command value deviation amount calculator 431 and an adder 432. As the control valve opening command value deviation amount calculator 431, a first-order lag calculator with gain is used. The control valve opening command value deviation amount calculator 431 is a speed deviation amount ω output from the speed deviation amount calculation means 351._BIASAnd the output 43 a is output to the adder 432. The adder 432 is a control valve opening target value C from the active power controller 10._V0 ^*And the output 43a are added, and the output 43b is output to the prime mover control device 6 as a corrected control valve opening command value.
[0209]
In the control valve opening command correction means 43 having such a configuration, the control valve opening command value deviation amount calculator 431 has a speed deviation amount ω._BIASIs converted into a control valve opening command value deviation amount. Gain is determined by the ratio of speed change and control valve opening change. The primary delay time constant is determined from the delay time from when the control valve opening command value is changed to when the speed is changed.
[0210]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the converter, but when it is detected that the element is in a severe operating state, the prime mover control valve opening command value is corrected and the prime mover Since the torque decreases and the converter current decreases accordingly, the temperature rise of the element is suppressed and the operation can be continued.
[0211]
FIG. 23 is a circuit diagram in which the operating point changing means 140 of FIG.
[0212]
The control state changing means 44 instructs the frequency converter current control device 7 to change the control state when the second element abnormality detection signal 21b is input.
[0213]
In the control state changing means 44 having such a configuration, by changing the set value that determines the control state of the frequency converter current control device 7, the control state is changed without changing the operating point. Change to state.
[0214]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the converter, but if it is detected that the element is in a severe operating state, the frequency converter is changed to a control state that is easy for the element. Therefore, the temperature rise of the element is suppressed and the operation of the converter can be continued.
[0215]
FIG. 24 is a circuit diagram in which the control state changing means 44 in FIG. However, in this configuration, the converter is limited to a self-excited converter.
[0216]
The pulse number reduction means 45 instructs the frequency converter current control device 7 to change the control state when the element abnormality detection signal 21b is input.
[0217]
In the pulse number reducing means 45 having such a configuration, by reducing the switching frequency of the frequency converter 4, it is possible to reduce the loss of the elements of the frequency converter. Therefore, it is easy for the device to operate without changing the operating point.
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter. However, when it is detected that the element is in a severe operating state, the frequency converter 4 is reduced in the number of switching times. By doing so, the operation state is changed to an easy operation state for the element, so that the operation can be continued without damaging the element.
[0218]
FIG. 25 is a circuit diagram in which the pulse number reducing means 45 in FIG.
[0219]
The carrier frequency correcting means 46 includes a frequency divider 461, a changeover switch 462, a forbidden band retention detector 463, and an AND circuit 464.
[0220]
The frequency divider 461 receives the transmission frequency OSC and outputs an output signal 46 a to the changeover switch 462. The forbidden band retention detector 463 has a speed ω and a system frequency f._LAnd the output signal 46 b is output to the AND circuit 464. The AND circuit 464 switches the changeover switch 462 when the AND condition of the element abnormality detection signal 21b and the output signal 46b is satisfied, so that the output signal 46c becomes the signal 46b. The changeover switch 462 outputs the output 46c to the triangular wave generator 79 of the frequency converter 7 as a corrected transmission frequency.
[0221]
In the carrier frequency correcting means 46 having such a configuration, the frequency divider 461 divides the transmission frequency OSC by 1 / n. Forbidden band retention detector 463
| Ω-f_L| <F_BND
In this case, the output signal 46b is set to logic level 1. That is, the output signal 46b becomes logic level 1 when the speed is staying in the prohibited zone. Therefore, when the element abnormality detection signal 21b is detected while the forbidden band stays, the transmission frequency to the triangular wave generator 79 is corrected to the original transmission frequency OSC of 1 / n. As a result, the switching frequency of the element is reduced to 1 / n. The frequency division ratio 1 / n is determined within a range where the control characteristics do not deteriorate.
[0222]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter, but when it is detected that the device is in a severe operating state, the frequency divider uses the frequency divider frequency. Since the number of switching of the frequency converter 7 is reduced, the operation state is changed to an easy operation state for the element, so that the temperature rise of the element is suppressed and the operation of the frequency converter can be continued.
[0223]
Since the frequency of the converter current is small during operation in the forbidden band, the control characteristics do not deteriorate even if the number of times of switching is reduced.
[0224]
FIG. 26 is a circuit diagram in which the pulse number reducing means 45 in FIG.
[0225]
The output voltage correction means 47 receives the output voltage signal v from the voltage calculator 77 of the frequency converter 7._IIs output to the triangular wave generator 78 as an output voltage signal after correcting the output signal 47a.
[0226]
In addition, since this structure has a big effect with respect to a self-excited frequency converter, it demonstrates by the case where it applies to a self-excited frequency converter.
[0227]
In the output voltage correcting means 47 having such a configuration, the self-excited frequency converter generates a gate pulse in accordance with the output voltage, so that the output voltage is corrected so as to substantially reduce the gate pulse. Thus, the switching loss of the element can be reduced.
[0228]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter, but when it is detected that the element is in a severe operating state, the switching loss of the frequency converter 7 is reduced. By doing so, the operation state is changed to an easy operation state for the element, so that the operation can be continued without damaging the element.
[0229]
FIG. 27 is a circuit configuration diagram showing a specific example of the output correction means 47 in FIG.
[0230]
In FIG. 26, the output voltage correction means 48 includes a forbidden band retention detector 481 and a dead band 482.
[0231]
The forbidden band stay detector 481 is the same as the forbidden band stay detector 463 in FIG. The dead band 482 is generated by the output voltage signal v from the output voltage calculator 77 of the frequency converter 7._IIs output to the triangular wave generator 78 as a corrected output voltage signal.
[0232]
This method is effective for the PWM method of triangular wave comparison.
[0233]
The forbidden band retention detector 481 having such a configuration and the output voltage signal v_IBecomes equal to or less than the dead band width, the corrected output voltage signal output to the triangular wave generator 78 becomes zero, and no gate pulse is generated. The dead band width is a value corresponding to the minimum pulse width.
[0234]
In the PWM gate pulse generation method based on the triangular wave comparison used in the self-excited frequency converter, a narrow pulse less than the specified value cannot be generated due to element restrictions, and a gate pulse with a width greater than the specified value must be output. .
[0235]
By the way, since the output voltage of the frequency converter current control device 7 has a high proportion proportional to the output frequency, the output voltage signal becomes small in the vicinity of the forbidden band. Even in this case, pulses having a width equal to or greater than the minimum width are continuously output, and the switching loss tends to increase due to unnecessary pulses in terms of control.
[0236]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter, but if it is detected that the element is in a severe operating state, unnecessary switching for control may be eliminated. Therefore, the loss of the element can be reduced without impairing the control characteristics. Therefore, since the operation state is changed to be easy for the element, the operation can be continued without damaging the element.
[0237]
FIG. 28 is a circuit configuration diagram showing a specific example of the output voltage correcting means in FIG.
[0238]
In FIG. 28, the output voltage correction means 49 includes absolute value detectors 491-R to 491-T, a maximum phase detector 492, a shift amount detector 493, and adders 494-R to 494-T.
[0239]
The absolute value detectors 491-R to 491-T receive the instantaneous currents i-R to i-T of the converter and output outputs 49a-R to 49a-T to the maximum phase detector 492. . Also, the deviation detector 493 outputs an output voltage v._I-R ~ v_I-T and the signal 49b are input, and the output signal 49c is output to the adders 494-R to 494-T. Furthermore, the adders 494-R to 494-T are v_I-R ~ v_I-T and the output 49c of the displacement detector 493 are added, and the outputs 49-R to 49-T are output as corrected output voltages to the gate pulse generator 79 of the frequency converter current control device 7. is there.
[0240]
In the output voltage correcting means 49 having such a configuration, the case where the absolute value 49a-R of the R-phase current of the converter is the maximum will be described. Since 49a-R is the maximum, 49b-R is at logic level 1. Since the deviation amount detector 493 has a logic level 1 of 49b-R, the output voltage v_I−R is the deviation output 49c = v_I-R.
[0241]
In the above description, the R-phase current is the maximum, but 49c is the output voltage signal of the phase with the maximum absolute value of the current. Therefore, the corrected output voltage of the phase with the maximum current absolute value is zero.
[0242]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter, but when it is detected that the element is in a severe operating state, the current is the maximum and the most severe state. Since the output voltage of a phase becomes zero, the switching loss of that phase is reduced, and the converter current is controlled by the line voltage, even if the same amount of deviation is given to all phases, it will affect the current control. Absent. Therefore, the most severe loss of the element can be reduced without impairing the control characteristics, and the operation state can be changed to an easy state for the element.
[0243]
This effect can be further enhanced by using this means together with the configuration shown in FIG.
[0244]
FIG. 29 is a circuit diagram in which the control state changing means 44 in FIG. However, this configuration is limited to a self-excited frequency converter.
[0245]
The link voltage correction means 50 receives an element abnormality detection signal and instructs the frequency converter current control device 7 to change the link voltage.
[0246]
In the self-excited frequency converter, the converter and the inverter are connected via a DC link capacitor, the converter controls the DC link voltage, and the inverter controls the output voltage of the frequency converter. The DC link voltage correction means 50 can increase the voltage setting value used for converter control based on the preset deviation amount by the element abnormality detection signal 21b. As a result, the link voltage increases, and the converter current that realizes the determined active power and reactive power decreases.
[0247]
According to the variable speed control device having such a configuration, it is not necessary to immediately stop the frequency converter, but when it is detected that the element is in a severe operating state, the DC link voltage of the frequency converter 7 is Therefore, the same operating state (active power, reactive power) can be realized with a small converter current. Therefore, by reducing the current, the operation state is changed to an easy operation state for the element, so that the operation can be continued without damaging the element.
[0248]
FIG. 30 is a circuit diagram showing a third embodiment of the variable speed control apparatus according to the present invention. The same components as those in FIG. .
[0249]
In the third embodiment, as shown in FIG. 30, a speed forbidden band avoidance controller 51 is provided instead of the speed forbidden band controller 9 in FIG.
[0250]
FIG. 31 is a circuit configuration diagram showing a first specific example of the speed forbidden band avoidance controller 51.
[0251]
In FIG. 31, the speed forbidden band avoidance controller 51 includes speed forbidden band detecting means 511, speed target value correcting means 512, and speed command value correcting means 513.
[0252]
The speed forbidden band detecting means 511 has a system frequency f_LIs input, forbidden band upper limit speed ω_UAnd forbidden band lower limit speed ω_LIs output to the speed target value correcting means 512. Further, the speed target value correcting means 512 has a speed target value ω.₀ ^*And ω_U, Ω_LIs input, the corrected speed target value ω₁ ^*Is output to the speed command value correcting means 513. Further, the speed command value correcting means 513 outputs the output 51a to the speed command value ω.^*Is output to the speed controller 8.
[0253]
In the speed forbidden band avoidance controller 51 having such a configuration, the forbidden band upper limit speed ω_UAnd forbidden band lower limit speed ω_LAre each obtained by the equation (4). Therefore, as shown by the broken line in FIG. 32, when the system frequency changes, ω_L, Ω_UBoth change. Conventionally, as indicated by the alternate long and short dash line, the frequency is constant even when the system frequency is changed.
[0254]
Further, the speed target value correcting means 512 has a speed target value ω.₀ ^*Is ω_LAnd ω_UEven if it becomes a value between, it is corrected so as not to take a value between them, and the corrected speed target value ω₁ ^*Ask for.
[0255]
Further, the speed command value correcting means 513 is used to correct the corrected speed target value ω.₁ ^*Even if a sudden change occurs, the speed change rate is controlled so that the speed of the wound induction machine can be controlled.
[0256]
According to the variable speed control device having such a configuration, the forbidden band upper limit speed ω_UAnd forbidden band lower limit speed ω_LUnlike the conventional speed forbidden band avoidance control, the speed forbidden band changes when the system frequency fluctuates.
[0257]
Therefore, even if the system frequency fluctuates, the slip frequency, that is, the frequency of the converter does not fall within the forbidden band, so that the device is not severely operated. In addition, since the speed command value does not change suddenly, there is no sudden fluctuation in active power, and the system is not adversely affected.
[0258]
FIG. 33 is a block diagram showing a second specific example of the speed prohibition band avoidance controller shown in FIG.
[0259]
In FIG. 33, the speed prohibition band avoidance controller 52 includes a subtractor 521, an adder 522, a hysteresis function unit 523, and a change rate limiter 524.
[0260]
The subtracter 521 and the adder 522 have a system frequency and a forbidden bandwidth f._BNDIs entered and the forbidden band lower limit speed ω_LAnd forbidden band upper limit speed ω_UIs output to the hysteresis function unit 523. The hysteresis function unit 523 has a speed target value ω.₀ ^*And ω_U, Ω_LIs input, the corrected speed target value ω₁ ^*Is output to the change rate limiter 524. The change rate limiter 524 outputs the output 52a to the speed command value ω.^*Is output to the speed controller 8.
[0261]
In the speed forbidden band avoidance controller 52 configured as described above, the functions of the hysteresis function unit 523 and the change rate limiter 524 are the same as those in FIG.
65 is different from FIG. 65 in that the jump point and the jump point of the hysteresis function unit 523 change due to frequency fluctuation.
[0262]
FIG. 34 shows the speed target value ω.₀ ^*Shows the operation when the system frequency changes while rising at a constant rate of change. In FIG. 32, ω₀ ^*Is a solid line, ω_UAnd ω_LIs a dotted line, ω₁ ^*Is a dashed line, ω^*Is indicated by a broken line.
[0263]
As shown in FIG.₀ ^*Is ω_LTiming t4 when ω and ω₀ ^*Is ω_UDuring the timing t5 exceeding₁ ^*Is ω_LWill be the same. Ω at timing t5₁ ^*Changes in steps, ω₀ ^*Is equal to System frequency and ω₀ ^*Since the change in speed is slow, the speed command value ω is until timing t5.^*Is ω₁ ^*Is almost equal to Ω at timing t5₁ ^*Changes in steps, but ω^*Changes at a predetermined rate of change as shown by a broken line.
[0264]
According to the variable speed control device having such a configuration, as shown in FIG.^*Is in the speed prohibition zone for a short time. Conventionally, if the system frequency fluctuates, there is a possibility that the time for stopping in the forbidden band may become longer, but as shown in FIG. 34, the speed command value ω^*Is limited to a short time of (t6-t5).
[0265]
Therefore, even if the system frequency fluctuates, the slip frequency, that is, the converter frequency does not fall within the forbidden band, so that the device is not operated severely. In addition, since the speed command value does not change suddenly, there is no sudden fluctuation in active power, and the system is not adversely affected.
[0266]
FIG. 35 is a circuit diagram showing a configuration in which a proportional controller 53 is added to the speed forbidden band avoidance controller 51 of FIG. However, the controller 106 of the active power controller 10 is composed of an integral controller and a proportional control activator, and the input shares the control deviation 10e, but the control deviation 10e for integral control._IAnd control deviation 10e for proportional control_PAre separated.
[0267]
The proportional control killer 53 includes a comparator 531 and an analog switch 532. The comparator 531 is an input ω of the hysteresis function unit 523.₀ ^*And output ω₁ ^*And the analog switch 532 is turned on based on the comparison result. The analog switch 532 includes a control deviation 10e for proportional control included in the controller 106 of the active power controller 10._PTo kill.
[0268]
In the proportional controller 53 having such a configuration, the speed target value ω₀ ^*Is in the speed prohibition zone ω₀ ^*And ω₁ ^*Therefore, the comparator 531 turns off the analog switch 532. Therefore, the control deviation 10e for proportional control_PBecomes 0, and the controller 106 performs only integral control.
[0269]
Further, when the controller 106 has proportional control, the speed target value ω is changed by the change of the control deviation 10e.₀ ^*May change beyond the hysteresis width. In this case, ω₁ ^*Is ω_LAnd ω_UIs repeated alternately, and the speed command value ω^*May stay in the speed prohibition zone.
[0270]
According to the variable speed control device having such a configuration, even if the control deviation 10e varies, the integral value of the control deviation 10e₀ ^*Changes so ω^*Ω before the speed cross₀ ^*Can be prevented from changing in the opposite direction. Thereby, the driving | operation within a forbidden zone can be avoided and a severe driving | operation is avoided for an element.
[0271]
FIG. 36 is a circuit diagram showing a configuration in which forbidden band passage waiting means 54 is added to speed forbidden band avoidance controller 51 in FIG.
[0272]
36, the forbidden band passage waiting means 54 includes a high value selector 541, a low value selector 542, comparators 543 and 544, an off-delay timer 545, and analog switches 546, 547, 548 and 549.
[0273]
The high value selector 541 generates a corrected speed target value ω.₁ ^*And forbidden band upper limit speed ω_UIs input, an on / off command 54 a is output to the analog switch 546. The low value selector 542 is ω₁ ^*And forbidden band lower limit speed ω_LIs input, the output signal 54 b is output to the analog switch 547. The comparator 543 is ω₁ ^*And system frequency f_LAre input, the analog switches 546 and 547 are switched. The comparator 544 is ω₁ ^*And speed target value ω₀ ^*Is output to the off-delay timer 545. The off-delay timer 545 switches the analog switches 548 and 549. Analog switch 549 is ω1^*And signals 54a, 54b, ω through analog switches 546, 547, 548, 549.₁ ^*Is selected as signal 54e, which is the second modified speed target value ω.₂ ^*Is input to the speed command value correcting means 513.
[0274]
In the forbidden band passage waiting means 54 having such a configuration, the high value selector 541 has the corrected speed target value ω.₁ ^*And forbidden band upper limit speed ω_UThe higher value is selected as output 54a. The low value selector 542 is used for the corrected speed target value ω.₁ ^*And forbidden band lower limit speed ω_LIs selected as the output 54b. The comparator 543 has a speed command value ω^*When the frequency is above the system frequency, the analog switch 546 is turned on. When the frequency is below the system frequency, the analog switch 547 is turned on. The comparator 544 is ω₀ ^*And ω₁ ^*Output 54d becomes logic level 1 when. The off-delay timer 545 turns on the analog switch 548 when the output 54d is at the logic level 1, and turns on the analog switch 549 after a lapse of a specified time after the output 54d becomes the logic level 0.
[0275]
Next, the operation of the forbidden band passage waiting means 54 will be described with reference to FIG.
[0276]
Speed target value ω₀ ^*After entering the speed prohibition zone, ω₀ ^*Is the system frequency f_LTiming t₀Until
(A): ω₂ ^*= Ω₁ ^*, Ω₁ ^*= Ω_L, 54c = 54b, 54a = ω_U, 54b = ω_L
It has become. Timing t₀To speed target value ω₀ ^*Is forbidden band upper limit speed ω_UUntil timing t1 when
(B): ω₂ ^*= Ω₁ ^*, Ω₁ ^*= Ω_L, 54c = 54a, 54a = ω_U, 54b = ω_L,
It becomes. Speed target value ω at timing t1₀ ^*Is forbidden band upper limit speed ω_UBeyond
(C): ω₂ ^*= 54c, 54c = 54a, 54a = ω₁ ^*, Ω₁ ^*= Ω₀ ^*, 54b = ωL,
It becomes. Thereafter, the speed target value ω before the timing t2 when the off-delay timer 545 returns.₀ ^*Is forbidden band lower limit speed ω_LEven if
(D): ω₂ ^*= 54c, 54c = 54a, 54a = ω_U, 54b = ω₁ ^*, Ω₁ ^*= Ω_L
And ω₂ ^*Is ω_UStop on. Speed target value ω after timing t2₀ ^*After the vehicle goes out of the speed prohibition zone, it returns to normal operation.
[0277]
As described above, after the corrected speed target value passes through the speed prohibition band, the corrected speed target value does not pass through the prohibition band until after the specified time has elapsed.
[0278]
In FIG. 35, when the controller 106 has proportional control, the speed target value ω is changed by the change of the control deviation 10e.₀ ^*May change beyond the forbidden bandwidth. In this case, ω₁ ^*Is ω_LAnd ω_UThe speed command value ω^*May stay in the speed prohibition zone.
[0279]
According to the variable speed control device having such a configuration, the speed command value ω^*After passing the speed forbidden band, it always stops outside the forbidden band for the timer set time or longer. Therefore, since the frequency of forbidden band passage is suppressed, severe operation for the element can be avoided.
[0280]
FIG. 37 is a circuit diagram showing a configuration in which a gate pulse number reducing means 55 including a forbidden band retention detector (comparator) 551 and a gate pulse number reducing means 45 is added to the speed forbidden band avoiding controller 51 in FIG. is there.
[0281]
The forbidden band retention detector 551 has a speed target value ω.₀ ^*And the corrected speed target value ω₁ ^*Enter. The gate pulse number reducing means 45 is the same as that shown in FIG.
[0282]
In the gate pulse number reducing means 55 having such a configuration, the comparator 551 becomes logic level 1 while passing through the speed forbidden band, the gate pulse number reducing means 45 is activated, and the gate pulse of the frequency converter current control device 7 is Reduced.
[0283]
According to the variable speed control device having such a configuration, the gate pulse when passing through the speed forbidden band is reduced. Since the speed forbidden band and the slip frequency forbidden band coincide with each other, the device does not fall into a harsh state when passing through the forbidden band.
[0284]
FIG. 38 is a circuit diagram showing a configuration in which the gate pulse number reducing unit 45 in FIG. 37 is replaced with a current amplitude correcting unit 562.
[0285]
The current amplitude correcting means 562 changes various set values that determine the current amplitude.
[0286]
According to the gate pulse number reducing means 56 having such a configuration, the comparator 551 becomes logic level 1 while passing through the forbidden band, the current amplitude correcting means 562 is activated, and the current of the frequency converter 4 is corrected. However, the amplitude of the converter current is modified so as to reduce the element loss without extending the forbidden band passage time.
[0287]
According to the variable speed control device having such a configuration, the converter current is corrected so as to reduce the loss of the element when passing through the forbidden band. In addition, since the forbidden band passage time is not extended, the device does not fall into a harsh state when passing through the forbidden band.
[0288]
FIG. 39 is a circuit diagram in which the current amplitude correcting unit 562 in FIG. 38 is configured by the reactive current command value correcting unit 57, and has the same configuration as FIG.
[0289]
In the reactive current command value correcting means 57 having such a configuration, the output signal of the comparator 551 becomes a logic level 1 while passing through the speed prohibition band, and the reactive current command value correcting means 571 is activated to activate the frequency converter current control device. 7 is a reactive current set value Id determined in advance.₀₂Reduced to Reactive current set value Id₀₂Is the minimum value required when passing through the speed prohibition zone.
[0290]
According to the variable speed control device having such a configuration, the reactive current command value of the frequency converter current control device 7 is reduced when passing through the forbidden band, so that the current flowing through the element is reduced. In addition, even if the reactive current is reduced, the speed control is not affected, so the forbidden band passage time is not extended. Therefore, the device does not fall into a harsh state when passing through the forbidden band.
[0291]
40 is a circuit configuration diagram of the effective current correcting means 58 showing a specific example of the current amplitude correcting means 562 in FIG.
[0292]
The effective current correction means 58 includes a comparator 581, analog switches 582 and 583, and an adder 584.
[0293]
The comparator 581 is the speed command value ω from the speed prohibition band avoidance controller 51.^*And the system frequency f from the frequency detector 16_LIs entered. The analog switches 582 and 583 are turned on and off in response to a switching command from the comparator 581. When the analog switch 582 is turned on, the signal 58a input to the adder 584 is an increased bias set value Iq.⁺The signal 58a input to the adder 584 when the analog switch 363 is on is the debias setting value Iq.^-It becomes. The adder 584 has a signal 58 a and an effective current command value Iq from the speed controller 8.^*And the output 58b is output to the frequency converter current controller 7 as a corrected effective current command value.
[0294]
In the effective current correcting means 58 having such a configuration, the frequency converter is self-excited, the frequency converter is regenerative operation when the slip frequency is positive, and the frequency converter is power running when the slip frequency is negative. The operation will be described with reference to FIG.
[0295]
The comparator 581^*> F_LThat is, the slip frequency is positive and the analog switch 362 is turned on, and ω^*≦ f_LThat is, the slip frequency is negative and the analog switch 363 is turned on. Therefore, during regenerative operation, the increased bias set value Iq⁺The minute effective current command value increases. Also, during power running, the reduced bias set value Iq^-Minute effective current command value decreases. Accordingly, the time required for passing the forbidden band is almost the same as the case where the above correction is not performed.
[0296]
FIG. 41 shows a path through which an R-phase current flows. That is, at the timing when the effective component current flows from the frequency converter in the direction of the winding induction machine, the current flows through either the GTO-U or the diode DX. The difference between the energization time of GTO-U and the energization time of diode D-X is proportional to the output voltage. Therefore, when the output voltage is positive, that is, during powering operation, the energization time of GTO-U becomes longer, and when the output voltage is negative, that is, during regenerative operation, the energization time of GTO-U becomes shorter. Similarly, when the direction of the effective current is reversed, the energization time of GTO-X becomes longer during power running operation, and the energization time of GTO-X becomes shorter during regenerative operation. In any case, the element loss of the GTO increases during power running.
[0297]
Accordingly, during powering operation in which the element loss increases, the effective current decreases and the loss can be suppressed. Moreover, the time required for passing the forbidden band is almost the same as the case where the above correction is not performed.
[0298]
According to the variable speed control device having such a configuration, it is possible to reduce the loss of the element when passing through the forbidden band, and therefore it is possible to pass through the forbidden band in a control state that is easy for the element. Moreover, the time required for passing through the prohibited zone does not increase.
[0299]
FIG. 42 is a circuit diagram in which the current amplitude correcting means 562 in FIG.
[0300]
In FIG. 42, the forbidden band passage timing controller 59 includes comparators 591 and 592, a phase detector 593, function generators 594 and 595, AND circuits 596 and 597, an increase direction blocker 598 and a decrease direction blocker 599. The
[0301]
The comparators 591 and 592 include a speed target value ω.₀ ^*, And outputs 59a and 59b to AND circuits 596 and 597. The phase detector 593 is an instantaneous value i of the converter current._I-R, i_I-S, i_IWhen -T is input, the output signal θ is output to the function generators 594 and 595. The function generators 594 and 595 output the output signals 59c and 59d to the AND circuits 596 and 597. When the control deviation 10e of the active power controller 10 is input, the increase direction blocker 598 and the decrease direction blocker 599 output their output signals to the controller 106. However, when the output signals 59e and 59f of the AND circuits 596 and 597 are at the logic level 1, the increase direction blocking and the decrease direction blocking means act respectively.
[0302]
In the forbidden band passage timing controller having such a configuration, the comparator 591 has a speed target value ω.₀ ^*From ωU-Δω to ω_UIs at logic level 1 and the comparator 592₀ ^*Is ω_LTo ω_LLogic level 1 when in the range of + Δω. The phase detector 593 obtains the phase θ of the current vector based on the R phase from the three-phase current. The function generator 594 is at a logic level 1 when θ is θ1 to θ2, or 120 ° + θ1 to 120 ° + θ2, or 240 ° + θ1 to 240 ° + θ2. Similarly, the function generator 595 has a logic level 1 between θ between −θ1 and −θ2, or between − (120 ° + θ1) and − (120 ° + θ2), or between − (240 ° + θ1) and − (240 ° + θ2). Become. However, a phase between θ1 and θ2 is an unfavorable phase for starting the forbidden band passage.
[0303]
When the output signal 59e of the AND circuit 596 is at logic level 1, the increase direction blocking means is active, and when the output signal 59f of the AND circuit 597 is at logic level 1, the decrease direction blocking means is activated. That is
If 59e = 1, 10e> 0, 59g = 0
If 59e = 1, 10e ≦ 0, 59g = 10e
When 59f = 1, 10e ≧ 0, 59g = 10e
59g = 0 for 59f = 1, 10e <0
59e = 0, 59f-0, 59g = 10e
It becomes.
[0304]
Next, the speed target value ω₀ ^*Will be described in the speed-up direction, i.e. 10e positive, passing through the forbidden band. ω₀ ^*Is ω_USince the output signals 59a and 59e are at logic level 0 until -Δω, ω₀ ^*Normally rises but ω_UWhen -Δω is reached, if the phase is not favorable for the start of forbidden band passage, 59e becomes logic level 1 and ω₀ ^*Is ω_UStop at -Δω. When the phase of the converter current advances and 59c returns to logic level 0, the output signal 59e returns and ω₀ ^*Rises to ω_UTo. Therefore, the corrected current target value ω₁ ^*Becomes ωU, and the current command value ω^*Begins to rise.
[0305]
As described above, when passing through the forbidden band, the passage start, that is, ω^*The phase of the current vector when starting to rise is controlled to a preferred value.
[0306]
In the forbidden band passage timing controller 59 having such a configuration, the rate of change when the forbidden band passes is constant, and the phase θ when the forbidden band lower limit speed is passed is used as a parameter. An example is shown in FIG. However, timings t1 and t2 are timings when the speed target value passes the forbidden band lower limit speed and the forbidden band upper limit speed. It can be seen that the current waveform during passage of the forbidden band differs depending on the phase during passage of the forbidden band lower limit speed. From the viewpoint of the element that flows the R-phase positive current, θ_IIt can be seen that the energization area increases with increasing from -30 °. From the above, it can be seen that the current area during passage of the forbidden band can be reduced by appropriately selecting the phase of the current vector at the start of the forbidden band passage.
[0307]
According to the variable speed control device having such a configuration, the current area during the passage of the forbidden band can be reduced by appropriately selecting the phase of the current at the start of the forbidden band passage. Therefore, since the converter current when passing through the forbidden band is reduced, the current flowing through the element is reduced, and it is possible to avoid a harsh state for the element when passing through the forbidden band.
[0308]
FIG. 44 is a circuit diagram in which the current amplitude correcting means 562 in FIG.
[0309]
The tap raising command calculator 60 receives the forbidden band detection signal 56a and outputs the tap raising command value 60a to a main transformer tap controller (not shown).
[0310]
In such a configuration, the comparator 561 becomes logic level 1 while passing through the forbidden band, and the tap raising command calculator 60 raises the tap of the main transformer via the main transformer tap controller.
[0311]
According to the variable speed control device having such a configuration, the tap of the main transformer is raised prior to passing through the forbidden band, and the current of the frequency converter 7 is reduced. Therefore, the device is in a comfortable state when passing through the forbidden band.
[0312]
FIG. 45 is a circuit diagram in which the current amplitude correcting means 562 in FIG. 38 is constituted by a DC link voltage correcting means 61 of a self-excited frequency converter.
[0313]
In such a configuration, when the speed target value enters the speed prohibition band, the DC link voltage set value is increased by converter control. Since the speed command value passes through the speed forbidden band after the speed target value has passed through the speed forbidden band, the control for increasing the DC link voltage by the converter is completed at this time. For this reason, even if it is the same active power, the primary current of a winding induction machine becomes small. As a result, the converter current also decreases.
[0314]
Therefore, the loss of the element when passing through the forbidden band is reduced, and it is possible to avoid a severe operating state for the element. In addition, there is an effect that can be realized without changing the time required for passing the forbidden band.
[0315]
FIG. 46 is a circuit configuration diagram in which the current amplitude correcting means 562 in FIG. 38 is replaced with a prime mover torque correcting means 62.
[0316]
The prime mover torque correction means 62 includes a comparator 621 and changeover switches 622 and 623.
[0317]
The changeover switch 622 is changed over by a comparator 621, and the changeover switch 623 is changed over by a forbidden band detection signal 56a. The input signal 62b of the changeover switch 622 is a control valve opening command value for obtaining a prime mover torque that is easy for the converter current when passing through the forbidden band in the speed increasing direction. The input signal 62b is a control valve opening command value for obtaining a motor torque that is easy for the converter current when passing through the forbidden band in the descending direction.
[0318]
In the prime mover torque correcting means 62 having such a configuration, the comparator 621 includes a speed target value ω.₀ ^*62a is selected as the output signal 62c of the changeover switch 622 when the reference synchronization speed is below the reference synchronization speed, and 62b is selected above the reference synchronization speed. Prior to passing the forbidden band, 62c is selected for the changeover switch 623 by the forbidden band detection signal 56a. This reduces the prime mover torque and consequently the converter current.
[0319]
According to the variable speed control device having such a configuration, the current in the frequency converter 7 is reduced prior to passing through the forbidden band. Therefore, the loss of the element at the time of passing through the forbidden band is reduced, and it is possible to avoid a harsh operating state for the element, and also to be realized without changing the time required for passing through the forbidden band.
[0320]
FIG. 47 is a circuit configuration diagram in which a fluctuation suppressor 63 is added to the speed prohibition band avoidance controller 51 shown in FIG.
[0321]
In FIG. 47, the fluctuation suppressor 63 is constituted by a comparator 631 and fluctuation removal means 632.
[0322]
The comparator 431 receives the ω from the active power controller 10.₀ ^*And the speed command value ω from the speed prohibition band avoidance controller 51^*Is input to the active power controller 11 via the fluctuation removal means 632.
[0323]
In the fluctuation suppressor 63 having such a configuration, the output signal 63a of the comparator 631 becomes the logic level 1 during the forbidden band avoidance control. The fluctuation active removal capability 632 removes the fluctuation of the active power controller 11 when the output signal 63 a is logic level 1.
[0324]
According to the variable speed control device having such a configuration, when the speed target value enters the speed forbidden band, the fluctuation of the speed target value is suppressed, so the frequency of the speed target value passing through the speed forbidden band is suppressed. Since the frequency of forbidden band passing, which is a severe operating state for the element, is suppressed, it is possible to avoid a severe operating state for the element.
[0325]
FIG. 48 is a circuit diagram showing a first example in which the fluctuation suppressor 63 in FIG.
[0326]
In FIG. 48, the output 10 b of the settling rate calculator 102 in the active power controller 10 is input to the adder 101 via the analog switch 64.
[0327]
In such a configuration, when the speed target value enters the speed prohibition band, the analog switch 64 is opened by the switching command 56a from the prohibition band retention detector 551 to lock the governor-free control component, and the speed target based on the governor-free control component. Since the fluctuation of the value is suppressed, the frequency with which the speed target value passes the speed prohibition zone is suppressed.
[0328]
Therefore, since the frequency of forbidden band passing, which is a severe operating state for the element, is suppressed, it is possible to avoid falling into a severe operating state for the element.
[0329]
FIG. 49 is a circuit diagram showing a second example in which the fluctuation suppressor 63 in FIG.
[0330]
In FIG. 49, the output 10 c of the limiter 103 in the active power controller 10 is input to the adder 101.
[0331]
In such a configuration, when the speed target value enters the speed prohibition band, the analog switch 64 is opened by the switching command 56a from the prohibition band retention detector 551, the AFC control component is locked, and the speed target value of the AFC control component is set. The fluctuation is suppressed.
[0332]
Therefore, since the frequency of forbidden band passing, which is a severe operating state for the element, is suppressed, it is possible to avoid falling into a severe operating state for the element.
[0333]
FIG. 50 is a circuit diagram in which the fluctuation suppressor 63 in FIG. 47 includes a low-pass filter 661, a comparator 662, and a changeover switch 663.
[0334]
The low-pass filter 661 receives the ω from the active power controller 10.₀ ^*Is input, the fluctuation component of the speed target value is suppressed. The comparator 662 receives the ω from the active power controller 10.₀ ^*And ω from the speed forbidden band avoidance controller 51^*And the changeover switch 663 selects the output of the low-pass filter 661 and inputs it to the speed controller 8 during the prohibited band avoidance control.
[0335]
According to the variable speed control device having such a configuration, when the speed target value enters the speed prohibition band, the low-pass filter suppresses the fast fluctuation component included in the speed target value, so that the speed target value passes through the speed prohibition band. The frequency of performing is suppressed. Therefore, since the frequency of forbidden band passing, which is a severe operating state for the element, is suppressed, it is possible to avoid a severe operating state for the element.
[0336]
FIG. 51 is a circuit diagram showing a fourth embodiment of the variable speed control apparatus according to the present invention. The same reference numerals are given to the same components as those in FIG. 62, and the description thereof will be omitted. Different parts will be described here. .
[0337]
In the fourth embodiment, as shown in FIG. 51, the speed forbidden band controller 9 and the speed controller 8 in FIG. 62 are replaced with a slip frequency forbidden band avoiding controller 67 and a slip frequency controller 18, respectively. .
[0338]
FIG. 52 is a circuit configuration diagram showing a specific example of the slip frequency forbidden band avoidance controller 67 and the slip frequency controller 18.
[0339]
52, the slip frequency forbidden band avoidance controller 67 includes a slip frequency target value calculator 671, a slip frequency target value correcting means 672, and a slip frequency command value calculator 673.
[0340]
The slip frequency target value calculator 671 has a speed target value ω.₀ ^*Is input, the output signal S₀ ^*Is output to the slip frequency target value correcting means 672. Output signal S of slip frequency target value correcting means 672₁ ^*Is a slip frequency command value S via a slip frequency command value calculator 673.^*Is output to the slip frequency controller 18.
[0341]
The slip frequency controller 18 includes a slip frequency detecting means 181, a subtractor 182, and a controller 183.
[0342]
The slip frequency detecting means 181 detects the slip S from the speed, the system frequency, the phase reference in the frequency converter current control, etc., but this configuration does not depend on the detection method. The subtractor 182 is S^*When S and S are input, an output signal 18 a is output to the controller 183.
[0343]
In the variable speed control device having such a configuration, each signal S of the slip frequency target value calculator 67 is obtained.₀ ^*, S₁ ^*, S^*Each has the meaning of a slip frequency target value, a corrected slip target value, and a slip frequency command value. Corrected slip target value S₁ ^*Is determined not to fall within the slip frequency band.
[0344]
However, the slip frequency forbidden band is forbidden width f_BNDAnd is not affected by the system frequency. -F_BNDTo f_BNDBetween is a forbidden zone. Corrected slip target value S₁ ^*In accordance with the slip frequency command value S^*Since the slip frequency S is controlled, the slip frequency S does not enter the slip frequency forbidden band. Since the slip frequency S is the frequency itself of the frequency converter 4, the element becomes severe -f_BNDTo f_BNDDriving at low frequencies during is avoided.
[0345]
According to the variable speed control device having such a configuration, when the system frequency fluctuates in the past, there is a possibility that the time for stopping in the forbidden band may become longer, but the slip frequency command value S^*However, the time during which the slip frequency stays in the forbidden frequency band is limited to a short time. Further, since the minor loop of the active power control is the slip frequency control, the slip frequency can be directly controlled, and the slip frequency forbidden band avoidance control is not affected by the fluctuation of the system frequency. Therefore, operation at a low frequency, which is a severe operation state for the element, can be surely avoided.
[0346]
FIG. 53 is a circuit configuration diagram showing a specific example of the slip frequency forbidden band avoidance controller of FIG.
[0347]
In FIG. 53, the slip frequency forbidden band avoidance controller 68 includes a subtractor 681, a hysteresis function unit 682, and a change rate limiter 683.
[0348]
The subtractor 681 generates a speed target value ω₀ ^*When the system frequency is input, the output 68a of the slip frequency target value S₀ ^*To the hysteresis function unit 682. The hysteresis function unit 682 converts the output 68b to the corrected slip frequency target value S.₁ ^*As a change rate limiter 683. The change rate limiter 683 slides the output 68c to the slip frequency command value S.^*Is output to the slip frequency controller 18.
[0349]
The jump point and the jump point of the hysteresis function device 682 are the forbidden band width f._BNDF determined by_BND, -F_BNDbecome. Others are the same as FIG.
[0350]
According to the variable speed control device having the above-described configuration, the slip frequency target value is corrected by the hysteresis function so as not to enter the slip frequency prohibition band, the slip frequency command value is determined from the corrected slip frequency target value, and the slip frequency is determined. Since it passes in a short time without staying in the prohibited zone, the same effect as in FIG. 51 can be obtained. Further, since it is not necessary to use the system frequency for the hysteresis function, it can be realized with a simple function.
[0351]
54 is a circuit configuration diagram in which a proportional control activator 69 is added to the slip frequency forbidden band avoidance controller 68 of FIG. However, the controller 106 of the active power controller 10 includes an integral controller and a proportional controller, and a control deviation 10e for integral control._IAnd control deviation 10e for proportional control_PAre separated.
[0352]
The comparator 691 has an input S of the hysteresis function unit 682.₀ ^*And output S₁ ^*And the analog switch 692 is turned on based on the comparison result. The analog switch 692 is a control deviation 10e for proportional control included in the controller 106 of the active power controller 10._PTo kill.
[0353]
In the slip frequency forbidden band avoidance controller 68 configured as described above, the slip frequency target value S₀ ^*Is in the slip band forbidden band, S₀ ^*And S₁ ^*Therefore, the comparator 691 turns off the analog switch 692. Therefore, the control deviation 10e for proportional control_PBecomes 0, and the controller 106 performs only integral control.
[0354]
Therefore, if the controller 106 has proportional control, the slip frequency target value S is changed by the change of the control deviation 10e.₀ ^*May change beyond the hysteresis width. In this case, S₁ ^*-F_BNDAnd f_BNDThe slip frequency command value S will be repeated alternately.^*May stay in the prohibited zone.
[0355]
According to such a variable speed control device, even if the control deviation 10e varies, the integral value of the control deviation 10e is S.₀ ^*Changes so S^*Before crossing the forbidden band₀ ^*Can be prevented from changing in the opposite direction. Thereby, the driving | operation within a forbidden zone can be avoided and a severe driving | operation is avoided for an element.
[0356]
FIG. 55 is a circuit configuration diagram in which forbidden band passage waiting means 70 is added to the slip frequency forbidden band avoidance controller 67 in FIG.
[0357]
In FIG. 55, the forbidden band passage waiting means 70 comprises a high value selector 701, a low value selector 702, comparators 703 and 704, an off-delay timer 705, and analog switches 706, 707, 708, and 709. .
[0358]
The high value selector 701 includes the corrected slip frequency target value S.₁ ^*And the forbidden bandwidth are input, the output 70 a is output to the analog switch 706. Low value selector 702 is S₁ ^*And the forbidden bandwidth are input, the output 70 b is output to the analog switch 707. Comparator 703 has S₁ ^*And system frequency f_LIs input, the analog switches 570 and 707 are switched.
[0359]
Further, the comparator 704 has S₁ ^*Slip frequency target value S₀ ^*Is input to the off-delay timer 705. The off-delay timer 705 switches the analog switches 708 and 709.
[0360]
Furthermore, the analog switch 709 is S₁ ^*And signals 70a, 70b, S via analog switches 706, 707, 708, 709.₁ ^*Is selected as signal 70e, which is the second corrected speed target value S.₂ ^*Is input to the slip frequency command value correcting means 673.
[0361]
The forbidden band passage waiting means 70 having such a configuration does not allow the abnormal slip frequency target value to be a value within the forbidden band for a certain period of time after the slip frequency target value has entered the forbidden band. For this reason, the frequency of the converter current does not repeatedly pass through the forbidden band in a short time, and therefore, it is possible to avoid a severe operating state for the element as in the forbidden band waiting means of FIG.
[0362]
【The invention's effect】
As described above, according to the present invention, when the device is in a severe operating state, the load on the device can be reduced, and the system frequency can be changed without increasing the capacity of the frequency converter. Even so, it is possible to avoid damage to the elements of the converter, and further to provide a variable speed control device that can lighten the burden on the elements when passing through the forbidden band.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a first embodiment of a variable speed control apparatus according to the present invention.
FIG. 2 is a circuit configuration diagram showing a first specific example of the element temperature abnormality detection device according to the embodiment;
FIG. 3 is a circuit configuration diagram showing a second specific example of the element temperature abnormality detection device according to the embodiment;
FIG. 4 is a circuit configuration diagram showing a third specific example of the element temperature abnormality detection device according to the embodiment;
FIG. 5 is a circuit configuration diagram showing a fourth specific example of the element temperature abnormality detection device according to the embodiment;
FIG. 6 is a circuit configuration diagram showing a fifth specific example of the element temperature abnormality detection device according to the embodiment;
FIG. 7 is a circuit configuration diagram showing a first specific example of the element abnormality detection device according to the embodiment;
FIG. 8 is a circuit configuration diagram showing a second specific example of the element abnormality detection device according to the embodiment;
FIG. 9 is a circuit configuration diagram showing a third specific example of the element abnormality detection device according to the embodiment;
FIG. 10 is a circuit configuration diagram showing a fourth specific example of the element abnormality detection device according to the embodiment;
FIG. 11 is a circuit configuration diagram showing a fifth specific example of the element abnormality detection device according to the embodiment;
FIG. 12 is a circuit configuration diagram showing a sixth specific example of the element abnormality detection device according to the embodiment;
FIG. 13 is a circuit configuration diagram showing a second embodiment of a variable speed control device according to the present invention.
FIG. 14 is a circuit configuration diagram showing a first specific example of the speed change device according to the embodiment;
FIG. 15 is a circuit configuration diagram showing a second specific example of the speed change device according to the embodiment;
FIG. 16 is a circuit configuration diagram showing a third specific example of the speed change device according to the embodiment;
17 is a circuit diagram showing another configuration example of the speed deviation amount calculation means in FIG. 14;
18 is a circuit diagram showing a configuration example when a speed target value tracking device is added to the speed changing device shown in FIG. 14 as the operating point changing means of FIG. 13;
19 is a circuit diagram showing a configuration example of a speed changing device in which the speed command value correcting means in FIG. 14 is replaced with an active power set value correcting means.
20 is a circuit diagram showing a configuration example in which the operating point changing unit in FIG. 13 is replaced with a reactive current command value correcting unit.
FIG. 21 is a circuit diagram showing a configuration example in the case where voltage set value tracking means is added to the active power set value correcting means shown in FIG. 19;
22 is a circuit diagram showing a configuration example in which the speed command value correcting means in FIG. 14 is replaced with a control valve opening command value correcting means.
FIG. 23 is a circuit diagram in which the operating point changing means of FIG. 13 is configured by control state changing means.
24 is a circuit diagram in which the control state changing means in FIG. 23 is constituted by pulse number reducing means.
25 is a circuit diagram in which the pulse number reduction means in FIG. 24 is configured by carrier frequency correction means.
26 is a circuit diagram in which the pulse number reducing means in FIG. 24 is configured by output voltage correcting means.
FIG. 27 is a circuit configuration diagram showing a specific example of output correction means in FIG. 26;
28 is a circuit configuration diagram showing a specific example of output voltage correction means in FIG.
29 is a circuit diagram in which the control state changing unit in FIG. 23 is configured by a DC link voltage correcting unit.
FIG. 30 is a circuit configuration diagram showing a third embodiment of a variable speed control apparatus according to the present invention.
FIG. 31 is a circuit configuration diagram showing a first specific example of a speed prohibition band avoidance controller according to the embodiment;
FIG. 32 shows the movement of the system frequency and the forbidden band upper limit speed ω in the speed forbidden band avoidance controller._UAnd forbidden band lower limit speed ω_LAnd relationship diagram.
FIG. 33 is a circuit configuration diagram showing a first specific example of a speed prohibition band avoidance controller according to the embodiment;
FIG. 34 shows a speed target value ω in the speed band prohibition controller.₀ ^*Explanatory drawing of operation | movement in case system | strain frequency changes while rising at a fixed change rate.
FIG. 35 is a circuit diagram showing a configuration in which a proportional controller is added to the speed forbidden band avoidance controller in the same embodiment;
FIG. 36 is a circuit diagram showing a configuration in which a prohibition passage waiting unit is added to the speed prohibition band avoidance controller according to the embodiment;
FIG. 37 is a circuit diagram showing a configuration in which gate pulse number reduction means is added to the speed forbidden band avoidance controller in FIG. 31;
38 is a circuit diagram showing a configuration in which the gate pulse number reducing means in FIG. 37 is replaced with current amplitude correcting means.
39 is a circuit diagram in which the current amplitude correcting means in FIG. 38 is configured by reactive current command value correcting means.
40 is a circuit configuration diagram of effective current correcting means showing a specific example of current amplitude correcting means in FIG. 38;
FIG. 41 is a diagram showing a path when the effective current flows in the R phase of the frequency converter in the effective current correction of FIG. 40;
42 is a circuit diagram in which the current amplitude correcting means in FIG. 38 is configured by a forbidden band passage timing controller.
FIG. 43 is a diagram showing an example of an R-phase current when passing through the forbidden band, with the phase θ when passing through the forbidden band lower limit speed as a parameter in the forbidden band passing timing controller of FIG. 42;
44 is a circuit diagram in which the current amplitude correcting means in FIG. 38 is configured by a tap-up command calculator.
45 is a circuit diagram in which the current amplitude correcting means in FIG. 38 is configured by DC link voltage correcting means of a self-excited frequency converter.
46 is a circuit configuration diagram in which the current amplitude correcting means in FIG. 38 is replaced with prime mover torque correcting means.
47 is a circuit configuration diagram in which a fluctuation suppressor is added to the speed forbidden band avoidance controller shown in FIG. 31. FIG.
48 is a circuit diagram showing a first example in which the fluctuation suppressor in FIG. 47 is configured by an analog switch.
FIG. 49 is a circuit diagram showing a second example in which the fluctuation suppressor in FIG. 47 is configured by an analog switch.
FIG. 50 is a circuit diagram in which the fluctuation suppressor in FIG. 47 is configured by a low-pass filter, a comparator, and a changeover switch.
FIG. 51 is a circuit configuration diagram showing a fourth embodiment of a variable speed control device according to the present invention;
FIG. 52 is a circuit configuration diagram showing a specific example of a slip frequency forbidden band avoidance controller and a slip frequency controller in the same embodiment;
FIG. 53 is a circuit configuration diagram showing a specific example of a slip frequency forbidden band avoidance controller according to the embodiment;
54 is a circuit configuration diagram in which a proportional control activator is added to the slip frequency forbidden band avoidance controller in FIG. 53;
FIG. 55 is a circuit configuration diagram in which forbidden band passage waiting means is added to the slip frequency forbidden band avoidance controller in the same embodiment;
FIG. 56 is a circuit diagram showing a configuration example of a control device of a conventional variable speed power generation system.
57 is a circuit configuration diagram showing details of the frequency converter current control device shown in FIG. 56. FIG.
58 is a circuit configuration diagram of a speed controller in the frequency converter current control device of FIG. 57. FIG.
59 is a circuit configuration diagram showing details of an active power controller in FIG. 56. FIG.
60 is a circuit configuration diagram showing details of the voltage controller shown in FIG. 56. FIG.
61 is a waveform diagram of a current flowing through the frequency converter in the control device. FIG.
FIG. 62 is a circuit configuration diagram showing another conventional variable speed power generation system control device.
FIG. 63 is a circuit diagram showing a configuration example of a speed prohibition band avoidance controller in the control device of the same system;
FIG. 64 is a view showing a characteristic of a speed command value in the control device of the system.
FIG. 65 shows a target speed value ω in the control device of the system.₀ ^*And speed command value ω^*Explanatory drawing about control of.
[Explanation of symbols]
1 ... Winding induction machine
2 ... Generator breaker
3 ... Main transformer
4 ... Frequency converter
5 ... prime mover
6 ... Motor controller
7. Frequency converter current control device
8 ... Speed controller
10 ... Active power control device
11 ... Voltage controller
12 ... Voltage detector
13 ... Phase detector
14 ... Current detector
15. Speed detector
16: Frequency detector
17 ... Active power detector
21 ... Element abnormality detection means
23-27 ... Element temperature abnormality detection device
28-33 ... Element abnormality detection device
140: Driving point changing means
35-37 ... Speed change device
38 ... Speed deviation amount calculating means
39 ... Speed target value tracking device
40 ... Active power set value correction means
42 ... Voltage set value following means
43 ... Control valve opening command value correction means
44. Control state changing means
45. Means for reducing the number of pulses
46. Carrier frequency correction means
47-49 ... Output voltage correction means
50. DC link voltage correction means
51, 52 ... Speed prohibition zone avoidance controller
54 ... Forbidden band passage waiting means
55, 56 ... Gate pulse reduction means
57 ... Reactive current command value correction means
58. Effective current correction means
59 ... Forbidden band passage timing controller
60 ... Tap-up command calculator
61 ... DC link voltage correction means
62 ... Motor torque correcting means
63 ... Fluctuation suppressor
64, 65 ... Analog switches
67 ... Slip frequency forbidden band avoidance controller
68 ... Proportional control active killer
70: Means for waiting for forbidden band passage

Claims (3)

It is possible to connect the primary side of the winding induction machine, which is axially coupled to the prime mover, to the system via the main transformer and generator-side circuit breaker, and to connect the frequency converter controlled by the current controller on the secondary side. In a variable speed control device for controlling a transmission system,
When detecting that the element of the frequency converter is in a thermally severe state, comprising an element abnormality detecting means for outputting a stop signal to stop the frequency converter,
The element abnormality detecting means includes a temperature detector that detects the temperature of the heat dissipation fin of each element, a temperature detector of cooling water that cools the frequency converter, a temperature of the heat dissipation fin of the element, and a temperature of the cooling water. A temperature estimator that estimates the temperature of the element, a comparator that compares the estimated temperature value of each element with a specified value, and a stop signal to the frequency converter when the estimated temperature value of any element exceeds the specified value A variable speed control device comprising an OR circuit that outputs Connect the primary side of the winding induction machine, which is axially coupled to the prime mover, to the system via the main transformer and generator-side circuit breaker, and connect the self-excited frequency converter controlled by the current controller to the secondary side. In a variable speed control device for controlling a variable speed system,
An element abnormality detecting means for stopping the self-excited frequency converter by outputting a stop signal when detecting that the element of the self-excited frequency converter is in a thermally severe state;
The element abnormality detection means counts a gate pulse output from the converter current control device and when the converter current is positive and a gate pulse when the converter current is negative, and each half wave thereof is counted. A variable speed control device comprising: positive side and negative side gate pulse number counters that detect the element abnormality based on an integrated value of the number of gate pulses and output a stop signal to the self-excited frequency converter . It is possible to connect the primary side of the winding induction machine, which is axially coupled to the prime mover, to the system via the main transformer and generator-side circuit breaker, and to connect the frequency converter controlled by the current controller on the secondary side. In a variable speed control device for controlling a transmission system,
Speed target value correction means for correcting the speed target value so that the speed target value does not enter the speed prohibition band determined by the system frequency and the prohibition band width, and the speed command value from the speed target value corrected by the speed target value correction means. A variable speed control device comprising: a speed forbidden band avoidance controller comprising means for calculating; and a fluctuation suppressing means for suppressing fluctuation of the speed target value when the speed target value enters the speed forbidden band .

Images