JP4568599B2 - Logic circuit dividing method and apparatus - Google Patents

Description

  The present invention relates to a logic circuit dividing method and apparatus, and more particularly, when a logic circuit formed for each functional block is realized by a plurality of FPGAs / PLDs, etc., a dividing program based on the logic synthesis and layout results of each block Thus, the present invention relates to a logic circuit dividing method and apparatus for optimally allocating a circuit to each FPGA / PLD.

  In LSI development, a development flow for converting to ASIC at the time of mass production using FPGA / PLD or the like as a prototype until logic verification is widely adopted, and is increasing. Here, FPGA is Field Programmable Gate Array (Large Scale PLD), PLD is Programmable Logic Device (LSI that can program logic circuit at hand), and ASIC is for Application Specific Integrated Integrated Integration Circuit).

  However, in order to realize an ASIC logic circuit as a SoC (System on a Chip), several to several tens of FPGAs / PLDs are required, and a lot of man-hours are spent on the division work. The reason for this is that the use of internal resources such as the circuit scale and the number of pins used for each device is limited, making it increasingly difficult to optimally select the device and number of devices used by the user. .

  As a conventional system of this type, a graph is generated by reading RTL, a partial circuit is selected, an adjacent node is divided, a new circuit part is generated, a generated circuit component, a new circuit part Is known (see, for example, Patent Document 1). There is also known a logic circuit simulation system that performs simulation by mapping a plurality of types of logic circuits such as RTL to a programmable gate array such as an FPGA (see, for example, Patent Document 2).

Also, a logic analyzer that takes into account design efficiency and operation timing when assigning a large-scale ASIC or electronic circuit of a logic device to a plurality of programmable chips is known (for example, see Patent Document 3). Also known is an integrated circuit design apparatus and design method for designing layout of an integrated circuit after inputting logic circuit connection information and performing logic verification of the connection information (see, for example, Patent Document 4).
JP 2000-222442 (paragraphs 0025 to 0030, FIGS. 1 to 3) JP 2004-70658 A (paragraphs 0018 to 0029, FIG. 1) Japanese Patent No. 3184420 (paragraphs 0014 to 0027, FIGS. 1 to 3) JP-A-9-138817 (paragraphs 0012 to 0019, FIGS. 1 and 2)

  In the conventional technique, when a division operation is performed using a net list after logic synthesis (Net List: data in which circuit connection states are expressed by cells such as AND and OR) as input data, if a circuit change occurs, the effect is There is a problem that the influence of the change is large because the corresponding block covers a plurality of blocks. Further, when dividing work using existing circuits, a recent high-speed large-scale circuit has a problem that a difference from an estimated value is large in terms of performance in actual layout.

  Due to these problems, a large number of return man-hours occur, and therefore, an increase in TAT (Turn Around Time: time required for obtaining a result of requested processing) of SoC development is a problem.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a logic circuit dividing method and apparatus capable of reducing the number of man-hours to return.

  Note that RTL (Register Transfer Level: level of circuit design expressed by operation between registers) of a logic circuit is described for each functional block. Then, by dividing the RTL as input data, when a circuit change occurs, it becomes easy to identify the corresponding block, and the influence of the change can be minimized. Also, by logically synthesizing and laying out the RTL in advance and creating a database of all block information, the accuracy of estimation can be improved and the difference from the actual layout can be reduced.

(1) According to the first aspect of the present invention, the logic circuit is divided in the logic synthesis layout unit by receiving the RTL and the device of the logic circuit and the setting file for setting the number of devices and the operation speed of the device as input data. Logic synthesis and layout are performed for each block, and logic circuit information, which is the result data of logic synthesis and layout, is stored in a database. The logic circuit information stored in the database, the number of input device pins, and the device Based on the number, the usage rate of the device, and the I / O , the logic circuit program is used to distribute the blocks obtained by dividing the logic circuit into a plurality of FPGAs or PLDs.

(2) The invention described in claim 2 is characterized in that priorities are assigned in advance to the blocks, and division is performed based on the priorities .
(3) The invention according to claim 3 is characterized in that, when the division is performed, the division is performed on each FPGA or PLD in descending order of usage rate of each block . Here, the usage rate indicates a ratio when the usage amount of the device is 100%.

( 4 ) The invention described in claim 4 is an input data section for inputting RTL, setting the number of devices and the operation speed of the device, and a database creating section for receiving the output of the input data section and creating a database. When a database created by the database creation unit, and a database storage unit for storing in the database a logic circuit information which is the result data of the logic synthesis and layout, and logic circuit information stored in said database, entered A division processing unit for allocating blocks obtained by dividing a logic circuit into a plurality of FPGAs or PLDs using a logic circuit program based on the number of device pins, the number of devices, the device usage rate, and I / O ; And a result data part for storing the result data in response to the output of the division processing part.

(6) Further, according to the present invention, when the division is performed, the division is performed for each FPGA / PLD in order from the lowest usage rate of each block.
(7) Further, the present invention is characterized in that, in the case of performing the division, if the usage rate of a certain block exceeds the usage rate of each FPGA / PLD to be divided, the corresponding block is hierarchically expanded and divided. To do.

(8) Further, the present invention is characterized in that the division is performed by setting an arbitrary upper limit value for the usage rate of the input / output pins / used devices.
(9) Further, the present invention is characterized in that, in the case of performing the division, the input / output pins are duplicated and deleted in consideration of branching of the output signal.

  (10) Further, the present invention is characterized in that, when the division is performed, if the performance cannot be satisfied, the RTL correction is notified.

(1) According to the first aspect of the invention, more accurate division can be performed .

( 2 ) According to the invention described in claim 2 , the division intended by the user can be made possible.
( 3 ) According to the invention described in claim 3 , it is possible to improve the processing speed due to the law.

( 4 ) According to the invention described in claim 4, it is possible to perform more accurate division.
(6) Further, according to the present invention, it is possible to improve the processing speed due to the law.

(7) Further, according to the present invention, it is possible to improve the processing speed due to the law and to divide the circuit into an optimum circuit scale.
(8) Further, according to the present invention, adaptation to specifications intended by the user can be facilitated.

(9) Further, according to the present invention, it is possible to effectively use pins and improve speed (reduction in delay due to an increase in fan-out).
(10) Further, according to the present invention, it is possible to improve processing speed and user convenience (determination of feasibility).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of a logic circuit which is input data of the present invention. The logic circuit (Func Top) is composed of each block (Func), and the connection between the blocks is described in the TOP RTL. Then, connection data used for the division work is extracted from the RTL. The logic circuit information of block 1 (Func 1), block 2 (Func 2), and block 3 (Func 3) is described in RTL1, RTL2, and RTL3, respectively. LVi in each block (i is an arbitrary integer) indicates a level. This level LVi represents the level of description and is represented by a tree structure.

  Using this RTL, logic synthesis and layout are performed, and logic synthesis / layout data used for division work is extracted. In the configuration of the present invention in which the RTL of the logic circuit is described for each functional block, when a circuit change occurs in a certain block, the corresponding block can be easily identified, and the influence of the change can be minimized.

  FIG. 2 is a principle configuration diagram of the present invention. The present invention includes a logic synthesis layout unit 1, a database 2, and a divided program unit 3. The logic synthesis layout unit 1 performs logic synthesis and layout using the logic circuit RTL 4 and the setting file 5 shown in FIG. 1 as input data, and stores the logic circuit information as result data as the database 2. Based on this, the logic circuit division program unit 3 performs distribution to the FPGA / PLD. In the figure, an example in which the division result is distributed to the FPGA 6 is shown. In the figure, an example in which FPGA 1 and FPGA 2 are divided is shown. By logically synthesizing and laying out the RTL of the logic circuit in advance and making all block information into a database, making all block information into a database can improve estimation accuracy and reduce the difference from the actual layout. it can.

  FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 10 is an input data section for inputting RTL and various settings, 20 is a database creation section for creating a database in response to the output of the input data section 10, and 30 is connected to the database creation section 20 for various types. A database storage unit for storing information, 40 is connected to the database storage unit 30 and receives the output of the input data unit 10 and performs a division process, and 50 receives the output of the division processing unit 40 and results It is a result data part for storing data.

  In the input data unit 10, 11 is an RTL receiving unit for storing RTL describing the logic circuit of the ASIC, and 12 is various setting units for inputting devices, the number, the operation speed, and the like. In the database creation unit 20, 21 is a connection number extraction unit that extracts the number of connections between each block from the RTL, 22 is a logic synthesis unit that performs logic synthesis using the RTL, and 23 receives the output of the logic synthesis unit 22 and performs logic synthesis. This is a layout unit (wiring placement unit) that lays out using the combined netlist.

  In the database storage unit 30, 31 is a database that stores the number of connections, logic synthesis, and layout data created by the database creation unit 20 as a database. In the division processing unit 40, 41 is an initial determination unit that compares the database with various setting values and determines whether or not the various setting values are within a predetermined range, and 42 distributes to each FPGA / PLD using the database. This is a circuit dividing unit. In the result data unit 50, 51 is a result data storage unit that stores the result of distributing the ASIC circuit to each FPGA / PLD, and 52 is a correction notification unit that performs correction notification when RTL correction is required.

  FIG. 4 is a diagram showing an example of setting items of the present invention. The items of the number of pins, the number of pins, the usage rate, and the I / O are input to each item of the device used (for example, DEVICE-1, DEVICE-2...). Here, the usage rate represents a ratio when the usage amount of the device is 100% (the same applies hereinafter). Various information (number of memories, number of FFs, number of multipliers, etc.) of each device is registered in advance. The priority of each item is the highest in the number of pins, followed by the number, then the usage rate, and then I / O. The priority of DEVICE is highest in DEVICE-1, followed by DEVICE-2, and continues with DEVICE-3.

  FIG. 5 is a diagram showing an example of connection extraction according to the present invention. The figure shows the correspondence between the number of inputs / number of outputs between blocks. For example, it indicates that there are 50 pins from the output of RTL1 to the input of RTL2. With this data, you can see the number of pins connected. This data is used when determining the number of pins in the mounted device.

  FIG. 6 is a flowchart showing the initial division operation of the present invention. First, the RTL receiving unit 11 inputs an RTL (S1). Next, the various setting units 12 determine whether to set various variables such as the device, the number, the operation speed, and the like (S2). If set, skip to step S3. If not set (default setting), skip to step S4. Various setting units 12 input various variables (S3). Various variables are as shown in FIG.

  Next, the connection number extraction unit 21 extracts the number of connections between each hierarchical block from the TOP RTL which is input data (S4). The number of connections between each hierarchical block is as shown in FIG. Next, the connection number extraction unit 21 receives the output of the RTL reception unit 11 and stores the connection number data extracted in step S4 in the database 31 (S5). The logic synthesis unit 22 logically synthesizes the RTL of each hierarchical block that is input data (S6).

  Next, the logic synthesis unit 22 stores the result of logic synthesis in step S6 in the database 31 (S7). Next, the initial determination unit 41 determines whether the layout data stored in the database 31 is within the set operation speed range (S8). If it is within the range, skip to the division detail flow. If it is out of range, the process proceeds to step S9. Next, the layout unit 23 performs layout (placement and routing) using the netlist of the logic synthesis result (S9). The layout unit 23 stores the result of the layout in step S9 in the database 31 (S10).

  Next, the initial determination unit 41 determines whether the layout data stored in the database 31 is within the range of the set operation speed (S11). If it is within the setting range, the process proceeds to step S12. If it is outside the setting range, the process proceeds to step S13. In step S12, the initial determination unit 41 determines whether the layout data is within the set device range (S12). If it is within the range, the process skips to the division detail flow, and if it is outside the range, the process proceeds to step S15.

  Next, the initial determination unit 41 determines whether or not to change the set operation speed (S13). When the change is made, the process is fed back to step S3. When not changing, it progresses to step S14. In step S14, the circuit dividing unit 42 receives the logic synthesis / layout data, notifies the correction notification unit 52 of the RTL correction, and ends the process. The correction notification unit notifies a display (not shown) that there has been a correction notification. In step S <b> 15, the initial determination unit 41 determines whether or not priority is given to the change of the setting device over the hierarchy development processing of the block exceeding the setting device range. If priority is given to changing the setting device, the process is fed back to step S3, and if priority is given to the hierarchy development process, the process proceeds to step S16. In step S16, the initial determination unit 41 hierarchically develops blocks exceeding the set device range based on the logic synthesis / layout data and feeds back to step S4.

FIG. 7 is a flowchart showing the detailed division operation of the present invention. In this embodiment, the usage rate is a keyword, and a block with a high usage rate is prioritized.
The circuit divider 42 determines whether there is an unmounted block among the blocks in the logic circuit (S1). If there is an unmounted block, the process proceeds to step S2, and if there is no unmounted block (all blocks mounted), the process skips to step S11. Next, the circuit dividing unit 42 designates a block having the highest usage rate among unmounted blocks as a mounting candidate (S2, hereinafter referred to as a specified block).

  The circuit dividing unit 42 determines whether there is a block that is duplicated and used in common (hereinafter referred to as a duplicated block) in the logic circuit (S3). If there is a duplicate block, the process skips to step S4. If not, the designated block is skipped to step S5. In step S4, the circuit dividing unit 42 adds the designated block and the duplicated block to the corresponding block (the usage rate is totaled).

  Next, in step S5, it is determined whether or not the usage rate of the corresponding block exceeds the upper limit value of the usage rate specified in the setting file in advance. If it exceeds, the process proceeds to step S6. If not, the process skips to step S7. In step S6, the circuit dividing unit 42 expands the designated block into a plurality of blocks, and feeds back to step S2. In step S7, the circuit dividing unit 42 determines whether there is a block that falls within a range of values obtained by subtracting the usage rate of the corresponding block from the upper limit value of the usage rate among the unmounted blocks. If there is, the process proceeds to step S8, and if not, the process skips to step S9.

  In step S8, the circuit dividing unit 42 matches the block having the highest usage rate among the blocks corresponding in step S7 to the corresponding block (the usage rates are totaled), and feeds back to step S7. In step S9, the circuit dividing unit 42 determines the corresponding block as a 1 FPGA block. Next, the circuit dividing unit 42 registers all blocks included in the corresponding block as mounting blocks, and feeds back to step S1 (S10). As a result, when there is no unmounted block, the circuit dividing unit 42 stores the result data in the result data storage unit 51 (S11), and the process ends.

  Next, examples of the present invention will be described. FIG. 8 is a diagram showing a block configuration example of a logic circuit which is input data of the present invention. The RTL of this logic circuit is described for each of AAA, BBB, CCC, DDD, and ZZZZ functional blocks, and the connection between the blocks is described as TOP RTL. AAA has AA1, AA2 and AA3, BBB has BB1 and BB2, and CCC has CC1 and CC2 in the lower hierarchy.

  FIG. 9 is a diagram showing an example of a setting file which is input data of the present invention. This file uses DEVICE-1 as the device used, the number of pins is 1000 pins, the number of devices used is 4, the upper limit of the usage rate of each device is 75%, and the upper limit of the number of I / O pins used by the user is In this example, 700 pins, minimum operation speed 50 MHz, duplicate block ZZZ, hierarchy development priority, no setting speed change, and high usage rate priority are set. The duplicate block ZZZ is a basic block (circuit) that is commonly used in each block (see FIG. 14).

The logic circuit of the present invention will be described below along the flow with the RTL and the setting file as input data. In the present embodiment, the limitation on the number of used memories, FFs, multipliers,.
(Example of RTL correction)
The number of connections between each block is extracted from TOP RTL. FIG. 10 is a diagram showing a connection extraction example of the present invention. The correspondence relationship between the number of input pins / the number of output pins shown in FIG. This data is used when determining the number of I / O pins in the mounted device. Next, RTL logic synthesis of each block is performed, and the result is extracted. FIG. 11 is a diagram illustrating a database example of each block. Create a database of the usage rate and operation speed shown in the figure. Of these results, the DDD operating speed is 45 MHz and does not satisfy the minimum operating speed of 50 MHz, which is the set value shown in FIG.

Next, layout is performed using the net list of each block, and the result is extracted. The usage rate and operation speed shown in FIG. Of these results, DDD is not different from the logic synthesis result and does not satisfy the set value. Furthermore, since no setting speed change is set, logic synthesis and layout information are added, RDD correction of DDD is notified to the correction notification unit 52, and the process ends. After correcting the DDD RTL, logic circuit division with the same configuration as described above will be described along the flow.
(Result data example)
Similarly to the above, when the number of connections is extracted, FIG. 10 is similarly obtained. The RTL logic synthesis of each block is performed, and the result is shown in FIG. FIG. 12 is a diagram showing another database example of each block. This result is compared with the set value shown in FIG. Since it is within the range as a result of the comparison, the process proceeds to the detailed division flow. A description will be given along the division principle diagram shown in FIG.

S1: The logic circuit is distributed to 4 FPGAs.
S2: Among the unimplemented blocks, the AAA block (80%) and the common block ZZZ (2%), which have the highest usage rate in the highest hierarchy, are the implementation candidates (82%), and the value and the upper limit (75%) As a result, the AAA block is hierarchically expanded, and AAA1 (45%), AA2 (25%), and AA3 (10%) are set as the highest hierarchy. Here, the database is updated to the database (hierarchical development) shown in FIG.

  S3: The block BBB (65%) and the common block ZZZ (2%) with the highest usage rate are set as implementation candidates (67%), and the value is compared with the upper limit (75%). Next, based on a value (8%) obtained by subtracting the value from the upper limit value, a block within the range is searched from the unmounted blocks. As a result, since there is no corresponding block, FPGA 1 is set by BBB and ZZZ, and the number of pins 670 (a value obtained by subtracting the connection between BBB and ZZZ) is within the set value, so it is determined as 1 FPGA.

  S4: The block CCC (50%) with the highest usage rate and the common block ZZZ (2%) are set as implementation candidates (52%), and the value is compared with the upper limit (75%). Next, as a result of searching for a block within the range from the unimplemented block based on a value obtained by subtracting the value from the upper limit value (75−52 = 23%), the AA3 block (10%) corresponds to the implementation candidate ( 52 + 10 = 62%).

  Next, as a result of searching for a block within the range from the unmounted blocks based on the value subtracted from the upper limit value (75−62 = 13%), there is no corresponding block, so CCC, AAA, and ZZZ are set to FPGA2, Similarly, since the number of pins is within the set value, it is determined as 1 FPGA.

S5: The same processing as S4 is performed, and FPGA3 is determined by AA1, AA2, and ZZZ.
S6: The same processing as S3 and S4 is performed, and FPGA4 is determined by DDD and ZZZ.
As described above in detail, according to the present invention, it is possible to perform division with higher accuracy and to reduce the man-hours for return. In the above-described embodiment, the case where the division is performed in order from the highest usage rate has been described as an example of the division. However, the present invention is not limited to this, and the following example can also be used.

  Further, according to the present invention, the common block of clock / reset can be duplicated. In this way, it is possible to improve the operation speed and reduce the clock / reset.

  In addition, according to the present invention, priorities can be assigned to the blocks in advance, and division can be performed based on the priorities. In this way, the division intended by the user can be made possible.

  Further, according to the present invention, when performing the division, it is possible to divide each FPGA / PLD in order from the lowest usage rate of each block. In this way, it is possible to improve the processing speed due to the law.

  Further, according to the present invention, in the case of performing the division, if the usage rate of a certain block described above exceeds the usage rate of each FPGA / PLD to be divided, the corresponding block is hierarchically expanded and divided. be able to. In this way, it is possible to improve the processing speed due to the law and to divide the circuit into an optimum circuit scale.

  Further, according to the present invention, when the division is performed, the division can be performed by setting an arbitrary upper limit value for the usage rate of the input / output pins / used devices. In this way, adaptation to the specifications intended by the user can be facilitated.

  Further, according to the present invention, when performing the division, the input / output pins can be duplicated / deleted in consideration of branching of the output signal. In this way, it is possible to effectively use the pins and improve the speed (reduction in delay due to an increase in fan-out).

  In addition, according to the present invention, when the division is performed, if the performance cannot be satisfied, the RTL correction can be notified. In this way, it is possible to improve processing speed and user convenience (determination of feasibility).

(Supplementary note 1) RTL of each block is synthesized and laid out in advance,
Create a database of information about the block,
Based on this database, each FPGA / PLD is automatically divided.
A logic circuit dividing method.

(Supplementary note 2) The logic circuit dividing method according to supplementary note 1, wherein a common block of clock / reset is duplicated.
(Supplementary note 3) The logic circuit dividing method according to supplementary note 1, wherein priorities are assigned in advance to the respective blocks, and division is performed based on the priorities.

(Supplementary note 4) The logic circuit division method according to supplementary note 1, wherein in the case of performing the division, the division is performed for each FPGA / PLD in descending order of usage rate of each block.
(Supplementary Note 5) An input data part for inputting RTL and making various settings;
A database creation section for creating a database in response to the output of the input data section;
A database storage unit connected to the database creation unit and storing various types of information;
A division processing unit connected to the database storage unit and performing a division process in response to an output of the input data unit;
A result data part that receives the output of the division processing part and stores the result data;
A logic circuit dividing device constituted by:

(Supplementary note 6) The logic circuit division method according to supplementary note 1, wherein, in the case of performing the division, the division is performed for each FPGA / PLD in order from the lowest usage rate of each block.
(Supplementary note 7) In the case of performing the division, if the usage rate of a certain block exceeds the usage rate of each FPGA / PLD to be divided, the corresponding block is hierarchically expanded and divided. Logic circuit division method.

(Supplementary note 8) The logic circuit division method according to supplementary note 1, wherein in the case of performing the division, the division is performed by setting an arbitrary upper limit value for the usage rate of the input / output pins / used devices.
(Supplementary note 9) The logic circuit division method according to supplementary note 1, wherein in the division, the input / output pins are duplicated and deleted in consideration of branching of the output signal.

  (Supplementary note 10) The logic circuit division method according to supplementary note 1, wherein when the division is performed, if the performance cannot be satisfied, the RTL correction is notified.

It is a block block diagram of the logic circuit which is the input data of this invention. It is a principle block diagram of this invention. It is a block diagram which shows one embodiment of this invention. It is a figure which shows the example of a setting item of this invention. It is a figure which shows the connection extraction example of this invention. It is a flowchart which shows the division | segmentation initial stage operation | movement of this invention. It is a flowchart which shows the division | segmentation detailed operation | movement of this invention. It is a figure which shows the block structural example of the logic circuit which is the input data of this invention. It is a figure which shows the example of a setting file which is input data of this invention. It is a figure which shows the connection extraction example of this invention. It is a figure which shows the database example of each block. It is a figure which shows the other database example of each block. It is a figure which shows the other database example of each block. It is explanatory drawing of the division | segmentation by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Input data part 11 RTL acceptance part 12 Various setting part 20 Database preparation part 21 Connection number extraction part 22 Logic synthesis part 23 Layout part 30 Database storage part 31 Database 40 Division | segmentation process part 41 Initial determination part 42 Circuit division part 50 Result data part 51 Result data storage unit 52 Correction notification unit

Claims (4)

The logic synthesis layout unit performs logic synthesis and layout for each block obtained by dividing the logic circuit by receiving the logic circuit RTL and device, and the setting file for setting the number of devices and the operation speed of the device as input data.
Store logic circuit information, which is the result data of logic synthesis and layout, in a database,
Logic for a plurality of FPGA or PLD using logic circuits programmed based on the logic circuit information stored in the database, the number and device usage entered number of pins of the device and the device and the I / O Sort the blocks that divide the circuit ,
A logic circuit dividing method.   2. The logic circuit dividing method according to claim 1, wherein priorities are assigned to the respective blocks in advance, and division is performed based on the priorities.   3. The logic circuit dividing method according to claim 2, wherein in the division, the division is performed for each FPGA or PLD in order from the highest usage rate of each block. An input data part for inputting the RTL and setting the number of devices and the operation speed of the device; a database creation part for creating a database in response to the output of the input data part;
A database created by the database creation unit;
A database storage unit for storing logic circuit information as result data of logic synthesis and layout in the database;
Logic for a plurality of FPGA or PLD using logic circuits programmed based on the logic circuit information stored in the database, the utilization and I / O of the input pin count devices and device number and device A division processing unit for distributing blocks divided into circuits ;
A result data part that receives the output of the division processing part and stores the result data;
A logic circuit dividing device comprising:

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