JP4568856B2 - Program writing method in software defined radio - Google Patents

Description

  The present invention relates to a program writing method in a software defined radio, and more particularly to a method for efficiently writing a program using a small storage medium such as a memory card.

  In recent years, cellular mobile communication means such as mobile phones and PHS have become widespread, and voice communication and Internet access have become possible everywhere. Wireless access systems other than cellular mobile communications include wireless LAN wireless access systems using 2.4 GHz, 5 GHz, and 25 GHz bands, and FWA (Fixed There are fixed wireless access systems represented by Wireless Access), and their spread is also progressing.

In this way, the user can use many wireless access systems in the future. However, it is difficult for users to carry around terminals that can use all these wireless access systems with current technology.
In addition, a technology for performing communication between different wireless access systems and performing communication using a plurality of wireless communication systems is not generally provided.

In addition, these wireless access systems are also scheduled to use the same radio frequency band, such as the 2.4 GHz band in which a plurality of IEEE802 wireless LANs, Bluetooth, and the like are mixed. That is, there is a need to perform communication with a certain quality in the presence of many interferences.
In order to perform communication while satisfying the required quality in an environment where a plurality of communication systems are mixed, from the viewpoint of the user who has the terminal, the location of the user and the frequency congestion at that location (interference Degree, received signal strength), and the amount of information that the user wants according to the conditions that the user thinks about the terminal (for example, want to reduce the charge or save power) It is necessary to select the best communication line regardless of whether it is wired or wireless and to convey information to the other party of communication.

Also, from the viewpoint of the base station, it recognizes (recognizes) the state of other base stations using the same frequency existing within the area covered by the own station, and gives the user the highest communication quality. There is a need to select a communication system that can.
In this way, a mechanism is built in the radio that “recognizes the environment in which each radio is located in a mixed communication system and selects the necessary communication system according to the recognition result” However, a system for performing seamless communication between a plurality of systems using the system is considered as a new generation mobile communication.

In addition, software wireless technology is attracting attention as an indispensable technology for realizing new generation mobile communication.
As disclosed in Non-Patent Document 1, software-defined radio technology has been proposed as a technology that quickly responds to bugs, upgrades, and the like that occur in communication devices.
Further, as disclosed in Non-Patent Documents 2 and 3 by the present inventors, the effectiveness is shown as means for realizing the functions of a plurality of radios in a space-saving environment such as a car. I came.

J. Mitra, IEEE Communications Magazine, vol.33, no.5, pp.26-38, 1995 Harada et al., IEICE Technical Report, SR99-12, pp. 81-88, 1999 H. Harada et.al., IEICE Trans. Commun., Vol. E85-B, No. 12, pp. 2703-2715, 2002

Further, Patent Literature 4 proposed by the present applicant is patent literature relating to software defined radio technology.
In the technique of Patent Document 4, the control unit manages the function of the software information set in the signal processing unit and the function of each of the plurality of software information stored in the information storage unit. On the other hand, the signal processing unit reads the software information corresponding to the other service function from the information storage unit and sets it in the signal processing unit in response to the request of the other service function in the state of executing the service function, The signal processing unit is configured to execute a plurality of service functions in parallel.
The present technology enables a plurality of available service functions to be used at the same time, and is a technology that improves user convenience.

This technology assumes switching between different communication systems, for example, switching and executing any one of ETC (Electric Toll Collection), FM Radio, AM Radio, and GPS (Global Positioning System) functions. ing. Therefore, when switching to another communication system in the middle of one access like Internet access, there is a problem that switching takes time in the present technology.
As described above, when performing seamless communication between various wireless access systems, it cannot be applied as it is.

Japanese Patent Laid-Open No. 2004-153662

As shown in Patent Documents 3 and 4 described above, in a software defined radio, a program corresponding to a wireless communication system to be switched is written in the software defined radio to switch functions.
In the conventional writing method, for example, as disclosed in Patent Document 5, a rewriting program is transmitted through a wired or wireless route, and the program in the software defined radio is rewritten.

  However, in this method, the program must be written by some transmission line, and the program cannot be rewritten without the transmission line. Therefore, although it is good when the communication control program is corrected as in Patent Document 5, there is a problem that it is difficult to deal with when writing a completely new communication protocol.

Japanese Patent Laid-Open No. 2002-094639

  The present invention was created in view of the above-described problems of the prior art, and an object thereof is to provide a method for easily writing a program in a software defined radio.

In order to solve the above problems, the present invention provides a program writing method in a software defined radio as follows.
That is, the software defined radio according to the present invention includes a display device and a signal processing device, and the signal processing device includes a central control signal processing device, a programmable signal processing device, and a wireless communication board. The central control signal processing apparatus includes a plurality of CPUs, and the programmable signal processing apparatus includes programmable electronic elements whose electronic circuit configuration can be programmed, and is configured with one or a plurality of categorized programmable electronic elements. Two or more electronic element groups are provided.
Each of the plurality of CPUs performs signal processing of at least the data link layer and the network layer in the OSI hierarchical model, while the plurality of programmable signal processing devices have the OSI hierarchy higher than the physical layer or the physical layer and the physical layer in the model. The processing related to the portion requiring signal processing at high speed in the upper layer of the model is performed.
In the software defined radio having the above-described configuration, a program of an electronic circuit configuration related to a predetermined communication protocol is recorded in a small storage medium using a semiconductor storage element, and includes the following steps.

(1) a step in which a user connects the small storage medium to a small storage medium reading unit attached to either the display device or the signal processing device;
(2) a step of displaying a list of communication protocols recorded in a small storage medium on the display device by a status display processing unit of the display device;
(3) The wireless frequency band, the power that can be output, the band that can be output, or the band that can be received by the wireless communication board information display processing unit of the display device, which is written in advance in the wireless communication board existing in the software defined radio. Reading and displaying at least one piece of information about the width and system name that can be supported
(4) a step in which a user selects a desired communication protocol from the list using the input unit of the display device;
(5) transferring the program to a memory space on the signal processing device;
(6) A step of writing the program from the memory space to the programmable electronic element when the communication protocol is used in the software defined radio.

In the above-described program writing method, a program that defines the processing of a CPU related to a predetermined communication protocol is recorded on a small storage medium, and when the communication protocol is used in a software defined radio, the memory space is used for the CPU. It may further include a step of writing the program to the memory.

  According to the invention described in claim 3, at least one of a compact flash (registered trademark) card, a memory stick card, a smart media, an SD card, a multimedia card, and an xD picture card can be used as a small storage medium.

  According to the fourth aspect of the present invention, at least one of FPGA or DSP can be used as the programmable electronic element.

The present invention can also provide the following software defined radio.
That is, the invention according to claim 5 is a software defined radio including a display device and a signal processing device, and reads out a small storage medium using a semiconductor memory element in at least one of the display device and the signal processing device. As well as
The signal processing device includes a central control signal processing device, a programmable signal processing device, and a wireless communication board.
The central control signal processor uses a plurality of CPUs, and the programmable signal processor uses a programmable electronic element whose electronic circuit configuration is programmable, and includes two or more categorized programmable electronic elements. An electronic element group, a memory space for storing a program of an electronic circuit configuration relating to a predetermined communication protocol for a programmable electronic element, a transfer unit for transferring a program read from a small storage medium reading unit to the memory space, and a memory space And a writing unit for writing the program into the programmable electronic element.

On the other hand, the display device can output the frequency band pre-written in the status display processing unit that displays a list of communication protocols recorded on a small storage medium and the radio communication board in the software defined radio A wireless communication board information display processing unit that reads and displays at least one information of a correct power, an outputable or receivable bandwidth, and a compatible system name, and an input for a user to select a desired communication protocol from the list A part.
Then, while causing each of the plurality of CPUs to perform signal processing of at least the data link layer and the network layer in the OSI hierarchical model, each of the plurality of programmable signal processing devices has a physical layer or physical layer and physical layer in the same model. It is characterized in that processing related to a portion requiring signal processing at a high speed in the upper layer of the OSI hierarchical model is performed.

In the software defined radio described above, the present invention provides a memory space that stores a program that defines the processing of a CPU related to a predetermined communication protocol, and a transfer unit that transfers the program read from the small storage medium reading unit to the memory space. And a writing unit for writing the program from the memory space to the CPU memory.

The invention described in claim 7 provides a software defined radio that is at least one of a compact flash (registered trademark) card, a memory stick card, a smart media, an SD card, a multimedia card, and an xD picture card as a small storage medium.

  The invention according to claim 8 provides a software defined radio which is at least one of FPGA and DSP as the programmable electronic element.

By providing the above configuration, the present invention allows a desired communication protocol to be stored in a small storage medium, and a necessary electronic circuit configuration to be written in the software defined radio can be written only by a simple operation of connecting the communication protocol.
As a result, even if the software defined radio is not equipped with a communication protocol in advance, only the necessary protocol can be implemented. Furthermore, it is possible to provide a software defined radio that can appropriately cope with new communication standards.

Hereinafter, embodiments of the present invention will be described based on examples shown in the drawings. The embodiment is not limited to the following.
As shown in FIG. 1, the software defined radio (1) according to the present invention includes a display device (2) and a signal processing device (3). The display device (2) and the signal processing device (3) are electrically connected.

  The display device (2) includes a CRT or liquid crystal monitor and a display unit (4) comprising the display control means, and the content displayed by the user on the display unit (4) corresponding to the display unit (4). An input unit (5) for selecting desired information is included. A keyboard, mouse, touch panel, or the like is used as the input unit (5). Such a device (2) can be easily configured by, for example, a known personal computer.

  The signal processing device (3) is responsible for signal processing and transmission / reception related to wireless communication. Although the detailed configuration will be described later, the signal processing device (3) includes a programmable electronic element (6) capable of programming an electronic circuit configuration as a feature of the present invention. Yes. FPGAs and DSPs are known as examples of the programmable electronic element (6). In addition, it has a memory space (7), a reading unit (8) for a small storage medium composed of semiconductor elements, and a small storage medium (9).

  In the present invention, for the software defined radio function of the signal processing device (3), the electronic circuit configuration program recorded in the small storage medium (9) is read from the reading unit (8) and stored in the memory space (7). After the transfer, the program of the software defined radio can be easily updated by writing in the FPGA (6) at a necessary opportunity.

Next, a detailed configuration of the signal processing device (3) will be described.
As shown in FIG. 2, the signal processing device (3) includes a CPU board (10) as a central control signal processing device, an FPGA board (20) as a programmable signal processing device, and a wireless communication board (30). .

The communication protocol used in the apparatus of the present invention is arbitrary. For example, the signal received by the wireless communication board (30) is subjected to signal processing such as decoding by the FPGA board (20), and converted into a TCP / IP packet by the CPU board (10). It can be converted and output from the connected personal computer in the form of a moving still image or sound.
During wireless transmission, the captured moving / still image or audio signal is input to the FPGA board (20) in the form of a TCP / IP packet by the CPU board (10).

The CPU board (10) has two CPUs, a main CPU (11) and a sub CPU (12), and has a system bus (13) (14) corresponding to each of them.
The CPU board (10) and the FPGA board (20) are connected by connectors (15) and (16). In the present invention, each board is provided separately and can be easily connected by connectors (15) and (16).

  For the FPGA board (20), an FPGA which is a programmable electronic element capable of programming an electronic circuit configuration is used. As a feature of the present invention, two categorized FPGA groups (referred to as right and left channels for convenience) (21) (22) are formed, and two FPGAs (23) (24) are provided for each channel. Is placed.

  The main CPU (11) and the sub CPU (12) of the CPU board (10) are configured to be able to control any of the left and right channel FPGA groups. The operation of the both is as follows. While the main CPU (11) performs wireless communication using the FPGA group of one channel, the sub CPU (12) sets the FPGA group of the other channel as the switching destination communication method. To wait for communication.

  Signal processing is switched from the main CPU (11) to the sub CPU (12) when switching from the user to a switching instruction or a communication method waiting at a predetermined switching trigger. This switching is simply a switching of the signal path on the circuit in a state where communication has already been established, so that the communication system can be switched instantaneously without interruption.

The signal processing device (3) provided by the present invention is a software defined radio using the CPU board having a plurality of CPUs and the FPGA board having a plurality of FPGAs.
Further, each component will be described in detail below.

FIG. 3 shows a detailed configuration of the FPGA board (20).
The FPGA group of each channel includes a serial interface (40) for controlling the wireless communication board (30), a digital interface for external connection (41), and a plurality of AD / DAs for inputting / outputting signals transmitted / received by the wireless communication board. A converter (42), an interface (43) for programming the electronic circuit configuration in the FPGA, and the like are provided.

  The serial interface (40) includes a digital output, an analog input, an AD / DA converter for analog output, and a buffer.

In addition, an operation clock is input from the wireless communication board (30). As shown in FIG. 1, one system of input clocks is divided into a predetermined multiple of clocks and distributed to each FPGA group for input. FIG. 3 shows the clock input interface (44) after distribution.
Thus, by dividing and using one input clock, it is possible not only to supply clocks having a plurality of types of frequencies to the FPGA group, but also to operate the two channels in a completely synchronized state.

The FPGA board mainly performs processing that requires high-speed processing among processing of the first layer (physical layer) and processing of the second layer and higher in the OSI reference model. In other words, this is high-speed processing when performing electrical conversion, mechanical processing, and communication adjustment between users for sending data to a communication line.
As shown in the figure, two FPGA groups constitute one system, and this FPGA board has four FPGAs. Therefore, at least two communication systems can be operated simultaneously.

  The number of CPUs and the number of FPGA groups of the present invention can be arbitrarily configured by a plurality. That is, when selecting an optimum system at high speed from a large number of communication systems, two or more standby systems may be operated together with one active system, in which case there are three CPUs and FPGA groups. The above configuration may be used.

Further, each FPGA (23) has a compact flash (registered trademark) interface unit (45) as a reading unit for reading the compact flash (registered trademark), and when the compact flash (registered trademark) (46) is inserted. The program information is transferred to the flash ROM, which is the memory space (7), by the processing of the main CPU (11) through the connector (15).
Then, the main CPU (11) writes a program from the flash ROM to the FPGA (23).
The trigger for transfer and writing will be described later.

  In this embodiment, a compact flash (registered trademark) is used as a small storage medium. However, any compact storage medium using a semiconductor element may be used, for example, a compact flash ( In addition to a registered trademark card, a memory stick card, smart media, SD card, multimedia card, xD picture card, or the like can be used.

The specification of the FPGA board used in this embodiment is that the AD converter has 2 channels and the conversion rate is 170 Msps and 12 bits, and the DA converter has 2 channels and the conversion rate is 500 Msps and 12 bits.
As the FPGA, XC2V4000, XC2V6000, and XC2V8000 (product names) of Xilinx (registered trademark) are used.

FIG. 4 shows a detailed configuration of the CPU board (10).
An RS232C interface (50) is connected to each CPU (11) (12).
Further, SDRAM (51) and flash ROM (52) are connected to the system buses (13) and (14), and software for signal processing is stored in the flash ROM (52).

A network adapter (53) such as Ethernet (registered trademark), an audio codec processing circuit (54), and a data transmission bus (55) such as USB are connected to the system bus. Any one of these may be provided or a plurality of these may be provided according to the system requirements. Other interfaces may also be included.
In addition to the FPGA board, an FPGA (56) is provided on the system bus.

Then, a program defining the CPU processing from the outside is written into the flash ROM (52) using the interface (57) or (58). Thereafter, the programs required for the CPU (11) (12) are expanded from the flash ROM into the SDRAM (51) for those required for the CPU (11), and the programs required for the CPU (12) are expanded to the SDRAM (52). , Drive the program. The DPRAM is used for exchanging information shared between the CPUs (11) and (12).
A program for realizing various communication systems is written in the flash ROM (52) and the FPGA (56), and performs signal processing to be described later.

When the compact flash (registered trademark) (58) is inserted into the compact flash (registered trademark) interface unit (57) provided in the CPU board (10), the main CPU (11) or the sub CPU (12) is connected to each system bus ( 13) Transfer the program to the flash ROM (52) on (14).
When the FPGA (56) or the CPU (11) (12) is driven when necessary from the program ROM (52), the program is written into the SDRAM (51), (52), and a predetermined communication system is obtained. It functions as a device that realizes

Note that the CPU board of this embodiment is composed of two CPUs that operate on a 430 MIPS μ-ITRON that operates at 240 MHz so that it can also be used in a portable terminal.
In this embodiment, the functions below the IP layer of W-CDMA and IEEE802.11a wireless LAN are softwareized on the above platform. These software can be changed freely according to user's wishes, propagation path information, etc.

The triggers for transfer and writing are as follows.
The present invention provides a method for writing a program to a software defined radio. The procedure is shown in FIG.
When the program is installed, the user first inserts a compact flash (registered trademark) (CF) into the compact flash (registered trademark) interface of the CPU board (10) and FPGA board (20) (S1).

When the user instructs reading from the CF from the display unit (2) (S2), a screen as shown in FIG. 6 is displayed.
On the screen, a list of programs in the CF is displayed in the column (60) (S3), and the user selects the desired protocol and presses the install button (61) (S4) to transfer to the flash ROM ( S5) is possible.
The status of the transfer is displayed on the indicator (62).

  A list of programs (protocol list) installed in the flash ROM is displayed in a column (63). The user can delete it at any time by indicating an unnecessary protocol and pressing the uninstall button (64).

The information of the wireless communication board (30) is automatically transferred to the SDRAM (51) of the CPU board when the signal control device (3) is started, and is displayed on the right side of the list of programs (65) written in each FPGA. It is displayed on a certain wireless communication board information display processing unit (66).
This display screen shows a state in which four wireless communication boards are connected. The information of the wireless communication board (30) includes at least one information of a wireless frequency band, outputable power, outputable or receivable bandwidth, and compatible system name.

When a user selects a wireless communication board to be set from the information column (67) and clicks on it, a screen as shown in FIG. 7 is displayed.
A list of protocols is displayed in the left column (70), and a protocol used in the wireless communication board can be selected in the right column (72) by pressing an add or delete button (71).

  The arrangement in the right column (72) has the highest priority from the top. When the wireless communication board supports a plurality of protocols, it is selected and used from the upper protocol in the order in which communication is possible.

FIG. 8 shows an example of writing a program indicating the electronic circuit configuration from the flash ROM (52) to the FPGA of the CPU board (10) and the FPGA board (20).
Usually, parameters required for switching represented by received signal power and bit error rate are measured from the wireless communication board (30) through the wireless communication interface unit (40) of the FPGA board (20). When the parameter reaches a predetermined threshold (S6), the main CPU (11) detects it (S7).

Then, according to the priority set as described above, the sub CPU (12) and the FPGA (23) (24) actually used by the program at a predetermined time are written (S8) (S9).
As described above, the writing method of the present invention can cope with a plurality of communication systems by writing a program to the sub CPU and the waiting FPGA.

Next, an example in which the above different communication system is introduced into the FPGA board and the CPU board will be described.
First, in the W-CDMA software, a physical layer is installed on the FPGA board. Further, a codec processing unit is installed in the FPGA 1 (23), and a modulation / demodulation processing unit is installed in the FPGA 2 (24).

  The electronic circuit configuration at this time is shown in FIGS. FIG. 9 shows an electronic circuit composed of the FPGA 1 (23), and the function indicated by each block name in the figure is as shown in Table 1 below. Table 1 shows the number of slices necessary for the function.

  FIG. 10 shows an electronic circuit composed of the FPGA 2 (24), and the function indicated by each block name in the figure is as shown in Table 2 below. Table 2 shows the number of slices necessary for the function.

  As can be seen from the table, the capacity of the turbo decoder is large as the capacity of the physical layer because this software is compatible with HSDPA. From the above results, it can be seen that FPGA1 (23) requires an 8 million gate class FPGA and FPGA2 (24) requires a 6 million gate class FPGA.

On the other hand, a signal processing program related to the data link layer (second layer) and the network layer (third layer) is installed on the CPU board. Thereby, for example, input / output by the IP protocol becomes possible.
After being converted to the IP protocol, it can be connected to a personal computer or the like by an Ethernet (registered trademark) adapter provided in the apparatus, and can perform IP communication. The CPU board of the apparatus has second and third layers. It is a requirement to perform at least layer processing, and a processing circuit for processing more layers may be provided.

  The present invention is capable of switching between different communication systems. For example, when the W-CDMA is installed in the left-channel FPGA group, the IEEE802.11a wireless LAN system can be installed in the right-channel FPGA group. .

Specifically, as in the case of W-CDMA, a physical layer (a codec in FPGA1 and a modem in FPGA2) is installed in the FPGA, and a data link layer and a network layer are installed in the CPU. Since IEEE802.11a does not require codec processing, the FPGA 1 actually has only an interface with the CPU board.
FIG. 11 shows the configuration of software entering the FPGA 1 and FPGA 2 for IEEE802.11a, and Table 3 shows the contents of each block name and the number of FPGA slices to be used.

From Table 3, FPGA2 requires 20000 slices, that is, 6 million gate class FPGA, but FPGA1 has only 700 CPU slices because it is only a CPU interface.
That is, it can be built with one 6 million gate class FPGA. In addition, common to W-CDMA and IEEE802.11a, quadrature modulation / demodulation is performed by digital signal processing.

  As the wireless communication board (30) connected to the FPGA board (20), for example, a board for 5 GHz band and a board for 2 GHz band are provided. The wireless communication board holds information such as a corresponding frequency band in advance, and notifies the type of the connected wireless communication board (30) through the serial interface (40). Also, information about the reception status such as the received signal level and the bit error rate can be notified through the interface (40).

The wireless communication board includes a frequency conversion circuit that performs frequency conversion between a radio frequency signal and an intermediate frequency signal or a baseband signal. The frequency conversion circuit performs frequency conversion by mixing with the local oscillation signal output from the frequency synthesizer. This technique is well known. Of course, an antenna (not shown) is attached to the wireless communication board.
The frequency of the local oscillation signal generated from the frequency synthesizer is instructed by a control signal from the FPGA board.

The intermediate frequency signal or baseband signal that is an analog signal is output by the DA converter (42) of the FPGA board at the time of transmission, and is transmitted from the wireless communication board to the AD converter (42) of the FPGA board at the time of reception. Is.
The FPGA board (20) associates a wireless communication system with the wireless communication board (30), and the CPU board (10), the FPGA board (20), and the wireless communication board (30) cooperate to perform wireless communication. I do.

It is a whole block diagram of the software defined radio of the present invention. It is a whole block diagram of the signal processing apparatus in the software defined radio of the present invention. It is a block diagram of the programmable signal processing apparatus of this invention. It is a block diagram of the central control signal processing apparatus of this invention. It is a flowchart which shows the transfer procedure to flash ROM. It is a display image of the display part which implement | achieves the writing procedure by this invention. It is a display image of the display part which implement | achieves the writing procedure by this invention. It is a flowchart which shows the write-in procedure to FPGA. It is a block diagram of the electronic circuit programmed to FPGA1 at the time of W-CDMA communication. It is a block diagram of the electronic circuit programmed to FPGA2 at the time of W-CDMA communication. It is a block diagram of the electronic circuit programmed in the FPGA group at the time of IEEE802.11a communication.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Software defined radio 2 Display apparatus 3 Signal processing apparatus 4 Display part 5 Input part 6 FPGA
7 Memory space 8 Reading section 9 Compact Flash (registered trademark)
10 CPU board 11 Main CPU
12 Sub CPU
13 System bus 14 System bus 15 Connector 16 Connector 20 FPGA board 21 Left channel FPGA group 22 Right channel FPGA group 23 FPGA
24 FPGA
30 wireless communication board

Claims (8)

A method of writing a program in a software defined radio,
The software defined radio includes a display device and a signal processing device, and the signal processing device further includes a central control signal processing device, a programmable signal processing device, and a wireless communication board.
The central control signal processing device includes a plurality of CPUs,
The programmable signal processing device includes a programmable electronic element having a programmable electronic circuit configuration, and includes two or more electronic element groups each including one or more categorized programmable electronic elements,
While causing each of a plurality of CPUs to perform signal processing of at least the data link layer and the network layer in the OSI hierarchical model,
In a configuration in which a plurality of the programmable signal processing devices perform processing related to a portion requiring signal processing at high speed in a physical layer in the same model or a layer above the physical layer and the physical layer in the OSI hierarchical model,
Recording a program of an electronic circuit configuration related to a predetermined communication protocol on a small storage medium using a semiconductor storage element,
A user connecting the small storage medium to a small storage medium reading unit attached to either the display device or the signal processing device;
A step of displaying a list of communication protocols recorded in a small storage medium on the display device by a status display processing unit of the display device;
The wireless communication board information display processing unit of the display device has a wireless frequency band pre-written in the wireless communication board existing in the software defined radio, power that can be output, output is possible, or reception is possible. Reading and displaying at least one piece of information on the bandwidth and the system name that can be supported,
A step in which a user selects a desired communication protocol from the list by using an input unit of a display device, and also selects a wireless communication board for driving the protocol;
Transferring the program to a memory space on a signal processing device;
Writing the program from the memory space to the programmable electronic device when using the communication protocol in a software defined radio,
A method for writing a program in a software defined radio, comprising:   In the method for writing the program,
  A program that defines the processing of the CPU related to a predetermined communication protocol is recorded on the small storage medium,
  Writing the program from the memory space into the memory for the CPU when the communication protocol is used in a software defined radio
  The program writing method in the software defined radio according to claim 1, further comprising: The software according to claim 1 or 2, wherein the small storage medium is at least one of a compact flash (registered trademark) card, a memory stick card, a smart media, an SD card, a multimedia card, and an xD picture card. A method for writing a program in a radio. The method for writing a program in a software defined radio according to any one of claims 1 to 3, wherein the programmable electronic element is at least one of an FPGA and a DSP. A software defined radio comprising a display device and a signal processing device,
A reading unit for a small storage medium using a semiconductor storage element in at least one of the display device and the signal processing device;
The signal processing device is composed of a central control signal processing device, a programmable signal processing device, a wireless communication board,
A plurality of CPUs in the central control signal processor;
Two or more electronic element groups composed of one or a plurality of programmable electronic elements categorized using programmable electronic elements whose electronic circuit configuration is programmable in the programmable signal processing device;
A memory space for storing a program of an electronic circuit configuration according to a predetermined communication protocol for a programmable electronic element;
A transfer unit that transfers the program read from the small storage medium reading unit to a memory space;
A writing unit for writing the program from the memory space to the programmable electronic element,
On the display device,
A state display processing unit that displays a list of communication protocols recorded in a small storage medium and a wireless frequency band pre-written in the wireless communication board existing in the software defined radio, power that can be output, output possible or A wireless communication board information display processing unit that reads and displays at least one information of a receivable bandwidth and a system name that can be supported,
An input unit for a user to select a desired communication protocol from the list;
While causing each of a plurality of CPUs to perform signal processing of at least the data link layer and the network layer in the OSI hierarchical model,
A plurality of the programmable signal processing devices are configured to perform processing related to a portion requiring signal processing at high speed in a physical layer in the model or a layer above the physical layer and the physical layer in the OSI hierarchical model. Software radio to do.   In the software defined radio,
  A memory space for storing a program defining the processing of the CPU according to a predetermined communication protocol;
  A transfer unit that transfers the program read from the small storage medium reading unit to a memory space;
  A writing unit for writing the program from the memory space to the CPU memory;
  The software defined radio according to claim 5, further comprising: The software according to claim 5 or 6 , wherein the small storage medium is at least one of a compact flash (registered trademark) card, a memory stick card, a smart media, an SD card, a multimedia card, and an xD picture card. transceiver. The software-defined radio according to any one of claims 5 to 7 , wherein the programmable electronic element is at least one of an FPGA and a DSP.