JP4572153B2 - Video signal detection circuit - Google Patents

Description

  The present invention relates to a video signal detection circuit that detects the presence or absence of a video signal by inputting a video signal and detecting whether or not the sync chip level of the synchronization signal has reached a predetermined value.

  As this type of video signal detection circuit, there is a circuit shown in FIG. In this circuit, when the sync chip level of the synchronizing signal is deeper than a predetermined level at the timing of the horizontal synchronizing signal in the video signal input to the input terminal 1, the transistor Q1 base-biased by the voltage source V1. The emitter potential is lowered, the transistor Q1 is turned on, the current Ia flows, the capacitor C1 is charged with the polarity shown in the figure, and the voltage becomes the sink chip clamp voltage. The capacitor C1 and the transistor Q1 constitute a sink chip clamp circuit 2. The current source I1 supplies a discharge current I1 for improving sag to the capacitor C1. The current Ia is amplified N times in the current amplifier circuit 3 and input to the I / V conversion circuit 4 as the current Ib (= N · Ia), where it is converted into a voltage signal and input to the low-pass filter 5 in the next stage. The low-pass filter 5 smoothes the pulse voltage output from the I / V conversion circuit 4 at every timing of the synchronization signal. The smoothed output voltage V2 of the low-pass filter 5 is clipped with a non-standard component in the limiter circuit 6 and input to the comparator 7A. When the input voltage V2 to the comparator 7A exceeds the voltage V3 of the voltage source V3, a high level voltage is output to the output terminal 8 to indicate that a video signal has been detected. However, if the transistor Q1 is not turned on at every timing of the synchronizing signal of the video signal, no pulse voltage is output from the I / V conversion circuit 4, and the output voltage of the comparator 7A remains at a low level, and the video signal is detected. Indicates not to be done.

  However, when the video signal is AM-modulated or a ghost signal, the sync chip level of the synchronization signal of the video signal may be around the level at which the transistor Q1 operates, that is, near the video signal detection limit level. In this case, the output voltage V2 of the low-pass filter 5 fluctuates in the vicinity of the voltage V3, and the detection output of the comparator 7 becomes unstable.

  An object of the present invention is to enable stable detection by improving the detection capability when the sync chip level of the synchronizing signal of the input video signal is at the detection limit level and the detection operation becomes unstable. An image signal detection circuit is provided.

According to a first aspect of the present invention, there is provided a sync chip clamp circuit for clamping a sync chip of a video signal, a processing means for converting a current flowing during a clamp operation of the sync chip clamp circuit to remove a high frequency component, and the processing means And a comparator that compares the output voltage with a predetermined value and outputs a detection signal or a non-detection signal, and a current that flows through the sync chip clamp circuit when the detection signal is output from the comparator Current subtracting means for subtracting the first current from the current corresponding to the current, the current subtracted by the subtracting means is supplied to the processing means, and the hysteresis corresponding to the first current is supplied to the comparator Is set.
According to a second aspect of the present invention, in the video signal detection circuit according to the first aspect, when the detection signal is output from the comparator, the amplification for switching the amplification degree of the current input from the sync chip clamp circuit to the processing means And the hysteresis of the comparator is set in accordance with a change amount of the amplification factor of the first current and the amplification unit.
According to a third aspect of the present invention, there is provided a sync chip clamp circuit for clamping a sync chip of a video signal, a processing means for converting a current flowing during a clamp operation of the sync chip clamp circuit to remove a high frequency component, and the processing means And a comparator that compares the output voltage with a predetermined value and outputs a detection signal or a non-detection signal. In the video signal detection circuit, when the non-detection signal is output from the comparator, Current subtracting means for subtracting the first current from the current corresponding thereto is provided.

  According to the present invention, when the sink chip level is in the vicinity of the detection limit level, once detected or once non-detected, the state is maintained, and the error current flowing at the pedestal level can be canceled, The detection operation is stabilized.

[First embodiment]
FIG. 1 is a circuit diagram of a video signal detection circuit according to a first embodiment of the present invention. Reference numeral 1 denotes an input terminal 1 for video signals. C1 is a coupling capacitor, Q1 is an npn transistor to which a bias voltage V1 is applied to the base, and these constitute a sink chip clamp circuit 2. I1 is a current source (current I1) for sag improvement, and discharges the capacitor C1 with the current I1. Reference numeral 3 denotes a current amplifying circuit composed of a current mirror circuit or the like, which amplifies the input current Ia N times and outputs it as a current Ib (= N · Ia). 4 is an I / V conversion circuit that converts the output current Ib into a voltage signal, 5 is a low-pass filter that smoothes the output pulse of the I / V conversion circuit 4 and converts it to a DC voltage V2, and 6 is an output of the low-pass filter 5. A limiter circuit that clips the voltage V2 when it falls outside a predetermined standard, and a comparator 7 with hysteresis that compares the output voltage of the low-pass filter 4 with the voltage V3 of the voltage source V3. I2 is a current source (current I2), SW1 is a switch, and these series circuits are connected between the input side of the current amplifier circuit 3 and the power source Vcc. A switch control circuit 9 generates a control signal for turning on the switch SW1 when the output voltage of the comparator 7 becomes a high level. The current amplifying circuit 3, the I / V conversion circuit 4, the low-pass filter 5, the limiter circuit 6 and the like constitute processing means in claims. Further, the switch control circuit 9, the current source I2, and the switch SW1 constitute subtracting means in claims.

  In this embodiment, when the sync chip level of the sync signal is deeper than the pedestal level at the timing of the horizontal sync signal in the video signal input to the input terminal 1, the voltage source V1 biases. The potential of the emitter of the transistor Q1 is lowered, the transistor Q1 is turned on, the current Ia flows, the capacitor C1 is charged with the polarity shown in the figure, and the voltage becomes the sink chip clamp voltage. The current Ia is amplified N times in the current amplifier circuit 3 and input to the I / V conversion circuit 4 as the current Ib (= N · Ia), where it is converted into a voltage signal and input to the low-pass filter 5 in the next stage. The low-pass filter 5 smoothes the pulse voltage output from the I / V conversion circuit 4 at every timing of the synchronization signal. The smoothed output voltage V2 of the low-pass filter 5 is clipped by the limiter circuit 6 for a non-standard level and is input to the comparator 7. When the input voltage level V2 to the comparator 7 exceeds the voltage V3 of the voltage source V3, a high level voltage is output to the output terminal 8, and a video signal is detected. However, if the transistor Q1 is not turned on every timing of the synchronizing signal of the video signal, the pulse voltage is not output from the I / V conversion circuit 4, and the output voltage V2 of the comparator 7 remains at a level lower than the voltage V3. The video signal is not detected.

  When the video signal is detected and the output voltage of the comparator 7 becomes high level, the switch SW1 is turned on by the switch control circuit 9 and the current source I2 is connected to the sink chip clamp circuit 2, so that the timing of the synchronization signal The current I2 of the current source I2 is included in a part of the current that sometimes flows through the sink chip clamp circuit 2. That is, if the current flowing through the sink chip clamp circuit 2 is Ic, the input current Ia of the current amplifier circuit 3 is reduced to Ia = Ic−I2.

  Therefore, when the sink chip level is sufficiently deep, the current Ic is sufficiently large and the influence of the current I2 is small, and a high level voltage is continuously output from the comparator 7 without affecting the entire circuit. .

  However, when the sink chip level is shallow, since the current Ic is small, the influence of the current I2 is large and the current Ia is small. Accordingly, the current Ib is also small, and the output voltage V2 of the low-pass filter 4 is the current I2. It is lowered by the amount corresponding to. The comparator 7 has hysteresis of the voltage V4, and once the output voltage becomes high level, the voltage of the voltage source V3 becomes a voltage V3 '(= V3-V4) which is lower by the voltage V4.

  Therefore, if the voltage V4, which is the hysteresis width of the comparator 7, is set to be slightly larger than the voltage corresponding to the current I2, the state is maintained once the output voltage of the comparator 7 becomes a high level. Therefore, the video signal detection operation is stabilized.

This current I2 is set according to the sink chip level at the detection limit. When realizing a video signal detection circuit capable of detecting video signals up to −30 dB when 1 Vp-p of the input signal is 0 dB, the signal amplitude at −30 dB is 30 mVp-p. The voltage difference between the pedestal level and the sync tip level is about 1/3 of 10 mV, which is the detection limit. In the case of such a small potential difference, when the transistor Q1 is turned on at the time of the sink chip and the current Ic flows, the current may continue to flow even if the current level shifts to the pedestal level. . Therefore, when an error current corresponding to 10 mV is subtracted as the current I2, the current Ia becomes a current with the error canceled. For the current I2, the change ΔVbe in the base-emitter voltage of the transistor Q1 when the sink chip level is shifted to the pedestal level is
ΔVbe = 26mV × ln (Ic / I2) (1)
Therefore, the current I2 when ΔVbe becomes 10 mV can be obtained from this equation (1). Ic is a current during normal operation (when the difference between the sync tip level and the pedestal level is 286 mV in NTSC).

  From the above, in the conventional video signal detection circuit, detection / non-detection may be repeated in the vicinity of the sync chip level at the detection limit. According to the present embodiment, the sync chip level is temporarily set even at the detection limit. When detected, the error current flowing at the pedestal level can be canceled and the sync chip level detection state can be maintained.

[Second embodiment]
FIG. 2 is a circuit diagram of the video signal detection circuit of the second embodiment. Here, a switch SW2 is connected to a current source I3 that subtracts the current I3 from the output current Ib of the current amplifier circuit 3, and the switch control circuit 9 controls the on / off of the switch SW2. The current I3 of the current source I3 is I3 = N · I2 where the amplification factor of the current amplifier circuit 3 is N. The switch control circuit 9, the current source I3, and the switch SW2 constitute subtracting means in the claims. In the first embodiment described with reference to FIG. 1, when the sink chip is detected, the input current Ia of the current amplifying circuit 3 is switched from Ic to “Ic−I2”. The second embodiment of FIG. Then, the output current is switched from Ib to “Ib−I3” and input to the I / V conversion circuit 4. The difference in configuration is whether the subtraction process is performed on the input side or the output side of the current amplifier circuit 3. In this embodiment, once the sync chip level is detected even at the detection limit, the error current flowing at the pedestal level can be canceled and the sync chip level detection state can be maintained.

[Third embodiment]
FIG. 3 is a circuit diagram of a video signal detection circuit according to the third embodiment. Here, when a video signal is detected, the switch control circuit 9 switches the input current Ia of the current amplifier circuit 3 from Ic to “Ic−I2” and switches the amplification degree N of the current amplifier circuit 3. It is what. The hysteresis width V4 of the comparator 7 may be determined according to the change in the current I2 and the amplification degree N.

[Fourth embodiment]
FIG. 4 is a circuit diagram of the video signal detection circuit of the fourth embodiment. Here, when a video signal is detected, the switch control circuit 9 reduces the input current Ib of the I / V conversion circuit 4 by I3 and switches the amplification degree N of the current amplification circuit 3. is there. The hysteresis width V4 of the comparator 7 may be determined according to the change in the current I3 and the amplification degree N.

[Other examples]
In the first embodiment of FIG. 1, when the output of the comparator 7 is at a low voltage level and no video signal is detected, this is detected by the switch control circuit 9 and the switch SW1 is turned on. It may be. In this case, the input current Ia of the current amplifier circuit 3 decreases from Ic to “Ic−I2”, and the output voltage V2 of the low-pass filter 5 decreases. Unless this happens, the non-detection of the video signal is maintained, the error current is canceled, and the vicinity of the sync chip level at the detection limit is forced to be non-detection, thereby realizing a stable operation. In this case, it is not necessary to provide the comparator 7 with hysteresis. In the second embodiment of FIG. 2 also, when the output voltage of the comparator 7 is low and no video signal is detected, the switch control circuit 9 detects it and turns on the switch SW2. If it is, it operates similarly.

It is a circuit diagram of the video signal detection circuit of the first embodiment. It is a circuit diagram of the video signal detection circuit of the 2nd example. It is a circuit diagram of the video signal detection circuit of the 3rd example. It is a circuit diagram of the video signal detection circuit of the 4th example. It is a circuit diagram of a conventional video signal detection circuit.

Explanation of symbols

1: Video signal input terminal 2: Sync chip clamp circuit 3: Current amplifier circuit 4: I / V conversion circuit 5: Low-pass filter 6: Limiter circuit 7, 7A: Comparator 8: Output terminal 9: Switch control circuit

Claims (3)

A sync chip clamp circuit for clamping the sync chip of the video signal, a processing means for converting the current flowing during the clamping operation of the sync chip clamp circuit to remove a high frequency component, and comparing the output voltage of the processing means with a predetermined value In a video signal detection circuit comprising a comparator that outputs a detection signal or a non-detection signal,
A current subtracting means for subtracting a first current from a current flowing through the sink chip clamp circuit or a current corresponding thereto when the detection signal is output from the comparator; A video signal detection circuit, characterized in that a hysteresis corresponding to the first current is set in the comparator and supplied to the processing means. The video signal detection circuit according to claim 1.
Amplifying means for switching an amplification degree of a current input from the sync chip clamp circuit to the processing means when the detection signal is output from the comparator; and the hysteresis of the comparator includes the first current and the amplification A video signal detection circuit set in accordance with a change in the amplification degree of the means. A sync chip clamp circuit for clamping the sync chip of the video signal, a processing means for converting the current flowing during the clamping operation of the sync chip clamp circuit to remove a high frequency component, and comparing the output voltage of the processing means with a predetermined value In a video signal detection circuit comprising a comparator that outputs a detection signal or a non-detection signal,
A video signal detection circuit comprising current subtraction means for subtracting a first current from a current flowing through the sink chip clamp circuit or a current corresponding thereto when the non-detection signal is output from the comparator.

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