JP4573328B2 - Semiconductor device, semiconductor design apparatus and semiconductor design method - Google Patents

Description

  The present invention relates to a semiconductor device, a semiconductor design apparatus, and a semiconductor design method, and more particularly to a PLD (Programmable Logic Device) design apparatus, a PLD design method, and a PLD designed by the design apparatus.

  Semiconductor devices that can implement various random logic circuits on the user's side by arbitrarily writing logic are called PLDs (Programmable Logic Devices). In recent years, they have rapidly become large-scale and have a powerful ASIC development method. It is being recognized as. In particular, in recent years, an FPGA (Field Programmable Gate Array) has been developed and widely spread as a new PLD. Unlike semi-custom LSIs such as cell-based ICs, FPGAs are programmed and used by the user after chip manufacture.

  When developing a semiconductor device that employs an FPGA (hereinafter referred to as an FPGA device), the device is developed through a plurality of steps. The process generally includes a logic design process for designing a logic circuit based on a system specification, a logic synthesis process for generating a netlist (data expressing circuit connection state) from the designed logic circuit, and a netlist. There are an arrangement / wiring process for performing logic cell arrangement / wiring processing based on the above, and a programming process for programming an actual device.

  In the logic design process, the designed logic circuit is described in HDL (Hardware Description Language) using a text editor or the like. In the logic synthesis process, an EDA (Electronic Design Automation: electronic design automation software for semiconductor design) tool (for example, a logic synthesis tool) is used to generate a netlist based on circuit information described in HDL. In the placement / wiring process, placement / wiring processing is performed using an EDA tool (for example, placement / wiring tool) based on the created netlist. In the FPGA, a large number of logic elements that provide basic logic functions are arranged in advance. In the placement / wiring process, the EDA tool maps a logic cell to its logic element. Further, wiring between the mapped cells is performed. After the placement / wiring process is completed, a simulation for verifying the wiring delay is performed, and the operation timing is verified. When it is determined that the circuit designed by the operation verification satisfies the specifications, circuit information is input to the actual device in the programming process. In this process, an actual FPGA device is formed.

  As described above, the FPGA includes a logic element having a basic logic function. The user can realize random logic by combining a plurality of the logic elements. After programming by the user, it may be necessary to rewrite the program. In such a case, a technique for rewriting a program by rewriting an internal register is known (for example, see Patent Document 1).

  Conventionally, in order to realize a function of rewriting an FPGA internal register, for example, in a hardware emulator, a circuit described in HDL is mapped to a dedicated FF to which logic is added, and then an FPGA primitive (an FPGA in a “blank” state) Is mapped. When a rewrite control CPU is configured separately from the rewrite target FPGA, the rewrite is executed by reading and writing the debug target FPGA register using the control CPU.

JP-A-3-2011141

  As described above, an FPGA device capable of register rewriting can be configured by adding dedicated hardware for register rewriting, but the addition of dedicated hardware increases the scale of the FPGA circuit. linked.

  FPGAs have a shorter development period than semi-custom LSIs such as cell-based ICs, and are standard products, making them suitable for low-volume production applications. Especially, there is no need for large initial costs (mask design / manufacturing costs, etc.) It is a merit. However, generally, when the production quantity increases, the semi-custom LSI is more advantageous in terms of unit price per gate than the FPGA. Therefore, as the production quantity of the product equipment increases, the cost of the product equipment can be reduced by configuring a semiconductor device mounted with a semi-custom LSI such as a cell-based IC instead of the FPGA. Further, in the development of an ASIC (for example, a cell-based IC), development may be advanced using FPGA for prototyping in the development process.

  As described above, when a semiconductor device configured with an FPGA is configured with a semi-custom LSI, or when development is performed using an FPGA for prototyping, the circuit configuration to be mounted on the semi-custom LSI and the implementation at the time of FPGA mounting are realized. If there is a large difference from the circuit configuration that has been used, the equivalence between the circuits cannot be maintained, and a circuit that normally operates in the FPGA may become unstable in the cell-based IC.

  The problem to be solved by the present invention is an FPGA device having a circuit configuration capable of maintaining equivalence between circuits when a circuit realized by the FPGA device is configured by a semi-custom LSI, and the It is to provide an EDA capable of designing an FPGA device.

  The means for solving the problem will be described below using the numbers used in [Best Mode for Carrying Out the Invention]. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

In order to solve the above problems, a program for supporting the design of a semiconductor (FPGA) that constitutes a predetermined logic circuit by arbitrarily writing logic by a user is configured as follows. The program is
[A] a step in which a circuit design EDA (Electronic Design Automation) generates a first RTL (Resister Transfer Level) description model based on a logic design model of a semiconductor device;
[B] a circuit change EDA converting the first RTL description model into a second RTL description model;
[C] Preferably, the logic synthesis tool is a program for causing a computer to execute a method including the step of mapping the second RTL description model to an FPGA primitive.

Here, in the program, the step [a] includes a step of specifying a storage circuit in the semiconductor device, forming a reset circuit of the storage circuit, and generating the first RTL description model. preferable.
The step [b] includes a step of generating, in the first RTL description model, a rewrite value input terminal for receiving a rewrite value of the memory circuit and a memory value supply terminal for receiving a value held by the memory circuit. It is preferable.
Further, the step [c] includes a step of executing logic synthesis based on the second RTL description model to generate an FPGA netlist, and executing mapping based on the FPGA netlist. This is true. A computer is caused to execute a method including these steps.
Further, the [b] step includes one of a first terminal that receives the rewritten value supplied from the outside, a second terminal connected to the stored value supply terminal, and the first terminal and the second terminal. Generating a rewrite circuit model comprising a switch for providing a value supplied via the rewrite value input terminal, and connecting the output terminal of the switch and the rewrite value input terminal to the second RTL description model May be included.

  The rewrite circuit (31) supplies the rewrite value supplied from the first terminal to the memory circuit (register) side during debugging. When there is a memory circuit that is not rewritten, the closed circuit (36 → 37 → 42 → 41) is configured so that the connection of the switch (31) is switched and the output of the memory circuit returns to the same memory circuit again. As a result, the value of the memory circuit is kept. In addition, after the debugging is completed, a reset value is supplied instead of the rewritten value supplied at the time of debugging, so that the circuit operates as a normal reset circuit.

  According to the present invention, there is provided an FPGA device capable of maintaining circuit equivalence when a circuit configured with an FPGA is configured with a semi-custom LSI such as a cell-based IC, and an EDA for generating the FPGA device. It becomes possible to do.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a circuit configuration (circuit model) is described in RTL (Resister Transfer Level: a level in which a circuit is expressed by a flip-flop + combinational logic circuit), and a semiconductor device on which a circuit to be developed is mounted is an FPGA. A case will be described as an example. In the present embodiment, a description will be given assuming that a semi-custom LSI that requires equivalence with an FPGA is a cell-based IC.

  FIG. 1 is a block diagram showing an outline of the semiconductor development method of the present invention. FIG. 1 (a) shows an outline of a semiconductor development method of the present invention, and FIG. 1 (b) shows an outline of a conventional semiconductor development method for comparison with the present invention.

  Referring to FIG. 1A, in semiconductor development according to the present invention, logic design based on system specifications is performed, and a basic logic circuit is configured by RTL description (hereinafter referred to as a basic circuit configuration). The basic circuit configuration data is read into the circuit change EDA, and logic correction processing is executed. The circuit change EDA modifies the basic circuit configuration so that it can be programmed. A logic circuit generated by the logic correction process (hereinafter referred to as a post-correction circuit configuration) is read by a logic synthesis tool, and an FPGA netlist is generated. The generated FPGA netlist is sent to the FPGA development tool, and a circuit is formed by an actual device.

  Referring to FIG. 1B, in the conventional semiconductor development, a dedicated FF for realizing a register rewriting function is prepared, mapped to the dedicated FF, and then mapped to the FPGA. Here, as shown in FIGS. 1A and 1B, when a cell-based IC corresponding to the basic circuit configuration is configured, a cell-based IC netlist is generated. The cell-based IC netlist is read by the layout tool, and layout work for the cell-based IC is executed.

  As described above, if the difference between the circuit configuration mounted on the cell base IC and the circuit configuration realized by the FPGA device is large, a problem may occur when the circuit configuration is mounted on the cell base IC. . The semiconductor development apparatus according to the present embodiment includes the circuit change EDA described above, and the circuit change EDA constitutes a circuit capable of programming (register rewriting) by executing an appropriate logic correction process. . The detailed configuration and operation of the present embodiment will be described below. In this embodiment, a semiconductor circuit that is symmetrical to development is designed using a computer, and then programming to an actual FPGA device is performed.

  FIG. 2 is a block diagram illustrating the configuration of the semiconductor design apparatus of this embodiment. Referring to FIG. 2, the semiconductor design apparatus of the present embodiment includes information based on a circuit design computer 1, an input device 2 for inputting information to the circuit design computer 1, and output data output from the circuit design computer 1. And an output device 3 for performing the output. The circuit design computer 1 is an information processing apparatus that performs design of a semiconductor device. As shown in FIG. 2, the circuit design computer 1 includes a CPU 4, a memory 5, and a mass storage device 6, which are connected via a bus 7. The CPU 4 is an arithmetic processing unit that controls various devices and processes input / output data. The memory 5 is a storage device that stores data processed by the CPU 4. The mass storage device 6 is a storage device that holds various tools used for semiconductor design and data used for semiconductor design.

  As shown in FIG. 2, the large-capacity storage device 6 includes an EDA tool group 8, design data 9, a circuit data storage area 10, FPGA logic element data 11, and a debugger program 12. The EDA tool group 8 is computer software that supports development of a semiconductor device. A plurality of EDA (Electronic Design Automation) tools are included. Referring to FIG. 2, the EDA tool group 8 includes a circuit change EDA 13, a logic synthesis tool 14, an editor 15, and a circuit design EDA 18. The design data 9 is design data of a semiconductor device designed based on system specifications. The basic circuit data 16 and the corrected circuit data 17 of the present embodiment described below are generated based on the design data 9.

  The circuit data storage area 10 is a storage area for holding basic circuit data 16 and corrected circuit data 17. The basic circuit data 16 is data indicating a circuit configuration of a register having a reset circuit. The post-correction circuit data 17 is data indicating a circuit configuration generated when a logical correction is executed based on the basic circuit data 16. Here, details of each circuit configuration will be described later.

  The FPGA logic element data 11 is data indicating the configuration of the gate of the blank-state FPGA. The debugger program 12 is computer software used when the FPGA device is debugged. Here, the operation of the present embodiment when using the circuit design computer 1 described above will be exemplified.

  FIG. 3 is a flowchart illustrating the overall operation of the circuit design in this embodiment. Referring to FIG. 3, in step S101, logic design is performed based on system specifications.

  In step S102, a logic circuit conforming to the specification is configured by describing the configuration of the designed circuit in an RTL description using an editor. The circuit design EDA 18 specifies a register constituting the logic circuit from the design data 9 constituted by the RTL description. The circuit design EDA specifying the register forms a reset unit for resetting a value held in the register, and connects the reset unit and the register to generate basic circuit data 16. The circuit change EDA 13 stores the basic circuit data 16 to be generated in the circuit data storage area 10.

  In step S103, the circuit change EDA 13 reads the basic circuit data 16 from the circuit data storage area 10. The circuit change EDA 13 executes logic correction of the basic circuit based on the read basic circuit data 16. Here, the details of the operation relating to the logic correction process executed by the circuit change EDA 13 will be described later. In step S <b> 104, the circuit change EDA 13 configures the modified circuit configuration by RTL description, and stores the modified circuit data 17 in the circuit data storage area 10.

  In step S105, the logic synthesis tool 14 reads the corrected circuit data 17 from the circuit data storage area 10 and executes logic synthesis. Based on the FPGA logic element data, the logic synthesis tool 14 maps the circuit indicated by the read corrected circuit data 17 to the FPGA primitive. In step S106, the logic synthesis tool 14 generates an FPGA netlist in response to the mapping completion, and stores the FPGA netlist in the mass storage device 6.

  In step S107, the corrected circuit data 17 is output to an FPGA development tool (not shown). The FPGA development tool supplied with the corrected circuit data 17 writes a program to an actual FPGA device based on the corrected circuit data 17 to manufacture an actual device.

  The above is the description of the overall configuration and operation in the present embodiment. Hereinafter, a detailed description will be given regarding the above-described logic correction processing.

  FIG. 4 is a circuit diagram illustrating the basic circuit configuration generated in step S102 in the above-described flowchart. The basic circuit diagram 21 shown in FIG. 4 is a circuit diagram when the basic circuit data 16 composed of the RTL description is displayed with circuit symbols. As shown in the basic circuit diagram 21, a semiconductor device generated based on design data includes a plurality of registers 22. The circuit change EDA 13 generates a plurality of basic circuits 21 corresponding to the plurality of registers. In addition, in the following embodiment, since the structure and operation | movement with the same code | symbol are attached | subjected, the overlapping description is abbreviate | omitted.

  Referring to FIG. 4, the basic circuit 21 includes a register 22 and a selector 23 provided in the previous stage of the register 22. As shown in FIG. 4, the selector 23 is connected to the reset value input signal line 24, the input side circuit internal logic signal line 25, and the reset input signal line 26. The value output from the selector 23 is supplied to the register 22, and the register 22 outputs the stored value via the register output signal line 27 in synchronization with the supplied clock.

  The reset value input signal line 24 is supplied with a reset value input to the register 22 at the time of reset. In response to the reset signal supplied from the reset input signal line 26, the selector 23 resets the value of the register 22 based on the reset value supplied from the reset value input signal line 24. Further, as shown in FIG. 4, the selector 23 is connected to a preceding logic circuit (not shown) via an input side circuit internal logic signal line 25. The selector 23 supplies the register 22 with a value supplied via the input side circuit internal logic signal line 25 in normal operation.

  FIG. 5 is a block diagram illustrating the corrected circuit configuration generated in step S103 in the flowchart of FIG. The post-correction circuit 28 shown in FIG. 5 displays the post-correction circuit data 17 composed of RTL descriptions by circuit symbols. As shown in FIG. 5, the corrected circuit 28 includes a basic circuit 21 and a rewrite circuit 31 connected to the basic circuit 21. As shown in the corrected circuit 28, the basic circuit 21 includes a basic circuit input terminal 41 and a basic circuit output terminal 42, and is connected to the rewrite circuit 31 via both terminals. Referring to FIG. 5, the rewriting circuit 31 includes a switch 32. The switch 32 is connected to the basic circuit output terminal 42 and the rewrite value input signal line 33. The basic circuit output terminal 42 is connected to the node 36 via the feedback input signal line 37, and supplies the value output from the register 22 to the switch 32.

  As shown in FIG. 5, the circuit generated by the logic correction switches the connection of the switch 32 in response to the switching signal supplied from the switching signal line 34. The FPGA device having the circuit configuration shown in the corrected circuit 28 can supply the rewrite value of the register 22 via the rewrite circuit 31. When rewriting is not performed on a specific register 22, the value of the register 22 can be held by switching the connection to the switch 32. Further, in the configuration of the corrected circuit 28, a reset operation can be realized by supplying a reset value (VDD or GND) via the rewrite value input signal line 33.

  FIG. 6 is a flowchart illustrating details of the above-described logic correction operation (operation for generating the corrected circuit 28). Referring to FIG. 6, in step S <b> 201, the circuit change EDA 13 executes reading of the basic circuit data 16. In step S202, the circuit change EDA 13 requests input of reset terminal information. In response to the request, the designer inputs the name of the reset terminal connected to the reset unit from the input device 2 as reset terminal information. The circuit change EDA 13 specifies a reset terminal based on the input reset terminal information. The circuit change EDA 13 identifies the basic circuit 21 by recognizing the selector 23 connected to the reset terminal and the subsequent register 22.

  In step S <b> 203, the circuit change EDA 13 specifies the output terminal of the register 22 included in the basic circuit 21 based on the specified configuration of the basic circuit 21 and the basic circuit data 16. In step S204, the circuit change EDA 13 specifies the basic circuit output terminal 42 in response to the specification of the output terminal of the register 22, and generates a path connecting from the node 36 to the basic circuit output terminal 42 via the feedback input signal line 37. To do. The circuit change EDA 13 specifies the reset value input signal line 26 included in the basic circuit 21 based on the specified configuration of the basic circuit 21 and the basic circuit data 16. The circuit change EDA generates a basic circuit input terminal 41 corresponding to the reset value input signal line 26 and specifies the reset value input signal line 26 connected to the basic circuit input terminal 41 as the rewrite value supply line 35.

  In step S205, the circuit change EDA 13 extracts data corresponding to the rewrite circuit 31 from the data storage area provided in the circuit design computer 1 in response to the specification of the basic circuit input terminal 41 and the basic circuit output terminal 42. The circuit change EDA 13 configures the corrected circuit 28 by adding the RTL description corresponding to the rewrite circuit 31 to the basic circuit data 16 based on the data. Further, the circuit change EDA 13 specifies a rewrite value input signal line 33 connected to an input pin (not shown) to which a rewrite value is supplied at the time of device manufacture. The circuit change EDA 13 connects the first input terminal of the switch 32 and the rewrite value input signal line 33, connects the second input terminal and the basic circuit output terminal 42, and further outputs the switch 32. The corrected circuit 28 is configured by connecting the terminal and the basic circuit input terminal 41. The circuit change EDA 13 outputs the RTL description corresponding to the corrected circuit 28 as the corrected circuit data 17.

  As described above, the FPGA device according to the present embodiment includes the reset unit (circuit configured by 23 and 26) for executing the reset operation of the LSI, and configures the basic circuit 21. The rewrite circuit 31 rewrites the register 22 using the reset unit. The circuit area of the rewrite circuit 31 is smaller than the circuit area of a dedicated circuit for rewriting a register value that has been conventionally used. Therefore, an FPGA device equipped with the circuit of the present invention can suppress an increase in circuit area as compared with a conventional FPGA device. In addition, when a circuit configured with an FPGA is configured with a semi-custom LSI such as a cell-based IC, it is possible to configure an FPGA device capable of maintaining the equivalent of the circuit with the semi-custom LSI.

  Hereinafter, other embodiments of the present invention will be described. FIG. 7 is a circuit diagram illustrating the configuration of the corrected circuit 28 according to another embodiment. Referring to FIG. 7, the modified circuit 28 of another embodiment includes an input buffer 43 connected between the basic circuit input terminal 41 and the selector 23, and between the basic circuit output terminal 42 and the node 36. And an output buffer 44 to be connected. As shown in FIG. 7, the modified circuit 28 according to another embodiment is connected to a computer outside the LSI (for example, the circuit design computer 1) via a basic circuit input terminal 41 and a basic circuit output terminal 42. Is possible. The corrected circuit 28 is connected to the circuit design computer 1 via the basic circuit input terminal 41 and the basic circuit output terminal 42, thereby rewriting the register without configuring a dedicated FF or the like to which logic is added. It becomes possible.

FIG. 1 is a block diagram showing an outline of the present invention. FIG. 2 is a block diagram illustrating the configuration of the semiconductor design apparatus of this embodiment. FIG. 3 is a flowchart illustrating the operation of the present embodiment. FIG. 4 is a circuit diagram illustrating the configuration of the basic circuit. FIG. 5 is a circuit diagram illustrating the configuration of the corrected circuit. FIG. 6 is a flowchart illustrating details of the logic correction operation. FIG. 7 is a circuit diagram illustrating the configuration of another embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Circuit design computer 2 ... Input device 3 ... Output device 4 ... CPU
DESCRIPTION OF SYMBOLS 5 ... Memory 6 ... Mass storage device 7 ... Bus 8 ... EDA tool group 9 ... Design data 10 ... Circuit data storage area 11 ... FPGA primitive 12 ... Debugger program 13 ... Circuit change EDA
DESCRIPTION OF SYMBOLS 14 ... Logic synthesis tool 15 ... Editor 16 ... Basic circuit data 17 ... Circuit data after correction 18 ... Circuit design EDA
DESCRIPTION OF SYMBOLS 21 ... Basic circuit 22 ... Register 23 ... Selector 24 ... Reset value input signal line 25 ... Input side circuit internal logic signal line 26 ... Reset input signal line 27 ... Register output signal line 28 ... Modified circuit 31 ... Rewrite circuit 32 ... Switch 33 ... Rewrite value input signal line 34 ... Switching signal line 35 ... Rewrite value supply line 36 ... Node 37 ... Feedback input signal line 41 ... Basic circuit input terminal 42 ... Basic circuit output terminal 43 ... Input buffer 44 ... Output buffer

Claims (6)

A program that supports design of a semiconductor device that constitutes a predetermined logic circuit by a user arbitrarily writing logic ,
(A) a circuit design EDA (Electronic Design Automation) generates a first RTL (Resister Transfer Level) description model based on the logic design model of the semiconductor device;
(B) a circuit change EDA converting the first RTL description model into a second RTL description model;
(C) the logic synthesis tool comprises the step of mapping the second RTL description model to an FPGA primitive ;
The step (a) includes:
Identifying a memory circuit inside the semiconductor device, configuring a reset circuit of the memory circuit to generate the first RTL description model,
The step (b)
Generating a rewrite value input terminal for receiving a rewrite value of the storage circuit and a storage value supply terminal for receiving a value held by the storage circuit in the first RTL description model;
A first terminal for receiving the rewritten value supplied from the outside, a second terminal connected to the stored value supply terminal, and a value supplied via one of the first terminal and the second terminal Generating a rewrite circuit model including a switch provided at a rewrite value input terminal;
Connecting the output end of the switch and the rewrite value input end to generate the second RTL description model
Including
The step (c) includes:
Performing a logic synthesis to generate an FPGA netlist based on the second RTL description model, and executing a mapping based on the FPGA netlist . program. The program according to claim 1 ,
The reset circuit includes a selection circuit that is provided between the memory circuit and a logic circuit provided in a previous stage of the memory circuit, and includes a first input terminal and a second input terminal.
The step (a) includes:
Connecting the second input terminal and the logic circuit;
The step (b)
A method comprising: generating a second RTL description model by forming a signal path connecting the output terminal of the switch and the first input terminal and connecting the second terminal and the output terminal of the memory circuit. A program that causes a computer to execute. A semiconductor design support apparatus that supports design of a semiconductor device that constitutes a predetermined logic circuit by a user arbitrarily writing logic ,
A circuit design apparatus for generating a first RTL description model based on a logic design model of a semiconductor device;
A circuit changing device for converting the first RTL description model into a second RTL description model;
A logic synthesis device for mapping the second RTL description model to an FPGA primitive ;
The circuit design apparatus includes:
Identifying a memory circuit inside the semiconductor device, constructing a reset circuit of the memory circuit, and generating the first RTL description model;
The circuit changing device includes:
Based on the first RTL description model, the second RTL description model having a rewrite value input terminal for receiving a rewrite value of the storage circuit and a stored value supply terminal for receiving a value held by the storage circuit,
The logic synthesis device includes:
Based on the second RTL description model, logic synthesis is performed to generate an FPGA netlist, mapping is performed based on the FPGA netlist,
The circuit changing device includes:
A first terminal for receiving the rewritten value supplied from the outside, a second terminal connected to the stored value supply terminal, and a value supplied via one of the first terminal and the second terminal A rewrite circuit model including a switch provided at a rewrite value input terminal is generated,
A semiconductor design support apparatus for generating the second RTL description model by connecting an output terminal of the switch and the rewrite value input terminal . In the semiconductor design support device according to claim 3 ,
The reset circuit includes a selection circuit that is provided between the memory circuit and a logic circuit provided in a previous stage of the memory circuit, and includes a first input terminal and a second input terminal.
The circuit design apparatus includes:
Connecting the second input terminal and the logic circuit;
The circuit changing device includes:
A semiconductor design support apparatus for generating the second RTL description model by forming a signal path connecting the output terminal of the switch and the first input terminal and connecting the second terminal and the output terminal of the memory circuit. A method of manufacturing a semiconductor device in which a user arbitrarily writes logic to constitute a predetermined logic circuit ,
(A) the circuit design EDA generates a first RTL description model based on the logic design model of the semiconductor device;
(B) a circuit change EDA converting the first RTL description model into a second RTL description model;
(C) a logic synthesis tool performs logic synthesis to generate an FPGA netlist corresponding to the second RTL description model; and (d) manufactures an actual FPGA device based on the FPGA netlist. Comprising steps,
The step (a) includes:
Identifying a memory circuit inside the semiconductor device, configuring a reset circuit of the memory circuit to generate the first RTL description model,
The step (b)
Converting to a second RTL description model having a rewrite value input terminal for receiving a rewrite value of the memory circuit and a memory value supply terminal for receiving a value held by the memory circuit ;
A first terminal for receiving the rewritten value supplied from the outside, a second terminal connected to the stored value supply terminal, and a value supplied via one of the first terminal and the second terminal Generating a rewrite circuit model including a switch provided at a rewrite value input terminal;
Connecting the output end of the switch and the rewrite value input end to generate the second RTL description model . A method of manufacturing a semiconductor device . In the manufacturing method of the semiconductor device according to claim 5 ,
The reset circuit includes a selection circuit that is provided between a logic circuit provided in a preceding stage of the memory circuit and the memory circuit and has a first input terminal and a second input terminal,
The step (a) includes:
Connecting the second input terminal and the logic circuit;
The step (b)
Forming a signal path connecting the output terminal of the switch and the first input terminal, and connecting the second terminal and the output terminal of the memory circuit, and generating the second RTL description model. Device manufacturing method.

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