JP4574134B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high voltage MOS transistor structure capable of reducing the occupied area and reducing the resistance.

  The MOS transistor used for the output of the driver IC is required to have a high breakdown voltage and a low ON resistance. In order to increase the breakdown voltage of the MOS transistor, it is necessary to provide a diffusion layer in the channel region for relaxing the electric field applied to the drain electrode. Further, in order to make the MOS transistor have a low ON resistance, it is necessary to increase the width of the channel region.

  However, increasing the width of the channel region means increasing the chip size, which increases the cost. Therefore, by using parallel MOS transistors configured by dividing the width of the channel region, the width of the channel region can be increased without increasing the chip size.

Conventionally, in the case of a MOS transistor in which there is no difference between the source structure and the drain structure, the chip size is reduced while increasing the width of the channel region by alternately arranging the source region and the drain region in a matrix form. was there. For example, Patent Documents 1 and 2 show MOS transistors in which source regions and drain regions are alternately arranged in a matrix. In Patent Document 1 and Patent Document 2, when attention is paid to a certain drain region, the source region is adjacent to the upper, lower, left, and right directions via the gate electrode.
Japanese Patent Laid-Open No. 05-013759 (2nd page, FIG. 1) Japanese Patent Laid-Open No. 04-130667 (page 1-2, FIG. 1-3)

  The MOS transistors arranged in a matrix are applied when there is no difference between the source structure and the drain structure. However, since the MOS transistor used for the output of the driver IC has a high breakdown voltage characteristic, the drain structure must be different from the source structure.

  Therefore, an object of the present invention is to provide a semiconductor device having a MOS transistor structure that has a high breakdown voltage characteristic and a low ON resistance and can reduce the chip area.

The solution according to the present invention includes a first conductivity type diffusion well formed on a semiconductor substrate, a gate electrode formed in a lattice shape on the first conductivity type diffusion well, and alternately in regions partitioned by the gate electrode. A source region and a drain region, wherein the source region has a second conductivity type first diffusion layer formed in the first conductivity type diffusion well, and the drain region has The second conductivity type second diffusion layer formed between the first conductivity type diffusion wells and a position between the gate electrode and the second diffusion layer so as to surround the second diffusion layer. A separation film formed so that a part of the gate electrode rides on, and a second conductive layer provided below the separation film so as to surround the second diffusion layer and having an impurity concentration lower than that of the second diffusion layer. have a third diffusion layer of the mold, a plurality of adjacent said drain All or part of the region, said isolation layer and said third diffusion layer is present continuously therebetween.

A semiconductor device according to the present invention includes a first conductivity type diffusion well formed in a semiconductor substrate, a gate electrode formed in a lattice shape on the first conductivity type diffusion well, and a region partitioned by the gate electrode. A semiconductor device including alternately formed source and drain regions, wherein the source region has a first conductivity type first diffusion layer formed in a first conductivity type diffusion well, and the drain region is A second diffusion layer of the second conductivity type formed between the first conductivity type diffusion wells and a position between the gate electrode and the second diffusion layer so as to surround the second diffusion layer A separation film formed so that a part of the gate electrode rides on the second diffusion layer, and provided below the separation film so as to surround the second diffusion layer, and having a lower impurity concentration than the second diffusion layer; Since it has a conductive type third diffusion layer, it has high breakdown voltage characteristics and low While having a N resistance, there is an effect that can allow the area of the chip size. Since all or a part of the adjacent drain regions have the separation film and the third diffusion layer continuously between each other, the width of all the channel regions can be configured with the minimum width, and the current efficiency Has the effect of improving. There is also an effect of reducing the area.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

(Embodiment 1)
FIG. 1 shows a plan view of a semiconductor device according to the present embodiment. The semiconductor device in FIG. 1 is a high voltage MOS transistor (hereinafter also simply referred to as a MOS transistor) formed on a semiconductor substrate, and a plurality of source regions 2 are formed in a region partitioned by a gate electrode 1 formed in a lattice shape. And drain regions 3 are provided in a matrix. A cross-sectional view of a portion indicated by a broken line A shown in FIG. 1 is shown in FIG. 2, and a cross-sectional view of a broken line B is shown in FIG.

  2 and 3, a p-type diffusion well 4 is formed in a semiconductor substrate, and the gate electrode 1 is formed in a lattice shape in the p-type diffusion well 4 via a gate insulating film. Note that the description of the gate insulating film is omitted in the drawings of this embodiment mode and the following embodiment modes. A source region 2 or a drain region 3 is formed in a region partitioned by the gate electrode 1. An n-type diffusion layer 5 is provided in the source region 2. An n-type diffusion layer 6 is also provided in the drain region 3. Further, in the drain region 3, a LOCOS (Local Oxidation of Silicon) oxide film 7, which is a separation film, is provided between the n-type diffusion layer 6 and the gate electrode 1. In the present embodiment, the n-type diffusion layer 6 is provided so as to surround the LOCOS oxide film 7. The gate electrode 1 is formed on a part of the LOCOS oxide film 7. Further, in the drain region 3, an n-type diffusion layer 8 having a lower impurity concentration than the n-type diffusion layer 6 is provided under the LOCOS oxide film 7. The n-type diffusion layer 8 is provided from the n-type diffusion layer 6 to the gate electrode 1 and surrounds the n-type diffusion layer 6.

  An interlayer insulating film 9 is provided on the gate electrode 1. The interlayer insulating film 9 is provided with a hole 10 for exposing the n-type diffusion layer 5 in the source region 2 and a hole 11 for exposing the n-type diffusion layer 6 in the drain region 3. A source wiring 12 is embedded in the hole 10, and a drain wiring 13 is embedded in the hole 11. 2 and 3, the n-type diffusion well 14 is provided in the drain region 3 at a position including a part of the n-type diffusion layer 6 and the n-type diffusion layer 8. By providing the n-type diffusion well 14, the electric field in the drain region can be gradually reduced. However, the object of the present invention can be achieved without providing the n-type diffusion well 14.

  The relationship between the plan view of FIG. 1 and the cross-sectional view of FIG. 2 will be described. First, the inner solid line in the source region 2 shown in FIG. 1 indicates the hole 10, and the outer solid line indicates the boundary line between the gate electrode 1 and the n-type diffusion layer 5. Next, the solid line of the drain region 3 shown in FIG. 1 indicates the hole 11, the boundary line between the n-type diffusion layer 6 and the LOCOS oxide film 7, and the gate electrode 1 riding on the LOCOS oxide film 7 in order from the innermost solid line. The boundary line is shown. A broken line of the drain region 3 shown in FIG. 1 indicates a boundary line between the n-type diffusion well and the p-type diffusion well. Further, the thick line of the drain region 3 shown in FIG. 1 indicates the boundary where the gate electrode 1 rides on the LOCOS oxide film 7. The plan view of the present embodiment and the following embodiments has the same configuration.

  In the present embodiment, the source region 2 and the gate region 3 are arranged in a matrix in the region partitioned by the gate electrode 1. The drain region 3 is disposed adjacent to the four sides of the source region 2. However, in the present embodiment, the source structure and the drain structure are different in order to have a high breakdown voltage characteristic. In FIG. 2, the drain structure constituted by the n-type diffusion layer 6, the LOCOS oxide film 7 and the n-type diffusion layer 8 is larger than the source structure constituted only by the n-type diffusion layer 5. Therefore, in order to simply arrange the source structure and the gate structure in a matrix, it is necessary to set the size of the region partitioned by the gate electrode 1 in accordance with the drain structure having a large structure. In this case, the source structure is also matched to the size of the drain structure, which increases the chip size and increases the cost.

  Therefore, in this embodiment, as shown in FIGS. 2 and 3, the size of the region partitioned by the gate electrode 1 is set on the basis of the size of the source structure, and the LOCOS oxidation which is a part of the drain structure is set. The gate electrode 1 is configured to run on the film 7. With this configuration, the region partitioned by the gate electrode 1 can be reduced according to the size of the source structure, the chip size can be reduced, and the cost can be reduced.

  Even in this embodiment, the drain structure basically does not change, so that high breakdown voltage characteristics can be maintained. In the configuration as in the present embodiment, the width of the channel region is not the same as the width of the gate electrode 1, and no channel is formed in the portion of the gate electrode 1 riding on the LOCOS oxide film 7. As a result, in the MOS transistor shown in FIG. 1, the channel region is formed so as to meander from side to side or up and down instead of a linear lattice. However, since the channel region is formed on the four sides in the source region 2 and the drain region 3, the ON resistance can be sufficiently lowered as compared with the conventional case. Note that a channel region is formed on only three sides at the end of the MOS transistor, and a channel region is formed only on two sides at the corner of the MOS transistor.

  In FIG. 1, a hole 15 is provided at the end of the gate electrode 1 for connection to another wiring. At the end of the MOS transistor, the end of the source region 2 is only the n-type diffusion layer 5, but the end of the drain region 3 is formed with the LOCOS oxide film 7 and the gate electrode 1. The LOCOS oxide film 7 and the gate electrode 1 at the end of the drain region 3 are also shown in FIG. Further, in FIG. 1, the corner portion of the drain region 3 is formed by an arc instead of a right angle. That is, the corner portion of the LOCOS oxide film 7 surrounding the n-type diffusion layer 6 is formed by an arc. For this reason, the MOS transistor according to the present embodiment has no portion where the electric field is concentrated in a plane, and high breakdown voltage characteristics can be obtained.

As described above, the semiconductor device described in this embodiment includes the p-type diffusion well 4 formed in the semiconductor substrate, the gate electrode 1 formed in a lattice shape on the p-type diffusion well 4, and the gate electrode. 1 is a semiconductor device including source regions 2 and drain regions 3 alternately formed in regions partitioned by 1, and the source region 2 has an n-type diffusion layer 5 formed in a p-type diffusion well 4. The drain region 3 surrounds the n-type diffusion layer 6 at a position between the n-type diffusion layer 6 formed between the p-type diffusion wells 4 and the gate electrode 1 and the n-type diffusion layer 6. LOCOS oxide film 7 formed so that a part of gate electrode 1 rides on, and is provided at a position below LOCOS oxide film 7 so as to surround n-type diffusion layer 6. Has an n-type diffusion layer 8 having a low impurity concentration. It has a low ON-resistance and breakdown voltage characteristics can allow the area of the chip size.

  In the semiconductor device described in the present embodiment, the n-type diffusion well 14 is provided so that the drain region 3 includes the n-type diffusion layer 6 and a part of the n-type diffusion layer 8. The electric field of the drain region 3 can be relaxed stepwise.

  Furthermore, in the semiconductor device described in the present embodiment, the size of the source structure constituted by the n-type diffusion layer 5 is the drain constituted by the n-type diffusion layer 6, the LOCOS oxide film 7 and the n-type diffusion layer 8. Since the size of the region smaller than the size of the structure and partitioned by the gate electrode 1 is determined based on the size of the source structure, the chip size can be further reduced.

  In the present embodiment, the separation film has been described as the LOCOS oxide film 7. However, the present invention is not limited to this and may be a trench oxide film or the like.

(Embodiment 2)
FIG. 4 is a plan view of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 4 is a high voltage MOS transistor formed on a semiconductor substrate, and a plurality of source regions 2 and drain regions 3 are arranged in a matrix in a region partitioned by a gate electrode 1 formed in a lattice shape. Is provided. FIG. 5 shows a cross-sectional view of the broken line C portion shown in FIG. 4, and FIG. 6 shows a cross-sectional view of the broken line D.

  The cross-sectional view shown in FIG. 5 has the same configuration as the cross-sectional view of FIG. 2 shown in the first embodiment. However, the cross-sectional view shown in FIG. 6 is different from the cross-sectional view of FIG. 3 shown in the first embodiment. The difference between the present embodiment and the first embodiment is that adjacent drain regions 3 are connected to each other by a LOCOS oxide film 7 and an n-type diffusion layer 8.

  More specifically, in FIGS. 5 and 6, a p-type diffusion well 4 is formed in a semiconductor substrate, and the gate electrode 1 is formed in a lattice shape in the p-type diffusion well 4 with a gate insulating film interposed therebetween. A source region 2 or a drain region 3 is formed in a region partitioned by the gate electrode 1. An n-type diffusion layer 5 is provided in the source region 2. An n-type diffusion layer 6 is also provided in the drain region 3. Further, in the drain region 3, a LOCOS oxide film 7, which is a separation film, is provided between the n-type diffusion layer 6 and the gate electrode 1. In the present embodiment, the LOCOS oxide film 7 is provided so as to surround the n-type diffusion layer 6 and the adjacent drain regions 3 are connected to each other. It is extended.

  Further, as shown in FIG. 5, the gate electrode 1 is formed on a part of the LOCOS oxide film 7 in a portion where the source region 2 and the drain region 3 are adjacent to each other. However, as shown in FIG. A portion where the three are adjacent to each other is formed on the LOCOS oxide film 7. Further, in the drain region 3, an n-type diffusion layer 8 having a lower impurity concentration than the n-type diffusion layer 6 is provided under the LOCOS oxide film 7. The n-type diffusion layer 8 is provided from the n-type diffusion layer 6 to the gate electrode 1 and surrounds the n-type diffusion layer 6. The n-type diffusion layer 8 connects the n-type diffusion layers 6 in the adjacent drain regions 3 to each other.

  An interlayer insulating film 9 is provided on the gate electrode 1. The interlayer insulating film 9 is provided with a hole 10 for exposing the n-type diffusion layer 5 in the source region 2 and a hole 11 for exposing the n-type diffusion layer 6 in the drain region 3. A source wiring 12 is embedded in the hole 10, and a drain wiring 13 is embedded in the hole 11. 5 and 6, the n-type diffusion well 14 is provided in the drain region 3 at a position including a part of the n-type diffusion layer 6 and the n-type diffusion layer 8. By providing the n-type diffusion well 14, the electric field in the drain region can be gradually reduced. However, the object of the present invention can be achieved without providing the n-type diffusion well 14.

  Also in this embodiment, as shown in FIGS. 5 and 6, the size of the region partitioned by the gate electrode 1 is set with reference to the size of the source structure, and the LOCOS oxide film 7 which is a part of the drain structure is set. The gate electrode 1 is configured to ride on the top. With this configuration, the region partitioned by the gate electrode 1 can be reduced according to the size of the source structure, the chip size can be reduced, and the cost can be reduced.

  Even in this embodiment, the drain structure basically does not change, so that high breakdown voltage characteristics can be maintained. In the configuration as in the present embodiment, the channel region is not formed in the portion of the gate electrode 1 riding on the LOCOS oxide film 7. Further, no channel region is formed under the LOCOS oxide film 7 and the n-type diffusion layer 8 that connect adjacent drain regions 3. As a result, in the MOS transistor shown in FIG. 4, the channel region is formed in a ring shape surrounding the source region 2 instead of the lattice shape. However, since the channel region is formed on the four sides in the source region 2 and the drain region 3, the ON resistance can be sufficiently lowered as compared with the conventional case. Note that a channel region is formed on only three sides at the end of the MOS transistor, and a channel region is formed only on two sides at the corner of the MOS transistor.

  In FIG. 6, all adjacent drain regions 3 are connected to each other by the LOCOS oxide film 7 and the n-type diffusion layer 8. However, according to the present invention, it is not necessary to connect all the adjacent drain regions 3 as shown in FIG. 6, and only a part of the adjacent drain regions 3 may be connected. For example, FIG. 7 shows a MOS transistor in which some drain regions 3 adjacent to each other are connected. FIG. 8 shows a cross-sectional view of the broken line E portion shown in FIG. 7, and FIG. 9 shows a cross-sectional view of the broken line F. Although the adjacent drain regions 3 are not connected to each other in the direction of the broken line E shown in FIG. 8, the adjacent drain regions 3 are connected to the LOCOS oxide film 7 and the n-type diffusion layer 8 in the downward direction of the broken line shown in FIG. Connected by. Note that FIG. 7 is an example, and how the adjacent drain regions 3 are connected to each other is arbitrary.

  In FIG. 4, the corner portion of the drain region 3 is not a right angle but an arc. That is, the corner portion of the LOCOS oxide film 7 surrounding the n-type diffusion layer 6 is formed by an arc. For this reason, the MOS transistor according to the present embodiment has no portion where the electric field is concentrated in a plane, and high breakdown voltage characteristics can be obtained.

  As described above, in the semiconductor device described in this embodiment, the LOCOS oxide film 7 and the n-type diffusion layer 8 are continuously present between all or a part of the plurality of adjacent drain regions. The width of all the channel regions can be configured with the minimum width, and the current efficiency is improved. There is also an effect of reducing the area.

  In the present embodiment, the separation film is described as the LOCOS oxide film 7, but the present invention is not limited to this and may be a trench oxide film or the like.

(Embodiment 3)
FIG. 10 is a plan view of the semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 10 is a high breakdown voltage MOS transistor formed on a semiconductor substrate, and a plurality of source regions 2 and drain regions 3 are arranged in a matrix in a region partitioned by a gate electrode 1 formed in a lattice shape. Is provided. FIG. 11 shows a cross-sectional view of the broken line G portion shown in FIG. A broken line of the source region 2 shown in FIG. 10 indicates a boundary line between the n-type diffusion layer 5 and the p-type diffusion layer 16.

  The cross-sectional view shown in FIG. 11 has substantially the same configuration as the cross-sectional view of FIG. 2 shown in the first embodiment. However, FIG. 11 differs from FIG. 2 in that a p-type diffusion layer 16 is provided in the center of the n-type diffusion layer 5 in the source region 2. The p-type diffusion layer 16 connects the p-type diffusion well 4 and the source wiring 12. In the present embodiment, the p-type diffusion layer 16 is provided in all the source regions 2.

  In a MOS transistor in which a plurality of source regions 2 and drain regions 3 are arranged in a matrix as in this embodiment, the substrate electrode is provided on the outer periphery of the MOS transistor. However, when the source region 2 and the drain region 3 to be arranged are increased, the distance between the central portion and the outer peripheral portion of the MOS transistor becomes large, and the substrate potential at the central portion becomes unstable. When the substrate potential becomes unstable, the breakdown voltage in the source region 2 may be deteriorated. Therefore, in the present embodiment, in order to stabilize the substrate potential, the p-type diffusion layer 16 that is the substrate electrode region is provided in the center of the n-type diffusion layer 5 in the source region 2. Since this p-type diffusion layer 16 connects the p-type diffusion well 4 and the source wiring 12, the substrate potential in each source region 2 is stabilized. In the present embodiment, it is possible to prevent the breakdown voltage in the source region 2 from being deteriorated and to be strong against latch-up.

  In FIG. 10, one hole 10 in which the source wiring 12 is buried is provided for each source region 2. The present invention is not limited to this, and a plurality of miniaturized small-diameter holes may be provided for each source region 2. FIG. 12 is a plan view of a MOS transistor in which a plurality of holes are provided for each source region 2. In FIG. 12, five holes 17 are provided in each source region 2. In the holes 17, four holes 17 a are arranged on the n-type diffusion layer 5, and one hole 17 b is arranged on the p-type diffusion layer 16. In FIG. 12, also in the drain region 3, four miniaturized small-diameter holes 18 are provided.

  As described above, in the semiconductor device described in this embodiment, the source region includes the p-type substrate electrode region that connects the p-type diffusion well 4 and the source wiring 12 to a part of the n-type diffusion layer 5. Therefore, the substrate potential is stabilized, it is possible to prevent the breakdown voltage degradation in the source region 2, and it is strong against latch-up. Further, if the source and the substrate are driven with the same potential, the substrate wiring and the source wiring can be made common, and the degree of freedom of wiring increases.

(Embodiment 4)
FIG. 13 shows a cross-sectional view of the end portion of the MOS transistor according to this embodiment. FIG. 13 is an enlarged view of the end portion of the MOS transistor shown in FIGS. 1 and 2, and the gate electrode 1 is formed on the LOCOS oxide film 7 at the end in the drain region 3 located at the end portion. Originally, since it is not necessary to form a channel at the end, it is not necessary to provide the gate electrode 1. FIG. 14 is a cross-sectional view when the gate electrode 1 is not formed on the terminal LOCOS oxide film 7.

  Next, a high voltage is applied to the drain wiring 13 at the end of the MOS transistor shown in FIG. Note that in the OFF state of the MOS transistor, the gate potential and the substrate potential are the same. When a high voltage is applied to the drain wiring 13, an n-type inversion layer 19 is generated on the surface of the p-type diffusion well 4 below the LOCOS oxide film 7. The n-type inversion layer 19 is electrically connected to the n-type diffusion layer 6 and the n-type diffusion layer 8. Therefore, the charges in the n-type diffusion layer 6 and the n-type diffusion layer 8 leak to the source region 2 or the like through the n-type inversion layer 19. As described above, there is a problem that a leak path from the drain region occurs at the end of the MOS transistor.

  Therefore, in this embodiment, the gate electrode 1 is provided on the terminal LOCOS oxide film 7 as shown in FIG. Thus, even if a high voltage is applied to the drain wiring 13 when the MOS transistor is OFF, the n-type inversion layer is shielded by the gate electrode 1 having the same potential as that of the substrate and is formed on the surface of the p-type diffusion well 4 below the LOCOS oxide film 7. 19 no longer occurs. As a result, in this embodiment, the problem that a leak path is generated at the MOS transistor end is avoided.

  As described above, in the semiconductor device described in the present embodiment, the drain region 3 located at the end of the region partitioned by the gate electrode 1 has the gate electrode 1 on the terminal LOCOS oxide film 7. Therefore, the leak path from the drain region 3 at the end can be blocked.

(Embodiment 5)
FIG. 15 is a plan view of the MOS transistor according to the present embodiment. In the MOS transistor shown in FIG. 1 of Embodiment 1, the end portion is the source region 2 or the drain region 3. However, in the present embodiment, all the end portions are arranged to be the source region 2. In FIG. 15, the n-type diffusion layer 5 and the p-type diffusion layer 16 whose end portions are the source regions 2 are formed. However, in the present embodiment, the drain region 3 is arranged so as to be adjacent to the four sides of the source region 2 in the present embodiment, except for the end portion. Therefore, at least one side of the source region located at the end is adjacent to the drain region.

  Since the drain structure has a high breakdown voltage characteristic, a restriction is imposed on the pattern layout, but the source region 2 has no such restriction. In the present embodiment, since all of the end portions are the source regions 2, the degree of freedom of pattern layout is increased as compared with the case where the drain regions 3 are located at the end portions. Also, as described in the fourth embodiment, when the drain region 3 is at the end, it is necessary to pay attention to the leak path, but when the source region 2 is at the end, this is not necessary.

  As described above, in the semiconductor device described in this embodiment, since the source region 2 is all disposed at the end of the region partitioned by the gate electrode 1, the entire periphery of the drain region 3 is separated by the channel. Therefore, there is no worry about the leakage path, and it is not necessary to consider the end pattern of the drain region 3, so that the degree of freedom in pattern layout increases. In addition, since there is no worry about the leakage path, separation and arrangement from other circuit elements adjacent to the MOS transistor become easy.

  In FIG. 15, the corner portion of the drain region 3 is not a right angle but an arc. That is, the corner portion of the LOCOS oxide film 7 surrounding the n-type diffusion layer 6 is formed by an arc. For this reason, the MOS transistor according to the present embodiment has no portion where the electric field is concentrated in a plane, and high breakdown voltage characteristics can be obtained. Furthermore, the substrate potential is further stabilized by surrounding the MOS transistor with the source wiring 12 and providing the p-type diffusion layer 16 as the substrate electrode.

(Embodiment 6)
In the present embodiment, the electrode material of the gate electrode 1 in the above-described embodiment is composed of a low resistance material. Here, the low-resistance material used for the gate electrode 1 shown in FIG. 1 includes silicide-based materials such as tungsten silicide, titanium silicide, cobalt silicide, and nickel silicide.

  As in the present invention, in the MOS transistor in which the source region 2 and the drain region 3 are arranged in a matrix, it is necessary to provide the input portion of the gate electrode on the outer periphery of the MOS transistor. Therefore, as the MOS transistor becomes larger, the gate electrode 1 becomes longer and it becomes difficult to obtain a stable gate potential. Therefore, it is necessary to provide a large number of holes 15 for connecting to the gate electrode 1, which may increase the pattern layout area and increase the cost.

  Therefore, in the semiconductor device described in the present embodiment, the gate electrode 1 is formed of a silicide-based material such as tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide. The number of 15 can be reduced and the cost can be reduced.

(Embodiment 7)
In the present embodiment, the substrate surfaces of the n-type diffusion layer 5 and the n-type diffusion layer 6 are silicided in the above embodiment. FIG. 16 shows a cross-sectional view of the MOS transistor according to the present embodiment. The cross-sectional view shown in FIG. 16 has substantially the same configuration as the cross-sectional view of FIG. 2 shown in the first embodiment. However, FIG. 16 differs from FIG. 2 in that a silicide film 20 is formed on the surfaces of the n-type diffusion layer 5 in the source region 2 and the n-type diffusion layer 6 in the drain region 3. By forming the silicide film 20 on the surfaces of the n-type diffusion layer 5 and the n-type diffusion layer 6, the contact resistance with the source wiring 12 and the drain wiring 13 is lowered. Also, the resistance of the diffusion region between the contact and the channel can be reduced.

  An object of the present invention is to reduce the area of a MOS transistor by arranging the source region 2 and the drain region 3 in a matrix and increasing the current efficiency per unit area to reduce the resistance. . Therefore, in each source region 2 and each drain region 3, the contact portion with the source wiring 12 and the drain wiring 13 is also reduced in area. However, a reduction in the area of the contact portion causes a problem that causes an increase in contact resistance.

  Therefore, in the semiconductor device described in the present embodiment, the silicidation film 20 is formed by silicidizing the surfaces of the n-type diffusion layer 5 and the n-type diffusion layer 6, so that the source wiring 12 and the drain wiring 13 are formed. Contact resistance is reduced. Further, by reducing the contact resistance, the diameter of the holes 10 and 11 can be reduced, and the number of the plurality of holes 17 and 18 shown in the third embodiment can be reduced. Increased freedom.

  Further, in the case where the p-type diffusion layer 16 of the substrate electrode shown in the third embodiment is provided in the n-type diffusion layer 5, both the surfaces of the p-type diffusion layer 16 and the n-type diffusion layer 5 are silicided to form one silicide. The film 20 is formed. Therefore, as shown in FIG. 12, it is not necessary to divide into the holes 17a of the n-type diffusion layer 5 and the holes 17b of the p-type diffusion layer 16, and only have to be provided on the silicided film 20. As a result, the degree of freedom increases in the pattern layout of holes and wirings.

(Embodiment 8)
FIG. 17 is a plan view of the source wiring 12 and the drain wiring 13 according to this embodiment. In FIG. 17, the source wiring 12 extending from the two sides of the outer peripheral wiring 21 and the drain wiring 13 extending from the two sides of the other outer peripheral wiring 22 are provided so as to be alternately parallel. The outer peripheral wiring 21 and the outer peripheral wiring 22 are electrically insulated. Each source wiring 12 and each drain wiring 13 are wiring layers provided in the MOS transistor shown in FIG. For this reason, each source line 12 is provided in a substantially 45 degree direction that is a diagonal direction along the source region 2 of FIG. Each drain wiring 13 is also provided in a substantially 45 degree direction which is a diagonal direction along the drain region 3 of FIG.

  Each source wiring 12 in FIG. 17 shows a portion corresponding to the hole 10. Further, each drain wiring 13 in FIG. 17 shows a portion corresponding to the hole 11. FIG. 17 shows the gate wiring 23 connected to the gate electrode 1. The gate wiring 23 also shows a portion corresponding to the hole 15.

  As described above, in the semiconductor device described in this embodiment, the source wiring 12 connected to the plurality of n-type diffusion layers 5 and the drain wiring 13 connected to the plurality of n-type diffusion layers 6 are provided. In addition, since the source wiring 12 and the drain wiring 13 are alternately wired in parallel, the lengths of the source wiring 12 and the drain wiring 13 can be optimized.

(Embodiment 9)
FIG. 18 is a plan view of the source wiring 12 and the drain wiring 13 according to this embodiment. In FIG. 18, unlike FIG. 17, only the source wiring 12 extends from the four sides of the outer peripheral wiring 24. The drain wiring 13 is alternately arranged in parallel with the source wiring 12, but is not connected to the outer peripheral wiring 24. Furthermore, in the present embodiment, an upper layer wiring 25 is provided in the upper layer of the source wiring 12 and along the outer peripheral wiring 24. The upper layer wiring 25 and the source wiring 12 are connected by a via hole 26 provided on the outer peripheral wiring. Further, an upper layer wiring 27 is provided in the upper layer of the drain wiring 13 and in the central portion of the semiconductor device. The upper wiring 27 and the drain wiring 13 are connected by a via hole 28 provided between the holes 11. The upper layer wiring 25 is provided so as to surround the upper layer wiring 27.

  In the source wiring 12 and the drain wiring 13 shown in FIG. 17, the distance from the outer peripheral wiring 21 to the end of the source wiring 12 and the distance from the outer peripheral wiring 22 to the end of the drain wiring 13 as the chip area of the MOS transistor increases. Becomes larger. For this reason, the resistance to the ends of the source wiring 12 and the drain wiring 13 increases, and the potential may become unstable. In the present embodiment, the drain wiring 13 is separated from the outer peripheral wiring 24 and connected to the upper wiring 27 to form a two-layer structure, thereby reducing the resistance. The source wiring 12 can be connected to the four sides of the outer peripheral wiring 24 because the drain wiring 13 is separated from the outer peripheral wiring 24, and further connected to the upper wiring 25 to reduce the resistance. I am trying. The source wiring 12 may be separated from the outer peripheral wiring 24 and connected to the upper wiring 27, and the drain wiring 13 may be connected to the four sides of the outer peripheral wiring 24 and connected to the upper wiring 25.

  As described above, in the semiconductor device described in this embodiment, the upper-layer wiring disposed in the center of the semiconductor device that is electrically connected to one of the source wiring 12 or the drain wiring 13 through the plurality of via holes 28. 27, and an upper layer wiring 25 that is electrically connected to the other of the source wiring 12 or the drain wiring 13 via a plurality of via holes 26 and is disposed at a position surrounding the upper layer wiring 27. The drain wiring 13 can be further reduced in resistance.

(Modification)
FIG. 19 is a plan view of the source wiring 12 and the drain wiring 13 according to a modification of the present embodiment. Also in FIG. 19, the drain wiring 13 is separated from the outer peripheral wiring 24 and connected to the upper layer wiring 27 to form a two-layer structure as in FIG. 18. The source wiring 12 is connected to the four sides of the outer peripheral wiring 24 and further connected to the upper wiring 25 to form a two-layer structure. However, in FIG. 19, a new source wiring 29 is provided so as to connect the source wirings 12 arranged in the diagonal direction. The new source line 29 is orthogonal to each source line 12 arranged in the diagonal direction. Since the new source wiring 29 is provided, each drain wiring 13 is divided at the center.

  In the source wiring 12 shown in FIG. 18, the distance to the center of the MOS transistor increases as the chip area of the MOS transistor increases. For this reason, the resistance of the source line 12 to the center of the MOS transistor increases, and the potential may become unstable. Therefore, in this modified example, a new source line 29 that is orthogonal to each source line 12 arranged in the diagonal direction and passes through the central portion of the MOS transistor is provided. Alternatively, the source wiring 12 may be separated from the outer peripheral wiring 24, the drain wiring 13 may be connected to the four sides of the outer peripheral wiring 24, and a new drain wiring orthogonal to the drain wiring 13 may be provided.

  As described above, in the semiconductor device described in the present modification, the source wiring 12 or the drain wiring 13 connected to the upper layer wiring 25 further includes a wiring orthogonal to the wiring pattern. The resistance value can be made uniform.

(Embodiment 10)
FIG. 20 is a plan view of the source wiring 12 and the drain wiring 13 according to a modification of the present embodiment. 20, source wirings 12 extending from two sides of the outer peripheral wiring 21 and drain wirings 13 extending from two sides of the other outer peripheral wiring 22 are alternately provided in parallel as in FIG. The outer peripheral wiring 21 and the outer peripheral wiring 22 are electrically insulated. However, in FIG. 20, upper layer wirings 30 and 31 are provided on the source wiring 12 and the drain wiring 13. The upper layer wiring 30 is connected to the outer peripheral wiring 21 and the source wiring 12 by a via hole 32 provided on the outer peripheral wiring 21 and the source wiring 12. Further, the upper layer wiring 31 is connected to the outer peripheral wiring 22 and the drain wiring 13 by a via hole 33 provided on the outer peripheral wiring 22 and the drain wiring 13. The upper layer wiring 30 is a wiring that covers the outer wiring 21 and the lower half of the MOS transistor, and the upper wiring 31 is a wiring that covers the outer wiring 22 and the upper half of the MOS transistor.

  In the source wiring 12 and the drain wiring 13 shown in FIG. 17, the distance from the outer peripheral wiring 21 to the end of the source wiring 12 and the distance from the outer peripheral wiring 22 to the end of the drain wiring 13 as the chip area of the MOS transistor increases. Becomes larger. For this reason, the resistance to the ends of the source wiring 12 and the drain wiring 13 increases, and the potential may become unstable. In the present embodiment, the source wiring 12 is connected to the upper layer wiring 30 to form a two-layer structure, and the drain wiring 13 is connected to the upper layer wiring 31 to form a two-layer structure, thereby reducing the resistance. The layout of the upper layer wirings 30 and 31 is not limited to that shown in FIG.

  As described above, in the semiconductor device described in the present embodiment, the upper-layer wiring 30 that is electrically connected to the source wiring 12 through the plurality of via holes 32 and disposed in a substantially half region of the semiconductor device; Since the upper wiring 31 is further provided which is electrically connected to the drain wiring 13 through the plurality of via holes 33 and is disposed in a substantially half region of the remaining semiconductor device, the source wiring 12 and the drain wiring 13 are further reduced. It can be made resistant.

(Embodiment 11)
Wirings such as the source wiring 12 and the drain wiring 13 are formed using a lithography technique. For this reason, the formed wiring is affected by the resolution of the exposure apparatus. In recent years, the exposure apparatus has been improved by using modified illumination for miniaturization of wiring. However, these improvements improve the resolution only in a specific direction of the exposure apparatus, and degrade the resolution in other directions. The direction in which the exposure characteristic is improved is set in a direction parallel or perpendicular to the side of the chip on which the MOS transistor is formed. The directions parallel or perpendicular to the side of the chip are defined as the X direction and the Y direction.

  In FIG. 17 of the eighth embodiment, the source wiring 12 and the drain wiring 13 are formed in a 45 degree direction with respect to the X direction and the Y direction. In such a case, a desired wiring shape may not be obtained. In FIG. 17, the horizontal direction is the X direction and the vertical direction is the Y direction. The same applies to other plan views according to the present invention. Therefore, in the present embodiment, the patterns of the source wiring 12 and the drain wiring 13 are formed in accordance with the exposure characteristics. FIG. 21 shows a pattern of the source wiring 12 and the drain wiring 13 in accordance with the exposure characteristics. In FIG. 21, the source wiring 12 extending from the two sides of the outer peripheral wiring 21 and the drain wiring 13 extending from the two sides of the other outer peripheral wiring 22 are provided alternately in parallel. Each source line 12 and each drain line 13 are provided substantially in the Y direction. In order to obtain the pattern of the source wiring 12 and the drain wiring 13 shown in FIG. 21, it is necessary to make the arrangement of the MOS transistors shown in FIG. This embodiment is effective when the processing dimensions of the source wiring 12 and the drain wiring 13 are stricter than the processing dimensions of the MOS transistor.

  In the case of the arrangement of the source region 2 and the drain region 3 of the MOS transistor shown in FIG. 15, a comb-shaped source wiring 12 and drain wiring 13 as shown in FIG. In FIG. 22, all of the wiring is configured in the X direction or the Y direction, so that the high-resolution part of the exposure apparatus can be used. Furthermore, it can be aligned with the pattern direction of the gate wiring.

  As described above, in the semiconductor device described in this embodiment, the source wiring 12 and the drain wiring 13 are arranged so that the wiring pattern directions of the source wiring 12 and the drain wiring 13 are parallel or perpendicular to the sides of the chip. 13 fine processing can be performed stably.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 4 of this invention. It is a top view of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing of the semiconductor device which concerns on Embodiment 7 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on Embodiment 8 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on Embodiment 9 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on the modification of Embodiment 9 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on Embodiment 10 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on Embodiment 11 of this invention. It is a top view of the source wiring 12 and the drain wiring of the semiconductor device which concerns on Embodiment 11 of this invention.

Explanation of symbols

1 gate electrode, 2 source region, 3 drain region, 4 p-type diffusion well, 5, 6, 8 n-type diffusion layer, 7 LOCOS oxide film, 9 interlayer insulation film, 10, 11, 15, 17, 18 holes, 12 29 source wiring, 13 drain wiring, 14 n-type diffusion well, 16 p-type diffusion layer, 19 n-type inversion layer, 20 silicidation film, 21, 22, 24 peripheral wiring, 23 gate wiring, 25, 27, 30, 31 Upper layer wiring, 26, 28, 32, 33 Via holes.

Claims (10)

A first conductivity type diffusion well formed in a semiconductor substrate;
A gate electrode formed in a lattice shape on the first conductivity type diffusion well;
A semiconductor device comprising a source region and a drain region alternately formed in regions partitioned by the gate electrode,
The source region includes a first conductivity type first diffusion layer formed in the first conductivity type diffusion well,
The drain region is
A second conductivity type second diffusion layer formed between the first conductivity type diffusion wells;
A separation membrane provided so as to surround the second diffusion layer at a position between the gate electrode and the second diffusion layer, and formed so that a part of the gate electrode rides on the second diffusion layer;
Wherein under the separation membrane, the second is provided so as to surround the diffusion layers, it has a third diffusion layer of the second impurity concentration lower than the diffusion layer and the second conductivity type,
All or part of the plurality of adjacent drain regions are characterized in that the separation film and the third diffusion layer are continuously present between each other .
Semiconductor device. The semiconductor device according to claim 1,
Said drain region, said second diffusion layer and is characterized that you have a second conductivity type diffusion well is provided so as to encompass a portion of the third diffusion layer,
Semiconductor device. The semiconductor device according to claim 1 or 2, wherein
The source region is characterized Rukoto comprises a first of said substrate electrode region of the first conductivity type which connects the first conductivity type diffusion well and the source lines in a part of the diffusion layer,
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
In the drain region located at the end of the region partitioned by the gate electrode, the gate electrode is provided on the separation film at the end ,
Semiconductor device. A semiconductor device according to any one of claims 1 to 3 ,
The source region is all disposed at the end of the region partitioned by the gate electrode,
Semiconductor device. A semiconductor device according to any one of claims 1 to 5 ,
The gate electrode is formed of a silicide-based material ,
Semiconductor device. A semiconductor device according to any one of claims 1 to 6,
Surface of the first diffusion layer and said second diffusion layer is characterized that you have to form a silicide film by siliciding,
Semiconductor device. A semiconductor device according to any one of claims 1 to 7,
The source wiring connected to a plurality of the first diffusion layers;
A plurality of drain wirings connected to the second diffusion layer,
The source wiring and the drain wiring are wired so as to be alternately parallel ,
Semiconductor device. The semiconductor device according to claim 8 ,
A first wiring disposed in the center of the semiconductor device, electrically connected to one of the source wiring or the drain wiring through a plurality of via holes;
Via said other of the plurality of via holes of the source wiring or the drain wiring are electrically connected, characterized Rukoto second wiring and further comprising a disposed at a position surrounding the first wire,
Semiconductor device. The semiconductor device according to claim 8 ,
The wiring pattern direction of the source wiring and the drain wiring is arranged parallel or perpendicular to the sides of the chip, characterized in Rukoto,
Semiconductor device.

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