JP4574302B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and is particularly effective when applied to a process of inspecting electrical characteristics by bringing a probe into contact with an extraction electrode formed in a chip region of a semiconductor wafer (hereinafter referred to as a wafer). Technology.

  Japanese Laid-Open Patent Publication No. 2002-018733 (Patent Document 1) is a cleaning disk made of a soft polymer material in which an abrasive is mixed and the tip of a contact pin can be pierced, and is substantially the same as a wafer. A technique for cleaning the tip portion of a contact pin using a cleaning disk formed in the outer shape of is disclosed.

  In Japanese Patent Laid-Open No. 10-339766 (corresponding US Pat. No. 6,130,104) (Patent Document 2), a soft cleaner having a cleaner layer made of a base material made of rubber and a filler dispersed in the base material, A technique for piercing a probe needle to remove a deposit on the needle tip is disclosed.

  In Japanese Unexamined Patent Publication No. 11-133116 (corresponding US Pat. No. 6,170,116) (Patent Document 3), the tip of the probe needle is pierced into a polishing sheet formed of a fibrous stainless steel in a mesh shape. A technique for removing foreign matters such as aluminum oxide adhering to the tip is disclosed.

  In Japanese Patent Laid-Open No. 11-087438 (corresponding US Pat. No. 6,056,627) (patent document 4), in the pulling-out operation of the probe tip from the cleaning member, the foreign matter reattached to the probe tip is removed by the foreign matter removing film. Technology is disclosed.

In Japanese Patent Laid-Open No. 2001-351554 (Patent Document 5), by providing an aluminum film for measuring the contact resistance value of the probe needle on a part of the cleaning sheet, it is immediately possible to know the cleaning time of the probe needle. A technique capable of cleaning the probe needle is disclosed.
JP 2002-018733 A Japanese Patent Laid-Open No. 10-339766 JP-A-11-133116 Japanese Patent Laid-Open No. 11-087438 JP 2001-351554 A

  Generally, in the process of manufacturing IC (Integrated Circuit) and LSI (Large Scale Integration), the process of testing the electrical characteristics of a semiconductor device formed in the chip area of a wafer to test whether it is a good product or a defective product. Exists. This process is performed by mounting the probe card on an apparatus called a prober and bringing the probe (probe) of the probe card into contact with a lead electrode (bonding pad) formed in the chip region of the wafer. Specifically, in the electrical contact between the probe and the extraction electrode, a predetermined pressure is further applied between the probe and the extraction electrode after the probe is brought into contact with the extraction electrode. As a result, the probe is displaced and the aluminum oxide formed on the surface of the extraction electrode is removed, and the underlying aluminum and the probe come into contact with low contact resistance.

  In the process of inspecting the electrical characteristics by bringing the probe into contact with the extraction electrode, foreign matters such as aluminum oxide adhering to the tip of the probe have an adverse effect on the electrical connection between the probe and the extraction electrode. May have an effect. For this reason, the tip of the probe is cleaned. The tip of the probe is cleaned, for example, by removing a foreign substance adhering to the tip of the probe by piercing the probe into a cleaning sheet containing an abrasive or a cleaning wafer having a cleaning sheet attached thereto.

  When the cleaning sheet is used, the probe is periodically pierced into the cleaning sheet placed outside the wafer while the electrical characteristics are inspected by bringing the probe into contact with the drawing electrode of the wafer. At this time, the position of the cleaning sheet that pierces the probe is changed for each cleaning. That is, the position of the cleaning sheet that pierces the probe moves while partially overlapping from the initial position (initial), and cleaning is performed. When switching electrical products and inspecting electrical characteristics, the probe can be cleaned by returning to the initial position of the cleaning sheet or by continuously changing the cleaning position. May be cleaned at the same location. At the position where the cleaning has already been performed, foreign matter remains on the cleaning sheet. Therefore, when cleaning is performed again at that location, there is a problem that the foreign matter reattaches to the probe.

  Further, when a cleaning wafer with a cleaning sheet attached is used, there is a problem that the probe cannot be cleaned while the electrical property inspection of the wafer is being performed. That is, when using a cleaning wafer, first, after the electrical property inspection of the wafer is completed, the wafer is removed from the prober stage. After the cleaning wafer is placed on the prober stage, cleaning is performed by piercing the probe of the cleaning wafer. As described above, since it is necessary to remove the wafer from the prober stage and newly arrange a cleaning wafer, there is a problem that the operating rate of the apparatus is lowered.

  One object of one invention disclosed in the present application is to provide a semiconductor device manufacturing technique capable of effectively removing foreign matter adhering to the tip of a probe.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  One aspect of the invention disclosed in the present application is: (a) a step of forming extraction electrodes mainly composed of aluminum in a plurality of chip regions of a semiconductor wafer; and (b) bringing a probe into contact with the extraction electrodes. And (c) a step of removing foreign matter adhering to the probe, wherein the step (c) is a member inside or outside the semiconductor wafer and made of aluminum. The probe is brought into contact with the member containing as a main component.

Moreover, the outline | summary of the other invention disclosed by this application is shown as a bullet.
1. A semiconductor device manufacturing method including the following steps:
(A) For a plurality of unit test areas to be tested on the first wafer placed on the wafer stage of the wafer prober (the unit test area usually includes one or more chip areas) And, for each of the unit test areas, sequentially performing an electrical test by bringing a probe needle into contact with an aluminum pad in the unit test area;
(B) In the step (a), the probe needle is placed on the first wafer during the test for the first unit test area and the second unit test area of the plurality of unit test areas. Contact with aluminum pads other than the plurality of unit test areas to be tested (for example, peripheral imperfect chip areas, that is, pads corresponding to the probe needles, but lack a part of the chip area) A step of performing separation from the first time at least once (probe needle cleaning by tapping on the aluminum pad in the dummy chip region).
2. In the manufacturing method of the semiconductor device according to the first item, the first number is two or more times.
3. In the method for manufacturing a semiconductor device according to the first item, the first number is three or more times.
4). In the method of manufacturing a semiconductor device according to the first item, the first number is 5 times or more.
5). In the method of manufacturing a semiconductor device according to the first item, the first number is 7 times or more.
6). The method for manufacturing a semiconductor device according to any one of Items 1 to 5, further including the following steps:
(C) In the step (a), the probe needle is moved between the third unit test area and the fourth unit test area among the plurality of unit test areas to be tested. The third unit test area and the fourth unit test area are continuously tested without making contact with or leaving an aluminum pad other than the plurality of unit test areas to be tested on one wafer. The process to execute.
7). In the method of manufacturing a semiconductor device according to the sixth aspect, the test result in the first unit test area includes a specific defect (here, “include” means that, for example, two in the unit test area The measurement result of one of the chips includes a specific defect, etc.), and the defect is continuously generated in the preceding first number of unit test areas. Yes.
8). 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first number is three or more.
9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first number is five or more.
10. In the method of manufacturing a semiconductor device according to the seventh item, the first number is seven or more.
11. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first number is 10 or more.
12 In the method of manufacturing a semiconductor device that performs wafer probe inspection on a plurality of wafer lots, the first probe needle cleaning is cleaning inside the wafer, and the second probe needle cleaning is cleaning outside the wafer.
13. 13. The method for manufacturing a semiconductor device according to item 12, wherein the first probe needle cleaning is cleaning by tapping in the wafer.
14 14. The method for manufacturing a semiconductor device according to item 12 or 13, wherein the second probe needle cleaning is cleaning with a cleaning sheet outside the wafer.
15. 15. The method of manufacturing a semiconductor device according to any one of Items 12 to 14, wherein the first probe needle cleaning is performed between wafers (every wafer, that is, every time one wafer is finished, every two wafers, or For every N sheets, the second probe needle cleaning is performed between lots as needed.
16. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the external cleaning member in the second probe needle cleaning is the cleaning sheet, and the product type to be tested is changed by changing the lot. Sometimes, the cleaning position on the cleaning sheet does not return to the initial position, but a position shifted from the preceding cleaning position by the vector amount determined by the product type to be tested is used.

Furthermore, the outline | summary of the other invention disclosed by this application is shown as a bullet.
1. (A) forming a lead electrode mainly composed of aluminum in a plurality of chip regions of a semiconductor wafer; and (b) conducting an electrical characteristic test by bringing a probe into contact with the lead electrode. (C) removing foreign matter adhering to the probe, wherein the step (c) is a member inside or outside the semiconductor wafer, the member containing aluminum as a main component. A method of manufacturing a semiconductor device in which a needle is brought into contact.
2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (c), the probe is applied to the extraction electrode formed in a dummy region that is not a product among the plurality of chip regions. A method for manufacturing a semiconductor device to be contacted.
3. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the probe is applied to the lead-out electrode formed in a defective chip region among the plurality of chip regions. A method for manufacturing a semiconductor device to be contacted.
4). 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step (b) and the step (c) are performed at substantially the same temperature.
5). 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is a step of removing foreign matter attached to the probe and the probe is brought into contact with the member three times or more. A method for manufacturing a semiconductor device.
6). 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is a step of removing foreign matter attached to the probe, and the probe is brought into contact with the member five times or more. A method for manufacturing a semiconductor device.
7). 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is a single step of removing the foreign matter adhering to the probe and the probe contacts the member seven times or more. Device manufacturing method.
8). 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (c) further includes bringing the probe into contact with a cleaning sheet placed outside the semiconductor wafer.
9. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (c), the probe is placed on a wafer stage instead of the semiconductor wafer, and the member mainly composed of aluminum is also used. For manufacturing a semiconductor device.
10. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (c) further includes placing the probe on a cleaning wafer placed on a wafer stage in place of the semiconductor wafer and having a cleaning sheet attached thereto. For manufacturing a semiconductor device.
11. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the probe is brought into contact with the member outside the semiconductor wafer, and further, the cleaning outside the semiconductor wafer is performed. A method of manufacturing a semiconductor device, wherein the probe is brought into contact with a sheet.
12 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the probe is brought into contact with the member outside the semiconductor wafer, and the member is equivalent to the extraction electrode. For manufacturing a semiconductor device having a simple structure.
13. In the method of manufacturing a semiconductor device according to the first aspect, in the step (b), the plurality of probes are simultaneously brought into contact with the plurality of extraction electrodes formed in the plurality of chip regions, The step (c) is a method of manufacturing a semiconductor device in which a plurality of the probes are simultaneously brought into contact with the member.
14 2. The method of manufacturing a semiconductor device according to claim 1, wherein the pressure causing the probe to contact the extraction electrode in the step (b) and the probe contacting the member in the step (c). A method of manufacturing a semiconductor device in which the pressure is the same.
15. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the step (c) is performed when the position of the cleaning sheet that contacts the probe is changed every time and the construction product is changed. A method of manufacturing a semiconductor device in which the position of the cleaning sheet with which the probe is brought into contact does not return to the initial position.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since the tip of the probe is brought into contact with a member that is inside or outside of the wafer and that contains aluminum as a main component, foreign matter adhering to the tip of the probe can be effectively removed.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  A wafer refers to a silicon single crystal substrate (generally a substantially planar circular shape) used for manufacturing an integrated circuit, an epitaxial silicon substrate, a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, and a composite substrate thereof. . In addition, the term “semiconductor device” as used herein refers not only to a semiconductor device such as a silicon wafer or a sapphire substrate or an insulator substrate, but also to a TFT (Thin-Film-Transistor) unless otherwise specified. ) And STN (Super-Twisted-Nematic) liquid crystal or the like made on other insulating substrates such as glass.

  In this application, when referring to a material, for example, even if “silicon” is mentioned, a material containing silicon as a main constituent component (for example, SiGe or the like) is used except when a particularly pure material is specified. Including). The same applies to “aluminum”, “Al pad” and the like (for example, including AlCu alloy).

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. (The subsequent embodiments incorporate the preceding embodiment within a consistent range. In other words, they are omitted in later embodiments.) In principle are described in the corresponding preceding examples).

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is an external view showing a schematic configuration of a prober (wafer prober) 1 according to the first embodiment. In FIG. 1, the prober 1 in the first embodiment has a loader / unloader unit 2, a wafer stage 3, and a cleaning table 4.

  The loader / unloader unit 2 has a function of taking out a wafer from a wafer cassette containing a plurality of wafers and placing the wafer on the wafer stage 3, and collecting the wafer placed on the wafer stage 3 and storing it in the wafer cassette. ing.

  The wafer stage 3 is for placing a wafer, and an electrical characteristic inspection of the wafer is performed on the wafer stage 3. The cleaning table 4 is provided with a cleaning sheet for cleaning the probe that is brought into contact with the wafer.

  FIG. 2 is a diagram showing a configuration on the wafer stage 3 of the prober 1. In FIG. 2, a test head 5 is provided on the wafer stage 3 of the prober 1, and a measurement performance board 6 is disposed below the test head 5. A probe card 7 is provided below the measurement performance board 6, and a plurality of probes 8 are formed on the probe card 7. The probe 8 is made of tungsten, for example. The probe 9 is brought into contact with the wafer 9 disposed on the wafer stage 3, whereby the electrical characteristic inspection of the wafer 9 is performed. That is, by contacting the probe 8 with a plurality of lead electrodes (bonding pads) formed in the chip region of the wafer 9, the electrical characteristics of the semiconductor device formed in the chip region of the wafer 9 are inspected.

  Here, when the probe 8 is brought into contact with a lead electrode containing aluminum as a main component and an electrical characteristic inspection is performed, aluminum oxide debris adheres to the tip of the probe 8. For this reason, the contact resistance between the probe 8 and the extraction electrode is increased, resulting in contact failure.

  Conventionally, in order to prevent the above-described poor contact, the tip of the probe 8 is pierced into the cleaning sheet disposed on the cleaning table 4 to remove the aluminum oxide waste adhering to the tip of the probe 8. At this time, the position of the cleaning sheet for piercing the probe 8 is changed every cleaning. That is, the position of the cleaning sheet that pierces the probe 8 moves from the initial position for each cleaning, and cleaning is performed at a new position that is not always used for cleaning. However, since the cleaning position moves while overlapping partly, the probe 8 may be cleaned at the same position (for example, at a position shifted by a certain amount in an oblique direction, contact with the cleaning sheet may be performed). However, it may return to the previous position again during many cleanings).

  When the electrical characteristics are inspected by changing the construction product, the cleaning of the probe 8 can be performed by returning to the initial position of the cleaning sheet or by continuously changing the cleaning position. May be cleaned at the same location. Since the foreign matter remains on the cleaning sheet at the position where the cleaning has already been performed, if the cleaning is performed again at that location, the foreign matter will reattach to the probe 8.

  Since the cleaning sheet contains an abrasive, the tip of the probe 8 is polished each time the probe 8 is pierced into the cleaning sheet. Accordingly, when cleaning is performed many times, the tip of the probe 8 becomes thin, the contact area between the probe 8 and the extraction electrode decreases, and the contact resistance increases.

  Therefore, in the prober 1 according to the first embodiment, the probe 8 is cleaned by bringing the probe 8 into contact with an extraction electrode (member) formed inside the wafer 9. That is, the wafer 9 has a plurality of chip regions, but the probe 8 is brought into contact with a dummy extraction electrode formed in a dummy region which is not a product in the chip region, so that the probe 8 is contacted a plurality of times. The aluminum oxide waste adhering to the surface is removed. In this way, the probe 8 can be cleaned by bringing the probe 8 into contact with the dummy extraction electrode inside the wafer 9. When the probe 8 is cleaned with the dummy extraction electrode formed in the dummy region, it has been empirically found that the removed aluminum oxide debris does not easily reattach to the tip of the probe 8. 8 can be reliably performed. Therefore, according to the first embodiment, the foreign matter attached to the tip of the probe 8 can be effectively removed.

  In the case of using the cleaning sheet, the tip of the probe 8 is cut and thinned by the abrasive contained in the cleaning sheet. However, in the first embodiment, no abrasive is used and a dummy is used. Foreign matter adhering to the tip of the probe 8 is removed by bringing it into contact with or separating from the extraction electrode (tapping). For this reason, it can prevent that the front-end | tip of the probe 8 becomes thin, and can suppress that the contact resistance of the probe 8 and the electrode for extraction of a product becomes high. Needless to say, this means that the probe needle cleaning by the “tapping” operation that repeats the touchdown and takeoff to the aluminum pad immediately below the probe needle in a short time on the aluminum pad in the wafer. The combined use of probe needle cleaning by other means including a cleaning sheet outside the wafer is not excluded.

  In addition, since the cleaning can be performed with a member (extracting electrode) inside instead of the outside of the wafer 9, the probe 8 can be cleaned for each wafer. That is, since the electrical property inspection of the wafer 9 can be performed with the tip of the probe 8 always cleaned, a highly reliable inspection can be performed. Furthermore, according to the first embodiment, since the probe 8 can be cleaned inside the wafer 9, it is not necessary to move the probe 8 to an external cleaning sheet. Therefore, throughput can be improved. Note that it is not always necessary to perform tapping for each sheet. That is, it is effective to perform tapping at an appropriate timing in the wafer in advance in view of the inspection status. For example, if a specific defect appears continuously in multiple unit probe operations (from touchdown for measurement to take-off due to test completion for that area), it automatically goes to the pad in the neighboring or predetermined dummy area It is effective in terms of avoiding erroneous measurement to move and execute tapping. Therefore, if specific defects do not occur or are few, it is also important to save time that no tapping is performed while the wafer is being tested. However, this does not preclude performing tapping while testing the wafer, even in such a case. That is, even in such a case, a simple cleaning effect of the needle tip can be expected.

  Further, the combined use of other means outside the wafer (for example, a cleaning sheet outside the wafer) has a complementary effect due to the difference in the cleaning principle. Further, the effect of reducing the wear of the probe needle due to the decrease in the number of the other means can be expected. That is, referring to the probe inspection result of the preceding wafer (for example, automatically), when there is a high probability that the dust at the tip of the needle is not removed, external cleaning between wafers (before the next wafer is inspected) It is effective to execute (automatically or in advance). In particular, when a specific defect frequently occurs in the wafer (during the test of the wafer) and tapping is performed, if the same defect occurs frequently thereafter, external cleaning of the wafer may be performed again. It is effective to reduce inspection.

  In addition, it is effective in terms of time saving that the cleaning within the wafer is performed by tapping as described above and the external cleaning is performed between batches. In this case, it is not always necessary to carry out between all batches. If the specific defect information in the batch is referred to (automatically) and executed when a contact failure is expected, the wear of the needle tip can be reduced.

  FIG. 3 shows an example of a chip area (unit test area to be tested on the wafer) formed on the wafer 9. As shown in FIG. 3, a plurality of chip regions are formed on the wafer 9, and in the plurality of chip regions, a chip region 10 that is not a product and a dummy chip region (not a product) There is a dummy area 11. The chip region 10 in which the product is formed has a quadrangular shape, but the chip region 11 serving as a dummy has a shape in which a part of the quadrangular shape is missing. Since the chip region 11 having a partially cut shape cannot pass the appearance inspection, it is not a product. However, the dummy chip region 11 has the same structure as the chip region 10 in which the product is formed. That is, in the same manner as the extraction electrode 10a is formed in the chip region 10, the extraction electrode 11a is also formed in the chip region 11.

  In the first embodiment, the chip region 11 formed in the peripheral portion of the wafer 9 is used for cleaning the probe 8. That is, the chip region 11 is a dummy region that cannot be a product, but an extraction electrode 11a is formed in the same manner as the product. Therefore, the probe 8 can be cleaned by bringing the probe 8 into contact with or separating from the extraction electrode 11a. In particular, by using the extraction electrode 11a mainly composed of aluminum to remove foreign matter attached to the tip of the probe 8, the foreign matter attached to the probe 8 can be effectively removed.

  In the first embodiment, the example in which the probe 8 is cleaned using the extraction electrode 11a formed in the dummy chip region 11 is shown. You may make it use the extraction electrode of the chip | tip area | region currently formed.

  FIG. 4 is a diagram showing a result of conducting an electrical characteristic inspection using the probe 8 on the semiconductor device formed in the chip region of the wafer 9. In FIG. 4, the horizontal axis indicates columns, and the vertical axis indicates rows. For example, it is indicated that the inspection result of the chip area where the value on the vertical axis is “15” and the value on the horizontal axis is “30” is “8”. Is “15” and the value on the horizontal axis is “31”), the inspection result is also “8”. FIG. 4 shows the result of inspecting in this order from the top and finally inspecting all the chip regions formed on the wafer 9.

  Here, for example, “8” indicates a memory failure, and “/” indicates a non-defective product. “H” indicates a start-up test failure, and “E” indicates a function test failure. “2” indicates a logic test failure, and “D” indicates a DC screening test failure. In particular, “W” indicates a contact failure of the probe 8 which is a problem in this specification.

  As shown in FIG. 4, at first, the contact failure “W” does not occur so much, but when the value on the vertical axis is changed from “30” to “31”, it is understood that the contact failure “W” frequently occurs. . This is presumably because the contact resistance is increased due to foreign matter adhering to the probe 8. Therefore, the probe 8 was brought into contact with the extraction electrode in the dummy region at the position indicated by the arrow in FIG. 4 (the value on the vertical axis is “32”). Then, it turns out that generation | occurrence | production of poor contact "W" has decreased sharply after that. After that, when the probe 8 is not brought into contact with the extraction electrode in the dummy region, it can be seen that contact failure “W” occurs again when the value on the vertical axis is “38” or later. From this, it can be seen that the foreign matter adhering to the tip of the probe 8 can be removed by repeating the contact and separation of the probe 8 with the extraction electrode in the dummy region a plurality of times. For example, it is effective to bring the probe 8 into contact with the extraction electrode in the dummy region at least once, that is, twice or three times in one step of removing the foreign matter adhering to the probe 8. In particular, from the viewpoint of effectively removing foreign matter adhering to the tip of the probe 8, it is desirable that the probe 8 is brought into contact with the extraction electrode in the dummy region five times or more, more than seven times.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. Here, an element in which a nonvolatile memory and a logic circuit are formed will be described as an example of a semiconductor device. In FIG. 5, first, the previous process is performed (S101). Here, of the processes in the previous process, a process of forming the uppermost extraction electrode will be described with reference to FIGS.

  As shown in FIG. 6, a titanium film 21, a titanium nitride film 22, a titanium film 23, and an aluminum film 24 are sequentially formed on the interlayer insulating film 20 formed on the wafer. These films can be formed using, for example, a sputtering method. The thickness of the titanium film 21 is about 100 mm, the thickness of the titanium nitride film 22 is about 1000 mm, the thickness of the titanium film 23 is about 200 mm, and the thickness of the aluminum film 24 is about 6000 mm. Here, the left area indicates a chip area as a product in the chip area of the wafer, and the right area indicates a dummy chip area in the chip picture area of the wafer.

  Subsequently, as shown in FIG. 7, by using a photolithography technique and an etching technique, the titanium film 21, the titanium nitride film 22, the titanium film 23, and the aluminum film 24 are patterned to form extraction electrodes 25a and 25b. To do.

  Next, as shown in FIG. 8, a silicon nitride film 26, for example, is formed on the interlayer insulating film 20 on which the extraction electrodes 25a and 25b are formed. The silicon nitride film 26 can be formed using, for example, a CVD (Chemical Vapor Deposition) method. Then, the silicon nitride film 26 is patterned using a photolithography technique and an etching technique. The patterning is performed so that the extraction electrodes 25a and 25b are exposed. Thereby, a protective film made of the silicon nitride film 26 can be formed.

  Subsequently, as shown in FIG. 9, after forming, for example, a polyimide resin film 27 on the silicon nitride film 26, patterning is performed using a photolithography technique and an etching technique to form a surface protective film made of the polyimide resin film. To do. In this way, extraction electrodes 25a and 25b can be formed on the uppermost layer of the wafer. Thereafter, the back surface of the wafer (surface opposite to the element formation surface) is ground.

  Next, a wafer test is performed as shown in FIG. 5 (S102). In the wafer test, basic characteristics of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) such as a threshold voltage (Vth) characteristic are inspected.

  Subsequently, naming is performed (S103). In the naming, the lot number, wafer number and product name are written on the wafer.

  Then, after the memory is erased (S104), a memory high temperature test is performed (S105). In the memory high temperature test, memory write and read tests are performed in a high temperature state. This memory high temperature test uses a probe. Subsequently, retention baking is performed (S106). The retention bake is performed at about 240 ° C to about 360 ° C. Next, a memory room temperature test is performed (S107). In the memory normal temperature test, memory write and read tests are performed at a temperature of about 25 ° C. This memory room temperature test also uses a probe.

  Subsequently, a logic test is performed (S108). In this logic test, the logic circuit is tested at about 95 ° C. to about 125 ° C. The logic test process will be described with reference to FIGS. First, as shown in FIG. 10, a logic test is performed by bringing a probe 28 connected to a probe card into contact with an extraction electrode 25a formed in a chip region as a product. When this logic test is performed on a plurality of chip regions formed on the wafer, a foreign material 29 made of aluminum oxide or the like adheres to the tip of the probe 28 as shown in FIG. If the foreign matter 29 adheres to the probe 28, the contact resistance increases and a contact failure occurs, so the probe 28 is cleaned. As shown in FIG. 12, the probe 28 is cleaned by bringing the probe 28 into contact with or separating from the extraction electrode 25b formed in the dummy chip region (tapping). Then, as shown in FIG. 13, the foreign matter adhering to the tip of the probe 28 is removed. Here, the cleaning of the probe 28 is performed at about the same temperature as about 95 ° C. to about 125 ° C. where the logic test is performed. For cleaning the probe 28, the pressure at which the probe 28 is brought into contact with the extraction electrode 25b is set substantially equal to the pressure at which the probe 28 is brought into contact with the extraction electrode 25a for the logic test. Thereby, a foreign material can be removed effectively.

  That is, in the first embodiment, for a plurality of unit test areas (chip areas) to be tested on a wafer placed on the wafer stage of a wafer prober, a probe ( A probe needle 28 is brought into contact with the extraction electrode 25a (aluminum pad) in the unit test area, and electrical tests are sequentially performed. The probe 28 is brought into contact with or separated from the lead-out electrode 25b of the dummy chip region between the electrical tests for the first unit test region and the second unit test region among the plurality of unit test regions. By doing so, the probe 28 is cleaned. Note that it is not necessary to clean the probe 28 every time the unit test area is tested. That is, between the electrical test for the first unit test area and the second unit test area, the probe 28 is cleaned using the dummy area, while the third unit test area and the fourth unit test area are cleaned. In the test area, the third unit test area and the fourth unit test area can be continuously tested without being brought into contact with or separated from the extraction electrode 25b in the dummy area. In this case, it is effective to clean the probe 28 using the dummy area when defects are continuously generated in a plurality of unit test areas. For example, the probe 28 is cleaned using the dummy area between the first unit test area and the electrical test for the second unit test area to be tested after the first unit test area. The test condition is that the test result of the first unit test area includes a specific defect, and the defect continues in the first number of unit test areas to be tested prior to the first test area. It is possible that this is the case. Here, the first number indicating the number of consecutive failures can be, for example, 3 or more or 5 or more. In particular, when the first number is 7 or more or 10 or more, the need for cleaning the probe 28 using the dummy area increases. Further, it is not necessary to clean the probe 28 using the dummy area for each wafer. For example, the probe 28 may be cleaned using the dummy area for each predetermined number of wafers.

  In this way, the probe 28 is cleaned by bringing the probe 28 into and out of contact with the dummy chip area on the wafer, and the electrical characteristics of the first lot of wafers are further inspected. In the meantime, the probe 28 can be cleaned by inserting the probe 28 into a cleaning sheet arranged on the cleaning table 4. In other words, the probe 28 is cleaned by bringing the probe 28 into and out of contact with the extraction electrode formed in the dummy chip region, and every time a predetermined number of wafers are processed, the probe 28 is exposed to the outside of the wafer. The probe 28 is cleaned using a certain cleaning sheet. Thereby, since the probe is cleaned by two methods, the foreign matter adhering to the tip of the probe can be effectively removed. For example, the cleaning of the probe 28 using the cleaning sheet can be performed for each lot, but it may not be performed for each lot.

  Further, according to the first embodiment, it is not necessary to remove the wafer from the wafer stage 3 at the time of cleaning the probe 28, so that it is possible to suppress a decrease in throughput due to the cleaning. In the cleaning sheet, for example, a cushion layer made of acrylic foam is formed on liner paper, and the cleaning layer is formed on the cushion layer. And it has the structure where the abrasive material application layer which apply | coated the abrasive material on the cleaning layer was formed. By piercing the probe 28 into the cleaning sheet having such a structure, the tip of the probe 28 is polished with an abrasive and reaches the cleaning layer, so that foreign matter is removed from the probe 28.

  In this way, the electrical property inspection of the wafer of the first lot is completed. Next, for example, the electrical characteristic inspection of the wafer in the second lot of the same product as the first lot is performed. Even when the electrical characteristics of the wafers in the second lot are to be inspected, the probe 28 is brought into contact with or separated from the extraction electrode in which a chip area serving as a dummy is formed every predetermined number of wafers. 28, and each time a predetermined number of wafers are processed, the probe 28 is also cleaned using a cleaning sheet outside the wafer. At this time, the position where the probe 28 is brought into contact with the cleaning sheet is different from the position where the probe 28 is brought into contact with the cleaning of the first lot described above. In this manner, the reattachment of foreign matter to the probe 28 can be suppressed by shifting the position of the cleaning sheet with which the probe 28 is brought into contact.

  Subsequently, for example, an electrical characteristic inspection is performed on a third lot having a different start product from the first lot and the second lot. Even when the electrical characteristics inspection of the wafer in the third lot is performed, the probe 28 is brought into contact with or separated from the extraction electrode formed in the chip area as a dummy every predetermined number of wafers. 28, and each time a predetermined number of wafers are processed, the probe 28 is also cleaned using a cleaning sheet outside the wafer. At this time, the position at which the probe 28 is brought into contact with the cleaning sheet is returned to the initial position because the start product has been changed (the first embodiment is not limited to the one that returns to the initial position in this way. Needless to say, the present invention can be applied to the case where the product to be tested does not return to the initial position when the product to be tested is changed, as will be described with reference to Embodiment 6. Unless otherwise replaced by the sixth embodiment, all are incorporated in the sixth embodiment as they are). That is, in the first lot, the probe 28 is returned to the initial position where it is brought into contact with the cleaning sheet. Therefore, when the probe 28 is cleaned only with the cleaning sheet, the probe 28 returns to the initial position, and there is a possibility that foreign matter may reattach to the probe 28. However, in the first embodiment, since the probe 28 is cleaned by bringing the probe 28 into contact with or separating from the extraction electrode formed in the dummy chip region, the foreign matter is not reattached. Can be prevented.

  Next, as shown in FIG. 5, after performing an appearance inspection of the wafer (S109), the wafer is dispensed (S110). Thereafter, the wafer is divided into individual chips by dicing (S111) and packaged in an assembly process (S112). Thus, the manufacturing method of the semiconductor device in the first embodiment is performed.

  The first embodiment can be applied not only when, for example, an electrical characteristic inspection is performed on one chip area at a time, but also when an electrical characteristic inspection is performed on a plurality of chip areas at once. That is, in the case where the electrical property inspection is performed by simultaneously bringing the probe 28 into contact with a plurality of lead electrodes formed in a plurality of adjacent chip regions, the probe 28 is also cleaned with a dummy formed on the wafer. A plurality of probes 28 can be simultaneously brought into contact with the tip region and the tip region adjacent thereto. At this time, since all of the chip areas used for cleaning are rarely dummy chip areas, the dummy chip area and a normal chip area adjacent to this area are used for cleaning. The adjacent normal chip area is not a product because it is used for cleaning. The normal chip area is sacrificed somewhat. Therefore, such a method is effective when the peripheral yield is particularly low.

  In the first embodiment, the probe 28 is cleaned by bringing the probe 28 into contact with or separating from the extraction electrode formed in the dummy chip region, and at the same time, the cleaning outside the wafer. The example which cleans the probe 28 using the sheet | seat was shown.

(Embodiment 2)
In the first embodiment, the example in which the probe is cleaned using the extraction electrode formed in the dummy chip region has been described. However, in the second embodiment, aluminum provided outside the wafer is used. An example in which the probe is cleaned using a member containing as a main component will be described.

  As shown in FIG. 2, the prober 1 is provided with a cleaning table 4, and a member mainly composed of aluminum is disposed on the cleaning table 4. The foreign matter attached to the tip of the probe can be removed by bringing the tip of the probe into contact with or away from the member. As described above, in the second embodiment, the probe is cleaned by using a member provided outside the wafer in place of the extraction electrode formed in the dummy chip region. However, since the extraction electrode and the above-described member are common in that aluminum is the main component, the second embodiment can obtain the same effect as the first embodiment.

  In the second embodiment, the member disposed on the cleaning table 4 is mainly composed of aluminum. However, the member may have a structure equivalent to the extraction electrode. That is, as described in the first embodiment, the extraction electrode has a laminated structure of, for example, a titanium film, a titanium nitride film, a titanium film, and an aluminum film, but the member disposed on the cleaning table 4 is also a titanium film. A laminated structure of a titanium nitride film, a titanium film, and an aluminum film may be formed. Thereby, a probe can be made to contact a member on the conditions equivalent to the case where it contacts with the electrode for extraction. According to the second embodiment, since it is not necessary to remove the wafer from the wafer stage 3 when cleaning the probe, it is possible to suppress a decrease in throughput due to cleaning.

(Embodiment 3)
In the third embodiment, an example in which a lead electrode formed in a dummy chip region is used and a member mainly composed of aluminum is used in cleaning the probe.

  In the third embodiment, the probe is cleaned by bringing the probe into contact with or separating from the extraction electrode formed in the dummy chip region. Further, the wafer is temporarily removed from the wafer stage 3, a member mainly composed of aluminum is arranged on the wafer stage 3, and the probe is brought into contact with the arranged member, thereby cleaning the probe. As described above, since the probe is cleaned by two methods, according to the third embodiment, the foreign matter adhering to the tip of the probe can be effectively removed. In addition, although the member which has aluminum as a main component has been arrange | positioned on the wafer stage 3 and the probe is cleaned, it does not restrict to this, For example, the member which has aluminum as a main component is outside the wafer, for example, cleaning You may comprise so that it may arrange | position to the stand 4. FIG. In this case, the cleaning sheet is arranged on the cleaning table 4 in the first embodiment, but in the third embodiment, a member mainly composed of aluminum is arranged on the cleaning table 4 instead of the cleaning sheet.

(Embodiment 4)
In the fourth embodiment, an example will be described in which, when the probe is cleaned, a lead-out electrode formed in a dummy chip region is used, and a cleaning wafer with a cleaning sheet attached is also used. That is, an example will be described in which the cleaning of the probe is performed using a cleaning sheet with a cleaning sheet attached in place of the cleaning sheet described in the first embodiment.

  In the fourth embodiment, the probe is cleaned by bringing the probe into contact with or separating from the extraction electrode formed in the dummy chip region. Further, the wafer is temporarily removed from the wafer stage 3, a cleaning wafer is arranged on the wafer stage 3, and the probe is cleaned by piercing the arranged member. For example, electrical characteristics inspection is performed on a predetermined number of wafers in one lot, and then the wafers are removed from the wafer stage 3. Then, the cleaning wafer is placed on the wafer stage 3, and the probe is cleaned by bringing the probe into contact with the cleaning wafer. Thereafter, the cleaning wafer is removed from the wafer stage, and electrical characteristics inspection is performed again on the new wafer. As described above, since the probe is cleaned by two methods, according to the fourth embodiment, the foreign matter adhering to the tip of the probe can be effectively removed. In the above description, the cleaning wafer is used for cleaning in one lot. However, the cleaning wafer is used before the processing of the next lot after the processing of one lot is completed, that is, between lots. May be.

(Embodiment 5)
In the fifth embodiment, an example of using a cleaning sheet disposed outside the wafer and using a member mainly composed of aluminum disposed outside the wafer when cleaning the probe will be described. That is, in the first embodiment, the example in which the cleaning sheet is arranged outside the wafer is shown. In the fifth embodiment, an example in which a member mainly composed of aluminum is also arranged outside the wafer will be described.

  In the fifth embodiment, the foreign matter attached to the probe is removed by bringing the probe into contact with or away from a member mainly composed of aluminum. Further, the probe is cleaned by piercing the probe into a cleaning sheet placed outside the wafer. As described above, since the probe is cleaned by two methods, according to the fifth embodiment, the foreign matter adhering to the tip of the probe can be effectively removed. In the fifth embodiment, the cleaning may be performed by bringing a probe into contact with a dummy chip region inside the wafer. By cleaning the probe by bringing the probe into contact with the dummy chip area in this way, the number of cleanings performed outside the wafer can be reduced, so that the throughput can be improved.

(Embodiment 6)
In the sixth embodiment, the probe is cleaned using the extraction electrode formed in the dummy chip area, and the probe is cleaned using the cleaning sheet arranged outside the wafer. An example will be described. The difference from the first embodiment is that in the first embodiment, the example of returning to the initial position when the start product is changed has been described, but in the sixth embodiment, the initial position is changed even if the start product is changed. An example that does not return to will be described.

  FIG. 14 shows the movement of the position where the probe is pierced in the cleaning sheet 30. In FIG. 14, in the first cleaning, the probe is cleaned in a region 31 a at the upper left of the cleaning sheet 30. That is, the probe is pierced within the region 31a of the cleaning sheet 30. Subsequently, in the second cleaning, the probe is cleaned in the region 31b deviated from the region 31a. Similarly, the probe is cleaned in the region 31c and the region 31d.

  Here, when the start product is changed, the first embodiment returns to the initial position, that is, the region near the region 31a. Therefore, when the start product is changed, the region 31a used for cleaning mostly overlaps with the previous product, so that foreign matter may be reattached to the probe. However, in the sixth embodiment, even if the start product is changed, the initial position is not returned, and the probe is cleaned in the region 31e as shown in FIG. That is, the probe is cleaned using a position shifted from the preceding cleaning position by a vector amount determined by the product type to be tested. For this reason, there is less risk of foreign matter reattaching than when the cleaning position returns to the initial position. In this manner, the cleaning of the probe is sequentially performed in the region 31f and the region 31g.

  However, as shown in FIG. 14, the cleaning position moves little by little (about the diameter of the probe) in a diagonally downward or diagonally upward direction. For this reason, a region overlapping with a part is formed, and thus cleaning may be performed at a position where a part of the probe is once pierced. Therefore, there remains a possibility that foreign matter will reattach to the probe.

  Therefore, in the sixth embodiment, in addition to using the cleaning sheet arranged outside the wafer, the probe is cleaned using the extraction electrode formed in the dummy chip region in the wafer. (It is not necessary to use both methods together. This is the same as described in Example 1). Therefore, even when foreign matter is reattached to the probe by cleaning with the cleaning sheet, the foreign matter can be removed by cleaning using the extraction electrode formed in the dummy chip region.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  One invention disclosed in the present application can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the external view which showed schematic structure of the prober in Embodiment 1 of this invention. FIG. 3 is a diagram showing a schematic configuration of a prober in the first embodiment. It is the figure which showed the several chip area | region currently formed on the wafer. It is the figure which showed the result of the electrical property test | inspection in each chip area | region. 3 is a flowchart showing a manufacturing process of the semiconductor device in the first embodiment. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; It is the figure which showed the movement of the position which pierces a probe in a cleaning sheet.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Prober 2 Loader / Unloader part 3 Wafer stage 4 Cleaning stand 5 Test head 6 Measurement performance board 7 Probe card 8 Probe 9 Wafer 10 Chip area 10a Draw electrode 11 Chip area 11a Draw electrode 20 Interlayer insulation film 21 Titanium film 22 Titanium nitride film 23 Titanium film 24 Aluminum film 25a Lead electrode 25b Lead electrode 26 Silicon nitride film 27 Polyimide resin film 28 Probe 29 Foreign material 30 Cleaning sheets 31a to 31g

Claims (4)

Supplying a semiconductor wafer having a plurality of chip regions, each of the plurality of chip regions having a semiconductor integrated circuit and a plurality of electrodes electrically connected to the semiconductor integrated circuit;
Supplying a probe card having a plurality of probes capable of contacting the plurality of electrodes of the semiconductor wafer;
Performing electrical inspection of the semiconductor integrated circuit by bringing the plurality of probes of the probe card into contact with the plurality of electrodes of the semiconductor wafer;
A cleaning step of cleaning the plurality of probes of the probe card after the electrical inspection step;
The cleaning step includes a first cleaning step of contacting the plurality of probes a plurality of times with a plurality of electrodes formed in a chip region of a dummy region that is not used as a product in the plurality of chip regions of the semiconductor wafer. A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the chip region of the dummy region is disposed in a peripheral region of the semiconductor wafer. A method of manufacturing a semiconductor device according to claim 1,
The cleaning step further includes a second cleaning step different from the first cleaning step,
The method of manufacturing a semiconductor device, wherein the second cleaning step includes a step of bringing the plurality of probes into contact with a cleaning sheet disposed outside the semiconductor wafer. A method of manufacturing a semiconductor device according to claim 3,
The method for manufacturing a semiconductor device, wherein the cleaning sheet includes an abrasive for polishing the plurality of probes.

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