JP4575865B2 - Signal receiving device - Google Patents

Description

  The present invention relates to a signal receiving apparatus, and more particularly, to a signal receiving apparatus provided with a plurality of receiving means for receiving the same transmission signal using a plurality of antennas installed at spatially different positions.

2. Description of the Related Art Conventionally, a signal receiving apparatus including a plurality of receiving units that receive the same radio signal using a plurality of antennas installed at spatially different positions is known (for example, see Patent Document 1). In this apparatus, a weight for each of a plurality of antennas is calculated, and a convolution calculation is performed on the calculated weights, so that an error correction code is performed and received data is demodulated. Therefore, according to the above signal receiving apparatus, it is possible to reduce errors in data transmission.
JP 2004-40782 A

  However, in order to perform the error correction as described above in the above signal receiving apparatus, advanced signal processing using a dedicated DSP (Digital Signal Processor) or the like is required, and as a result, the apparatus itself is complicated. In addition, there is a disadvantage that it is difficult to reduce the size of the apparatus.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a signal receiving apparatus capable of realizing error correction of a received signal with a simple configuration.

The object is to provide a plurality of receiving means for receiving the same transmission signal, and a delay means provided corresponding to each receiving means for delaying the received digital signal by a shorter time than the baud rate of the digital signal. Provided for each receiving means, and a pulse generating means for generating a pulse signal by taking an exclusive OR of the received digital signal and the output of the delay means, and provided for each receiving means. A counting means for counting the number of edges per predetermined time of the pulse signal generated by the pulse generating means and a receiving means corresponding to each of the receiving means, and the number of edges obtained by counting by the counting means is predetermined. Comparing means for determining whether or not the number is equal to or less than the number and a receiving means are provided for each receiving means, and the number of edges is set to the predetermined number by the comparing means A first masking means for masking the received digital signal and a receiving means corresponding to each receiving means, and the comparing means determines that the number of edges exceeds the predetermined number. logical sum, a second masking means for masking the pulse signal generated by said pulse generating means, the digital signals respectively received by the plurality of receiving means after the masking processing by said first masking means if you By combining the received data generating means for generating the received data and each pulse signal generated by the pulse generating means provided corresponding to each receiving means after the masking process by the second masking means Synchronous clock generating means for generating synchronous clock data based on the combined result; and A reception data generated by the signal data generating means, and synchronous clock data generated by the synchronization clock generating means, based on, are achieved by a signal receiving apparatus and a demodulating means for demodulating a transmission signal.

  In the invention of this aspect, when an unstable portion exists in the digital signal received by the receiving means, the unstable portion is subjected to masking processing, and the digital signals received by the plurality of receiving means are ORed. Combined to generate received data. According to such a configuration, it is possible to generate reception data from which an unstable error portion of the digital signal received by the receiving means is deleted, and to generate the reception data by a simple process on software. it can. Therefore, according to the present invention, the error correction of the received signal can be realized with a simple configuration.

In the above signal receiving apparatus, the first masking means is an AND circuit that takes a logical product of the received digital signal and the result of the comparing means, and the second masking means is the pulse signal. An AND circuit that takes a logical product of the pulse signal generated by the generation unit and the result of the comparison unit may be used.

Further, the signal receiving apparatus described above, by comparing the received data generated by the digital signal and the reception data generating means which is received by the receiving means, specifying the receiving means has received an incorrect digital signal If the erroneous signal reception detection means is provided, for example, when an erroneous signal is received due to a failure of the reception means, the reception means in which the failure or the like has occurred can be reliably identified.

  According to the present invention, error correction of a received signal can be realized with a simple configuration.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration diagram of a system including a signal receiving apparatus according to a first embodiment of the present invention. The system of the present embodiment is a system that is mounted on a vehicle and detects tire pressure by transmitting and receiving tire pressure data obtained using a sensor from a transmitting station to a receiving station, for example.

  The system according to this embodiment includes a sensor 10 that outputs an analog signal corresponding to a physical quantity as data, a wireless sensor transmission station 12 that transmits after modulating the output signal of the sensor 10, and a signal transmitted from the wireless sensor transmission station 12. And a wireless sensor receiving station 14 as a signal receiving device for receiving and demodulating the signal. For example, the sensor 10 and the wireless sensor transmitting station 12 are both disposed on a rotating tire or wheel, and the wireless sensor receiving station 14 is disposed on the vehicle body side near the tire or wheel.

  The wireless sensor transmission station 12 includes an electronic control unit (hereinafter referred to as ECU) 20 and an RF transceiver 22. The ECU 20 is connected to the sensor 10 and converts an analog signal output from the sensor 10 into digital data, and an RF transceiver 22 that controls the RF transceiver 22 that modulates the digital data obtained by the AD converter 24. And a control unit 26. The RF transceiver 22 has an antenna 28 outside, and modulates the digital data obtained by the AD conversion unit 24 of the ECU 20 and transmits it from the antenna 28 under the control of the RF transceiver 22.

  The wireless sensor receiving station 14 includes two systems of RF transceivers 30 and 32, a single error detection circuit 34, and an ECU 36. The wireless sensor receiving station 14 is a space diversity type receiver using two systems of RF transceivers 30 and 32. Hereinafter, the system on the RF transceiver 30 side is referred to as a first system, and the system on the RF transceiver 32 side is referred to as a second system.

  Each RF transceiver 30, 32 has antennas 38, 40 outside, and demodulates the signals received by the antennas 38, 40 into digital data. The error detection circuit 34 is connected to the RF transceivers 30 and 32. The error detection circuit 34 is a circuit that detects a transmission error of a signal received by the RF transceivers 30 and 32 and corrects the error part by a method described in detail later. . Further, the ECU 36 receives the reception data (digital data) and the synchronous clock data obtained from the error detection circuit 34, and detects a parameter (for example, tire pressure) based on the output of the sensor 10.

  FIG. 2 shows a detailed configuration diagram of the error detection circuit 34 of the present embodiment. FIG. 3 shows signal waveforms at various parts of the error detection circuit 34 of this embodiment. In this embodiment, the error detection circuit 34 includes a counter 42, a counter reset circuit 44, a digital comparator 46, and an AND circuit 48 provided in the first system on the RF transceiver 30 side, and also on the RF transceiver 32 side. A counter 50, a counter reset circuit 52, a digital comparator 54, and an AND circuit 56 are provided in the second system.

  The counter 42 receives the digital data demodulated by the first-system RF transceiver 30, and has a function of detecting the rising edge of the digital data and counting the number of edges. The counter reset circuit 44 is a monostable multivibrator (mono-stable multivibrator) or a one-shot multivibrator. The counter reset circuit 44 receives the digital data demodulated by the RF transceiver 30 and receives a predetermined value from the falling edge of the digital data. It has a function of setting the counter 42 so that the counting operation of the counter 42 can be performed only for the time. In this embodiment, since the digital data is transmitted at a constant baud rate, the predetermined time is set to a time corresponding to the baud rate.

  The digital comparator 46 is a circuit that compares the count value count of the counter 42 with a predetermined set value set, and outputs a high signal when count ≦ set is satisfied, and outputs a low signal when count> set is satisfied. To do. The set value set is set to the number of edges per predetermined time that cannot be a normal transmission state of digital data. The AND circuit 48 receives the digital data from the RF transceiver 30 and the output signal of the digital comparator 46, and outputs a high signal when both signals are in a high state.

  Similarly, the counter 50 receives the digital data demodulated by the second-system RF transceiver 32, and has a function of detecting the rising edge of the digital data and counting the number of edges. The counter reset circuit 52 is a monostable multivibrator (mono-stable multivibrator) or a one-shot multivibrator, to which digital data demodulated by the RF transceiver 32 is input. It has a function of setting the counter 50 so that the above-described counting operation of the counter 50 can be performed only for the time. The predetermined time is also set to a time corresponding to the baud rate of the digital data.

  The digital comparator 54 is a circuit that compares the count value count of the counter 50 with a predetermined set value set, and outputs a high signal when count ≦ set is satisfied, and outputs a low signal when count> set is satisfied. To do. The set value set is set to the number of edges per predetermined time that cannot be a normal transmission state of digital data. The AND circuit 56 receives the digital data from the RF transceiver 32 and the output signal of the digital comparator 54, and outputs a high signal when both signals are high signals.

  The inputs of the OR circuit 58 are connected to the outputs of the AND circuits 48 and 56. The output of the OR circuit 58 is connected to the input of the EX-OR circuit 60 and to a delay circuit 62 that delays the output of the OR circuit 58 by an extremely short time compared to the baud rate of the digital data. The output of the delay circuit 62 is connected to the input of the EX-OR circuit 60 described above and the ECU 36 described above. The EX-OR circuit 60 outputs a pulse signal having a pulse width corresponding to the delay by the delay circuit 62 when the output of the OR circuit 58 rises and falls.

  The input of the AND circuit 64 is connected to the output of the EX-OR circuit 60. The input of the AND circuit 64 is also connected to a monostable multivibrator (mono-stable multivibrator) or a one-shot multivibrator (hereinafter referred to as SS) 66. The output of the AND circuit 64 is input to SS66. The SS 66 has a function of outputting a low signal for a predetermined time from the fall of the signal output from the AND circuit 64. The predetermined time is set to a shorter time depending on the baud rate of the digital data. The ECU 36 is connected to the output of the AND circuit 64.

  In the above configuration, when the digital data received and demodulated by the RF transceivers 30 and 32 are free from noise and there is no unstable part that can be an error part, the outputs of the digital comparators 46 and 54 are in the high state. Therefore, the error detection circuit 34 outputs digital data having the same waveform as the digital data input from the RF transceivers 30 and 32 (with delay by the delay circuit 62) to the error detection circuit 34. Synchronous clock data corresponding to the baud rate is output. In this case, the ECU 36 of the wireless sensor receiving station 14 uses the sensor parameter based on the digital data from the sensor 10 normally wirelessly transmitted from the wireless sensor transmitting station 12 and the synchronous clock data obtained by the delay of the digital data. Can be detected.

  On the other hand, when noise is mixed in any one of the digital data received and demodulated by the RF transceivers 30 and 32 and an unstable portion which becomes an error portion exists, the output from the error detection circuit 34 is as follows. become.

  That is, for example, when digital data of the first system on the RF transceiver 30 side becomes unstable due to noise mixing or a decrease in radio wave intensity, the digital data input to the first system side of the error detection circuit 34 is short. By repeating high and low in time, the count value count of the counter 42 that started the counting operation at the beginning of the unstable portion exceeds the set value set. In this case, the digital comparator 46 outputs a low signal, the output of the AND circuit 48 is in a low state, and this output low state is continued for a predetermined time corresponding to the digital data baud rate by the counter reset circuit 44. . However, at this time, if the digital data of the second system on the RF transceiver 32 side is in a stable state in which noise mixing or the like does not occur, the output of the digital comparator 54 is maintained in the high state. The digital data input to the system side is output from the AND circuit 56 as it is.

  In the present embodiment, the wireless sensor receiving station 14 performs an OR combination on the received digital data received by the plurality of antennas 38 and 40 of the first and second systems by the OR circuit 58. Therefore, when the received digital data of either the first system or the second system is unstable, the output of the OR circuit 58 to which the outputs of the AND circuits 48 and 56 are input is unstable. Regardless of the digital data, the other stable digital data itself is obtained. Even in such a situation, the error detection circuit 34 has the same waveform as the normal digital data input from the RF transceiver 30 or 32 to the error detection circuit 34. Digital data (however, delayed by the delay circuit 62) is output, and synchronous clock data corresponding to the baud rate is output. In this case, the ECU 36 of the wireless sensor receiving station 14 uses the sensor parameter based on the digital data from the sensor 10 normally wirelessly transmitted from the wireless sensor transmitting station 12 and the synchronous clock data obtained by the delay of the digital data. Is detected.

  In this regard, according to the signal receiving apparatus of the present embodiment, when an error caused by noise mixing or a decrease in radio wave intensity occurs in the received digital data of either the first system or the second system, the error part is masked. Thus, the data bits in the error portion can be complemented with the other normal received digital data. That is, even if an error occurs in the received digital data of either the first system or the second system, it is possible to create received digital data from which the unstable error part is deleted.

  In this embodiment, the reception digital data for deleting the error part is generated by digital processing with a simple configuration such as the counters 42 and 50, the digital comparators 46 and 54, the AND circuits 48 and 56, and the OR circuit 58. Is done. Therefore, according to the signal receiving apparatus of the present embodiment, it is possible to implement error determination and error correction of received digital data with a simple configuration. For this purpose, it is possible to reduce the size of the device itself.

  In the first embodiment, the RF transceiver 30 having the antenna 38 and the RF transceiver 32 having the antenna 40 are added to the counters 42 and 50 of the error detection circuit 34 in the “receiving means” described in the claims. The counter reset circuits 44 and 52 and the digital comparators 46 and 54 are included in the “unstable part detection means” described in the claims, and the AND circuits 48 and 56 are included in the “masking means” described in the claims. The OR circuit 58 corresponds to “reception data generation means” described in the claims.

  The signal receiving apparatus according to the second embodiment of the present invention uses an error detection circuit 100 as shown in FIG. 4 in place of the error detection circuit 34 as shown in FIG. 2 in the configuration shown in FIG. FIG. 4 shows a detailed configuration diagram of the error detection circuit 100 of the present embodiment. FIG. 5 shows signal waveforms at various parts of the error detection circuit 100 of this embodiment.

  In this embodiment, the error detection circuit 100 includes a delay circuit 102, an EX-OR circuit 104, a counter 106, a counter reset circuit 108, a digital comparator 110, and two AND circuits provided in the first system on the RF transceiver 30 side. 112, 114, and a delay circuit 116, an EX-OR circuit 118, a counter 120, a counter reset circuit 122, a digital comparator 124, and two AND circuits 126 provided in the second system on the RF transceiver 32 side, 128.

  The delay circuit 102 has a function of delaying the digital data demodulated by the first-system RF transceiver 30 by an extremely short time compared to its baud rate. The EX-OR circuit 104 receives the digital data demodulated by the first-system RF transceiver 30 and the output of the delay circuit 102. The EX-OR circuit 104 outputs a pulse signal having a pulse width corresponding to the delay by the delay circuit 102 when the source waveform of the digital data from the RF transceiver 30 rises and falls.

  A counter 106 is connected to the output of the EX-OR circuit 104. The counter 106 has a function of counting the number of rising edges and falling edges of the pulse signal output from the EX-OR circuit 104. The counter reset circuit 108 is a monostable multivibrator (mono-stable multivibrator) or a one-shot multivibrator, and receives the output of the EX-OR circuit 104. The counter 106 is set so that the counter 106 can perform the counting operation. In this embodiment, since the digital data is transmitted at a constant baud rate, the predetermined time is set to a time corresponding to the baud rate.

  The digital comparator 110 is a circuit that compares the count value count of the counter 106 with a predetermined set value set, and outputs a high signal when count ≦ set is satisfied, and outputs a low signal when count> set is satisfied. To do. The set value set is set to the number of edges per predetermined time that cannot be a normal transmission state of digital data.

  Both the AND circuits 112 and 114 are connected to the output of the digital comparator 110. The output of the EX-OR circuit 104 is connected to the input of the AND circuit 112. The AND circuit 112 outputs a high signal when a pulse signal is input from the EX-OR circuit 104 when the output signal of the digital comparator 110 is in a high state. Further, digital data from the RF transceiver 30 is directly input to the input of the AND circuit 114. The AND circuit 114 outputs a high signal when the digital data from the RF transceiver 30 is in a high state when the output signal of the digital comparator 110 is in a high state.

  Similarly, the delay circuit 116 has a function of delaying the digital data demodulated by the second-system RF transceiver 32 by an extremely short time compared to its baud rate. The EX-OR circuit 118 receives the digital data demodulated by the second-system RF transceiver 32 and the output of the delay circuit 116. The EX-OR circuit 118 outputs a pulse signal having a pulse width corresponding to the delay by the delay circuit 102 when the source waveform of the digital data from the RF transceiver 32 rises and falls.

  A counter 120 is connected to the output of the EX-OR circuit 118. The counter 120 has a function of counting the number of rising edges and falling edges of the pulse signal output from the EX-OR circuit 118. The counter reset circuit 122 is a monostable multivibrator (mono-stable multivibrator) or a one-shot multivibrator, and the output of the EX-OR circuit 118 is input thereto. The counter 120 is set so that the counting operation of the counter 120 can be performed. In this embodiment, since the digital data is transmitted at a constant baud rate, the predetermined time is set to a time corresponding to the baud rate.

  The digital comparator 124 is a circuit that compares the count value count of the counter 120 with a predetermined set value set, and outputs a high signal when count ≦ set is satisfied, and outputs a low signal when count> set is satisfied. To do. The set value set is set to the number of edges per predetermined time that cannot be a normal transmission state of digital data.

  Both the AND circuits 126 and 128 are connected to the output of the digital comparator 124. The output of the EX-OR circuit 118 is connected to the input of the AND circuit 126. The AND circuit 126 outputs a high signal when a pulse signal is input from the EX-OR circuit 118 when the output signal of the digital comparator 124 is in a high state. Further, digital data from the RF transceiver 32 is directly input to the input of the AND circuit 128. The AND circuit 128 outputs a high signal when the digital data from the RF transceiver 32 is in a high state when the output signal of the digital comparator 124 is in a high state.

  An OR circuit 130 is connected to the output of the AND circuit 114 on the first system side and the output of the AND circuit 128 on the second system side. The ECU 36 is connected to the output of the OR circuit 130. The input of the OR circuit 132 is connected to the output of the AND circuit 112 on the first system side and the output of the AND circuit 126 on the second system side. The output of the OR circuit 132 is connected to the input of the AND circuit 134. The input of the AND circuit 134 is also connected to a monostable multivibrator (mono-stable multivibrator) or one-shot multivibrator (hereinafter referred to as SS) 136. The output of the AND circuit 134 is input to SS136. The SS 136 has a function of outputting a low signal for a predetermined time from the falling edge of the pulse signal output from the AND circuit 134. The predetermined time is set to a shorter time depending on the baud rate of the digital data. The ECU 36 is connected to the output of the AND circuit 134.

  In the above configuration, when the digital data received and demodulated by the RF transceivers 30 and 32 are free from noise and there is no unstable part that can be an error part, the outputs of the digital comparators 110 and 124 are in a high state. Therefore, the error detection circuit 100 outputs digital data having the same waveform as that of the digital data input from the RF transceivers 30 and 32 (no delay) to the error detection circuit 100 and synchronization corresponding to the baud rate. Clock data is output. In this case, the ECU 36 of the wireless sensor receiving station 14 uses the sensor parameter based on the digital data from the sensor 10 normally wirelessly transmitted from the wireless sensor transmitting station 12 and the synchronous clock data obtained by the delay of the digital data. Can be detected.

  On the other hand, when noise is mixed in any one of the digital data received and demodulated by the RF transceivers 30 and 32 and an unstable part which becomes an error part exists, the output from the error detection circuit 100 is as follows. become.

  That is, for example, when the digital data of the first system on the RF transceiver 30 side becomes unstable due to noise mixing or radio field strength reduction, the digital data input to the first system side of the error detection circuit 100 is short. By repeating high and low in time, the count value count of the counter 106 that started the counting operation at the beginning of the unstable portion exceeds the set value set. In this case, the digital comparator 110 outputs a low signal, and the output of the AND circuit 114 is in a low state, and this output low state is continued for a predetermined time corresponding to the digital data baud rate by the counter reset circuit 108. . However, at this time, if the digital data of the second system on the RF transceiver 32 side is in a stable state in which noise mixing or the like does not occur, the output of the digital comparator 124 is maintained in the high state. The digital data input to the system side is output from the AND circuit 128 as it is.

  In the present embodiment, the wireless sensor receiving station 14 performs a logical OR combination on the received digital data received by the plurality of antennas 38 and 40 of the first and second systems. Therefore, when the received digital data of either the first system or the second system is unstable, the output of the OR circuit 130 to which the outputs of the AND circuits 114 and 128 are input is unstable. Regardless of the digital data, the other stable digital data itself becomes the same, and even in such a situation, the error detection circuit 100 has the same waveform as the normal digital data input from the RF transceiver 30 or 32 to the error detection circuit 100. Digital data (no delay) is output, and synchronous clock data corresponding to the baud rate is output. In this case, the ECU 36 of the wireless sensor receiving station 14 uses the sensor parameter based on the digital data from the sensor 10 normally wirelessly transmitted from the wireless sensor transmitting station 12 and the synchronous clock data obtained by the delay of the digital data. Is detected.

  In this regard, according to the signal receiving apparatus of the present embodiment, as in the first embodiment described above, an error caused by mixing of noise in the received digital data of one of the first system and the second system or a decrease in radio field intensity. When the error occurs, the error portion can be masked and deleted, and the data bits of the error portion can be complemented with the other normal received digital data. That is, even if an error occurs in the received digital data of either the first system or the second system, it is possible to create received digital data from which the unstable error part is deleted.

  In this embodiment, the reception digital data for deleting the error part is created by the delay circuits 102 and 116, the EX-OR circuits 104 and 118, the counters 106 and 120, the digital comparators 110 and 124, the AND circuit 114, 128 and the OR circuit 130 and the like are performed by digital processing with a simple configuration. Therefore, according to the signal receiving apparatus of the present embodiment, as in the first embodiment described above, it is possible to implement error determination and error correction of received digital data with a simple configuration. Thus, it is possible to reduce the size of the apparatus itself in order to perform error determination / correction of received data.

  In the second embodiment, the delay circuits 102 and 116, the EX-OR circuits 104 and 118, the counters 106 and 120, the counter reset circuits 108 and 122, and the digital comparators 110 and 124 included in the error detection circuit 100 are included. In the “unstable part detection means” described in the claims, the AND circuits 114 and 128 are in the “masking means” described in the claims, and the OR circuit 130 is the “received data generation” described in the claims. It corresponds to “means”.

  By the way, in the first and second embodiments described above, a transmission error of digital data received by the RF transceivers 30 and 32 having the plurality of antennas 38 and 40 included in the wireless sensor receiving station 14 is detected, and the error portion is detected. However, in addition to this, the received digital data received by the RF transceivers 30 and 32 and the digital data output from the error detection circuits 34 and 100 are compared. It is good to do. According to such a configuration, it is possible to identify the RF transceivers 30 and 32 that have received digital data in which an unstable part that becomes an error part due to noise mixing or a decrease in radio field strength is present. By specifying the transceivers 30 and 32, it is possible to detect whether or not the RF transceivers 30 and 32 and the antennas 38 and 40 are out of order. Further, the sensor 10 and the wireless sensor transmission station 12 disposed on the tire side can be detected. It becomes possible to grasp the tendency that the wireless sensor receiving station 14 becomes difficult to receive the transmission signal from the wireless sensor transmitting station 12 due to the positional relationship.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of a system provided with the signal receiver which is 1st Example of this invention. It is a detailed block diagram of the error detection circuit of a present Example. It is a signal waveform of each part of the error detection circuit of a present Example. It is a detailed block diagram of the error detection circuit of 2nd Example of this invention. It is a signal waveform of each part of the error detection circuit of a present Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Sensor 12 Wireless sensor transmission station 14 Wireless sensor reception station 34 Error detection circuit

Claims (3)

A plurality of receiving means for receiving the same transmission signal ;
Delay means provided corresponding to each receiving means, for delaying the received digital signal by a shorter time than the baud rate of the digital signal;
A pulse generation unit provided corresponding to each reception unit, and generating a pulse signal by taking an exclusive OR of the received digital signal and the output of the delay unit;
Counting means that is provided corresponding to each receiving means and counts the number of edges per predetermined time of the pulse signal generated by the pulse generating means;
Comparing means provided corresponding to each receiving means, and determining whether or not the number of edges obtained by counting by the counting means is a predetermined number or less;
A first masking unit that is provided corresponding to each receiving unit, and masks the received digital signal when the comparison unit determines that the number of edges exceeds the predetermined number;
A second masking means provided corresponding to each receiving means, and masking the pulse signal generated by the pulse generating means when the comparing means determines that the number of edges exceeds the predetermined number ; ,
By ORing join each digital signals received after the masking processing by said first masking means by the plurality of receiving means, and receiving data generating means for generating a reception data,
Synchronous clock generation for generating synchronous clock data on the basis of the result of ORing the pulse signals generated by the pulse generating means provided corresponding to each receiving means after the masking processing by the second masking means Means,
A demodulating means for demodulating a transmission signal based on the received data generated by the received data generating means and the synchronous clock data generated by the synchronous clock generating means;
A signal receiving apparatus comprising: The first masking means is an AND circuit that takes a logical product of the received digital signal and the result of the comparing means,
2. The signal receiving apparatus according to claim 1, wherein the second masking means is an AND circuit that takes a logical product of the pulse signal generated by the pulse generating means and the result of the comparing means . By comparing the received data generated by the digital signal and the received data generating means which is received by the receiving means, further comprising a false signal reception detecting means for specifying the receiving means has received an incorrect digital signal The signal receiving apparatus according to claim 1 or 2, characterized in that: