JP4577480B2

JP4577480B2 - Insulated gate semiconductor device

Info

Publication number: JP4577480B2
Application number: JP2003162393A
Authority: JP
Inventors: 馨瀬理
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2003-06-06
Filing date: 2003-06-06
Publication date: 2010-11-10
Anticipated expiration: 2023-06-06
Also published as: JP2004363477A

Description

【０００１】
【発明の属する技術分野】
本発明はＩＧＢＴ、ＦＥＴ等の絶縁ゲ−ト型半導体装置に関する。
【０００２】
【従来の技術】
【特許文献１】
特開平６−６９５０９号公報
【特許文献２】
特開昭５８−２５２６４号公報
ＩＧＢＴ即ち絶縁ゲ−ト型バイポ−ラトランジスタは例えば前記特許文献１等で公知である。また、複数のセルを含む絶縁ゲ−ト型電界効果トランジスタの電極パターンは前記特許文献２等で公知である。
【０００３】
本件出願人は、周知のＩＧＢＴの原理に従って、図１及び図２に示す構造のＩＧＢＴを作成した。このＩＧＢＴは、図１で点線で示す複数の微小トランジスタ又は最小活性素子領域とも呼ばれるセルＱを有する。なお、図１には図示を簡単にするために複数のセルの一部のみが示されている。更に詳細に説明すると、ＩＧＢＴは、一方の主面２と他方の主面３とを有する半導体基板１と、エミッタ電極４と、コレクタ電極５と、ゲ−ト電極６と、ゲ−ト接続導体７と、補助導体８とを有する。半導体基板１は、Ｎ型ドリフト領域９ａ及びＮ⁺型バッファ領域９ｂを含むＮ型半導体領域９と、Ｐ型ベ−ス領域１０と、Ｎ型のエミッタ領域１１と、Ｐ型コレクタ領域１２と、第１及び第２の補助半導体領域１３ａ，１３ｂから成るＰ型補助半導体領域１３と、ＦＬＲ即ちフィ−ルドグリミッテイングリング１４とを備えている。
【０００４】
基板１の一方の主面２上に第１の絶縁層１５が配置され、この第１の絶縁層１５のゲ−ト絶縁膜部分１５ａの上にゲ−ト電極６の第１の部分６ａが配置されている。第１の絶縁層１５の保護膜部分１５ｂの上にゲ−ト電極６の第２の部分６ｂが配置されている。
【０００５】
第１の絶縁層１５の上に配置された第２の絶縁層１６の上に、エミッタ電極４、ゲ−ト接続導体７、及び補助導体８が配置されている。第１及び第２の部分６ａ、６ｂから成るゲ−ト電極６は第１及び第２の絶縁層１５、１６の間に配置されている。
【０００６】
金属層から成るゲ−ト接続導体７は、複数のセルのゲ−ト電極６を相互に接続するためのゲ−ト相互接続部分７ａと、このゲ−ト相互接続部分７ａを介してゲ−ト電極６を外部回路に接続するためのゲ−ト外部接続部分７ｂとから成る。図１の平面図から明らかなように、ゲ−ト相互接続部分７ａは、一般にゲ−トバスラインと呼ばれている部分であって、分断領域２１を除いてエミッタ電極４を環状に囲む第１の部分７ａ１と、エミッタ電極４を２分するために第１の部分７ａ１の対向する２つの辺を結ぶ第２の部分７ａ２とから成る。ゲ−ト相互接続部分７ａは第２の絶縁層１７の開口１９を介してゲ−ト電極６の第２の部分６ｂに接続されている。ゲ−ト外部接続部分７ｂは、一般にゲ−トパッドと呼ばれている部分であり、ワイヤ（図示せず）を接続することができるようにゲ−ト相互接続部分７ａよりも十分に広い幅に形成されている。ゲ−ト外部接続部分７ｂから各セルＱのゲ−ト電極６の第１の部分６ａまでの距離は互いに異なるが、金属層から成るゲ−ト相互接続部分７ａがゲ−ト外部接続部分７ｂと略同電位となり、各セルのオン・オフ動作のバラツキが少なくなる。
【０００７】
２つに分断されたエミッタ電極４はエミッタパッドとして機能するように大面積に形成され、第１及び第２の絶縁層１５、１６の開口１８を通して各セルＱのベ−ス領域１０及びエミッタ領域１１に接続されている。従って、各セルＱのベ−ス領域１０及びエミッタ領域１１はエミッタ電極４によって相互に接続されている。なお、ゲ−ト相互接続部分７ａの第２の部分７ａ２で分断されたエミッタ電極４の一方の半分と他方の半分との両方がエミッタパッドとして機能し、ここに接続されるワイヤ（図示せず）によって電気的に相互接続され、１つのエミッタ電極として機能する。
【０００８】
補助半導体領域１３は第１及び第２の補助半導体領域１３ａ，１３ｂから成る。第１の補助半導体領域１３ａは、ベ−ス領域１０よりも深く形成され、ＩＧＢＴのオン期間にＰ型コレクタ領域１２からＮ⁺型バッファ領域９ｂ及びＮ型ドリフト領域９ａに注入された少数キャリアがＩＧＢＴのタ−ンオフ時にＮ⁺型バッファ領域９ｂ及びＮ型ドリフト領域９ａに長い時間蓄積することを防ぐために設けられている。即ち、Ｐ型の補助半導体領域１３はタ−ンオフ時に蓄積キャリアを引き抜いてタ−ンオフ時間を短くする機能を有する。この目的を達成するために、第１の絶縁層１５の保護膜部分１５ｂと第２及び第３の絶縁層１６、１７に形成された開口２０を介して補助導体８がＰ⁺型の第２の補助半導体領域１３ｂに接続されている。また、補助導体８は、エミッタ電極４及びゲ−ト電極７を囲むように環状に形成され、ゲ−ト相互接続部分７ａの分断領域２１の中の連結部分２２のみでエミッタ電極４に電気的に接続されている。
【０００９】
【発明が解決しようとする課題】
ところで、補助導体８とエミッタ電極４とが１つの連結部分２２のみで接続されていると、補助導体８の各部の位置と連結部分２２との距離に大幅なバラツキが生じ、連結部分２２から遠い領域の蓄積キャリアの排出時間が長くなり、キャリアの排出に偏りが生じる。この結果としてスイッチング速度を十分に高めることができなかった。
また、図２のＩＢＧＴからＰ型コレクタ領域１２を省いた構成の絶縁ゲ−ト型電界効果トランジスタにおいては、Ｐ型補助半導体領域１３がＰ型ベ−ス領域１０と同様に寄生ダイオ−ドとして機能し、順方向電圧降下の低減効果等が得られる。しかし、補助導体８が連結部分２２のみを介してソースとして機能する電極４に対して図１に示すように接続されていると、寄生ダイオ−ドの効果にバラツキが生じる。
ＩＧＢＴ，ＦＥＴにおける上記問題を解決するために環状のゲ−ト相互接続部分７ａに複数の分断箇所を設け、ソース又はエミッタ電極４と補助導体８との連結部分を増やすことが考えられる。しかし、もし、この様な構造にすると、ゲ−ト相互接続部分７ａの複数の分断箇所を電気的に接続する導体を追加して設けることが必要になり、構成が複雑になるばかりでなく、コストの上昇を招く。
【００１０】
そこで、本発明の目的は、補助半導体領域の効果を容易に高めることができる絶縁ゲ−ト型半導体装置を提供することにある。
【００１１】
【課題を解決するための手段】
上記課題を解決し、上記目的を達成するための本発明は、複数の絶縁ゲート型半導体素子のセルを含む絶縁ゲート型半導体装置であって、
半導体基板と第１及び第２の主電極（例えばエミッタ電極４とコレクタ電極５）とゲート電極とゲート接続導体と第１の補助導体と複数の第２の補助導体と第１及び第２の絶縁層とを有し、
前記第１及び第２の絶縁層は前記半導体基板の一方の主面上に順次に配置され、
前記第１の絶縁層は比較的薄いゲート絶縁膜部分と比較的厚い保護膜部分とを有し、
前記半導体基板は、この一方の主面に一部が露出するように配置され且つ第１導電型を有している第１の半導体領域（例えばドリフト領域９ａ及びバッファ領域９ｂ）と、前記セルを形成するために前記第１の半導体領域の中に島状に配置され且つ第２導電型を有している第２の半導体領域（例えばベース領域１０）と、前記セルを形成するために前記第２の半導体領域の中に島状に配置され且つ第１導電型を有している第３の半導体領域（例えばエミッタ領域１１）と、前記第２の半導体領域よりも外側において前記第１の半導体領域の中に島状に配置され且つ第２導電型を有している補助半導体領域（例えば第１及び第２の補助半導体領域１３ａ，１３ｂ）とを備え、
前記第２の半導体領域はチャネル形成部分を有し、
前記第１の主電極は前記第２の絶縁層の上に配置され且つ前記複数のセルの前記第２及び第３の半導体領域にそれぞれ接続され、
前記第２の主電極は前記半導体基板の他方の主面に配置され且つ前記第１の半導体領域に直接に又は別な半導体領域を介して接続され、
前記ゲート電極は前記第１の絶縁層の上に配置され且つ前記チャネル形成部分に対向する第１の部分とこの第１の部分を前記ゲート接続導体に接続するための第２の部分とを有し、
前記ゲート接続導体は、前記第２の絶縁層の上に配置され且つ平面的に見て前記複数のセルの外側に配置され且つ前記複数のセルの前記ゲート電極を相互に接続するために前記ゲート電極の前記第２の部分に接続されたゲート相互接続部分と、このゲート相互接続部分を外部に接続するためのゲート外部接続部分とを有し、
前記ゲート相互接続部分は前記第１の主電極よりも外側に配置され且つ前記第２の絶縁層の開口を介して前記ゲート電極の前記第２の部分に接続され、
前記第１の補助導体は前記半導体基板の一方の主面側において前記ゲート相互接続部分よりも外側に配置され且つ前記補助半導体領域に接続され、
前記複数の第２の補助導体のそれぞれは前記第１及び第２の絶縁層の間に配置され且つ前記第１の主電極及び前記第１の補助導体にそれぞれ接続されていることを特徴とする絶縁ゲート型半導体装置に係わるものである。
【００１２】
なお、請求項２に示すように、前記半導体基板は、更に、前記第１の半導体領域と前記半導体基板の他方の主面との間に第２導電型の第４の半導体領域（例えばコレクタ領域１２）を有し、前記第２の主電極が前記第４の半導体領域に接続されていることが望ましい。
また、請求項３に示すように、前記半導体基板の他方の主面に前記第１及び第４の半導体領域（例えばコレクタ領域１２）の両方が露出し、前記第２の主電極が前記第第１及び４の半導体領域に接続されている構成とすることができる。
また、請求項４に示すように、前記第４の半導体領域（例えばコレクタ領域）を、前記第１の半導体領域の中に突出している第１の部分（１２ａ）と、前記第１の部分及び前記第１の半導体領域に隣接配置され且つ前記第２の主電極に接続されている第２の部分（１２ｂ）とを有している構成にすることができる。
また、請求項５に示すように、前記第１の半導体領域は、前記半導体基板の一方の主面側に配置されたドリフト領域（９ａ）と、前記ドリフト領域と前記第４の半導体領域との間に配置され且つ前記ドリフト領域よりも高い不純物濃度を有しているバッファ領域（９ｂ）とから成ることが望ましい。
また、請求項６に示すように、前記補助半導体領域は、不純物濃度が比較的低い第１の補助半導体領域（１３ａ）と前記第１の補助半導体領域の中に島状に配置され且つ前記第１の補助半導体領域よりも高い不純物濃度を有している第２の補助半導体領域（１３ｂ）とから成り、前記第１の補助導体（８ａ）は前記第２の補助半導体領域に接続されていることが望ましい。
また、請求項７に示すように、前記第２の補助導体（８ｂ）は、前記ゲート電極（６）と同一の材料で形成されていることが望ましい。
また、請求項８に示すように、前記第１の補助導体は、前記第２の絶縁層の上において前記第１の主電極に接続されている連結部分（２２）を有していることが望ましい。
また、請求項９に示すように、前記第１の主電極と前記ゲート接続導体と前記第１の補助導体とが金属、好ましくは同一の金属で形成され、前記ゲート電極と前記第２の補助導体が導電性を有する多結晶シリコンで形成されていることが望ましい。
【００１３】
【発明の効果】
各請求項の発明によれば、次の効果が得られる。
（１）複数の第２の補助導体（８ｂ）が第１の主電極（例えばエミッタ電極４）と第１の補助導体（８ａ）との間を電気的を接続する。これにより、第１の補助導体と第１の主電極との接続箇所が多くなり、第１の主電極の電位に対する第１の補助導体の各部の電位のバラツキが小さくなり、補助半導体領域の効果を良好に得ることができる。
（２）第２の補助導体（８ｂ）は、ゲ−ト電極と同様に第１及び第２の絶縁層の間に配置されるので、容易に形成することができる。
また、請求項２〜４の発明によれば、ＩＧＢＴが構成され、タ−ンオフ時の蓄積キャリアの排出を迅速に行うことが可能になる。
また、請求項５の発明によれば、第１の半導体領域のバッファ領域によって空乏層の広がりの抑制、及び少数キャリアの注入の抑制を達成することができる。
また、請求項７の発明によれば、第２の補助導体をゲ−ト電極と同時に形成するので、コストの低減を図ることができる。
また、請求項８の発明によれば、連結部分と第２の補助導体との両方で第１の補助導体と第１の主電極との間が接続されているので、補助半導体領域の効果を更に高めることができる。
また、請求項９の発明によれば、第１の主電極とゲート接続導体と第１の補助導体とを金属で容易かつ低抵抗に形成し、且つゲート電極と第２の補助導体とを導電性を有する多結晶シリコンで容易に形成できる。
【００１４】
【発明の実施形態】
次に、図３〜図８を参照して本発明の実施形態に従う絶縁ゲート型半導体装置を説明する。
【００１５】
【第１の実施形態】
図３〜図６に示す第１の実施形態の絶縁ゲート型半導体装置としてのＩＧＢＴは、図１及び図２の補助導体８の代りに第１及び第２の補助導体８ａ、８ｂを設け、この他は図１及び図２と同一に構成したものである。従って、図３〜図６において図１及び図２と実質的に同一の部分には同一の符号が付されている。
即ち、図３〜図６に示す第１の実施形態のＩＧＢＴは、図１及び図２と同様に、図３で点線で示す複数の微小トランジスタ又は最小活性素子領域とも呼ばれるセルＱを有する。なお、図３には図示を簡単にするために複数のセルの一部のみが示されている。また、図３〜図６のＩＧＢＴは、図１及び図２と同様に、一方の主面２と他方の主面３とを有するシリコン半導体基板１と、第１の主電極としてのエミッタ電極４と、第２の主電極としてのコレクタ電極５と、ゲ−ト電極６と、ゲ−ト接続導体７と、第１の補助導体８ａとを有する他に、新たに第２の補助導体８ｂを有する。図３〜図６の第１の補助導体８ａは図１及び図２の補助導体８に相当するものである。
図４の半導体基板１は、Ｎ型ドリフト領域９ａ及びＮ⁺型バッファ領域９ｂを含む第１の半導体領域としてのＮ型半導体領域９と、第２の半導体領域としてのＰ型ベ−ス領域１０と、第３の半導体領域としてのＮ型のエミッタ領域１１と、第４の半導体領域としてのＰ型コレクタ領域１２と、Ｐウェルとも呼ぶことができる第１及び第２の補助半導体領域１３ａ，１３ｂから成る補助半導体領域１３と、ＦＬＲ即ちフィ−ルドリミッテイングリング１４とを備えている。
Ｎ型ドリフト領域９ａは半導体基板１の一方の主面２に一部が露出するように配置されている。Ｎ⁺型バッファ領域９ｂはＮ型ドリフト領域９ａと半導体基板１の他方の主面３との間に配置され且つＮ型ドリフト領域９ａに隣接している。このＮ⁺型バッファ領域９ｂは空乏層の広がりの抑制、及び少数キャリアの注入の抑制の機能を有する。従つて、これらの機能が要求されない時にはＮ⁺型バッファ領域９ｂを省き、第１の半導体領域としてのＮ型半導体領域９をＮ型ドリフト領域９ａのみで構成することもできる。第２の半導体領域としてのＰ型ベ−ス領域１０はＮ型ドリフト領域９ａの中に島状に配置されている。第３の半導体領域としてのＮ型のエミッタ領域１１はＰ型ベ−ス領域１０の中に島状に配置されている。第４の半導体領域としてのＰ型コレクタ領域１２はＮ⁺型バッファ領域９ｂと半導体基板１の他方の主面３との間に配置されている。補助半導体領域１３及びＦＬＲ即ちフィ−ルドリミッテイングリング１４は平面的に見て、即ち基板１の主面２に対して垂直な方向から見て、複数のセルＱを含む主領域を囲むように配置され且つＮ型ドリフト領域９ａの中に島状に配置されている。
【００１６】
半導体基板１の一方の主面２上に例えばシリコン酸化膜から成る第１の絶縁層１５が配置され、この第１の絶縁層１５の比較的薄いゲ−ト絶縁膜部分１５ａの上にゲ−ト電極６の第１の部分６ａが配置されている。即ち、ゲ−ト電極６の第１の部分６ａはＰ型ベ−ス領域１０のチャネル領域及びこの近傍の上に第１の絶縁層１５のゲ−ト絶縁膜部分１５ａを介して配置されている。第１の絶縁層１５の比較的厚い保護膜部分１５ｂの上にゲ−ト電極６の第２の部分６ｂが配置されている。
【００１７】
第１の絶縁層１５の上に配置された例えばシリコン酸化膜から成る第２の絶縁層１６の上に、それぞれが同一の金属層から成るエミッタ電極４、ゲ−ト接続導体７、及び補助導体８が配置されている。導電性を有する多結晶シリコンから成り且つ第１及び第２の部分６ａ、６ｂを有しているゲ−ト電極６は、第１及び第２の絶縁層１５、１６の間に配置されている。
【００１８】
金属層から成るゲ−ト接続導体７は、複数のセルのゲ−ト電極６を相互に接続するためのゲ−ト相互接続部分７ａと、このゲ−ト相互接続部分７ａを介してゲ−ト電極６を外部回路に接続するためのゲ−ト外部接続部分７ｂとから成る。図３の平面図から明らかなように、ゲ−ト相互接続部分７ａは、一般にゲ−トバスラインと呼ばれている部分であって、分断領域２１を除いてエミッタ電極４を平面的に見て、即ち基板１の主面２に対して垂直な方向から見て環状に囲む第１の部分７ａ１と、エミッタ電極４を２分するために第１の部分７ａ１の対向する２つの辺を結ぶ第２の部分７ａ２から成る。金属層から成るゲ−ト相互接続部分７ａは第２の絶縁層１７の開口１９を介して導電性を有する多結晶シリコンから成るゲ−ト電極６の第２の部分６ｂに接続されている。ゲ−ト外部接続部分７ｂは、一般にゲ−トパッドと呼ばれている部分であり、ワイヤ（図示せず）を接続することができるようにゲ−ト相互接続部分７ａよりも十分に広い幅に形成されている。ゲ−ト外部接続部分７ｂから各セルＱのゲ−ト電極６の第１の部分６ａまでの距離は互いに異なるが、金属層から成るゲ−ト相互接続部分７ａがゲ−ト外部接続部分７ｂと略同電位となり、各セルＱのオン・オフ動作のバラツキが少なくなる。
【００１９】
２つに分断されたエミッタ電極４はエミッタパッドとして機能するように大面積に形成され、第１及び第２の絶縁層１５、１６の開口１８を通して各セルＱのベ−ス領域１０及びエミッタ領域１１に接続されている。エミッタ電極４のベ−ス領域１０に対する接続箇所は周知のようにゲ−ト電極６の第１の部分６ａの下のベ−ス領域１０のチャネル部分と反対側である。複数のセルＱのベ−ス領域１０及びエミッタ領域１１はエミッタ電極４によって相互に接続されている。なお、ゲ−ト相互接続部分７ａの第２の部分７ａ２で分断されたエミッタ電極４の一方の半分と他方の半分との両方がエミッタパッドとして機能し、ここに接続されるワイヤ（図示せず）によって電気的に相互接続され、１つのエミッタ電極として機能する。
【００２０】
補助半導体領域１３はＰ型の第１の補助半導体領域１３ａとＰ⁺型の第２の補助半導体領域１３ｂから成り、平面的に見て、即ち基板１の主面２に対して垂直な方向から見て、複数のセルＱを含む主領域を囲むように配置されている。Ｐ型の第１の補助半導体領域１３ａは、ベ−ス領域１０よりも深く形成され、ＩＧＢＴのオン期間にＰ型コレクタ領域１２からＮ⁺型バッファ領域９ｂ及びＮ型ドリフト領域９ａに注入された少数キャリアがＩＧＢＴのタ−ンオフ時にＮ⁺型バッファ領域９ｂ及びＮ型ドリフト領域９ａに長い時間蓄積することを防ぐために設けられている。即ち、Ｐ型の補助半導体領域１３はタ−ンオフ時に蓄積キャリアを引き抜いてタ−ンオフ時間を短くする機能を有する。この目的を達成するために、第１の絶縁層１５の保護膜部分１５ｂと第２及び第３の絶縁層１６、１７に形成された開口２０を介して金属層から成る第１の補助導体８ａがＰ⁺型の第２の補助半導体領域１３ｂに接続されている。また、第１の補助導体８ａは、エミッタ電極４及びゲ−ト接続導体７を囲むように環状に形成され、ゲ−ト相互接続部分７ａの分断領域２１の中の連結部分２２と本発明に従う第２の補助導体８ｂとでエミッタ電極４に電気的に接続されている。
【００２１】
本発明に従って設けられた第２の補助導体８ｂは、図３の平面図から明らかなように、複数箇所に配置され、金属から成る第１の補助導体８ａと金属から成るエミッタ電極４とを電気的に接続している。第２の補助導体８ｂの数は、ゲ−ト相互接続部分７ａとゲ−ト電極６の第２の部分６ｂとを接続する複数の開口１９の数を考慮して適当な値に決定される。
【００２２】
第２の補助導体８ｂは、第１の絶縁層１５の保護膜部分１５ｂと第２の絶縁層１６との間に配置された導電性を有する多結晶シリコンから成る。この第２の補助導体８ｂの一端はエミッタ電極４及びＰ型ベ−ス領域１０に接続され、この他端は第１の補助導体８ａ及び第２の補助半導体領域１３ｂに接続されている。
【００２３】
第２の補助導体８ｂを作成する時には、まず、例えばシリコンから成る半導体基板１の一方の主面２の上に第１の絶縁層１５を形成する。この時、必要に応じてゲ−ト電極６の第１の部分６ａの下のゲ−ト絶縁膜部分１５ａの厚みをこれ以外の保護膜部分１５ｂの厚みよりも薄くする。第１の絶縁層１５の保護膜部分１５ｂは、図４から明らかなように半導体基板１の一方の主面２の少なくともベ−ス領域１０と第２の補助半導体領域１３ｂとの間を覆っている。
【００２４】
次に、第1の絶縁層１５の上にシリコン多結晶層を形成する。次に、このシリコン多結晶層のゲ−ト電極６となる領域及び第２の補助導体８ｂとなる領域に不純物を選択的に導入する。これにより、不純物の導入によって導電性が与えられたゲ−ト電極６及び第２の補助導体８ｂが得られる。第２の補助導体８ｂの抵抗率は第１及び第２の補助半導体領域１３ａ、１３ｂの抵抗率よりも小さい。多結晶シリコン層の内で不純物が導入されなかった領域は必要に応じて酸化され、例えば第３の絶縁層１７となる。この実施形態では、シリコン多結晶層の不純物が導入されない部分が残存しているが、必要に応じてこれを除去してゲ−ト電極６と第２の補助導体８ｂのみを残してもよい。
図６は半導体基板１の一方の主面２の一部、及びこの上の第１及び第２の絶縁層１５、１６の開口１８、１９、２０、及びゲ−ト電極６の第２の部分６ｂ、及び第２の補助導体８ｂの配置関係を説明的に示す。この図６から明らかなように、第２の補助導体８ｂは外周側に並置されたセルＱのベ−ス領域１０の外周側部分から第２の補助半導体領域１３ｂまで帯状に延びている。この第２の補助導体８ｂはゲ−ト電極６の第２の部分６ｂから電気的に分離されるように配置されている。即ち、ゲ−ト電極６の第２の部分６ｂの外周部分が環状に形成されず、基板１の主面２に対して垂直の方向から見て即ち平面的に見て、外周部分に複数の凹部即ち切欠きがあり、この凹部の中に第２の補助導体８ｂが配置されている。
【００２５】
次に、ゲ−ト電極６及び第２の補助導体８ｂを有する第１の絶縁層１５の上に第２の絶縁層１６を設ける。次に、開口１８、１９、２０を形成する。次に、第２の絶縁層１６の上に金属層を形成し、しかる後、金属層を所定パタ−ンにエッチングすることによってエミッタ電極４、ゲ−ト接続導体７、及び第１の補助導体８ａを得る。
【００２６】
エミッタ電極４は、各セルＱのベ−ス領域１０及びエミッタ領域１１に開口１８を通って接続される。ゲ−ト接続導体７の環状のゲ−ト相互接続部分７ａは図５に示すように第２の絶縁層１６の開口１９を介してゲ−ト電極６の第２の部分６ｂに接続される。開口１９は第２の絶縁層１６に複数設けられ、ゲート電極６の第２の部分６ｂとゲ−ト相互接続部分７ａとは複数箇所で接続されている。
【００２７】
本実施形態によれば次の効果が得られる。
（１）エミッタ電極４と第１の補助導体８ａとが連結部分２２と複数の第２の補助導体８ｂとによって接続される。このため、環状に形成されている第１の補助導体８ａの位置の変化による電位のバラツキが小さくなり、ＩＧＢＴのタ−ンオン時に生じる蓄積キャリアを迅速に引き抜くことができる。即ち、多数のセルＱを含む基板１の主領域を囲むように配置されている第１及び第２の補助半導体領域１３ａ、１３ｂの近くの全てのキャリアを第１の補助導体８ａを介してエミッタ電極４に向ってバラツキの少ない状態で迅速に排出させることができ、ターンオフ時間を短縮することができる。
（２）第２の補助導体８ａはゲ−ト電極６と同一の不純物を含む多結晶シリコンから成るので、特別な工程を設けないで、ゲ−ト電極６と同時に形成することができる。この結果、第２の補助導体８ａを設けることによるコストの上昇を抑えることができる。
（３）エミッタ電極４とゲ−ト接続導体７と第１の補助導体８ａとを同一の金属層で容易に形成できる。
【００２８】
【第２の実施形態】
図７は、第２の実施形態に従うＩＧＢＴの一部を示す。このＩＧＢＴは、図４のドリフト領域９ａとバッファ領域９ｂとコレクタ領域１２のパタ−ンを変形した他は図３〜図６と同一に形成したものである。
【００２９】
図７では基板１の他方の主面３の全体にＰ型のコレクタ領域１２が露出せずに、Ｎ型のドリフト領域９ａ及びバッファ領域９ｂも露出している。従って、コレクタ領域１２のみでなく、ドリフト領域９ａ及びバッファ領域９ｂもコレクタ電極５に接続されている。なお、コレクタ領域１２はＩＧＢＴの主電流通路に配置され且つドリフト領域９ａの中に突出するような状態を有する。従って、コレクタ領域１２側からのキャリア注入量を調整することができる。
【００３０】
この実施形態においても、図示はされていないが、図３〜図６と同様な第１及び第２の補助半導体領域１３ａ、１３ｂ及び第１及び第２の補助導体８ａ、８ｂが設けられているので、第１の実施形態と同様な効果を得ることができる。
【００３１】
【第３の実施形態】
図８に示す第３の実施形態のＩＧＢＴは、図７のＩＧＢＴにＰ⁺型の第２のコレクタ領域１２ｂを付加し、この他は図７と同一に形成したものである。即ち、図８では、コレクタ領域が第１及び第２の部分１２ａ、１２ｂの組合せから成り、図１のコレクタ領域１２に相当する第１の部分１２ａの他に、Ｐ⁺型の第２の部分１２ｂを設けたものである。コレクタ電極５には第２の部分１２ｂが接続されている。図８のＩＧＢＴによっても図７のＩＧＢＴと同様な効果を得ることができる。
【００３２】
【変形例】
本発明は上述の実施例に限定されるものでなく、例えば、次の変形が可能なものである。
（１）図４からＰ型コレクタ領域１２を省き、Ｎ⁺バッファ領域９ｂを電極５に接続して絶縁ゲ−ト型電界効果トランジスタとすることができる。この場合には、図４のドリフト領域９ａがドレイン領域、エミッタ領域１１がソ−ス領域、エミッタ電極４がソ−ス電極、コレクタ電極５がドレイン電極として機能する。
（２）ベース領域１０のパターンをストライプ状、格子状態等に変形することができる。
（３）図３では、エミッタ電極４がゲ−ト相互接続部分７ａの第２の部分７ａ2によって２つに分けられているが、第２の部分７ａ2を省くこともできる。
（４）第１及び第２の補助半導体領域１３ａ、１３ｂは、平面的に見てエミッタ電極４を完全に囲むように形成することが望ましいが、複数個に分割されていてもよい。
（５）第２の補助導体８ｂによってエミッタ電極４と第１の補助導体８ａを十分に接続することができる時には、図３に示す連結部分２２による接続を省くことができる。
【図面の簡単な説明】
【図１】従来のＩＧＢＴを概略的に示す平面図である。
【図２】図のＡ−Ａ線を示す断面図である。
【図３】本発明の第１の実施形態に従うＩＧＢＴを概略的に示す平面図である。
【図４】図３のＡ'―Ａ '線を示す断面図である。
【図５】図６のゲ−ト接続用開口１９を通る部分における断面の一部を示す断面図である。
【図６】図４の半導体基板の主面の一部とゲ−ト電極及び第２の補助導体との関係を示す平面図である。
【図７】第２の実施形態のＩＧＢＴの一部を示す断面図である。
【図８】第３の実施形態のＩＧＢＴの一部を示す断面図である。
【符号の説明】
１半導体基板
４エミッタ電極（第１の主電極）
５コレクタ電極（第２の主電極）
６ゲ−ト電極
６ａ第１の部分
６ｂ第２の部分
７ゲ−ト接続導体
７ａゲ−ト相互接続部分
７ｂゲ−ト外部接続部分
８ａ第１の補助導体
８ｂ第２の補助導体
９ａドリフト領域
９ｂバッファ領域
１０ベ−ス領域（第２の半導体領域）
１１エミッタ領域（第３の半導体領域）
１２コレクタ領域（第４の半導体領域）
１３ａ第１の補助半導体領域
１３ｂ第２の補助半導体領域
１５第１の絶縁層
１５ａゲ−ト絶縁膜部分
１５ｂ保護膜部分
１６第２の絶縁層
Ｑセル[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate semiconductor device such as an IGBT or an FET.
[0002]
[Prior art]
[Patent Document 1]
JP-A-6-69509
[Patent Document 2]
JP 58-25264 A
An IGBT, that is, an insulated gate bipolar transistor is known from, for example, the above-mentioned Patent Document 1. Also, the electrode pattern of an insulated gate field effect transistor including a plurality of cells is known from Patent Document 2 and the like.
[0003]
The present applicant created an IGBT having the structure shown in FIGS. 1 and 2 in accordance with the well-known IGBT principle. This IGBT has a plurality of microtransistors or cells Q also called minimum active element regions indicated by dotted lines in FIG. In FIG. 1, only a part of a plurality of cells is shown for ease of illustration. More specifically, the IGBT includes a semiconductor substrate 1 having one main surface 2 and the other main surface 3, an emitter electrode 4, a collector electrode 5, a gate electrode 6, and a gate connection conductor. 7 and an auxiliary conductor 8. The semiconductor substrate 1 includes an N-type drift region 9a and N ⁺ From the N-type semiconductor region 9 including the type buffer region 9b, the P-type base region 10, the N-type emitter region 11, the P-type collector region 12, and the first and second auxiliary semiconductor regions 13a and 13b. A P-type auxiliary semiconductor region 13 and an FLR, ie, a field gritting ring 14 are provided.
[0004]
A first insulating layer 15 is disposed on one main surface 2 of the substrate 1, and a first portion 6 a of the gate electrode 6 is formed on the gate insulating film portion 15 a of the first insulating layer 15. Is arranged. A second portion 6 b of the gate electrode 6 is disposed on the protective film portion 15 b of the first insulating layer 15.
[0005]
On the second insulating layer 16 disposed on the first insulating layer 15, the emitter electrode 4, the gate connection conductor 7, and the auxiliary conductor 8 are disposed. The gate electrode 6 composed of the first and second portions 6 a and 6 b is disposed between the first and second insulating layers 15 and 16.
[0006]
The gate connection conductor 7 made of a metal layer includes a gate interconnection portion 7a for connecting the gate electrodes 6 of a plurality of cells to each other, and the gate interconnection portion 7a via the gate interconnection portion 7a. It comprises a gate external connection portion 7b for connecting the gate electrode 6 to an external circuit. As is apparent from the plan view of FIG. 1, the gate interconnecting portion 7a is a portion generally called a gate bus line, and is a first ring surrounding the emitter electrode 4 except for the dividing region 21. The portion 7a1 and a second portion 7a2 connecting two opposing sides of the first portion 7a1 to divide the emitter electrode 4 into two. The gate interconnection portion 7 a is connected to the second portion 6 b of the gate electrode 6 through the opening 19 of the second insulating layer 17. The gate external connection portion 7b is a portion generally called a gate pad, and has a width sufficiently wider than the gate interconnection portion 7a so that a wire (not shown) can be connected. Is formed. Although the distance from the gate external connection portion 7b to the first portion 6a of the gate electrode 6 of each cell Q is different from each other, the gate interconnection portion 7a made of a metal layer is different from the gate external connection portion 7b. And the variation in the on / off operation of each cell is reduced.
[0007]
The emitter electrode 4 divided into two is formed in a large area so as to function as an emitter pad, and the base region 10 and the emitter region of each cell Q through the openings 18 of the first and second insulating layers 15 and 16. 11 is connected. Accordingly, the base region 10 and the emitter region 11 of each cell Q are connected to each other by the emitter electrode 4. Note that both one half and the other half of the emitter electrode 4 separated by the second portion 7a2 of the gate interconnection portion 7a function as an emitter pad, and a wire (not shown) connected thereto. ) To function as one emitter electrode.
[0008]
The auxiliary semiconductor region 13 includes first and second auxiliary semiconductor regions 13a and 13b. The first auxiliary semiconductor region 13a is formed deeper than the base region 10, and is formed from the P-type collector region 12 to the N-type during the IGBT on period. ⁺ Minority carriers injected into the n-type buffer region 9b and the n-type drift region 9a are N when the IGBT is turned off. ⁺ It is provided to prevent accumulation in the type buffer region 9b and the N type drift region 9a for a long time. That is, the P-type auxiliary semiconductor region 13 has a function of extracting the stored carriers at the turn-off time and shortening the turn-off time. In order to achieve this object, the auxiliary conductor 8 is connected to P through the protective film portion 15b of the first insulating layer 15 and the opening 20 formed in the second and third insulating layers 16 and 17. ⁺ It is connected to the second auxiliary semiconductor region 13b of the mold. The auxiliary conductor 8 is formed in an annular shape so as to surround the emitter electrode 4 and the gate electrode 7, and is electrically connected to the emitter electrode 4 only by the connecting portion 22 in the dividing region 21 of the gate interconnection portion 7a. It is connected to the.
[0009]
[Problems to be solved by the invention]
By the way, if the auxiliary conductor 8 and the emitter electrode 4 are connected by only one connecting portion 22, the distance between the position of each part of the auxiliary conductor 8 and the connecting portion 22 is greatly varied, and is far from the connecting portion 22. The discharge time of the accumulated carriers in the region becomes long, and the discharge of carriers is biased. As a result, the switching speed could not be sufficiently increased.
Further, in the insulated gate field effect transistor in which the P-type collector region 12 is omitted from the IBGT in FIG. 2, the P-type auxiliary semiconductor region 13 is formed as a parasitic diode like the P-type base region 10. Functions and reduces the forward voltage drop. However, if the auxiliary conductor 8 is connected to the electrode 4 functioning as the source only through the connecting portion 22 as shown in FIG. 1, the effect of the parasitic diode varies.
In order to solve the above-mentioned problems in the IGBT and FET, it is conceivable to provide a plurality of dividing points in the annular gate interconnection portion 7a and increase the number of connecting portions between the source or emitter electrode 4 and the auxiliary conductor 8. However, if such a structure is used, it is necessary to additionally provide a conductor for electrically connecting a plurality of divided portions of the gate interconnection portion 7a, which not only complicates the configuration, Increases costs.
[0010]
Accordingly, an object of the present invention is to provide an insulated gate semiconductor device capable of easily enhancing the effect of the auxiliary semiconductor region.
[0011]
[Means for Solving the Problems]
The present invention for solving the above problems and achieving the above object is an insulated gate semiconductor device including a plurality of insulated gate semiconductor element cells,
Semiconductor substrate, first and second main electrodes (for example, emitter electrode 4 and collector electrode 5), gate electrode, gate connection conductor, first auxiliary conductor, and a plurality of second auxiliary conductors When First and second insulating layers;
The first and second insulating layers are sequentially disposed on one main surface of the semiconductor substrate. ,
The first insulating layer has a relatively thin gate insulating film portion and a relatively thick protective film portion. ,
The semiconductor substrate has a first semiconductor region (for example, a drift region 9a and a buffer region 9b) that is arranged so that a part of the semiconductor substrate is exposed and has the first conductivity type; A second semiconductor region (eg, a base region 10) disposed in an island shape in the first semiconductor region and having a second conductivity type to form the first semiconductor region; A third semiconductor region (for example, an emitter region 11) disposed in an island shape in the two semiconductor regions and having the first conductivity type, and the first semiconductor outside the second semiconductor region An auxiliary semiconductor region (for example, first and second auxiliary semiconductor regions 13a and 13b) disposed in an island shape in the region and having the second conductivity type;
The second semiconductor region has a channel forming portion;
The first main electrode is disposed on the second insulating layer and connected to the second and third semiconductor regions of the plurality of cells, respectively.
The second main electrode is disposed on the other main surface of the semiconductor substrate and connected to the first semiconductor region directly or via another semiconductor region;
The gate electrode has a first portion disposed on the first insulating layer and facing the channel forming portion, and a second portion for connecting the first portion to the gate connection conductor. And
The gate connection conductor is disposed on the second insulating layer and disposed on the outside of the plurality of cells in a plan view and connects the gate electrodes of the plurality of cells to each other. A gate interconnect portion connected to the second portion of the electrode, and a gate external connection portion for connecting the gate interconnect portion to the outside,
The gate interconnect portion is disposed outside the first main electrode and connected to the second portion of the gate electrode through an opening in the second insulating layer;
The first auxiliary conductor is disposed outside the gate interconnect portion on one main surface side of the semiconductor substrate and connected to the auxiliary semiconductor region;
Each of the plurality of second auxiliary conductors is disposed between the first and second insulating layers and connected to the first main electrode and the first auxiliary conductor, respectively. The present invention relates to an insulated gate semiconductor device.
[0012]
According to a second aspect of the present invention, the semiconductor substrate further includes a fourth semiconductor region (for example, a collector region) of a second conductivity type between the first semiconductor region and the other main surface of the semiconductor substrate. 12), and the second main electrode is preferably connected to the fourth semiconductor region.
According to a third aspect of the present invention, both the first and fourth semiconductor regions (eg, the collector region 12) are exposed on the other main surface of the semiconductor substrate, and the second main electrode is the first main surface. It can be configured to be connected to the first and fourth semiconductor regions.
According to a fourth aspect of the present invention, the fourth semiconductor region (for example, the collector region) includes a first portion (12a) protruding into the first semiconductor region, the first portion, and It can be configured to have a second portion (12b) that is disposed adjacent to the first semiconductor region and connected to the second main electrode.
Moreover, as shown in claim 5, the first semiconductor region includes a drift region (9a) disposed on one main surface side of the semiconductor substrate, and the drift region and the fourth semiconductor region. It is desirable to comprise a buffer region (9b) disposed between and having a higher impurity concentration than the drift region.
According to a sixth aspect of the present invention, the auxiliary semiconductor region is disposed in an island shape in the first auxiliary semiconductor region (13a) having a relatively low impurity concentration and the first auxiliary semiconductor region, and the first auxiliary semiconductor region. A second auxiliary semiconductor region (13b) having an impurity concentration higher than that of one auxiliary semiconductor region, and the first auxiliary conductor (8a) is connected to the second auxiliary semiconductor region. It is desirable.
Further, as shown in claim 7, it is desirable that the second auxiliary conductor (8b) is formed of the same material as the gate electrode (6).
Moreover, as shown in claim 8, the first auxiliary conductor has a connecting portion (22) connected to the first main electrode on the second insulating layer. desirable.
According to a ninth aspect of the present invention, the first main electrode, the gate connection conductor, and the first auxiliary conductor are formed of metal, preferably the same metal, and the gate electrode and the second auxiliary conductor are formed. It is desirable that the conductor is made of polycrystalline silicon having conductivity.
[0013]
【The invention's effect】
According to the invention of each claim, the following effects can be obtained.
(1) A plurality of second auxiliary conductors (8b) electrically connect the first main electrode (for example, the emitter electrode 4) and the first auxiliary conductor (8a). As a result, the number of connection points between the first auxiliary conductor and the first main electrode is increased, the variation in potential of each part of the first auxiliary conductor with respect to the potential of the first main electrode is reduced, and the effect of the auxiliary semiconductor region is reduced. Can be obtained satisfactorily.
(2) Since the second auxiliary conductor (8b) is disposed between the first and second insulating layers similarly to the gate electrode, it can be easily formed.
Further, according to the inventions of claims 2 to 4, an IGBT is configured, and it is possible to quickly discharge the accumulated carriers at the turn-off time.
According to the invention of claim 5, it is possible to suppress the depletion layer from spreading and the minority carrier injection by the buffer region of the first semiconductor region.
According to the invention of claim 7, since the second auxiliary conductor is formed simultaneously with the gate electrode, the cost can be reduced.
According to the invention of claim 8, since the first auxiliary conductor and the first main electrode are connected to each other by both the connecting portion and the second auxiliary conductor, the effect of the auxiliary semiconductor region can be reduced. It can be further increased.
According to the ninth aspect of the present invention, the first main electrode, the gate connection conductor, and the first auxiliary conductor are formed of metal easily and with low resistance, and the gate electrode and the second auxiliary conductor are electrically conductive. It can be easily formed with polycrystalline silicon having the property.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, an insulated gate semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
[0015]
[First Embodiment]
The IGBT as the insulated gate semiconductor device according to the first embodiment shown in FIGS. 3 to 6 includes first and second auxiliary conductors 8a and 8b instead of the auxiliary conductor 8 shown in FIGS. Others are the same as those shown in FIGS. Accordingly, in FIGS. 3 to 6, the same reference numerals are given to substantially the same parts as those in FIGS. 1 and 2.
That is, the IGBT according to the first embodiment shown in FIGS. 3 to 6 has a plurality of minute transistors or cells Q also called minimum active element regions indicated by dotted lines in FIG. 3, as in FIGS. 1 and 2. In FIG. 3, only a part of a plurality of cells is shown for simplification of illustration. 3 to 6, as in FIGS. 1 and 2, a silicon semiconductor substrate 1 having one main surface 2 and the other main surface 3, and an emitter electrode 4 as a first main electrode. In addition to having a collector electrode 5 as a second main electrode, a gate electrode 6, a gate connection conductor 7, and a first auxiliary conductor 8a, a second auxiliary conductor 8b is newly provided. Have. The first auxiliary conductor 8a in FIGS. 3 to 6 corresponds to the auxiliary conductor 8 in FIGS.
4 includes an N-type drift region 9a and an N-type drift region 9a. ⁺ An N-type semiconductor region 9 as a first semiconductor region including a type buffer region 9b, a P-type base region 10 as a second semiconductor region, and an N-type emitter region 11 as a third semiconductor region, A P-type collector region 12 as a fourth semiconductor region, an auxiliary semiconductor region 13 composed of first and second auxiliary semiconductor regions 13a and 13b, which can also be called a P-well, and an FLR, ie, a field limiting ring. 14.
N-type drift region 9 a is arranged so that a part thereof is exposed on one main surface 2 of semiconductor substrate 1. N ⁺ The type buffer region 9 b is disposed between the N type drift region 9 a and the other main surface 3 of the semiconductor substrate 1 and is adjacent to the N type drift region 9 a. This N ⁺ The type buffer region 9b has functions of suppressing the spread of the depletion layer and suppressing the injection of minority carriers. Therefore, N when these functions are not required. ⁺ The N-type semiconductor region 9 as the first semiconductor region can be configured only by the N-type drift region 9a without the type buffer region 9b. The P-type base region 10 as the second semiconductor region is arranged in an island shape in the N-type drift region 9a. An N-type emitter region 11 as a third semiconductor region is arranged in an island shape in the P-type base region 10. The P-type collector region 12 as the fourth semiconductor region is N ⁺ Disposed between mold buffer region 9 b and the other main surface 3 of semiconductor substrate 1. The auxiliary semiconductor region 13 and the FLR or field limiting ring 14 surround the main region including a plurality of cells Q when viewed in plan, that is, when viewed from a direction perpendicular to the main surface 2 of the substrate 1. And is arranged in an island shape in the N-type drift region 9a.
[0016]
A first insulating layer 15 made of, for example, a silicon oxide film is disposed on one main surface 2 of the semiconductor substrate 1, and a gate is formed on a relatively thin gate insulating film portion 15a of the first insulating layer 15. A first portion 6a of the first electrode 6 is disposed. That is, the first portion 6 a of the gate electrode 6 is disposed on the channel region of the P-type base region 10 and the vicinity thereof via the gate insulating film portion 15 a of the first insulating layer 15. Yes. A second portion 6b of the gate electrode 6 is disposed on the relatively thick protective film portion 15b of the first insulating layer 15.
[0017]
On the second insulating layer 16 made of, for example, a silicon oxide film disposed on the first insulating layer 15, the emitter electrode 4 made of the same metal layer, the gate connection conductor 7, and the auxiliary conductor 8 is arranged. The gate electrode 6 made of conductive polycrystalline silicon and having the first and second portions 6a, 6b is disposed between the first and second insulating layers 15, 16. .
[0018]
The gate connection conductor 7 made of a metal layer includes a gate interconnection portion 7a for connecting the gate electrodes 6 of a plurality of cells to each other, and the gate interconnection portion 7a via the gate interconnection portion 7a. It comprises a gate external connection portion 7b for connecting the gate electrode 6 to an external circuit. As is apparent from the plan view of FIG. 3, the gate interconnection portion 7a is a portion generally called a gate bus line, and the emitter electrode 4 is seen in a plan view except for the dividing region 21. That is, the second portion linking the two opposite sides of the first portion 7a1 in order to bisect the emitter electrode 4 and the first portion 7a1 that is annularly viewed from the direction perpendicular to the main surface 2 of the substrate 1. Part 7a2. The gate interconnection portion 7a made of a metal layer is connected to the second portion 6b of the gate electrode 6 made of polycrystalline silicon having conductivity through the opening 19 of the second insulating layer 17. The gate external connection portion 7b is a portion generally called a gate pad, and has a width sufficiently wider than the gate interconnection portion 7a so that a wire (not shown) can be connected. Is formed. Although the distance from the gate external connection portion 7b to the first portion 6a of the gate electrode 6 of each cell Q is different from each other, the gate interconnection portion 7a made of a metal layer is different from the gate external connection portion 7b. And the variation in the on / off operation of each cell Q is reduced.
[0019]
The emitter electrode 4 divided into two is formed in a large area so as to function as an emitter pad, and the base region 10 and the emitter region of each cell Q through the openings 18 of the first and second insulating layers 15 and 16. 11 is connected. As is well known, the connection point of the emitter electrode 4 to the base region 10 is opposite to the channel portion of the base region 10 under the first portion 6a of the gate electrode 6. The base region 10 and the emitter region 11 of the plurality of cells Q are connected to each other by the emitter electrode 4. Note that both one half and the other half of the emitter electrode 4 separated by the second portion 7a2 of the gate interconnection portion 7a function as an emitter pad, and a wire (not shown) connected thereto. ) To function as one emitter electrode.
[0020]
The auxiliary semiconductor region 13 includes a P-type first auxiliary semiconductor region 13a and P ⁺ The second auxiliary semiconductor region 13b of the type is arranged so as to surround the main region including the plurality of cells Q when viewed in plan, that is, when viewed from the direction perpendicular to the main surface 2 of the substrate 1. Yes. The P-type first auxiliary semiconductor region 13a is formed deeper than the base region 10, and the P-type collector region 12 to N ⁺ Minority carriers injected into the n-type buffer region 9b and the n-type drift region 9a are N when the IGBT is turned off. ⁺ It is provided to prevent accumulation in the type buffer region 9b and the N type drift region 9a for a long time. That is, the P-type auxiliary semiconductor region 13 has a function of extracting the stored carriers at the turn-off time and shortening the turn-off time. In order to achieve this object, the first auxiliary conductor 8a made of a metal layer is formed through the protective film portion 15b of the first insulating layer 15 and the openings 20 formed in the second and third insulating layers 16 and 17. Is P ⁺ It is connected to the second auxiliary semiconductor region 13b of the mold. The first auxiliary conductor 8a is formed in an annular shape so as to surround the emitter electrode 4 and the gate connection conductor 7, and according to the present invention, the connection portion 22 in the dividing region 21 of the gate interconnection portion 7a. The second auxiliary conductor 8b is electrically connected to the emitter electrode 4.
[0021]
As is apparent from the plan view of FIG. 3, the second auxiliary conductor 8b provided in accordance with the present invention is arranged at a plurality of locations, and electrically connects the first auxiliary conductor 8a made of metal and the emitter electrode 4 made of metal. Connected. The number of the second auxiliary conductors 8b is determined to an appropriate value in consideration of the number of the plurality of openings 19 connecting the gate interconnection portion 7a and the second portion 6b of the gate electrode 6. .
[0022]
The second auxiliary conductor 8 b is made of conductive polycrystalline silicon disposed between the protective film portion 15 b of the first insulating layer 15 and the second insulating layer 16. One end of the second auxiliary conductor 8b is connected to the emitter electrode 4 and the P-type base region 10, and the other end is connected to the first auxiliary conductor 8a and the second auxiliary semiconductor region 13b.
[0023]
When forming the second auxiliary conductor 8b, first, the first insulating layer 15 is formed on one main surface 2 of the semiconductor substrate 1 made of, for example, silicon. At this time, if necessary, the thickness of the gate insulating film portion 15a under the first portion 6a of the gate electrode 6 is made thinner than the thickness of the other protective film portion 15b. As is clear from FIG. 4, the protective film portion 15b of the first insulating layer 15 covers at least the space between the base region 10 and the second auxiliary semiconductor region 13b on one main surface 2 of the semiconductor substrate 1. Yes.
[0024]
Next, a silicon polycrystalline layer is formed on the first insulating layer 15. Next, impurities are selectively introduced into the region to be the gate electrode 6 and the region to be the second auxiliary conductor 8b of the silicon polycrystalline layer. As a result, the gate electrode 6 and the second auxiliary conductor 8b, which are given conductivity by introducing impurities, are obtained. The resistivity of the second auxiliary conductor 8b is smaller than the resistivity of the first and second auxiliary semiconductor regions 13a and 13b. A region in the polycrystalline silicon layer where no impurity is introduced is oxidized as necessary, and becomes, for example, the third insulating layer 17. In this embodiment, a portion of the silicon polycrystalline layer where impurities are not introduced remains, but this may be removed as necessary to leave only the gate electrode 6 and the second auxiliary conductor 8b.
FIG. 6 shows a part of one main surface 2 of the semiconductor substrate 1, the openings 18, 19, 20 of the first and second insulating layers 15, 16 thereon, and the second part of the gate electrode 6. An arrangement relationship between 6b and the second auxiliary conductor 8b is described in an explanatory manner. As is apparent from FIG. 6, the second auxiliary conductor 8b extends from the outer peripheral side portion of the base region 10 of the cell Q juxtaposed on the outer peripheral side to the second auxiliary semiconductor region 13b. The second auxiliary conductor 8b is disposed so as to be electrically separated from the second portion 6b of the gate electrode 6. That is, the outer peripheral portion of the second portion 6b of the gate electrode 6 is not formed in an annular shape, and a plurality of outer peripheral portions are formed in the outer peripheral portion as viewed from the direction perpendicular to the main surface 2 of the substrate 1, that is, in plan view. There is a recess or notch, and the second auxiliary conductor 8b is disposed in the recess.
[0025]
Next, the second insulating layer 16 is provided on the first insulating layer 15 having the gate electrode 6 and the second auxiliary conductor 8b. Next, openings 18, 19, and 20 are formed. Next, a metal layer is formed on the second insulating layer 16, and then the emitter electrode 4, the gate connection conductor 7, and the first auxiliary conductor are etched by etching the metal layer to a predetermined pattern. 8a is obtained.
[0026]
The emitter electrode 4 is connected to the base region 10 and the emitter region 11 of each cell Q through the opening 18. The ring-shaped gate interconnection portion 7a of the gate connection conductor 7 is connected to the second portion 6b of the gate electrode 6 through the opening 19 of the second insulating layer 16 as shown in FIG. . A plurality of openings 19 are provided in the second insulating layer 16, and the second portion 6b of the gate electrode 6 and the gate interconnection portion 7a are connected at a plurality of locations.
[0027]
According to this embodiment, the following effects can be obtained.
(1) The emitter electrode 4 and the first auxiliary conductor 8a are connected by the connecting portion 22 and the plurality of second auxiliary conductors 8b. For this reason, the variation in potential due to the change in the position of the first auxiliary conductor 8a formed in an annular shape is reduced, and the accumulated carriers generated when the IGBT is turned on can be quickly extracted. That is, all carriers in the vicinity of the first and second auxiliary semiconductor regions 13a and 13b arranged so as to surround the main region of the substrate 1 including a large number of cells Q are emitted through the first auxiliary conductor 8a. The electrode 4 can be discharged quickly with little variation, and the turn-off time can be shortened.
(2) Since the second auxiliary conductor 8a is made of polycrystalline silicon containing the same impurities as the gate electrode 6, it can be formed simultaneously with the gate electrode 6 without providing any special process. As a result, an increase in cost due to the provision of the second auxiliary conductor 8a can be suppressed.
(3) The emitter electrode 4, the gate connection conductor 7 and the first auxiliary conductor 8a can be easily formed of the same metal layer.
[0028]
[Second Embodiment]
FIG. 7 shows a part of the IGBT according to the second embodiment. This IGBT is formed in the same manner as in FIGS. 3 to 6 except that the patterns of the drift region 9a, the buffer region 9b and the collector region 12 in FIG. 4 are modified.
[0029]
In FIG. 7, the P-type collector region 12 is not exposed on the entire other main surface 3 of the substrate 1, and the N-type drift region 9a and the buffer region 9b are also exposed. Accordingly, not only the collector region 12 but also the drift region 9 a and the buffer region 9 b are connected to the collector electrode 5. The collector region 12 is disposed in the main current path of the IGBT and has a state of protruding into the drift region 9a. Therefore, the carrier injection amount from the collector region 12 side can be adjusted.
[0030]
Also in this embodiment, although not shown, first and second auxiliary semiconductor regions 13a and 13b and first and second auxiliary conductors 8a and 8b similar to those shown in FIGS. 3 to 6 are provided. Therefore, the same effect as the first embodiment can be obtained.
[0031]
[Third Embodiment]
The IGBT of the third embodiment shown in FIG. 8 is different from the IGBT of FIG. ⁺ A second collector region 12b of the mold is added, and the others are formed in the same manner as in FIG. That is, in FIG. 8, the collector region is composed of a combination of the first and second portions 12a and 12b, and in addition to the first portion 12a corresponding to the collector region 12 in FIG. ⁺ A second portion 12b of the mold is provided. A second portion 12 b is connected to the collector electrode 5. The same effect as the IGBT of FIG. 7 can be obtained by the IGBT of FIG.
[0032]
[Modification]
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The P-type collector region 12 is omitted from FIG. ⁺ The buffer region 9b can be connected to the electrode 5 to form an insulated gate field effect transistor. In this case, the drift region 9a in FIG. 4 functions as a drain region, the emitter region 11 functions as a source region, the emitter electrode 4 functions as a source electrode, and the collector electrode 5 functions as a drain electrode.
(2) The pattern of the base region 10 can be transformed into a stripe shape, a lattice state, or the like.
(3) In FIG. 3, the emitter electrode 4 is divided into two parts by the second part 7a2 of the gate interconnection part 7a, but the second part 7a2 can be omitted.
(4) The first and second auxiliary semiconductor regions 13a and 13b are preferably formed so as to completely surround the emitter electrode 4 in plan view, but may be divided into a plurality of portions.
(5) When the emitter electrode 4 and the first auxiliary conductor 8a can be sufficiently connected by the second auxiliary conductor 8b, the connection by the connecting portion 22 shown in FIG. 3 can be omitted.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a conventional IGBT.
FIG. 2 is a cross-sectional view taken along line AA in FIG.
FIG. 3 is a plan view schematically showing an IGBT according to the first embodiment of the present invention.
4 is a cross-sectional view taken along the line A′-A ′ of FIG. 3;
5 is a cross-sectional view showing a part of a cross section in a portion passing through a gate connection opening 19 in FIG. 6;
6 is a plan view showing a relationship between a part of the main surface of the semiconductor substrate of FIG. 4, a gate electrode, and a second auxiliary conductor. FIG.
FIG. 7 is a cross-sectional view showing a part of an IGBT according to a second embodiment.
FIG. 8 is a cross-sectional view showing a part of an IGBT according to a third embodiment.
[Explanation of symbols]
1 Semiconductor substrate
4 Emitter electrode (first main electrode)
5 Collector electrode (second main electrode)
6 Gate electrode
6a first part
6b second part
7 Gate connection conductor
7a Gate interconnection part
7b Gate external connection part
8a First auxiliary conductor
8b Second auxiliary conductor
9a Drift region
9b Buffer area
10 base region (second semiconductor region)
11 Emitter region (third semiconductor region)
12 Collector region (fourth semiconductor region)
13a First auxiliary semiconductor region
13b Second auxiliary semiconductor region
15 First insulating layer
15a Gate insulating film part
15b Protective film part
16 Second insulating layer
Q cell

Claims

An insulated gate semiconductor device including a plurality of insulated gate semiconductor element cells,
A semiconductor substrate, first and second main electrodes, a gate electrode, a gate connection conductor, a first auxiliary conductor, a plurality of second auxiliary conductors, and first and second insulating layers;
The first and second insulating layers are sequentially disposed on one main surface of the semiconductor substrate ,
The first insulating layer has a relatively thin gate insulating film portion and a relatively thick protective film portion ;
The semiconductor substrate is arranged such that a part of the semiconductor substrate is exposed and has a first conductivity type, and the first semiconductor region for forming the cell A second semiconductor region disposed in an island shape and having a second conductivity type, and an island shape disposed in the second semiconductor region and forming a first conductivity to form the cell A third semiconductor region having a mold and an auxiliary semiconductor region disposed in an island shape in the first semiconductor region outside the second semiconductor region and having the second conductivity type And
The second semiconductor region has a channel forming portion;
The first main electrode is disposed on the second insulating layer and connected to the second and third semiconductor regions of the plurality of cells, respectively.
The second main electrode is disposed on the other main surface of the semiconductor substrate and connected to the first semiconductor region directly or via another semiconductor region;
The gate electrode has a first portion disposed on the first insulating layer and facing the channel forming portion, and a second portion for connecting the first portion to the gate connection conductor. And
The gate connection conductor is disposed on the second insulating layer and disposed on the outside of the plurality of cells in a plan view and connects the gate electrodes of the plurality of cells to each other. A gate interconnect portion connected to the second portion of the electrode, and a gate external connection portion for connecting the gate interconnect portion to the outside,
The gate interconnect portion is disposed outside the first main electrode and connected to the second portion of the gate electrode through an opening in the second insulating layer;
The first auxiliary conductor is disposed outside the gate interconnect portion on one main surface side of the semiconductor substrate and connected to the auxiliary semiconductor region;
Each of the plurality of second auxiliary conductors is disposed between the first and second insulating layers and connected to the first main electrode and the first auxiliary conductor, respectively. Insulated gate semiconductor device.

The semiconductor substrate further includes a fourth semiconductor region of a second conductivity type between the first semiconductor region and the other main surface of the semiconductor substrate, and the second main electrode is the fourth main electrode. 2. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is connected to the semiconductor region.

The semiconductor substrate further includes a fourth semiconductor region of a second conductivity type between the first semiconductor region and the other main surface of the semiconductor substrate, and the other main surface of the semiconductor substrate includes the 2. The insulated gate semiconductor device according to claim 1, wherein both the first and fourth semiconductor regions are exposed, and the second main electrode is connected to the first and fourth semiconductor regions. .

The semiconductor substrate further includes a fourth semiconductor region of a second conductivity type between the first semiconductor region and the other main surface of the semiconductor substrate, and the fourth semiconductor region includes the first semiconductor region A first portion protruding into one semiconductor region, and a second portion adjacent to the first portion and the first semiconductor region and connected to the second main electrode. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is provided.

The first semiconductor region includes a drift region disposed on one main surface side of the semiconductor substrate, an impurity concentration disposed between the drift region and the fourth semiconductor region, and higher than the drift region. 5. The insulated gate semiconductor device according to claim 2, wherein the insulated gate semiconductor device comprises:

The auxiliary semiconductor region is disposed in an island shape in the first auxiliary semiconductor region having a relatively low impurity concentration and the first auxiliary semiconductor region, and has an impurity concentration higher than that of the first auxiliary semiconductor region. 6. The insulated gate type according to claim 1, further comprising a second auxiliary semiconductor region, wherein the first auxiliary conductor is connected to the second auxiliary semiconductor region. Semiconductor device.

The insulated gate semiconductor device according to claim 1, wherein the second auxiliary conductor is formed of the same material as the gate electrode.

The said 1st auxiliary conductor has a connection part connected to the said 1st main electrode on the said 2nd insulating layer, The Claim 1 thru | or 7 characterized by the above-mentioned. Insulated gate type semiconductor device.

The first main electrode, the gate connection conductor, and the first auxiliary conductor are made of metal, and the gate electrode and the second auxiliary conductor are made of conductive polycrystalline silicon. 9. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is a semiconductor device.