JP4578618B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor film having a crystal structure formed over a substrate having an insulating surface, a manufacturing method thereof, a semiconductor device using the semiconductor film as an active layer, and a manufacturing method thereof. In particular, the present invention relates to a thin film transistor in which an active layer is formed using a crystalline semiconductor film. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, an electro-optical device typified by an active matrix liquid crystal display device formed using thin film transistors, and An electronic device in which such an electro-optical device is mounted as a component is included in the category.
[0002]
[Prior art]
A thin film transistor (hereinafter referred to as a thin film transistor) whose active layer is an amorphous semiconductor film formed on a light-transmitting insulating substrate such as glass and crystallized by laser annealing or thermal annealing. , Written as TFT). A substrate mainly used for manufacturing this TFT is a glass substrate such as barium borosilicate glass or alumino borosilicate glass. Although such a glass substrate is inferior in heat resistance to a quartz substrate, the commercial price is low, and it has an advantage that a large-area substrate can be easily manufactured.
[0003]
The laser annealing method is known as a crystallization technique that does not raise the temperature of a glass substrate so much and can crystallize only an amorphous semiconductor film by applying high energy. In particular, an excimer laser capable of obtaining a large output with short wavelength light is considered to be most suitable for this application. In the laser annealing method using an excimer laser, a laser beam is processed by an optical system so as to be spot-like or linear on the irradiated surface, and the irradiated surface is scanned with the processed laser light (laser light irradiation). The irradiation position is moved relative to the irradiated surface). For example, the excimer laser annealing method using linear laser light is capable of laser annealing the entire irradiated surface by scanning only in the direction perpendicular to the longitudinal direction, and is excellent in productivity. It is becoming mainstream as a manufacturing technology.
[0004]
Laser annealing can be applied to crystallization of various semiconductor materials. However, considering the characteristics of the TFT, it is considered that the use of a crystalline silicon film as the active layer is suitable because high mobility can be achieved. The technology realized a monolithic liquid crystal display device in which a pixel TFT for forming a pixel portion on a single glass substrate and a TFT for a driving circuit provided around the pixel portion are formed.
[0005]
However, the crystalline silicon film produced by the laser annealing method is a collection of a plurality of crystal grains, and the position and size of the crystal grains are random, and it is possible to intentionally form crystal grains at an arbitrary position. There wasn't. For this reason, it has been almost impossible to form a channel formation region of a TFT in which crystallinity is regarded as the most important with a single crystal grain. At the crystal grain interface (grain boundary), the current transport characteristics of the carrier deteriorate due to the influence of recombination centers, trap centers, and potential levels at the grain boundaries due to amorphous structures and crystal defects. was there. As a result, TFTs having a crystalline silicon film as an active layer have not been obtained to date with characteristics equivalent to those of MOS transistors fabricated on a single crystal silicon substrate.
[0006]
As a method for solving such problems, it can be considered as an effective means to increase the crystal grains and control the position of the crystal grains to eliminate the crystal grain boundaries from the channel formation region. For example, "" Location Control of Large Grain Following Excimer-Laser Melting of Si Thin-Films ", R.Ishihara and A.Burtsev, Japanese Journal of Applied Physics vol.37, No.3B, pp1071-1075,1998" A method is disclosed in which the temperature distribution of a silicon film is controlled three-dimensionally to realize crystal position control and enlargement. According to the method, a refractory metal film is formed on a glass substrate, a silicon oxide film having a different thickness is partially formed thereon, and both surfaces of the substrate on which an amorphous silicon film is formed are formed. It is reported that the crystal grain size can be increased to several μm by irradiating excimer laser light.
[0007]
[Problems to be solved by the invention]
The method of Ishihara et al. Is characterized in that the thermal characteristics of the underlying material of the amorphous silicon film are locally changed to control the flow of heat to the substrate so as to have a temperature gradient. However, for that purpose, it is necessary to form a three-layer structure of a refractory metal layer / silicon oxide layer / semiconductor film on a glass substrate. Although it is structurally possible to form a top gate type TFT using this semiconductor film as an active layer, parasitic capacitance is generated between the semiconductor film and the refractory metal layer, resulting in an increase in power consumption. It becomes difficult to realize high-speed operation of the TFT.
[0008]
On the other hand, since the refractory metal layer also serves as a gate electrode, it can be effectively applied to a bottom gate type or an inverted stagger type TFT. However, in the three-layer structure, even if the thickness of the semiconductor film is excluded, the refractory metal layer and the silicon oxide layer have a film thickness suitable for the crystallization process and a film suitable for characteristics as a TFT element. Since the thicknesses do not necessarily match, both the optimum design in the crystallization process and the optimum design of the device structure cannot be satisfied at the same time.
[0009]
Further, when a refractory metal layer having no translucency is formed on the entire surface of the glass substrate, it is impossible to manufacture a transmissive liquid crystal display device. Although the refractory metal layer is useful in terms of high thermal conductivity, a chromium (Cr) film or a titanium (Ti) film typically used as a refractory metal material has high internal stress. There is a high possibility that a problem will occur in the adhesiveness. It is feared that the internal stress affects the semiconductor film formed in the upper layer and acts as a force for distorting the formed crystalline semiconductor film.
[0010]
The present invention is a technique for solving such problems. A crystalline semiconductor film in which the position and size of crystal grains are controlled is produced, and the crystalline semiconductor film is used as a channel formation region of a TFT. As a result, a TFT capable of high-speed operation is realized. It is another object of the present invention to provide a technology capable of applying such TFTs to various semiconductor devices such as a transmissive liquid crystal display device and an image sensor.
[0011]
[Means for Solving the Problems]
Means for solving the above problems will be described with reference to FIG. A heat conductive layer 2 having a light transmitting property and an insulating property is provided in close contact with the main surface of the substrate 1, and a first insulating layer 3 formed in an island shape or a stripe shape in a selected region on the heat conductive layer. Form. A second insulating layer 4 and a semiconductor film 5 are stacked thereon. First, the semiconductor film 5 is formed of a semiconductor film having an amorphous structure (amorphous semiconductor film). The first insulating layer 3 and the second insulating layer 4 have a function for controlling the flow rate of heat to the heat conducting layer 2. The second insulating layer 4 can be omitted. In any case, the amorphous semiconductor film 5 is continuously formed in the region where the first insulating layer 3 is provided on the substrate and the other regions.
[0012]
The semiconductor film 5 formed to have an amorphous structure becomes a crystalline semiconductor film by a crystallization process. Most preferably, the crystallization step is performed by laser annealing. In particular, use of an excimer laser that emits laser light having a wavelength of 400 nm or less as a light source is suitable because the semiconductor film can be preferentially heated. As the excimer laser, a pulse oscillation type or a continuous emission type can be used. The light applied to the semiconductor film 5 can be a linear beam, a spot beam, a planar beam, or the like in the optical system, and is not limited to the shape. The specific laser annealing conditions are appropriately determined by the practitioner. In the crystallization process of the present invention, a reaction that changes from a molten state to a solid state is performed as follows.
[0013]
In the laser annealing method, the semiconductor film is heated and melted by optimizing the condition of the laser beam (or laser beam) to be irradiated, and the generation density of crystal nuclei and the crystal growth from the crystal nuclei are controlled. In FIG. 1, a region A distinguished by a broken line is a region where the first insulating layer 3 is provided on the heat conductive layer 2. A region B indicates a peripheral region where the first insulating layer 3 is not provided. Since the pulse width of the excimer laser is several nsec to several tens of nsec, for example 30 nsec, when irradiated with a pulse oscillation frequency of 30 Hz, the semiconductor film is instantaneously heated by the pulse laser beam and cooled for a time much longer than the heating time. Will be. Although the semiconductor film is melted by the laser light irradiation, the region A is increased in volume by the amount of the first insulating layer formed as compared with the region B, so that the temperature rise is reduced. On the other hand, since heat is diffused through the heat conducting layer 2 immediately after the irradiation of the laser beam, the region B starts to cool more rapidly and changes to a solid state, whereas the region A is relatively slow. To be cooled.
[0014]
It is estimated that crystal nuclei are formed and formed in the cooling process from the molten state to the solid state, but the nucleation density correlates with the temperature of the molten state and the cooling rate, and is rapidly cooled from a high temperature. The tendency to increase the nucleation density has been obtained as empirical knowledge. Accordingly, in the region B that is rapidly cooled from the molten state, the generation density of crystal nuclei is higher than that in the region A, and a plurality of crystal grains are formed by the generation of crystal nuclei at random, and are generated in the region A. Grain shape is relatively smaller than crystal grains. On the other hand, in the region A, by optimizing the laser light irradiation conditions and the first insulating layer 3 and the second insulating layer 4, it becomes possible to control the temperature of the molten state and its cooling rate, Large grain crystals can be grown with one crystal nucleus.
[0015]
Other lasers that enable such crystallization are YAG laser and YVO. _Four There are solid-state lasers represented by lasers and YLF lasers. These solid-state lasers are preferably laser diode-excited, and their second harmonic (532 nm), third harmonic (354.7 nm), and fourth harmonic (266 nm) are used. Irradiation conditions can be a pulse oscillation frequency of 1 to 10 kHz, and a laser energy density of 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate. At this time, the superposition ratio (overlap ratio) of the linear laser light is 80 to 98%.
[0016]
For the crystallization process, only the laser annealing method is not applied, and a thermal annealing method and a laser annealing method may be combined. For example, after the amorphous semiconductor film is first crystallized by a thermal annealing method, it is also possible to form a crystalline semiconductor film by further irradiating laser light. A crystallization method using a catalytic element may be applied to the thermal annealing method.
[0017]
In such a crystallization process, the materials used for the heat conductive layer 2 and the first insulating layer 3 and the second insulating layer 4 formed in close contact with the main surface of the substrate and the film thickness thereof are determined as transients in heat conduction. It is an important selection item for the purpose of controlling general phenomena. The thermal conductivity layer has a thermal conductivity of 10 Wm at room temperature. ^-1 K ^-1 It is necessary to use the above materials. As such a material, a compound containing one or more kinds selected from aluminum oxide, aluminum nitride, aluminum oxynitride, silicon nitride, and boron nitride can be used. Or it is good also as a compound which consists of Si, N, O, and M (M is at least 1 type chosen from Al or rare earth elements).
[0018]
On the other hand, the first insulating layer 3 and the second insulating layer 4 have a thermal conductivity of 10 Wm at room temperature. ^-1 K ^-1 Use material that is less than. A silicon oxynitride film is desirably used as a material having such a thermal conductivity and suitable as a base layer of a TFT formed over a glass substrate. Of course, it is also possible to use a silicon nitride film, a silicon oxide film, or the like. However, as the most preferable material, the first insulating film 3 or the second insulating film 4 is made of SiH by plasma CVD. _Four , N ₂ A silicon oxynitride film formed from O is used, and the composition thereof may include an oxygen concentration of 55 atomic% to 70 atomic% and a nitrogen concentration of 1 atomic% to 20 atomic%.
[0019]
The first insulating layer 3 is similarly formed in an island shape or a stripe shape in accordance with the arrangement of the TFT active layer (the semiconductor film in which the channel formation region, the source region, the drain region, and the LDD region are formed) on the glass substrate. It is divided and formed. For example, the size is 0.35 × 0.35 μm according to the size of the TFT. ² Sub-micron size (channel length x channel width) or 8 x 8 μm ² 8 × 200μm ² Or 12 × 400μm ² And so on. By forming the first insulating layer 3 in accordance with at least the position and size of the channel formation region of the TFT, the channel formation region can be formed by one crystal grain of the crystalline semiconductor film formed thereon. It becomes possible. That is, a structure substantially equivalent to that obtained by forming a channel formation region with a single crystal film can be obtained. At this time, it is desirable that the angle of the side wall at the end face of the first insulating film is 10 degrees or more and less than 40 degrees with respect to the main surface of the glass substrate.
[0020]
By utilizing such a phenomenon, the crystal grains existing in the crystalline semiconductor film can be enlarged. Further, the position of the crystal grains can be arranged at a position where an active layer of the TFT is formed.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. In FIG. 2A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass is used for the substrate 501. For example, Corning # 7059 glass or # 1737 glass base can be preferably used. When such a glass substrate is preliminarily heat-treated at a temperature lower by about 10 to 20 ° C. than the glass strain point, deformation due to contraction of the substrate can be reduced in a later step.
[0022]
On the surface of the substrate 501 on which the TFT is to be formed, a heat conductive layer 502 that is light-transmitting, insulating, and excellent in heat conductivity is formed. The thickness of the heat conductive layer 502 is 50 to 500 nm, and the heat conductivity is 10 Wm. ^-1 K ^-1 That is necessary. Such materials include aluminum oxide (aluminum oxide (Al ₂ O _Three ) Is translucent in visible light and has a thermal conductivity of 20 Wm ^-1 K ^-1 It is suitable. Aluminum oxide is not limited to the stoichiometric ratio, and other elements may be added in order to control characteristics such as thermal conductivity characteristics and internal stress. For example, when aluminum oxide is mixed with nitrogen, aluminum oxynitride (AlN _x O _1-x : 0.02 ≦ x ≦ 0.5) or aluminum nitride (AlN) _x ) Can also be used. Alternatively, a compound containing silicon (Si), oxygen (O), nitrogen (N), and M (M is at least one selected from aluminum (Al) or a rare earth element) can be used. For example, AlSiON or LaSiON can be suitably used. In addition, boron nitride or the like can also be applied.
[0023]
Any of the above oxides, nitrides, and compounds can be formed by sputtering. This is formed by sputtering using a target having a predetermined composition and using an inert gas such as argon (Ar) or nitrogen. Also, the thermal conductivity is 1000Wm ^-1 K ^-1 A thin-film diamond layer or a DLC (Diamond Like Carbon) layer that reaches the maximum thickness may be provided.
[0024]
A first insulating layer 503 is formed thereon. The thermal conductivity of the first insulating layer is 10 Wm ^-1 K ^-1 Use material that is less than. As such a material, a silicon oxide film, a silicon nitride film, or the like can be selected, but a silicon oxynitride film is preferably formed. The silicon oxynitride film is made of SiH by plasma CVD. _Four , N ₂ O is produced as a source gas. O in this source gas ₂ May be added. Although the manufacturing conditions are not limited, the silicon oxynitride film as the first insulating film has a thickness of 50 to 500 nm, an oxygen concentration of 55 atomic% to 70 atomic%, and a nitrogen concentration of 1 atomic% to 20 atomic. % Or less. With such a composition, the internal stress of the silicon oxynitride film is reduced and the fixed charge density is reduced.
[0025]
The first insulating film 503 is formed into an island shape or a stripe shape by etching as shown in FIG. Etching is hydrogen fluoride (HF) or ammonium hydrogen fluoride (NH _Four HF ₂ ). The size of the first insulating films 504 and 505 formed in an island shape is determined as appropriate. The size depends on the application. For example, 0.35 × 0.35 μm according to the size of the TFT. ² Sub-micron size (channel length x channel width) or 8 x 8 μm ² 8 × 200μm ² Or 12 × 400μm ² And so on. The first insulating layers 504 and 505 are formed in accordance with at least the position and size of the channel formation region of the TFT, so that the channel formation region is formed with one crystal grain of the crystalline semiconductor film formed thereon. It becomes possible. Further, the first insulating layers 504 and 505 have a side wall angle on the end surface of the glass substrate 501 that is 10 ° or more and less than 40 °, and is stacked on the tapered surface. Ensure step coverage. The heat conductive layer 502 and the first insulating films 503 and 504 thus manufactured are referred to as a base layer in this specification.
[0026]
Next, a semiconductor film 506 having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0027]
Then, the amorphous semiconductor film 506 is crystallized using a laser annealing method. In addition to the crystallization method, a rapid thermal annealing method (RTA method) can also be applied. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. In the crystallization step, first, it is desirable to release hydrogen contained in the amorphous semiconductor film, and heat treatment is performed at 400 to 500 ° C. for about 1 hour so that the amount of hydrogen contained is 5 atomic% or less.
[0028]
When crystallization is performed by laser annealing, a solid-state laser such as a pulse oscillation type or continuous emission type excimer laser, argon laser, or YAG laser is used as the light source. FIG. 22 is a diagram showing the configuration of such a laser annealing apparatus. An excimer laser, an argon laser, or the like is applied to the laser light generator 2101. The laser beam emitted from the laser light generator 2101 is spread in one direction by the beam expanders 2102 and 2103, and the laser beam reflected by the mirror 2104 is divided by the cylindrical lens array 2105, and the cylindrical lenses 2106 and 2107 A linear beam having a line width of 100 to 1000 μm is irradiated so as to form an irradiation region 2110 on the sample surface. The substrate 2108 is held on a stage 2109 operable in the X direction, Y direction, and θ direction. Then, laser annealing can be performed over the entire surface of the substrate 2108 by moving the stage 2109 with respect to the irradiation region 2110. At this time, the substrate 2108 may be held in an air atmosphere, or a reaction chamber as shown in FIG. 23 may be provided, and crystallization may be performed while being held under reduced pressure or in an inert gas atmosphere.
[0029]
FIG. 23 is a diagram for explaining an embodiment relating to the substrate holding method of the laser annealing apparatus explained in FIG. The substrate 2108 held on the stage 2109 is set in the reaction chamber 2206. The reaction chamber can be in a reduced pressure state or an inert gas atmosphere by an exhaust system or a gas system (not shown), and the stage 2109 can move in the reaction chamber along the guide rail 2207. The laser light enters from a quartz window (not shown) provided on the upper surface of the substrate 2108. With such a structure, the substrate 2108 can be heated to 300 to 500 ° C. by a heating means (not shown) provided on the stage 2109. In FIG. 23, a transfer chamber 2201, an intermediate chamber 2202, and a load / unload chamber 2203 are connected to the reaction chamber 2206 and separated by gate valves 2208 and 2209.
A cassette 2204 capable of holding a plurality of substrates is installed in the load / unload chamber 2203, and the substrates are transferred by a transfer robot 2205 provided in the transfer chamber 2201. A substrate 2108 ′ represents the substrate being transferred. With such a configuration, laser annealing can be continuously performed under reduced pressure or in an inert gas atmosphere.
[0030]
The laser annealing conditions are appropriately selected by the practitioner. For example, the pulse oscillation frequency of an excimer laser is 30 Hz, and the laser energy density is 100 to 500 mJ / cm. ² (Typically 300-400mJ / cm ² ). Then, a linear beam having a line width of 100 to 1000 μm, for example, a line width of 400 μm, is irradiated over the entire surface of the substrate. Since this line width is larger than that of the first insulating film formed in an island shape, the amorphous silicon layer on the first insulating film can be crystallized by irradiation with one pulse of linear beam. Or you may irradiate several times, scanning a linear beam. At this time, the linear beam superposition ratio (overlap ratio) is preferably set to 50 to 98%. The shape of the laser beam can be processed in the same manner even if it is a planar shape.
[0031]
When the pulse oscillation frequency of the excimer laser is 30 Hz, the pulse width is several nanoseconds to several tens of nanoseconds, for example, about 30 nanoseconds. It is heated instantaneously and cooled for a time much longer than the heating time. At this time, as shown in FIG. 2D, when the region where the first insulating film is formed is the region A and the other region is the region B, the region A is formed with the first insulating film. Since the partial volume increases, the temperature rise due to the laser beam irradiation is lower than that in the region B. On the other hand, immediately after the end of the laser beam irradiation, heat diffuses through the heat conductive layer 502, so that the region B is cooled more rapidly.
[0032]
When a continuous light emission excimer laser is used for the laser generator 2101, a similar optical system is used. For example, when a continuous light excimer laser with an output of 1000 W is used, a linear beam of 400 μm × 125 mm may be scanned by the optical system and the entire surface of the substrate may be scanned at a scanning speed of 0.1 to 10 m / sec.
[0033]
In the laser annealing method, the generation density of crystal nuclei and the crystal growth from the crystal nuclei are controlled by optimizing the conditions of the laser beam to be irradiated.
In the region A, the temperature change between heating and cooling is relatively gentle. Therefore, crystal grains grow from the center of the semiconductor film 508 in the region A, and almost entirely over the first insulating layers 504 and 505. Single crystal grains can be grown. On the other hand, since the region B is rapidly cooled, the semiconductor film 507 in the region B grows only small crystal grains, and thus has a structure in which a plurality of crystal grains are aggregated. In this way, a crystalline semiconductor film in which the position of crystal grains is controlled can be formed.
[0034]
Thereafter, a photoresist pattern is formed on the region A of the formed crystalline semiconductor film, and the crystalline silicon film in the region B is selectively removed by dry etching to form island-like semiconductor layers 509 and 510. Also good. CF for dry etching _Four And O ₂ The mixed gas is used. The island-shaped semiconductor layers 509 and 510 thus fabricated have 10 ¹⁶ -10 ¹⁸ /cm ^Three Therefore, heat treatment is performed at a temperature of 300 to 450 ° C. in a hydrogen atmosphere, in a nitrogen atmosphere containing 1 to 3% hydrogen, or in an atmosphere containing hydrogen generated by plasma formation. It is better to carry out the hydrogenation step. Through this hydrogenation step, about 0.01 to 0.1 atomic% of hydrogen is added to the island-shaped semiconductor layers 509 and 510. In this manner, the island-like semiconductor layers 509 and 510 are formed of a single crystal grain and are substantially equivalent to a single crystal. Therefore, when an element such as a TFT is formed in this portion, it is formed on a single crystal silicon substrate. The characteristics comparable to the MOS transistor can be obtained.
[0035]
[Embodiment 2]
In the embodiment shown in FIG. 3, the heat conductive layer 502 is formed on the substrate 501 and the first insulating layers 504 and 505 are formed as in the first embodiment. Thereafter, a second insulating layer 511 is formed on the heat conductive layer and the first insulating layer. The second insulating layer is preferably formed using a silicon oxynitride film like the first insulating layer. Island-like semiconductor layers 509 and 510 are formed on the second insulating layer 511 by the same procedure as in the first embodiment.
[0036]
By changing the thickness of the second insulating layer 511, the rate at which heat is diffused from the semiconductor film to the substrate can be controlled. In addition, although depending on the type of material used for the heat conduction layer and the manufacturing conditions, aluminum nitride has a relatively large internal stress, which causes distortion at the interface with the semiconductor film, which adversely affects crystallization. However, if a silicon oxynitride film having a small internal stress is formed as shown in FIG. 3, such adverse effects can be mitigated. In this case, the thickness of the second insulating layer may be 5 to 100 nm.
[0037]
[Embodiment 3]
The manufacturing method of the crystalline semiconductor film used as the active layer of the TFT is not limited to the laser annealing method, and the laser annealing method and the thermal annealing method may be used in combination. For example, the substrate on which the semiconductor film 506 (amorphous silicon film) having an amorphous structure in the state of FIG. 2C is formed is heated at 600 to 670 ° C. for about 4 to 12 hours using a furnace annealing furnace. The same effect can be obtained by crystallizing and then processing by the laser annealing method described in the first embodiment. In addition, crystallization by a thermal annealing method can be applied to a crystallization method using a catalyst element disclosed in Japanese Patent Laid-Open No. 7-130652.
[0038]
As shown in FIG. 4A, a heat conductive layer 502 and first insulating layers 504 and 505 are formed over a glass substrate 501 in the same manner as in the first embodiment. Further, the second insulating layer 511 may be formed as in the second embodiment, or this layer may be omitted. Then, an amorphous semiconductor film 506 is formed with a thickness of 25 to 80 nm by plasma CVD or sputtering. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, an aqueous solution containing 10 ppm of the catalytic element in terms of weight is applied by a spin coating method to form the layer 512 containing the catalytic element. Catalyst elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au). The catalyst element-containing layer 511 may be formed with a thickness of 1 to 5 nm by a sputtering method or a vacuum deposition method in addition to the spin coating method.
[0039]
By selectively forming the first insulating layers 504 and 505, unevenness is formed on the surface of the amorphous semiconductor film 506. When an aqueous solution containing a catalytic element is applied by spin coating to form the layer 512 containing a catalytic element, the thickness of the layer 512 containing the catalytic element is not uniform, and the first insulating layer is relatively The recessed area that is not formed becomes thicker. As a result, the concentration of the catalytic element that diffuses into the semiconductor film in the next thermal annealing step also increases.
[0040]
Then, in the crystallization step shown in FIG. 4B, first, heat treatment is performed at 400 to 500 ° C. for about 1 hour, so that the hydrogen content of the amorphous silicon film is 5 atomic% or less.
Then, using a furnace annealing furnace, thermal annealing is performed at 550 to 600 ° C. for 1 to 8 hours in a nitrogen atmosphere. A crystalline silicon film can be obtained by the above steps. However, the crystalline semiconductor film 513 formed by thermal annealing in the steps so far consists of a plurality of crystal grains when observed microscopically with a transmission electron microscope or the like, and the size and arrangement of the crystal grains are uniform. It is not random. Further, when observed by Raman spectroscopy, it may be observed that an amorphous region remains locally.
[0041]
It is effective to control the crystal grains of the crystalline semiconductor film 513 so that they can be formed at predetermined positions and to carry out laser annealing at this stage for the purpose of increasing the grain size. In the laser annealing method, the crystalline semiconductor film 513 is once melted and then recrystallized, so that the above object can be achieved. For example, a XeCl excimer laser (wavelength 308 nm) is used to form a linear beam with an optical system, and an oscillation frequency of 5 to 50 Hz and an energy density of 100 to 500 mJ / cm ² Irradiation is performed with a linear beam overlap rate of 80 to 98%. At this time, as shown in FIG. 4C, in the region A where the first insulating layers 504 and 505 are formed and the region B other than that, the highest temperature heated by the laser beam irradiation as described above. Due to the difference in temperature and the cooling rate after irradiation, large crystal grains easily grow in the region A, while the region B grows only small crystal grains because of rapid cooling. In this way, a crystalline semiconductor film in which the position of the large grain shape is controlled can be formed.
[0042]
In this manner, the manufactured crystalline semiconductor film 514 formed over the first insulating layer can form substantially single crystal grains over the region. The other crystalline semiconductor films 515 are relatively small and are regions where random crystal grains are formed. However, the concentration of the catalytic element remaining on the surfaces of the crystalline semiconductor films 514 and 515 in this state is 3 × 10 ^Ten ~ 2x10 ¹¹ atoms / cm ² It is.
[0043]
Therefore, a gettering step disclosed in Japanese Patent Laid-Open No. 10-247735 may be performed. By this gettering step, the concentration of the catalytic element in the crystalline silicon film is reduced to 1 × 10. ¹⁷ atoms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atoms / cm ^Three It can be reduced to. First, as shown in FIG. 4D, a mask insulating film 516 is formed to a thickness of 150 nm on the surface of the crystalline semiconductor films 514 and 515, an opening 517 is formed by patterning, and the crystalline silicon film is formed. Expose. Then, a step of adding phosphorus is performed to provide a phosphorus-containing region 518 in the crystalline silicon film.
In this state, as shown in FIG. 4E, when heat treatment is performed in a nitrogen atmosphere at 500 to 800 ° C. (preferably 500 to 550 ° C.) for 5 to 24 hours, for example, 525 ° C. for 12 hours, The region 518 functions as a gettering site, and the catalytic element remaining in the crystalline silicon films 514 and 515 can be segregated in the phosphorus-containing region 518. Then, the mask insulating film 516 and the phosphorus-containing region 518 are removed, and island-like semiconductor layers 519 and 520 are formed as shown in FIG. 4F, so that the concentration of the catalytic element used in the crystallization process is increased. 1 × 10 ¹⁷ atoms / cm ^Three A crystalline silicon film reduced to the following can be obtained.
[0044]
As described above, when the crystalline silicon film manufactured by the thermal annealing method with the addition of the catalytic element is subjected to the crystallization step by the laser annealing method of the present invention, only the laser annealing method shown in the first embodiment is performed. Compared with the crystallization step, a crystalline semiconductor film having larger crystal grains can be obtained. However, the island-shaped semiconductor layers 519 and 520 thus manufactured have 10 ¹⁶ -10 ¹⁸ /cm ^Three Therefore, heat treatment is performed at a temperature of 300 to 450 ° C. in a hydrogen atmosphere, in a nitrogen atmosphere containing 1 to 3% hydrogen, or in an atmosphere containing hydrogen generated by plasma formation. By performing the hydrogenation process, the defect density is reduced to 10 ¹⁶ /cm ^Three It can be: Through this hydrogenation step, about 0.01 to 0.1 atomic% of hydrogen is added to the island-shaped semiconductor layers 519 and 520.
[0045]
【Example】
[Example 1]
In this embodiment, a manufacturing process of a CMOS circuit including an n-channel TFT and a p-channel TFT will be described with reference to FIGS.
[0046]
In FIG. 5A, barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass substrate is used for the substrate 101. And if it heat-processes beforehand by the temperature about 10-20 degreeC lower than a glass distortion point, the deformation | transformation by shrinkage | contraction of a board | substrate can be reduced in a subsequent process. On the surface of the substrate 101 on which the TFT is to be formed, at least one heat conductive layer 102 having translucency and insulation is formed. Here, aluminum oxynitride (AlN _x O _1-x : 0.02 ≦ x ≦ 0.5) with a thickness of 50 to 500 nm. In addition, Si, N, O, and M (M is at least one element selected from Al, Y, La, Gd, Dy, Nd, Sm, and Er), such as AlSiON and LaSiON, may be used. Such a heat conductive layer can be formed by sputtering. It can be formed by sputtering using a target having a desired composition and using an inert gas such as argon (Ar) or nitrogen. Also, the thermal conductivity is 1000Wm ^-1 K ^-1 A thin-film diamond layer or a DLC (Diamond Like Carbon) layer that reaches the maximum thickness may be provided.
[0047]
Then, SiH is formed thereon by plasma CVD. _Four , N ₂ A silicon oxynitride film made from O is formed to a thickness of 50 to 500 nm, and hydrogen fluoride (HF) or ammonium hydrogen fluoride (NH _Four HF ₂ The first insulating films 103 and 104 are formed in an island shape. The oxygen concentration of the first insulating film is 55 atomic% to 70 atomic% and the nitrogen concentration is 1 atomic% to 20 atomic%. By setting it as such a composition, the fixed charge density in a film | membrane can be reduced and a film | membrane can be densified further.
[0048]
The size of the first insulating films 103 and 104 formed in an island shape is the same as or slightly larger than the size of the island-shaped semiconductor layer to be formed as an active layer in a later step.
Alternatively, it is the same as or slightly larger than the size of the channel formation region of the TFT. The size of the island-shaped semiconductor layer is appropriately determined according to the required TFT characteristics. For example, it may be 20 μm × 8 μm (the length in the channel length direction × the length in the channel width direction). , 28 μm × 30 μm, 45 μm × 63 μm, etc. Therefore, the outer dimensions of the first insulating films 103 and 104 are set to the same size or about 1 to 20% larger than the same size according to the size of each island-like semiconductor layer. In addition, the step of the film to be laminated by taper etching so that the angle of the side wall at the end face of the first insulating films 103 and 104 is 10 degrees or more and less than 40 degrees with respect to the main surface of the glass substrate. Secure the valley.
[0049]
Furthermore, SiH is formed by plasma CVD. _Four , N ₂ A second insulating layer 105 made of a silicon oxynitride film formed from O is formed. The composition of the silicon oxynitride film is such that the oxygen concentration is 55 atomic% or more and 65 atomic% or less and the nitrogen concentration is 1 atomic% or more and 20 atomic% or less to reduce internal stress, and a semiconductor layer formed thereon To avoid direct stress. The second insulating film is formed with a thickness of 10 to 200 nm (preferably 20 to 100 nm). The second insulating layer can be omitted as shown in the first embodiment.
[0050]
Next, a semiconductor layer having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In addition, the second insulating layer and the amorphous semiconductor layer of the base layer may be formed continuously.
[0051]
Then, any one of the methods described in Embodiments 1 to 3 is selected, a crystalline semiconductor film (here, a crystalline silicon film) is formed, and etching is performed to form island-shaped semiconductor layers 107 and 108a. Etching is done by dry etching, CF _Four And O ₂ The mixed gas was used. Each of the island-like semiconductor layers 107 and 108a is composed of a single crystal grain, and a pattern formed by etching can be regarded as a substantially single crystal. Thereafter, a mask layer 109 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD, low pressure CVD, or sputtering. For example, in the case of the plasma CVD method, tetraethyl orthosilicate (TEOS) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And is formed to a thickness of 100 to 150 nm, typically 130 nm.
[0052]
FIG. 7A shows a top view in FIG. In FIG. 7A, the mask layer and the first and second insulating films are omitted. The island-shaped semiconductor layers 107 and 108b are provided so as to overlap with the first insulating films 103 and 104 patterned in an island shape, respectively. In FIG. 7A, the AA ′ cross section corresponds to the cross-sectional structure in FIG.
[0053]
Then, as shown in FIG. 5B, a photoresist mask 110 is provided, and the island-like semiconductor layer 108a for forming the n-channel TFT is controlled to have a threshold voltage of 1 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three An impurity element imparting p-type is added at a moderate concentration. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. Here, diborane (B ₂ H ₆ ) And boron (B) was added. Addition of boron (B) is not always necessary and may be omitted, but the semiconductor layer 108b to which boron (B) is added is formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. Can do.
[0054]
In order to form the LDD region of the n-channel TFT, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layer 108b. As an impurity element imparting n-type to a semiconductor, elements of Group 15 of the periodic table such as phosphorus (P), arsenic (As), and antimony (Sb) are known. A photoresist mask 111 is formed, and phosphine (PH) is added here to add phosphorus (P). _Three ) Was applied. The phosphorus (P) concentration in the impurity region 112 to be formed is 2 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (FIG. 5C). In this specification, the concentration of an impurity element imparting n-type contained in the impurity region 112 is defined as (n ^- ).
[0055]
Next, the mask layer 109 was removed with an etching solution such as hydrofluoric acid diluted with pure water. Then, a step of activating the impurity element added to the island-shaped semiconductor layer 108b in FIGS. 5B and 5C is performed. The activation can be performed by a method such as thermal annealing at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere, or laser annealing as another method. Moreover, you may carry out using both methods together. In this example, a laser activation method is used, an excimer laser beam is used to form a linear beam, an oscillation frequency of 5 to 50 Hz, and an energy density of 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed with an overlap rate of the linear beam of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision.
[0056]
The gate insulating film 113 is formed of an insulating film containing silicon with a film thickness of 40 to 150 nm using a plasma CVD method or a sputtering method. For example, a silicon oxynitride film having a thickness of 120 nm and the same as the first insulating film may be used. SiH _Four And N ₂ O to O ₂ A silicon oxynitride film manufactured by adding is preferable because the fixed charge density in the film is reduced. The gate insulating film is not limited to such a silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a stacked structure (FIG. 5D).
[0057]
As shown in FIG. 5E, a conductive layer is formed to form a gate electrode over the gate insulating film. Although this conductive layer may be formed as a single layer, it may have a laminated structure of two layers or three layers as required. In the present embodiment, a conductive layer (A) 114 made of a conductive nitride metal film and a conductive layer (B) 115 made of a metal film are stacked. The conductive layer (B) 115 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, the conductive layer (A) 114 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, nitride). It is made of molybdenum (MoN) or the like. Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be used for the conductive layer (A) 114. In the conductive layer (B) 115, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. In particular, the oxygen concentration is preferably set to 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0058]
The conductive layer (A) 114 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 115 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick TaN film was used for the conductive layer (A) 114 and a 350 nm Ta film was used for the conductive layer (B) 115, both of which were formed by sputtering. The TaN film was formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas. Ta used Ar as the sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to these sputtering gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a Ta film thereon. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 114. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 113. Can be prevented. In any case, the conductive layer (B) preferably has a resistivity in the range of 10 to 500 μΩcm.
[0059]
Next, a photoresist mask having a predetermined pattern is formed, and the conductive layers (A) 114 and (B) 115 are collectively etched to form gate electrodes 116 and 117. For example, CF by dry etching _Four And O ₂ Mixed gas, or Cl ₂ At a reaction pressure of 1 to 20 Pa. The gate electrodes 116 and 117 are integrally formed of 116a and 117a made of a conductive layer (A) and 116b and 117b made of a conductive layer (B). At this time, the gate electrode 117 provided in the n-channel TFT is formed so as to overlap with part of the impurity region 112 with the gate insulating film 113 interposed therebetween. Alternatively, the gate electrode can be formed using only the conductive layer (B) (FIG. 6A).
[0060]
FIG. 7B shows a top view of FIG. In FIG. 7B, the gate insulating film and the first and second insulating films are omitted. Gate electrodes 116 and 117 provided over the island-shaped semiconductor layers 107 and 108b through a gate insulating film are connected to a gate wiring 128. 7B, the AA ′ cross section corresponds to the cross sectional structure in FIG.
[0061]
Next, impurity regions 119 serving as a source region and a drain region are formed in the island-shaped semiconductor layer 107 that forms the p-channel TFT. Here, an impurity element imparting p-type is added using the gate electrode 116 as a mask, and an impurity region is formed in a self-aligning manner. At this time, the island-shaped semiconductor layer 108b for forming the n-channel TFT is covered with a photoresist mask 118. The impurity region 119 is diborane (B ₂ H ₆ ) Using an ion doping method. The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (FIG. 6B). In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 134 formed here is defined as (p ⁺ ).
[0062]
Next, an impurity region 121 for forming a source region or a drain region was formed in the island-shaped semiconductor layer 108b for forming the n-channel TFT. Here, phosphine (PH _Three ), And the phosphorus (P) concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (FIG. 6C). In this specification, the concentration of the impurity element imparting n-type contained in the impurity region 121 formed here is defined as (n ⁺ ). Phosphorus (P) is also added to the impurity region 119 at the same time, but the phosphorus (P) concentration added to the impurity region 117 is half that of the boron (B) concentration already added in the previous step. Since it is about １ ／, p-type conductivity is ensured and the TFT characteristics are not affected at all.
[0063]
Thereafter, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed by a thermal annealing method. A furnace annealing furnace may be used for this step. In addition, it can be performed by a laser annealing method or a rapid thermal annealing method (RTA method). The annealing treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. Went.
Further, before the annealing treatment, the protective insulating layer 122 with a thickness of 50 to 200 nm is preferably formed using a silicon oxynitride film, a silicon oxide film, or the like. The silicon oxynitride film can be formed under any of the conditions in Table 1, but in addition, SiH _Four 27SCCM, N ₂ Reaction pressure 160Pa, substrate temperature 325 ° C, discharge power density 0.1W / cm with O as 900SCCM ² (FIG. 6D).
[0064]
After the activation step, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is performed on the island-like semiconductor layer 10 by thermally excited hydrogen. ¹⁶ -10 ¹⁸ /cm ^Three This is a step of terminating the dangling bond. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0065]
After the activation and hydrogenation steps are completed, a silicon oxynitride film or a silicon oxide film is further stacked over the protective insulating layer, so that an interlayer insulating layer 123 is formed. The silicon oxynitride film is made of SiH in the same manner as the protective insulating layer 119. _Four 27SCCM, N ₂ O is 900 SCCM, the reaction pressure is 160 Pa, the substrate temperature is 325 ° C., and the discharge power density is 0.15 W / cm. ² As described above, it is formed with a thickness of 500 to 1500 nm (preferably 600 to 800 nm). Then, contact holes reaching the source region or the drain region of the interlayer insulating layer 123 and the protective insulating layer 122 TFT are formed, and source wirings 124 and 125 and a drain wiring 126 are formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is continuously formed by 100 nm, an aluminum film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm are formed by sputtering.
[0066]
Next, a silicon nitride film or a silicon oxynitride film is formed as the passivation film 127 with a thickness of 50 to 500 nm (typically 100 to 300 nm). Furthermore, when the hydrogenation treatment was performed in this state, a favorable result was obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Further, by such heat treatment, hydrogen existing in the interlayer insulating layer 123 and the protective insulating layer 122 can be diffused into the island-shaped semiconductor layers 107 and 108b to be hydrogenated. In any case, the defect density in the island-like semiconductor layers 107 and 108b is 10 ¹⁶ /cm ^Three It is desirable to make it below, and for that purpose, it was sufficient to apply about 0.01 to 0.1 atomic% of hydrogen.
[0067]
Thus, as shown in FIG. 6E, an n-channel TFT 151 and a p-channel TFT 150 were completed on the substrate 101. The p-channel TFT 150 has a channel formation region 152, a source region 153, and a drain region 154 in the island-shaped semiconductor layer 107. The n-channel TFT 151 includes a channel formation region 155, an LDD region 156 (hereinafter, such an LDD region is referred to as Lov) overlapping the island-shaped semiconductor layer 108 and the gate electrode 117, a source region 157, and a drain region 158. ing. The length of the Lov region in the channel length direction was 0.5 to 3.0 μm (preferably 1.0 to 1.5 μm) with respect to the channel length of 3 to 8 μm. Although each TFT has a single gate structure in FIG. 2, it may have a double gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.
[0068]
FIG. 7C shows a top view of FIG. The source wirings 124 and 125 are in contact with the island-shaped semiconductor layers 107 and 108b through contact holes provided in the interlayer insulating layer 123 and the protective insulating layer 122 (not shown). In FIG. 7C, the AA ′ cross section corresponds to the cross sectional structure in FIG.
[0069]
In the p-channel TFT 150 and the n-channel TFT 151 thus manufactured, the channel formation region is formed of a single crystal grain, that is, a single crystal. As a result, the current transport characteristic during the operation of the TFT is not affected by the potential of the grain boundary or the trap, so that a characteristic comparable to that of a MOS transistor fabricated on a single crystal silicon substrate can be obtained. In addition, a shift register circuit, a buffer circuit, a D / A converter circuit, a level shifter circuit, a multiplexer circuit, and the like can be formed using such TFTs. By appropriately combining these circuits, a semiconductor device manufactured on a glass substrate such as a liquid crystal display device, an EL display device, and a contact image sensor can be formed.
[0070]
[Example 2]
This embodiment will be described with reference to FIGS. 8A and 8B in which the underlying layer is manufactured in a different form from the TFT manufactured in Embodiment 1. FIG. The TFT cross-sectional structure shown in FIG. 8 is formed in accordance with the manufacturing procedure of Example 1, and here, differences from Example 1 are shown.
[0071]
FIG. 8A shows a case where SiH is formed on the heat conductive layer 102 and the selectively formed first insulating layers 103 and 104. _Four , N ₂ O, NH _Three Then, an insulating layer 133 made of a silicon oxynitride film manufactured by plasma CVD is provided. This silicon oxynitride film is a silicon oxynitride film having an oxygen concentration of 20 atomic% to 30 atomic% and a nitrogen concentration of 20 atomic% to 30 atomic%, and includes an oxygen content and a nitrogen content. Are formed almost equivalently. As a result, the internal stress can be reduced as compared with the silicon nitride film, and the alkali metal element can be blocked. Further, a second insulating layer 511 is formed thereon. The insulating layer 133 is formed to a thickness of 50 to 200 nm with respect to the thickness of the first insulating layers 103 and 104 being 50 to 500 nm. The third insulating layer has an effect of relaxing stress, and as a result, has an effect of suppressing fluctuations in the threshold voltage and S value of the TFT.
[0072]
In FIG. 8B, the size of the first insulating layers 134 and 135 is relatively smaller than that of the island-shaped semiconductor layers 107 and 108. The crystal grains on the first insulating layer are enlarged, but if the channel formation regions 152 and 155 are positioned in this portion at this time, the crystal grain boundaries can be eliminated in the channel formation region.
[0073]
In FIG. 8C, a groove is formed on the surface of the glass substrate 136 where the TFT is formed. The depth of the groove is 50 to 500 nm, and such groove processing is easily formed by forming a photoresist mask on the glass substrate surface in a predetermined pattern and etching with an aqueous solution containing hydrogen fluoride (HF). it can. And a heat conductive layer is formed in the surface in which the groove | channel was formed. The thickness of the heat conductive layer 137 is 50 to 500 nm. A first insulating layer is formed thereon with a thickness of 500 to 2000 nm. Thereafter, the surface is planarized by using a CMP (Chemical-Mechanical Polishing) method. For example, the heat conductive layer 137 is formed with a thickness of 100 nm on the surface where a groove with a depth of 200 nm is formed, and the first insulating layer is formed with a thickness of 1000 nm. Thereafter, planarization is performed using a CMP method, whereby the thickness of the first insulating layer 138 can be set to 500 nm in a portion where a groove is formed and 300 nm in a portion where a groove is not formed. As the CMP abrasive for the silicon oxynitride film used for the second insulating film, for example, a material obtained by dispersing fumed silica particles obtained by thermally decomposing silicon chloride gas in a KOH-added aqueous solution is used. A TFT is produced on the surface flattened in this manner in the same manner as in the first embodiment.
[0074]
FIG. 8D illustrates an example in which an n-channel TFT 151 and a p-channel TFT 150 are formed over one island-like semiconductor layer 143 formed over the first insulating layer 140. The steps for manufacturing each TFT are the same, and the structure shown in FIG. 8D can be completed by changing the layout pattern of the photomask to be used. As in FIG. 6D in Embodiment 1, the p-channel TFT 150 includes a channel formation region 152, a source region 153, and a drain region 154. The n-channel TFT 151 includes a channel formation region 155, an LDD region 156 that overlaps with the gate electrode 157, a source region 157, and a drain region 158.
FIGS. 6 to 8 show examples in which each TFT has a single gate structure, but the gate electrode may have a double gate structure or a multi-gate structure in which a plurality of gate electrodes are provided. . By bringing the two TFTs close to each other in this way, it is possible to reduce the variation in characteristics of the TFTs and to improve the degree of integration.
[0075]
[Example 3]
This embodiment mode will be described with reference to FIGS. 27 and 28 and a manufacturing process of a CMOS circuit composed of an n-channel TFT and a p-channel TFT having a structure different from that of Example 1. FIG. The permissible range of the process order and the manufacturing conditions here is in accordance with Example 1.
[0076]
As shown in FIG. 27A, a first insulating film 1502, second insulating films 1503 to 1505, and a third insulating film 1506 are formed over a glass substrate 1501 as in Example 1. There is no limitation on the size of the patterned second insulating film, but in order to form an island-shaped semiconductor layer of 45 μm × 65 μm (length in the channel length direction × length in the channel width direction) in a later step. For example, the size of the second insulating film 1504 is 50 μm × 70 μm. An amorphous silicon film 1507a is formed thereon.
[0077]
Next, as shown in FIG. 27B, a crystalline silicon film 1507b is formed by using the laser annealing method described in Embodiment 1. On the second insulating film, the crystal grain size grows to a size of several μm, but it is not necessarily a single crystal grain, and a plurality of crystal grains may exist.
[0078]
Then, as shown in FIG. 27C, a 45 μm × 65 μm island-shaped semiconductor layer 1508 is formed over the second insulating film 1504 with the third insulating film 1506 interposed therebetween. Then, a mask layer 1509 is formed. The steps shown in FIG. 6D to FIG. 7F explain the step of forming a CMOS circuit by forming an n-channel TFT and a p-channel TFT using the island-like semiconductor layer 1508 as an active layer. is there.
[0079]
FIG. 27D shows a channel doping process, in which a resist mask 1510 is provided, and boron (B) is added by ion doping to a region where an n-channel TFT is formed. In FIG. 27E, a resist mask 1511 is provided to form an n-channel TFT LDD region. ^- Impurity regions 1512 are formed. Then, as shown in FIG. 27F, the mask layer 1509 is removed and laser activation processing is performed, so that a gate insulating film 1513 is formed.
[0080]
In FIG. 28A, a conductive layer (A) 1514 and a conductive layer (B) 1515 are formed over the gate insulating film by a sputtering method. A preferred combination of these conductive layers is a combination in which the conductive layer (A) is TaN and the conductive layer (B) is Ta, or a combination in which the conductive layer (A) is WN and the conductive layer (B) is W. It is. Then, gate electrodes 1516 and 1517 are formed as shown in FIG. The gate electrodes 1516 and 1517 are constituted by 1516a and 1517a made of a conductive layer (A) and 1516b and 1517b made of a conductive layer (B).
[0081]
Then, using these gate electrodes as a mask, an impurity element is added by an ion doping method to form a source region and a drain region in a self-aligning manner. FIG. 28C shows a step of forming a source region and a drain region of a p-channel TFT, and an impurity element imparting p-type is added by an ion doping method. ⁺ Impurity regions 1519 are formed. At this time, a region where the n-channel TFT is formed is covered with a resist mask 1518. FIG. 28D shows a step of forming a source region and a drain region of an n-channel TFT. An impurity element imparting n-type conductivity is added by an ion doping method. ⁺ Impurity regions 1521 are formed. Although phosphorus (P) is also added to the impurity region 1519 at the same time, the concentration of phosphorus (P) added to the impurity region 1520 is half that of the boron (B) concentration already added in the previous step. Since it is about １ ／, p-type conductivity is ensured and the TFT characteristics are not affected at all.
[0082]
After that, as shown in FIG. 28E, a protective insulating layer 1522 is formed, and an activation process and a hydrogenation process are performed. After the activation and hydrogenation steps are completed, a silicon oxynitride film or a silicon oxide film is further stacked over the protective insulating layer, so that an interlayer insulating layer 1523 is formed. Then, contact holes reaching the source region or the drain region of the interlayer insulating layer 1523 and the protective insulating layer 1522 TFT are formed, and source wirings 1524 and 1525 and a drain wiring 1526 are formed. Next, a silicon nitride film or a silicon oxynitride film is formed as the passivation film 1527 with a thickness of 50 to 500 nm (typically 100 to 300 nm). Further, when the hydrogenation treatment is performed in this state, a favorable result can be obtained for improving the characteristics of the TFT.
[0083]
Thus, an n-channel TFT 1551 and a p-channel TFT 1550 can be completed over the substrate 1501. The p-channel TFT 1550 has a channel formation region 1552, a source region 1553, and a drain region 1554. The n-channel TFT 1551 has a channel formation region 1555, an LDD region 1556 that overlaps with the gate electrode 1517, a source region 1557, and a drain region 1558. In FIG. 28, each TFT has a single gate structure, but may have a double gate structure or a multi-gate structure provided with a plurality of gate electrodes.
[0084]
In this manner, the island-shaped semiconductor layer 1508 can be formed over the second insulating layer 1504 formed in one island shape, and two TFTs can be formed using the island-shaped semiconductor layer 1508. By bringing the two TFTs close to each other in this way, it is possible to reduce the variation in characteristics of the TFTs and to improve the degree of integration.
[0085]
[Example 4]
A method for manufacturing the pixel TFT of the pixel portion and the TFT of the driver circuit provided in the periphery of the pixel portion over the same substrate will be described in detail with reference to FIGS. However, in order to simplify the description, a CMOS circuit that is a basic circuit such as a shift register circuit and a buffer circuit is shown in the control circuit, and an n-channel TFT that forms a sampling circuit.
[0086]
In FIG. 9A, a barium borosilicate glass substrate or an alumino borosilicate glass substrate is used as the substrate 201. In this example, an aluminoborosilicate glass substrate was used. Aluminum nitride (AlN) is formed to a thickness of 50 nm as the heat conduction layer 202 on the surface of the substrate 201 on which the TFT is to be formed. A first insulating layer 203 to 206 made of a silicon oxynitride film processed into an island shape is formed thereon with a thickness of 200 nm. Further, a second insulating layer 207 made of a silicon oxynitride film was formed thereon with a thickness of 100 nm. In this manner, the heat conductive layer 202, the first insulating layers 203 to 206, and the second insulating layer 207 are stacked to form a base layer.
[0087]
Next, a semiconductor layer 208a having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Further, since the second insulating film 207 and the amorphous silicon layer 208a can be formed by the same film formation method, both may be formed continuously. After the second insulating film is formed, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere, so that variations in characteristics of TFTs to be manufactured and variations in threshold voltage can be reduced.
[0088]
Then, a crystalline silicon film 208b is formed from the amorphous silicon layer 208a. For this, as shown in Embodiment 1, the laser annealing method of the present invention is applied.
Further, the crystalline silicon film 208b may be formed by combining a thermal annealing method and a laser annealing method in accordance with the technique disclosed in Japanese Patent Application Laid-Open No. 7-130552 shown in the third embodiment. When the laser annealing method is used, for example, a XeCl excimer laser (wavelength 308 nm) is used as a laser beam generator, the laser annealing apparatus shown in FIG. ~ 50Hz, energy density 100 ~ 500mJ / cm ² Irradiation is performed with a linear beam overlap ratio of 80 to 98%. In this way, a crystalline silicon film 208b is obtained (FIG. 9B).
[0089]
Then, the crystalline silicon film 208b is etched and divided into islands, and island-like semiconductor layers 209 and 210a to 212a are formed as active layers. Thereafter, a mask layer 213 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD, low pressure CVD, or sputtering. For example, SiH by the low pressure CVD method _Four And O ₂ A silicon oxide film is formed by heating to 400 ° C. at 266 Pa (FIG. 9C).
[0090]
In the channel doping process, a photoresist mask 214 is provided and 1 × 10 6 is used for controlling the threshold voltage over the entire surface of the island-like semiconductor layers 210a to 212a forming the n-channel TFT. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three Boron (B) was added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. Although boron (B) is not necessarily added here, the semiconductor layers 210b to 212b to which boron (B) is added are preferably formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good (FIG. 9D).
[0091]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-like semiconductor layers 210b and 211b. Photoresist masks 215 to 218 were formed in advance. Here, in order to add phosphorus (P), phosphine (PH _Three ) Was applied. Impurity region (n ^- ) The phosphorus (P) concentration of 219, 220 is 1 × 10 ¹⁷ ~ 5x10 ¹⁹ atoms / cm ^Three (FIG. 10A). The impurity region 221 is a semiconductor layer for forming a storage capacitor of the pixel portion, and phosphorus (P) is added to this region at the same concentration.
[0092]
Next, the mask layer 213 is removed with hydrofluoric acid or the like, and a step of activating the impurity element added in FIGS. 9D and 10A is performed. The activation can be performed by thermal annealing at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or laser annealing as another method. Moreover, you may carry out using both together.
In this embodiment, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, an oscillation frequency of 5 to 50 Hz, and an energy density of 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning the linear beam with an overlap ratio of 80 to 98%.
Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision.
[0093]
Then, the gate insulating film 222 is formed with an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. For example, SiH _Four , N ₂ O, O ₂ As a raw material, a silicon oxynitride film formed by a plasma CVD method is used. (Fig. 10 (B))
[0094]
Next, a first conductive layer is formed to form a gate electrode. In this embodiment, a conductive layer (A) 223 made of a conductive nitride metal film and a conductive layer (B) 224 made of a metal film are laminated. Here, the conductive layer (B) 224 is formed with tantalum (Ta) to a thickness of 250 nm by sputtering using Ta as a target, and the conductive layer (A) 223 is formed with tantalum nitride (TaN) to a thickness of 50 nm. (FIG. 10C).
[0095]
Next, photoresist masks 225 to 229 are formed, and the conductive layer (A) 223 and the conductive layer (B) 224 are etched together to form gate electrodes 230 to 233 and a capacitor wiring 234. The gate electrodes 230 to 233 and the capacitor wiring 234 are integrally formed of 230a to 234a made of a conductive layer (A) and 230b to 234b made of a conductive layer (B). At this time, the gate electrodes 231 and 232 formed in the driver circuit are formed so as to overlap part of the impurity regions 219 and 220 with the gate insulating film 222 interposed therebetween (FIG. 10D).
[0096]
Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligning manner using the gate electrode 230 as a mask. A region where the n-channel TFT is formed is covered with a photoresist mask 235. And diborane (B ₂ H ₆ The impurity region (p ⁺ 234 is 1 × 10 ^{twenty one} atoms / cm ^Three (FIG. 11A).
[0097]
Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 237 to 239 are formed, and an impurity element imparting n-type conductivity is added to form impurity regions 241 to 244. This is the phosphine (PH _Three The impurity region (n ⁺ ) (P) concentration of 241 to 244 is 5 × 10 ²⁰ atoms / cm ^Three (FIG. 11B). The impurity region 240 already contains boron (B) added in the previous step, but phosphorus (P) is added at a concentration of 1/2 to 1/3 as compared with it. The influence of phosphorus (P) is not considered, and the TFT characteristics were not affected at all.
[0098]
Then, in order to form an LDD region of the n-channel TFT in the pixel portion, an impurity addition step for imparting n-type was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrode 233 as a mask. The concentration of phosphorus (P) to be added is 5 × 10 ¹⁶ atoms / cm ^Three 9A, FIG. 10A, and FIG. 10B, the impurity region is substantially reduced by adding it at a concentration lower than that of the impurity element added in FIG. ^- Only 245 and 246 are formed (FIG. 11C).
[0099]
Thereafter, a heat treatment process is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. went.
[0100]
In this thermal annealing, conductive films (C) 230c to 234c made of TaN are formed with a thickness of 5 to 80 nm from the surface of the Ta films 230b to 234b formed on the gate electrodes 230 to 233 and the capacitor wiring 234. In addition, tungsten nitride (WN) can be formed when the conductive layers (B) 230b to 234b are tungsten (W), and titanium nitride (TiN) can be formed when the conductive layers (B) 230b to 234b are titanium (Ti). Alternatively, the gate electrodes 230 to 234 can be similarly formed by exposing them to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, thermal annealing was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is performed on the island-like semiconductor layer 10 by thermally excited hydrogen. ¹⁶ -10 ¹⁸ /cm ^Three This is a step of terminating the dangling bond. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0101]
In the case where a catalytic element that promotes crystallization of silicon is used in the crystallization step and the gettering step described in Embodiment 3 is not performed thereafter, a small amount (1 × 10 10 ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three Degree) catalyst element remains. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. As one of means for removing the catalyst element, there is a means for utilizing the gettering action by phosphorus (P). The concentration of phosphorus (P) necessary for gettering is the impurity region (n) formed in FIG. ⁺ ), And the thermal annealing in the activation process performed here causes the catalytic element to segregate from the channel formation region of the n-channel TFT and the p-channel TFT to the impurity regions 240 to 244 to perform gettering. We were able to. As a result, the impurity regions 240 to 244 have 1 × 10 ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three About a catalytic element segregates (FIG. 11D).
[0102]
14A and 15A are top views of the TFT in FIG. 11D, and the AA ′ cross section and the CC ′ cross section are AA ′ and C in FIG. 11D. Corresponds to -C '. Further, the BB ′ cross section and the DD ′ cross section correspond to the cross sectional views of FIG. 16 (A) and FIG. 17 (A). Although the gate insulating film is omitted in the top views of FIGS. 14 and 15, the island-shaped semiconductor layers 209, 210, and 212 formed on the second insulating layers 203, 204, and 206 in the steps up to here are omitted. The gate electrodes 230, 231, 233 and the capacitor wiring 234 are formed as shown in FIG.
[0103]
When the activation and hydrogenation steps are completed, a second conductive layer serving as a gate wiring is formed. The second conductive layer is formed of a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu) which is a low resistance material. In any case, the resistivity of the second conductive layer is about 0.1 to 10 μΩcm. Further, a conductive layer (E) made of titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo) is preferably stacked. In this example, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) was formed as the conductive layer (D) 247, and a titanium (Ti) film was formed as the conductive layer (E) 248. The conductive layer (D) 247 may be 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 248 may be 50 to 200 (preferably 100 to 150 nm) (FIG. 12A). ).
[0104]
Then, in order to form a gate wiring connected to the gate electrode, the conductive layer (E) 248 and the conductive layer (D) 247 were etched to form gate wirings 249 and 250 and a capacitor wiring 251. The etching process starts with SiCl _Four And Cl ₂ And BCl _Three The conductive layer (E) is removed from the surface of the conductive layer (E) to the middle of the conductive layer (D) by a dry etching method using a mixed gas and then the conductive layer (D) is removed by wet etching with a phosphoric acid-based etching solution. Thus, the gate wiring can be formed while maintaining selective processability with the base.
[0105]
14B and 15B show top views of this state, and the AA ′ and CC ′ cross sections correspond to AA ′ and CC ′ in FIG. 12B. ing. Further, the BB ′ cross section and the DD ′ cross section correspond to BB ′ and DD ′ in FIGS. 16B and 17B. 14B and 15B, part of the gate wirings 249 and 250 overlaps with part of the gate electrodes 230, 231, and 233 and is in electrical contact. This state is also apparent from the cross-sectional structure diagrams of FIGS. 16B and 17B corresponding to the BB ′ cross section and the DD ′ cross section, and the conductive layer (C) forming the first conductive layer. And the conductive layer (D) forming the second conductive layer are in electrical contact.
[0106]
The first interlayer insulating film 252 is formed with a thickness of 500 to 1500 nm using a silicon oxide film or a silicon oxynitride film. In this example, SiH _Four 27SCCM, N ₂ O is 900 SCCM, reaction pressure is 160 Pa, substrate temperature is 325 ° C., discharge power density is 0.15 W / cm ² Form with. After that, contact holes reaching the source region or the drain region formed in each island-like semiconductor layer are formed, and source wirings 253 to 256 and drain wirings 257 to 260 are formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is continuously formed by 100 nm, an aluminum film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm are formed by sputtering.
[0107]
Next, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed as the passivation film 261 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Further, by such heat treatment, hydrogen existing in the first interlayer insulating film 252 can be diffused into the island-like semiconductor layers 209 and 210b to 212b to be hydrogenated. In any case, the defect density in the island-like semiconductor layers 107 and 108b is 10 ¹⁶ /cm ^Three It is desirable to set it as follows, and for that purpose, it was sufficient to apply about 0.01 to 0.1 atomic% of hydrogen (FIG. 12C). Note that an opening may be formed in the passivation film 261 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.
[0108]
FIGS. 14C and 15C are top views of this state, and the AA ′ and CC ′ sections correspond to AA ′ and CC ′ in FIG. is doing. Further, the BB ′ cross section and the DD ′ cross section correspond to BB ′ and DD ′ in FIGS. 16C and 17C. 14C and 15C, the first interlayer insulating film is omitted, but source wirings 253, 254, and the like are not illustrated in the source and drain regions of the island-shaped semiconductor layers 209, 210, and 212. 256 and drain wirings 257, 258, and 260 are connected through a contact hole formed in the first interlayer insulating film.
[0109]
Thereafter, a second interlayer insulating film 262 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C. Then, a contact hole reaching the drain wiring 260 is formed in the second interlayer insulating film 262, and pixel electrodes 263 and 264 are formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by sputtering to form a transmissive liquid crystal display device (FIG. 13).
[0110]
In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion on the same substrate was completed. A p-channel TFT 301, a first n-channel TFT 302, and a second n-channel TFT 303 are formed in the driver circuit, and a pixel TFT 304 and a storage capacitor 305 are formed in the pixel portion. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0111]
The p-channel TFT 301 of the driver circuit includes a channel formation region 306, source regions 307a and 307b, and drain regions 308a and 308b in the island-shaped semiconductor layer 209. The first n-channel TFT 302 includes a channel formation region 309, an LDD region (Lov) 310 that overlaps with the gate electrode 231, a source region 311, and a drain region 312 in the island-shaped semiconductor layer 210. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. In the second n-channel TFT 303, a channel formation region 313, an Lov region, and an Loff region (an LDD region that does not overlap with the gate electrode, hereinafter referred to as an Loff region) are formed on the island-shaped semiconductor layer 211. The length of the region in the channel length direction is 0.3 to 2.0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 304 has channel formation regions 318 and 319, Loff regions 320 to 323, and source or drain regions 324 to 326 in the island-shaped semiconductor layer 212. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 305 includes the capacitor wirings 234 and 251, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 327 connected to the drain region 326 of the pixel TFT 304 and doped with an impurity element imparting n-type conductivity. Is formed. Although the pixel TFT 304 has a double gate structure in FIG. 12, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.
[0112]
The configuration as described above makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the drive circuit, and to improve the operation performance and reliability of the semiconductor device. Furthermore, the LDD region, the source region, and the drain region can be easily activated by forming the gate electrode from a heat-resistant conductive material, and the wiring resistance can be sufficiently reduced by forming the gate electrode from a low-resistance material. Therefore, the present invention can be applied to a display device having a display area (screen size) of 4 inches class or more. Then, by using a crystalline silicon film having a single crystal structure which is selectively formed over the first insulating layers 203 to 206 forming the base layer, the n-channel TFT in the completed TFT has an S value. 0.10 V / dec or more and 0.30 V / dec or less, Vth is 0.5 V or more and 2.5 V or less, and field effect mobility is 300 cm. ² / V · sec or more can be realized. In the p-channel TFT, the S value is 0.10 V / dec or more and 0.30 V / dec or less, the Vth is −0.5 V or more and −2.5 V or less, and the field effect mobility is 200 cm. ² / V · sec or more can be realized.
[0113]
[Example 5]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 4 will be described. As shown in FIG. 19, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 603, a transparent conductive film 604, and an alignment film 605 were formed on the counter substrate 602 on the counter side. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process. Thereafter, a liquid crystal material 606 was injected between both substrates and completely sealed with a sealant (not shown).
A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 19 was completed.
[0114]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. 20 and the top view of FIG. 20 and 21 use the same reference numerals in order to correspond to the cross-sectional structure diagrams of FIGS. 9 to 13 and FIG. Further, the cross-sectional structure along the line EE ′ shown in FIG. 21 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.
[0115]
In FIG. 20, the active matrix substrate includes a pixel portion 406, a scanning signal driving circuit 404, and an image signal driving circuit 405 formed on the glass substrate 201. A pixel TFT 304 is provided in the display area, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 404 and the image signal driving circuit 405 are connected to the pixel TFT 304 by a gate wiring 250 and a source wiring 256, respectively. Further, an FPC (Flexible Print Circuit) 731 is connected to the external input / output terminal 734, and is connected to each drive circuit by input wirings 402 and 403.
[0116]
FIG. 21 is a top view showing almost one pixel in the display area 406. The gate wiring 250 intersects the underlying semiconductor layer 212 through a gate insulating film (not shown). Although not shown, the semiconductor layer includes a source region, a drain region, and n ^- A Loff region formed of a region is formed. Reference numeral 265 denotes a contact portion between the source wiring 256 and the source region 324, 266 denotes a contact portion between the drain wiring 260 and the drain region 326, and 267 denotes a contact portion between the drain wiring 260 and the pixel electrode 263. The storage capacitor 305 is formed in a region where the capacitor wirings 234 and 251 overlap with a semiconductor layer 327 extending from the drain region 326 of the pixel TFT 304 and a gate insulating film.
[0117]
Note that the active matrix liquid crystal display device of this example has been described with reference to the structure described in Example 4, but is not limited to the configuration of Example 4, and is described in Embodiments 1 to 3. An active matrix substrate completed by applying the configuration to the fourth embodiment may be used. In any case, the active matrix liquid crystal display device can be manufactured by freely combining the active matrix substrates provided with the base layer shown in Embodiment Mode 1.
[0118]
[Example 6]
FIG. 18 is a diagram illustrating an example of an arrangement of input / output terminals, a display region, and a drive circuit of a liquid crystal display device. In the pixel portion 406, m gate wirings and n source wirings intersect in a matrix. For example, when the pixel density is VGA, 480 gate wirings and 640 source wirings are formed, and in the case of XGA, 768 gate wirings and 1024 source wirings are formed. The screen size of the display area is 340 mm for the 13-inch class and 460 mm for the 18-inch class. In order to realize such a liquid crystal display device, the gate wiring needs to be formed of a low resistance material as shown in the third embodiment. When the time constant (resistance × capacitance) of the gate wiring is increased, the response speed of the scanning signal is decreased, and the liquid crystal cannot be driven at a high speed. For example, when the specific resistance of the material forming the gate wiring is 100 μΩcm, the screen size of the 6 inch class is almost the limit, but when it is 3 μΩcm, the screen size of the 27 inch class can be handled.
[0119]
A scanning signal driving circuit 404 and an image signal driving circuit 405 are provided around the display area 406. Since the length of the gate wiring of these drive circuits is inevitably increased with the increase in the screen size of the display area, in order to realize a large screen, aluminum (Al) or copper (Cu The gate wiring is preferably formed of a low resistance material such as Further, according to the present invention, the input wirings 402 and 403 that connect the input terminal 401 to each driving circuit can be formed of the same material as the gate wiring, which can contribute to a reduction in wiring resistance.
[0120]
On the other hand, when the screen size of the display area is 0.9 inch class, the length of the diagonal line is about 24 mm, and if the TFT is manufactured according to the submicron rule, the driving circuit provided in the periphery is 30 × 30 mm. ² Fits within. In such a case, it is not always necessary to form the gate wiring with the low resistance material as shown in the embodiment 4, and the gate wiring is formed with the same material as that for forming the gate electrode such as Ta or W. It is also possible to do.
[0121]
The liquid crystal display device having such a structure can be completed by using an active matrix substrate completed by applying the crystallization method shown in Embodiments 1 to 3 to Example 4. In any case, the active matrix liquid crystal display device can be manufactured by freely combining the active matrix substrates completed by the crystallization technique shown in the first to third embodiments.
[0122]
[Example 7]
In this embodiment, an example in which the present invention is applied to a display device (organic EL display device) using an active matrix organic electroluminescence (organic EL) material will be described with reference to FIG. FIG. 24A shows a circuit diagram of an active matrix organic EL display device. This organic EL display device includes a display area 11 provided on a substrate, an X-direction peripheral drive circuit 12, and a Y-direction peripheral drive circuit 13. The display area 11 is configured by a switching TFT 330, a storage capacitor 332, a current control TFT 331, an organic EL element 333, X-direction signal lines 18a and 18b, power supply lines 19a and 19b, Y-direction signal lines 20a, 20b, and 20c. Is done.
[0123]
FIG. 24B shows a top view of almost one pixel. The switch TFT 330 is preferably formed in the same manner as the p-channel TFT 301 shown in FIG. 13 and the current control TFT 331 is formed in the same manner as the n-channel TFT 303.
[0124]
By the way, in the case of an organic EL display device in an operation mode in which light is emitted upward from the TFT, the pixel electrode is formed of a reflective electrode such as Al. Here, the configuration of the pixel region of the organic EL display device has been described. However, as in the first embodiment, a peripheral circuit integrated active matrix display device in which a drive circuit is provided around the pixel region may be used. Although not shown, color display is also possible by providing a color filter. In any case, the active matrix organic EL display device can be manufactured by freely combining the active matrix substrates provided with the base layer shown in the first embodiment.
[0125]
[Example 8]
An active matrix substrate, a liquid crystal display device, and an EL display device manufactured by implementing the present invention can be used in various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display medium. Examples of electronic devices include personal computers, digital cameras, video cameras, portable information terminals (mobile computers, mobile phones, electronic books, etc.), navigation systems, and the like. An example of them is shown in FIG.
[0126]
FIG. 25A illustrates a personal computer which includes a main body 2001 including a microprocessor and a memory, an image input portion 2002, a display device 2003, and a keyboard 2004. A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can form a display device 2003 and other signal processing circuits.
[0127]
FIG. 25B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be applied to the display device 2102 and other signal control circuits.
[0128]
FIG. 25C illustrates a portable information terminal which includes a main body 2201, an image input portion 2202, an image receiving portion 2203, operation switches 2204, and a display device 2205. A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be applied to the display device 2205 and other signal control circuits.
[0129]
FIG. 25D illustrates an electronic game device such as a video game or a video game, which is incorporated in a main body 2301, a controller 2305, a display device 2303, and a main body 2301 each including an electronic circuit 2308 such as a CPU, a recording medium 2304, and the like. A display device 2302 is included. The display device 2303 and the display device 2302 incorporated in the main body 2301 may display the same information, or display the information on the recording medium 2304 using the former as a main display device and the latter as a sub display device. The operation state can be displayed, or a touch sensor function can be added to provide an operation panel. In addition, the main body 2301, the controller 2305, and the display device 2303 may be wired communication in order to transmit signals to each other, or may be wireless communication or optical communication by providing sensor units 2306 and 2307. A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be applied to the display devices 2302 and 2303. The display device 2303 can also use a conventional CRT.
[0130]
FIG. 25E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and operation switches 2405. A recording medium such as a DVD (Digital Versatile Disc) or a compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. . A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be suitably used for the display device 2402 and other signal control circuits.
[0131]
FIG. 25F illustrates a digital camera, which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be applied to the display device 2502 and other signal control circuits.
[0132]
FIG. 26A shows a front projector, which includes a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits. FIG. 26B shows a rear projector, which includes a main body 2701, a light source optical system and display device 2702, a mirror 2703, and a screen 2704. A TFT manufactured using a crystalline semiconductor film manufactured by the laser annealing method of the present invention can be applied to a display device and other signal control circuits.
[0133]
Note that FIG. 26C illustrates an example of the structure of the light source optical system and the display devices 2601 and 2702 in FIGS. 26A and 26B. The light source optical system and the display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 includes a plurality of optical lenses. FIG. 26C illustrates a three-plate type example using three liquid crystal display devices 2808; however, the invention is not limited to such a method, and a single-plate optical system may be used. In addition, an appropriate optical lens, a film having a polarization function, a film for adjusting a phase, an IR film, or the like may be provided in an optical path indicated by an arrow in FIG. FIG. 26D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 26D is an example and is not limited to the illustrated configuration.
[0134]
Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, the electronic apparatus of this example can be realized by using the crystallization technique of Embodiments 1 to 3 and using a configuration composed of any combination of Examples 1 to 7.
[0135]
【The invention's effect】
By using the crystallization technique of the present invention, a crystalline semiconductor film in which the position and size of crystal grains are controlled can be manufactured. By forming the crystal grain position of such a crystalline semiconductor film in accordance with the channel formation region of the TFT, it becomes possible to form at least the channel formation region with a single crystal grain, which is substantially a single crystal. Characteristics equivalent to those of a TFT manufactured using a semiconductor film can be obtained.
[0136]
In addition, by forming the heat conductive layer with a material having translucency and insulating properties, it is possible to eliminate the parasitic capacitance on the back channel side in the top gate type TFT, and in addition to the transmission type liquid crystal display device, By applying to various semiconductor devices such as an EL display device and an image sensor, the performance of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of the present invention.
FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a crystalline semiconductor film according to the present invention. FIGS.
FIG. 3 is a cross-sectional view showing a crystalline semiconductor film according to the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of a crystalline semiconductor film according to the present invention.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 7 is a top view illustrating a manufacturing process of a TFT.
FIG. 8 is a cross-sectional view illustrating a structure of a base layer.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
12 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT; FIG.
FIG. 13 is a cross-sectional view of a pixel TFT and a TFT of a driver circuit.
FIG. 14 is a top view illustrating a manufacturing process of a TFT of a driver circuit.
FIG. 15 is a top view illustrating a manufacturing process of a pixel TFT.
FIG. 16 is a cross-sectional view illustrating a manufacturing process of a TFT of a driver circuit.
FIG. 17 is a cross-sectional view illustrating a manufacturing process of a pixel TFT.
18 is a top view illustrating input / output terminals, wiring, and circuit arrangement of a liquid crystal display device. FIG.
FIG 19 is a cross-sectional view illustrating a structure of a liquid crystal display device.
FIG. 20 is a perspective view illustrating a structure of a liquid crystal display device.
FIG. 21 is a top view illustrating a pixel in a pixel portion.
FIG. 22 is a diagram showing a configuration of a laser annealing apparatus.
FIG. 23 is a diagram showing a configuration of a reaction chamber of a laser annealing apparatus.
FIG 24 illustrates a structure of an active matrix EL display device.
FIG 25 illustrates an example of a semiconductor device.
FIG. 26 shows a structure of a projection type liquid crystal display device.
FIG. 27 is a cross-sectional view illustrating a manufacturing process of a TFT.
28 is a cross-sectional view illustrating a manufacturing process of a TFT. FIG.

Claims (19)

A semiconductor device having a TFT on a glass substrate,
A thermal conductivity layer formed in close contact with the main surface of the glass substrate having a thermal conductivity of 10 Wm ⁻¹ K ⁻¹ or more and having translucency and insulation ;
A first insulating layer having a thermal conductivity of less than 10 Wm ⁻¹ K ⁻¹ formed in an island shape or a stripe shape in a selected region on the thermal conductive layer;
A semiconductor film made of a single crystal grain to which hydrogen is selectively formed and formed on the first insulating layer;
A channel formation region of the TFT, a semiconductor device characterized by being formed in a semiconductor film made of single crystal grains the hydrogen is added. A semiconductor device having a TFT on a glass substrate,
The thermal conductivity formed in close contact with the main surface of the glass substrate is 10 Wm ^-1 K ^-1 A heat conductive layer having translucency and insulation,
A thermal conductivity of 10 Wm formed in islands or stripes in selected areas on the thermal conductive layer. ^-1 K ^-1 Less than a first insulating layer;
A second insulating layer formed on the heat conducting layer and the first insulating layer;
A semiconductor film made of a single crystal grain selectively formed on the first insulating layer through the second insulating layer and doped with hydrogen;
The channel formation region of the TFT is formed in a semiconductor film made of a single crystal grain to which the hydrogen is added. 3. The semiconductor device according to claim 2, wherein the thickness of the second insulating layer is 5 to 100 nm. 4. The silicon oxynitride film according to claim 2, wherein the second insulating layer is a silicon oxynitride film having an oxygen concentration of 55 atomic% to 70 atomic% and a nitrogen concentration of 1 atomic% to 20 atomic%. A featured semiconductor device. In any one of claims 1 to 4, the thermally conductive layer is aluminum oxide, aluminum nitride, aluminum oxynitride, silicon nitride, a semiconductor device which is a boron nitride, a thin film diamond or DLC,. In any one of claims 1 to 4, wherein the heat conductive layer is Si, N, O, and M (M is at least one selected from Al or a rare earth element), comprising a compound containing a semiconductor apparatus. In any one of claims 1 to 6, wherein the first insulating layer, the content of oxygen concentration is not more than 55 atomic% or more 70 atomic%, and silicon oxynitride film containing nitrogen concentration is less 1 atomic% or more 20 atomic% A semiconductor device characterized by the above. In any one of claims 1 to 7, a semiconductor device the angle of the side wall in the end face of the first insulating layer, wherein the less than 1 0 degrees 40 degrees with respect to the main surface of the glass substrate . In any one of claims 1 to 8, wherein the semiconductor device includes a semiconductor device which is a display device or a liquid crystal display device, using the electroluminescent material. In any one of claims 1 to 8, wherein the semiconductor device includes a feature that a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disk player, an electronic game device, a projector, or a navigation system, Semiconductor device. A method for manufacturing a semiconductor device having a TFT on a glass substrate,
A step of forming a heat conductive layer having a light conductivity of 10 Wm ⁻¹ K ⁻¹ or more and having a light transmitting property and an insulating property in close contact with the main surface of the glass substrate;
Forming a first insulating layer having a thermal conductivity of less than 10 Wm ⁻¹ K ⁻¹ formed in an island shape or a stripe shape in a selected region on the thermal conductive layer;
Forming an amorphous semiconductor film on the thermally conductive layer and the first insulating layer;
After crystallizing the amorphous semiconductor film, a step of selectively forming a semiconductor film made of single crystal grains on said first insulating layer,
And hydrogenating the semiconductor film made of the single crystal grains, and forming a semiconductor film consisting of a single crystal grains hydrogen is added,
The method for manufacturing a semiconductor device characterized by forming a channel formation region of the TFT using a semiconductor film before Symbol hydrogen consists of a single crystal grains that have been added. A method for manufacturing a semiconductor device having a TFT on a glass substrate,
Thermal conductivity of 10 Wm in close contact with the main surface of the glass substrate ^-1 K ^-1 A step of forming a heat conductive layer having translucency and insulation,
A thermal conductivity of 10 Wm formed in islands or stripes in selected areas on the thermal conductive layer. ^-1 K ^-1 Forming less than the first insulating layer;
Forming a second insulating layer on the thermally conductive layer and the first insulating layer;
Forming an amorphous semiconductor film on the second insulating layer;
A step of selectively forming a semiconductor film made of a single crystal grain on the first insulating layer through the second insulating layer after crystallizing the amorphous semiconductor film;
Hydrogenating the semiconductor film made of a single crystal grain, and forming a semiconductor film made of a single crystal grain to which hydrogen is added,
A method for manufacturing a semiconductor device, wherein a channel formation region of the TFT is formed using a semiconductor film including a single crystal grain to which hydrogen is added. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the second insulating layer has a thickness of 5 to 100 nm. 14. The silicon oxynitride film according to claim 12, wherein the second insulating layer is formed using a silicon oxynitride film having an oxygen concentration of 55 atomic% to 70 atomic% and a nitrogen concentration of 1 atomic% to 20 atomic%. A method for manufacturing a semiconductor device. In any one of claims 11 to 14, the heat conductive layer, aluminum oxide, aluminum nitride, aluminum oxynitride, silicon nitride, a semiconductor, which comprises forming by using boron nitride, a thin film diamond or DLC, Device fabrication method. The heat conductive layer according to any one of claims 11 to 14 , wherein the heat conductive layer is formed of a compound material containing Si, N, O, and M (M is at least one selected from Al or a rare earth element). A method for manufacturing a semiconductor device. In any one of claims 11 to 16, wherein the first insulating layer, contains an oxygen concentration of not more than 55 atomic% or more 70 atomic%, or One silicon oxynitride containing organic nitrogen concentration is less than 1 atomic% or more 20 atomic% A method for manufacturing a semiconductor device, characterized by being formed using a film. 18. The semiconductor device according to claim 11, wherein an angle of a side wall at an end face of the first insulating layer is 10 degrees or more and less than 40 degrees with respect to a main surface of the glass substrate. Manufacturing method. In any one of claims 11 to 18, a method for manufacturing a semiconductor device which is characterized in that the crystallization of the amorphous semiconductor film by irradiation of the laser radiation.

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