JP4583326B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a CMOS type SRAM cell.

  This type of SRAM has a memory cell that is not a charge-holding type like a DRAM but a current-driven type using a flip-flop, so that it can be accessed at high speed and is used as a cache memory. Accordingly, higher speed is required.

  FIG. 10 is a pattern diagram of a conventional SRAM cell 1. FIG. 11A is a circuit diagram corresponding to the layout pattern of FIG. 10, and FIG. 11B is a general circuit diagram that makes it easy to understand the connection of this circuit.

  In the SRAM cell 1, an element isolation region 4 is formed between the pMOS region 2 and the nMOS region 3, and a word line WL, a reference potential supply line VSS, and a power supply potential supply line VCC are arranged in parallel to the element isolation region 4. Yes. A pair of bit lines BL and * BL indicated only by the center line are arranged along a direction perpendicular to the word line WL. The pMOS transistor QP1 and the nMOS transistor QN1 form a CMOS inverter, the pMOS transistor QP2 and the nMOS transistor QN2 form another CMOS inverter, and these CMOS inverters are cross-connected to form a flip-flop.

  The metal wirings S1 to S4 and the power supply potential supply line VCC are a metal wiring first layer, the reference potential supply line VSS is a metal wiring second layer, and the bit lines BL and * BL are a metal wiring third layer.

  The polysilicon wiring G1 includes the gates of the pMOS transistor QP1 and the nMOS transistor QN1, and one end thereof is connected to the p-type semiconductor region P2d of the pMOS transistor QP2 through a contact hole. Polysilicon wiring G2 includes the gates of pMOS transistor QP2 and nMOS transistor QN2, and one end thereof is connected to the n-type semiconductor region N1d of nMOS transistor QN1 through a contact hole. The p-type semiconductor region P1d of the pMOS transistor QP1 and the n-type semiconductor region N1d of the nMOS transistor QN1 are connected by a metal wiring S1 through a contact hole, and the p-type semiconductor region P2d of the pMOS transistor QP2 and the n-type of the nMOS transistor QN2 The semiconductor region N2d is connected by a metal wiring S2 through a contact hole. The n-type semiconductor region N1s of the nMOS transistor QN1 passes through the contact hole and is connected to the reference potential supply line VSS by the metal wiring S3. The n-type semiconductor region N2s of the nMOS transistor QN2 passes through the contact hole and is connected to the reference by the metal wiring S4. It is connected to the potential supply line VSS.

  In the case of reading data written in the SRAM cell 1, the bit lines BL and * BL are precharged (or not precharged) to a predetermined potential, and then the word line WL is set to a high level to cause the nMOS transistor QN3. And QN4 are turned on. As a result, a potential difference is generated between the bit line BL and the bit line * BL, and after this exceeds a predetermined value to prevent malfunction, it is amplified by a sense amplifier (not shown) and taken out via the data bus. .

  In such a conventional SRAM cell 1, an element isolation region 4 is formed between the pMOS region 2 and the nMOS region 3, and bit lines BL and * BL are arranged along a direction perpendicular to the element isolation region 4. Therefore, in the SRAM cell array, the bit lines BL and * BL become longer, and their capacitance and resistance increase, so that improvement in data reading speed is limited. The same applies to the data writing speed.

Under Symbol Patent Document 1, in the SRAM cell, to form a gate line of a pair of word transistors (transfer gates) in one word line, to one side of the word line, the load transistors constituting the first inverter And the gate of the driver transistor, the gate of the load transistor and the driver transistor constituting the second inverter are formed on the other side of the word line, the word line is arranged at the approximate center of the cell, There is disclosed a configuration in which a gate is disposed substantially in parallel and a pair of bit lines are disposed at right angles to a word line.

Japanese Patent Application Laid-Open No. 07-130877 Japanese Patent Laid-Open No. 07-130876 Japanese Patent Laid-Open No. 07-086436

  In view of such problems, it is an object of the present invention to provide a semiconductor device including a CMOS type SRAM cell capable of speeding up access.

In a semiconductor device having a first SRAM cell according to one embodiment of the present invention ,
A first p-type semiconductor region;
A second p-type semiconductor region formed in a first direction away from the first p-type semiconductor region;
A first n-type semiconductor region disposed at a first position between the first p-type semiconductor region and the second p-type semiconductor region and separated from the first p-type semiconductor region by a first distance;
The second p-type semiconductor region is disposed between the first p-type semiconductor region and the second p-type semiconductor region at a second position separated from the first p-type semiconductor region by a second distance longer than the first distance. A second n-type semiconductor region;
A first element isolation insulating region formed between the first p-type semiconductor region and the first n-type semiconductor region;
A second element isolation insulating region formed between the second p-type semiconductor region and the second n-type semiconductor region;
A first bit line extending in a second direction orthogonal to the first direction;
A second bit line extending in the second direction;
A word line extending in the first direction;
A first n-type transistor formed in the first p-type semiconductor region and having a first gate extending in the first direction;
A third n-type transistor having a third gate formed in the first p-type semiconductor region and extending in the first direction;
A second n-type transistor having a second gate formed in the second p-type semiconductor region and extending in the first direction;
A fourth n-type transistor having a fourth gate formed in the second p-type semiconductor region and extending in the first direction;
A first p-type transistor having a fifth gate formed in the first n-type semiconductor region and extending in the first direction;
A second p-type transistor having a sixth gate formed in the second n-type semiconductor region and extending in the first direction;
A first contact connected to the fifth gate of the first p-type transistor;
A second contact connected to a second drain of the second p-type transistor;
A third contact connected to the sixth gate of the second p-type transistor;
A fourth contact connected to the first drain of the first p-type transistor;
A fifth contact disposed between the first gate and the third gate and connected to a third drain of the first n-type transistor;
A sixth contact disposed between the second gate and the fourth gate and connected to a fourth drain of the second n-type transistor;
A first wiring interconnecting the first contact, the second contact, and the sixth contact;
A second wiring interconnecting the third contact, the fourth contact, and the fifth contact;
Have
The first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor constitute a flip-flop circuit,
The third n-type transistor is a first transfer gate connecting the first bit line and the fifth contact;
The fourth n-type transistor is a second transfer gate connecting the second bit line and the sixth contact;
The word line is connected to the third gate and the fourth gate;
The first gate and the fifth gate are formed of an integrated first conductor,
The second gate and the sixth gate are formed of an integral second conductor;
The third gate is formed of a third conductor;
The fourth gate is formed of a fourth conductor, and the second conductor and the third conductor are disposed on the fifth contact side with respect to the first conductor,
The first conductor and the fourth conductor are disposed on the sixth contact side with respect to the second conductor,
The first contact is disposed between the second p-type semiconductor region and the first n-type semiconductor region,
The third contact is disposed between the first p-type semiconductor region and the second n-type semiconductor region,
At least a part of the second n-type semiconductor region and at least a part of the first n-type semiconductor region are disposed so as to overlap in the first direction without contacting each other.

According to the above aspect, the first n-type semiconductor region disposed at the first position separated from the first p-type semiconductor region by the first distance and the first p-type semiconductor region are longer than the first distance. A second n-type semiconductor region disposed at a second position separated by a second distance, wherein at least a part of the second n-type semiconductor region and at least a part of the first n-type semiconductor region are mutually without contact, Ru is arranged to overlap the said 1p-type semiconductor region in a first direction to said 2p-type semiconductor region.

  Other objects, configurations and effects of the present invention will become apparent from the following description.

  Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 1A shows a schematic pattern of the first type SRAM cell 10, and FIG. 1B shows a schematic pattern of the second type SRAM cell 20. The first type SRAM cell 10 and the second type SRAM cell 20 are both the same as the conventional circuit shown in FIG. 11B, but the layout pattern is different from that of FIG. 10 and is parallel to the short side of the rectangle. A pair of bit lines BL and bit lines * BL are arranged along the line. The word line WL is parallel to the long side of the SRAM cell.

  2 to 7, elements corresponding to those in FIGS. 10 and 11 are denoted by the same reference numerals for easy association even if the pattern shapes are different. The elements corresponding to the first type SRAM cell 10 and the second type SRAM cell 20 are also denoted by the same reference numerals.

  2A is a pattern diagram of the semiconductor region (diffusion layer) and the polysilicon wiring of the first type SRAM cell 10, and FIG. 2B is a cross section taken along the line IIB-IIB in FIG. 2A. FIG. FIG. 3A is a pattern diagram in which the wiring pattern of the metal wiring first layer is superimposed on the pattern of FIG. FIG. 3B is a pattern diagram in which the wiring pattern of the metal wiring second layer is superimposed on the pattern of FIG. FIG. 6A is a circuit diagram corresponding to the layout pattern of FIG. The directions parallel to the long side and the short side of the first type SRAM cell 10 are defined as an X direction and a Y direction in the drawing, respectively.

  2A, in the relationship with FIG. 10, the pMOS region 12 corresponds to the pMOS region 2, the nMOS regions 13A and 13B correspond to the nMOS region 3, and the element isolation regions 14A and 14B correspond to the element isolation region 4. It corresponds. That is, with respect to the X direction of the first type SRAM cell 10, the pMOS region 12 is disposed in the central portion, the nMOS regions 13A and 13B are disposed on one end side and the other end side, respectively, and between the pMOS region 12 and the nMOS region 13A. In addition, element isolation regions 14A and 14B are formed between the pMOS region 12 and the nMOS region 13B, respectively. The nMOS regions 13A and 13B are formed in the p-type well 16 and 17 of the n-type semiconductor substrate 15, respectively, as shown in FIG. On the other hand, the pMOS region 12 is formed on the surface portion of the n-type semiconductor substrate 15. The field oxide films 14a and 14b are part of the element isolation regions 14A and 14B, respectively.

  A pMOS transistor QP1 and a pMOS transistor QP2 are formed in the pMOS region 12, an nMOS transistor QN1 and an nMOS transistor QN3 are formed in the nMOS region 13A, and an nMOS transistor QN2 and an nMOS transistor QN4 are formed in the nMOS region 13B. ing. The pMOS transistor QP1 and the nMOS transistor QN1 constitute one CMOS inverter of the flip-flop, and the pMOS transistor QP2 and the nMOS transistor QN2 constitute the other CMOS inverter of the flip-flop. The nMOS transistors QN3 and QN4 are both transfer gates.

  The pattern of FIG. 2A is point symmetric about the central point of the first SRAM cell 10. This simplifies exposure pattern processing in SRAM manufacturing. In the figure, s and d in the code indicate a source region and a drain region, respectively, and P and N at the head of the code indicate a p-type semiconductor region and an n-type semiconductor region, respectively. The numbers in the middle are the same as the numbers in the transistor symbols.

  The pMOS transistor QP1 includes p-type semiconductor regions P1s and P1d, a channel region between the p-type semiconductor regions P1s and P1d, and a gate disposed above the channel region via a gate oxide film. The gate is a part of the polysilicon wiring G10. Part. The gates of the pMOS transistor QP2 and the nMOS transistors QN1, QN2, QN3, and QN4 are part of the polysilicon wirings G20, G10, W10, and W20, respectively. The p-type semiconductor regions P2s and P2d of the pMOS transistor QP2 correspond to the p-type semiconductor regions P1s and P1d of the pMOS transistor QP1, respectively. The nMOS transistor QN1 includes n-type semiconductor regions N1s and N1d, a channel region between them, and a gate disposed above the channel region via a gate oxide film. The nMOS transistors QN2 to QN4 are the same as the nMOS transistor QN1.

  Since the nMOS transistor QN1 and the pMOS transistor QP1 are arranged on one side in the Y direction, the polysilicon wiring G10 is substantially straight. Similarly, the nMOS transistor QN2 and the pMOS transistor QP2 are arranged on the other side in the Y direction. Therefore, the polysilicon wiring G20 is substantially straight. The nMOS transistor QN1 and the nMOS transistor QN3 share the n-type semiconductor region N1d in the Y direction, and the nMOS transistor QN2 and the nMOS transistor QN4 share the n-type semiconductor region N2d in the Y direction. The pMOS transistors QP1 and QP2 are arranged on the nMOS transistor QN1 side and the nMOS transistor QN2 side of the pMOS region 12, respectively. These contribute to reducing the width in the Y direction of the first type SRAM cell 10 and reducing the occupation area of the first type SRAM cell 10.

  In FIG. 3A, reference numerals in FIG. 2A are omitted to avoid complication. The pattern of FIG. 3A is also point-symmetric with respect to the central point of the first SRAM cell 10 as in FIG.

  Metal wirings G11 and G21 are used for cross connection between the two inverters. That is, one end of the polysilicon wiring G20 and the n-type semiconductor region N1d are connected by the metal wiring G21 through the contact holes Ca1 and Ca2, and one end of the polysilicon wiring G10 and the n-type semiconductor region N2d are connected. The metal wiring G11 is connected through the contact holes Cb1 and Cb2.

  As for the power supply wiring, a power supply potential supply line VCC is arranged at the center in the X direction of the first type SRAM cell 10, and reference potential supply lines VSS11 and VSS12 are provided at one end and the other end of the first type SRAM cell 10, respectively. Is arranged. These power supply wirings VCC, VS11 and VSS12 are all parallel to the Y direction. The power supply potential supply line VCC is connected to the lower p-type semiconductor regions P1s and P2s through the contact holes Cc1 and Cc2, respectively. Since both the reference potential supply lines VSS11 and VSS12 are shared by adjacent SRAM cells, the center line thereof coincides with the boundary line (dotted line) of the first type SRAM cell 10. The reference potential supply line VSS11 is connected to the lower n-type semiconductor region N1s through the contact hole Cd1, and the reference potential supply line VSS12 is connected to the lower n-type semiconductor region N2s through the contact hole Cd2.

  The metal wirings B11, B21, W11, and W21 are all intermediate wirings for connecting the lower layer and the upper layer. The metal wiring B11 is connected to the lower n-type semiconductor region N3 through the contact hole Ca3, the metal wiring B21 is connected to the lower n-type semiconductor region N4 through the contact hole Cb3, and the metal wiring W11 is connected to the contact hole Ce1. The metal wiring W21 is connected to the lower polysilicon wiring W20 through the contact hole Cf1.

  In FIG. 3B, reference numerals in FIGS. 2A and 3A are omitted to avoid complication. 3B is also point-symmetric with respect to the center point of the first SRAM cell 10 as in FIG. 3A.

  In order to reduce the wiring width of the power supply wiring and increase the degree of integration, the reference potential supply lines VSS21 and VSS22 are respectively disposed directly above the reference potential supply lines VSS11 and VSS12 via an insulating layer. The pair of bit lines BL and * BL are arranged near and in parallel with the reference potential supply lines VSS21 and VSS22 in order to reduce noise by shielding with the reference potential supply lines VSS21 and VSS22, respectively. The bit line BL is connected to the lower metal wiring B11 through the contact hole Ca4, and the bit line * BL is connected to the lower metal wiring B21 through the contact hole Cb4. Further, data lines DL and * DL are arranged on both sides of the power supply potential supply line VCC along the power supply potential supply line VCC, and these are shielded by the power supply potential supply line VCC to reduce noise. 6 and 7, the data lines DL and * DL are omitted.

  The metal wirings W12 and W22 are both intermediate wirings for connecting the lower layer and the upper layer. The metal wiring W12 is connected to the lower metal wiring W11 through the contact hole Ce2, and is connected to the upper word line WL through the contact hole Ce3. The word line WL is a third wiring layer, and only its center line is shown in order to avoid complication of the pattern. Similarly, the metal wiring W22 is connected to the lower metal wiring W21 through the contact hole Cf2, and is connected to the upper word line WL through the contact hole Cf3.

  FIG. 4 is a pattern diagram of the second type SRAM cell 20. This pattern makes the pattern of the first type SRAM cell 10 of FIG. 3B line-symmetrical with respect to the X-direction center line (the center line of WL). The wirings W12, W22, W11, and W21 are removed, and the cell center side ends of the polysilicon wirings W10 and W20 are removed. Due to this symmetry, the empty areas 21 and 22 are effectively used in relation to the first type SRAM cell 10 and the pattern is shortened.

  That is, when the first-type SRAM cell 10 and the second-type SRAM cell 20 are aligned in the bit line direction as shown in FIG. 5 with the dotted lines as the cell boundaries being aligned, the metal wiring W21 in FIG. W22 is arranged in the empty area 22 in FIG. The metal wirings W11 and W12 of the first type SRAM cell 10 enter the vacant area 21 by arranging the first type SRAM cell 10 in the lower part of FIG. The polysilicon wirings W3 and W4 of the second type SRAM cell 20 are connected to the word line WL on the second type SRAM cell 20 as follows. That is, the first type SRAM cell 10 is arranged on both sides in the longitudinal direction of the second type SRAM cell 20 so as to be adjacent to the second type SRAM cell 20. Thus, the polysilicon wiring W20 of the first type SRAM cell 10 is connected to the polysilicon wiring W3 of the second type SRAM cell 20, and the polysilicon wiring W3 is connected to the word line of the first type SRAM cell 10 via the polysilicon wiring W20. Connected to WL. Similarly, the polysilicon wiring W10 of the first type SRAM cell 10 is connected to W4 of the second type SRAM cell 20, and the polysilicon wiring W4 is connected to the word line WL of the first type SRAM cell 10 via the polysilicon wiring W10. Connected.

  Such an arrangement and connection of the word lines WL are shown in FIG.

  The cell array 30 is arranged in a lattice pattern with the boundary lines aligned so that the first type SRAM cell 10 and the second type SRAM cell 20 are adjacent to each other in the X direction and the Y direction. From this figure, the connection of the polysilicon wirings W3 and W4 of the second type SRAM cell 20 to the word line WL can be easily understood. BL0 to BL3 and * BL0 to * BL3 are bit lines, and WL0 to WL3 are word lines.

  According to the first embodiment, as shown in FIG. 2A, the pMOS region 12 is arranged between the nMOS region 13A and the nMOS region 13B, and the bit line is formed in a direction perpendicular to the direction from the nMOS region 13A to 13B. Therefore, the bit line length per SRAM cell can be made shorter than before, thereby reducing the capacity and resistance of the bit line and improving the access speed of the semiconductor device.

  In the SRAM cell of FIG. 10, the power supply potential supply line VCC and the reference potential supply line VSS are parallel to the word line WL. Therefore, when one word line WL is selected in the SRAM, it follows the selected word line WL. The SRAM cell is supplied with a voltage from a pair of power supply potential supply line VCC and reference potential supply line VSS. On the other hand, in FIG. 1C, since the power supply wiring is arranged along a direction perpendicular to the word line, when one word line is selected, a pair of SRAM cells along the word line is selected. Since the voltage is supplied from the power supply wiring, the same effect as the widening of the power supply wiring width is obtained, the fluctuation of the power supply voltage is reduced as compared with the conventional one, and the noise resistance is improved.

  FIG. 8A shows the arrangement of the data bus DB in the SRAM cell array according to the first embodiment, and FIG. 8B shows the arrangement of the data bus DBA in the conventional SRAM cell array. In FIG. 8A and FIG. 8B, the dotted line indicates the boundary of the SRAM cell.

  Conventionally, the bit lines are connected to the data bus DBA at one end of the cell array block 30A. However, in this embodiment, the bit lines BL and * BL are respectively connected to the data at the outer end of the cell array block 30 every two cell array blocks 30. Connected to lines DL and * DL. Since the bit lines BL and * BL are connected to the transfer gate in each SRAM cell, the load is relatively large. However, the data lines DL and * DL do not have such a load. For this reason, the number of memory cells in the direction perpendicular to the data bus DB can be increased more than before, and thereby the length of the data bus DB can be made shorter than before, and the area occupied by the data bus DB is reduced accordingly. The storage capacity can be increased as compared with the conventional case. As shown in FIG. 3B, since the data lines DL and * DL are arranged in empty portions on the pMOS region 12, an increase in cell area due to the data lines DL and * DL can be avoided.

  Note that the present invention includes various other modifications.

  For example, in the above-described embodiment, the case where the cell outer shape indicated by the dotted line is a rectangular shape has been described, but the effect of the present invention can be obtained even if the SRAM cell outer shape is not rectangular. The external shape as shown in (C) may be sufficient.

  Further, by using a local interconnect under the contact hole, the bit line BL in FIG. 3B is arranged on the nMOS transistors QN1 and QN3 on the reference potential supply line VSS21 side, thereby reducing the length of the cell in the X direction. It is also possible to do.

  Further, in FIG. 3A, the metal wiring G21, the polysilicon wiring G20, and the p-type semiconductor region P1d are connected at the position of the contact hole Ca1, but the metal wiring G21 is connected to the metal wiring G21 like the contact holes Ce2 and Ce3. By connecting the polysilicon wiring G20 and the polysilicon wiring G20 and the p-type semiconductor region P1d through contact holes at different positions, the unevenness of the wiring layer is reduced and the reliability is improved. It may be.

  Of course, the data lines DL and * DL may not be provided.

(A) is a schematic pattern diagram of the first type SRAM cell, (B) is a schematic pattern diagram of the second type SRAM cell, and (C) is a cell array in which the first and second type SRAM cells are alternately arranged. It is a schematic pattern diagram. (A) is a pattern diagram of the semiconductor region and polysilicon wiring of the first type SRAM cell, and (B) is a sectional view taken along line IIB-IIB in (A). 2A is a pattern diagram in which the wiring pattern of the first layer of the metal wiring is superimposed on the pattern of FIG. 2A, and FIG. 2B is a pattern in which the wiring pattern of the second layer of the metal wiring is superimposed on the pattern of FIG. FIG. It is a pattern diagram of a second type SRAM cell. FIG. 6 is a pattern diagram in which a first type SRAM cell and a second type SRAM cell are juxtaposed in the bit line direction. 4A is a circuit diagram corresponding to the layout pattern of FIG. 3B, and FIG. 4B is a circuit diagram corresponding to the layout pattern of FIG. FIG. 6 is a circuit diagram corresponding to the layout pattern of FIG. 5. (A) is a layout diagram of data buses in the SRAM cell array according to the first embodiment, and (B) is a data bus layout diagram in the conventional SRAM cell array. (A)-(C) are cell external views which show the modification of an SRAM cell. It is a pattern diagram of a conventional SRAM cell. (A) is a circuit diagram corresponding to the layout pattern of FIG. 10, and (B) is a general circuit diagram in which the connection of (A) is easily understood.

Explanation of symbols

10 first type SRAM cell 12 pMOS region 13A, 13B nMOS region 14A, 14B element isolation region 14a, 14b field oxide film 15 n type semiconductor substrate 16, 17 p type well 20 second type SRAM cell 30 cell array block QP1, QP2 pMOS Transistors QN1 to QN4 nMOS transistors P1s, P2s, P1d, P2d p-type semiconductor regions N1s, N1d, N2s, N2d, N3, N4 n-type semiconductor regions G1, G2, G10, G20, W10, W20 polysilicon wirings S1-S4, B11, B21, W11, W21, W12, W22 Metal wiring BL, * BL Bit line DL, * DL Data line WL Word line DB, DBA Data bus

Claims (18)

A first p-type semiconductor region;
A second p-type semiconductor region formed in a first direction away from the first p-type semiconductor region;
A first n-type semiconductor region disposed at a first position between the first p-type semiconductor region and the second p-type semiconductor region and separated from the first p-type semiconductor region by a first distance;
The second p-type semiconductor region is disposed between the first p-type semiconductor region and the second p-type semiconductor region at a second position separated from the first p-type semiconductor region by a second distance longer than the first distance. A second n-type semiconductor region;
A first element isolation insulating region formed between the first p-type semiconductor region and the first n-type semiconductor region;
A second element isolation insulating region formed between the second p-type semiconductor region and the second n-type semiconductor region;
A first bit line extending in a second direction orthogonal to the first direction;
A second bit line extending in the second direction;
A word line extending in the first direction;
A first n-type transistor formed in the first p-type semiconductor region and having a first gate extending in the first direction;
A third n-type transistor having a third gate formed in the first p-type semiconductor region and extending in the first direction;
A second n-type transistor having a second gate formed in the second p-type semiconductor region and extending in the first direction;
A fourth n-type transistor having a fourth gate formed in the second p-type semiconductor region and extending in the first direction;
A first p-type transistor having a fifth gate formed in the first n-type semiconductor region and extending in the first direction;
A second p-type transistor having a sixth gate formed in the second n-type semiconductor region and extending in the first direction;
A first contact connected to the fifth gate of the first p-type transistor;
A second contact connected to a second drain of the second p-type transistor;
A third contact connected to the sixth gate of the second p-type transistor;
A fourth contact connected to the first drain of the first p-type transistor;
A fifth contact disposed between the first gate and the third gate and connected to a third drain of the first n-type transistor;
A sixth contact disposed between the second gate and the fourth gate and connected to a fourth drain of the second n-type transistor;
A first wiring interconnecting the first contact, the second contact, and the sixth contact;
A second wiring interconnecting the third contact, the fourth contact, and the fifth contact;
Have
The first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor constitute a flip-flop circuit,
The third n-type transistor is a first transfer gate connecting the first bit line and the fifth contact;
The fourth n-type transistor is a second transfer gate connecting the second bit line and the sixth contact;
The word line is connected to the third gate and the fourth gate;
The first gate and the fifth gate are formed of an integrated first conductor,
The second gate and the sixth gate are formed of an integral second conductor;
The third gate is formed of a third conductor;
The fourth gate is formed of a fourth conductor, and the second conductor and the third conductor are disposed on the fifth contact side with respect to the first conductor,
The first conductor and the fourth conductor are disposed on the sixth contact side with respect to the second conductor,
The first contact is disposed between the second p-type semiconductor region and the first n-type semiconductor region,
The third contact is disposed between the first p-type semiconductor region and the second n-type semiconductor region,
At least a part of the second n-type semiconductor region and at least a part of the first n-type semiconductor region are arranged to overlap each other in the first direction without being in contact with each other. A semiconductor device having the same. A first p-type semiconductor region;
A second p-type semiconductor region formed in a first direction away from the first p-type semiconductor region;
A first n-type semiconductor region disposed at a first position between the first p-type semiconductor region and the second p-type semiconductor region and separated from the first p-type semiconductor region by a first distance;
The second p-type semiconductor region is disposed between the first p-type semiconductor region and the second p-type semiconductor region at a second position separated from the first p-type semiconductor region by a second distance longer than the first distance. A second n-type semiconductor region;
A first element isolation insulating region formed between the first p-type semiconductor region and the first n-type semiconductor region;
A second element isolation insulating region formed between the second p-type semiconductor region and the second n-type semiconductor region;
A first bit line extending in a second direction orthogonal to the first direction;
A second bit line extending in the second direction;
A word line extending in the first direction;
A first n-type transistor formed in the first p-type semiconductor region and having a first gate extending in the first direction;
A third n-type transistor having a third gate formed in the first p-type semiconductor region and extending in the first direction;
A second n-type transistor having a second gate formed in the second p-type semiconductor region and extending in the first direction;
A fourth n-type transistor having a fourth gate formed in the second p-type semiconductor region and extending in the first direction;
A first p-type transistor having a fifth gate formed in the first n-type semiconductor region and extending in the first direction;
A second p-type transistor having a sixth gate formed in the second n-type semiconductor region and extending in the first direction;
A first contact connected to the fifth gate of the first p-type transistor;
A second contact connected to a second drain of the second p-type transistor;
A third contact connected to the sixth gate of the second p-type transistor;
A fourth contact connected to the first drain of the first p-type transistor;
A fifth contact disposed between the first gate and the third gate and connected to a third drain of the first n-type transistor;
A sixth contact disposed between the second gate and the fourth gate and connected to a fourth drain of the second n-type transistor;
A first wiring interconnecting the first contact, the second contact, and the sixth contact;
A second wiring interconnecting the third contact, the fourth contact, and the fifth contact;
Have
The first n-type transistor, the second n-type transistor, the first p-type transistor, and the second p-type transistor constitute a flip-flop circuit,
The third n-type transistor is a first transfer gate connecting the first bit line and the fifth contact;
The fourth n-type transistor is a second transfer gate connecting the second bit line and the sixth contact;
The word line is connected to the third gate and the fourth gate;
The first gate and the fifth gate are formed of an integrated first conductor,
The second gate and the sixth gate are formed of an integral second conductor;
The third gate is formed of a third conductor;
The fourth gate is formed of a fourth conductor, and the second conductor and the third conductor are disposed on the fifth contact side with respect to the first conductor,
The first conductor and the fourth conductor are disposed on the sixth contact side with respect to the second conductor,
The first contact is disposed between the second p-type semiconductor region and the first n-type semiconductor region,
The third contact is disposed between the first p-type semiconductor region and the second n-type semiconductor region,
At least a part of the second n-type semiconductor region and at least a part of the first n-type semiconductor region are arranged side by side in the first direction without being in contact with each other. A semiconductor device having the same. A third n-type semiconductor region;
A fourth n-type semiconductor region formed in a second direction away from the third n-type semiconductor region;
A seventh n-type semiconductor region formed away from the fourth n-type semiconductor region in the second direction;
An eighth n-type semiconductor region formed away from the third n-type semiconductor region in a first direction orthogonal to the second direction;
A sixth n-type semiconductor region formed away from the eighth n-type semiconductor region in the second direction;
A fifth n-type semiconductor region formed away from the sixth n-type semiconductor region in the second direction;
A third p-type disposed between the third n-type semiconductor region and the eighth n-type semiconductor region, at a first position separated from the third n-type semiconductor region by a first distance in the first direction; A semiconductor region;
A fourth p-type semiconductor region formed away from the third p-type semiconductor region in the second direction;
A second distance between the seventh n-type semiconductor region and the fifth n-type semiconductor region, the second distance being longer than the first distance in the first direction from the seventh n-type semiconductor region; A fifth p-type semiconductor region disposed at a position;
A sixth p-type semiconductor region formed away from the fifth p-type semiconductor region in a direction opposite to the second direction;
A first element isolation insulating region formed between the third n-type semiconductor region and the third p-type semiconductor region and between the fourth n-type semiconductor region and the fourth p-type semiconductor region;
A second element isolation insulating region formed between the fifth n-type semiconductor region and the fifth p-type semiconductor region and between the sixth n-type semiconductor region and the sixth p-type semiconductor region;
A first gate formed between the third n-type semiconductor region and the fourth n-type semiconductor region and extending in the first direction;
A third gate formed between the fourth n-type semiconductor region and the seventh n-type semiconductor region and extending in the first direction;
A second gate formed between the fifth n-type semiconductor region and the sixth n-type semiconductor region and extending in the first direction;
A fourth gate formed between the sixth n-type semiconductor region and the eighth n-type semiconductor region and extending in the first direction;
A fifth gate formed between the third p-type semiconductor region and the fourth p-type semiconductor region and extending in the first direction;
A sixth gate formed between the fifth p-type semiconductor region and the sixth p-type semiconductor region and extending in the first direction;
A first contact connected to the fifth gate;
A second contact connected to the sixth p-type semiconductor region;
A third contact connected to the sixth gate;
A fourth contact connected to the fourth p-type semiconductor region;
A fifth contact connected to the fourth n-type semiconductor region;
A sixth contact connected to the sixth n-type semiconductor region;
A first wiring interconnecting the first contact, the second contact, and the sixth contact;
A second wiring interconnecting the third contact, the fourth contact, and the fifth contact;
A first bit line connected to the seventh n-type semiconductor region and extending in the second direction;
A second bit line connected to the eighth n-type semiconductor region and extending in the second direction;
A word line connected to the third gate and the fourth gate and extending in the first direction;
Have
The third n-type semiconductor region, the fourth n-type semiconductor region, and the first gate constitute a first n-type transistor,
The fourth n-type semiconductor region, the seventh n-type semiconductor region, and the third gate constitute a third n-type transistor;
The fifth n-type semiconductor region, the sixth n-type semiconductor region, and the second gate constitute a second n-type transistor;
The sixth n-type semiconductor region, the eighth n-type semiconductor region, and the fourth gate constitute a fourth n-type transistor;
The third p-type semiconductor region, the fourth p-type semiconductor region, and the fifth gate constitute a first p-type transistor,
The fifth p-type semiconductor region, the sixth p-type semiconductor region, and the sixth gate constitute a second p-type transistor;
The first n-type transistor and the first p-type transistor constitute a first inverter,
The second n-type transistor and the second p-type transistor constitute a second inverter,
The first inverter and the second inverter constitute a flip-flop circuit,
The first gate and the fifth gate are formed of an integrated first conductor,
The second gate and the sixth gate are formed of an integral second conductor;
The third gate is formed of a third conductor;
The fourth gate is formed of a fourth conductor;
The second conductor and the third conductor are disposed on the fifth contact side with respect to the first conductor,
The first conductor and the fourth conductor are disposed on the sixth contact side with respect to the second conductor,
The first contact is disposed between the fourth n-type transistor and the first p-type transistor,
The third contact is disposed between the third n-type transistor and the second p-type transistor,
At least a part of the 4p type semiconductor region and at least a part of the sixth p type semiconductor region are arranged so as to overlap each other in the first direction without being in contact with each other. Semiconductor device. A third n-type semiconductor region;
A fourth n-type semiconductor region formed in a second direction away from the third n-type semiconductor region;
A seventh n-type semiconductor region formed away from the fourth n-type semiconductor region in the second direction;
An eighth n-type semiconductor region formed away from the third n-type semiconductor region in a first direction orthogonal to the second direction;
A sixth n-type semiconductor region formed away from the eighth n-type semiconductor region in the second direction;
A fifth n-type semiconductor region formed away from the sixth n-type semiconductor region in the second direction;
A third p-type disposed between the third n-type semiconductor region and the eighth n-type semiconductor region, at a first position separated from the third n-type semiconductor region by a first distance in the first direction; A semiconductor region;
A fourth p-type semiconductor region formed away from the third p-type semiconductor region in the second direction;
A second distance between the seventh n-type semiconductor region and the fifth n-type semiconductor region, the second distance being longer than the first distance in the first direction from the seventh n-type semiconductor region; A fifth p-type semiconductor region disposed at a position;
A sixth p-type semiconductor region formed away from the fifth p-type semiconductor region in a direction opposite to the second direction;
A first element isolation insulating region formed between the third n-type semiconductor region and the third p-type semiconductor region and between the fourth n-type semiconductor region and the fourth p-type semiconductor region;
A second element isolation insulating region formed between the fifth n-type semiconductor region and the fifth p-type semiconductor region and between the sixth n-type semiconductor region and the sixth p-type semiconductor region;
A first gate formed between the third n-type semiconductor region and the fourth n-type semiconductor region and extending in the first direction;
A third gate formed between the fourth n-type semiconductor region and the seventh n-type semiconductor region and extending in the first direction;
A second gate formed between the fifth n-type semiconductor region and the sixth n-type semiconductor region and extending in the first direction;
A fourth gate formed between the sixth n-type semiconductor region and the eighth n-type semiconductor region and extending in the first direction;
A fifth gate formed between the third p-type semiconductor region and the fourth p-type semiconductor region and extending in the first direction;
A sixth gate formed between the fifth p-type semiconductor region and the sixth p-type semiconductor region and extending in the first direction;
A first contact connected to the fifth gate;
A second contact connected to the sixth p-type semiconductor region;
A third contact connected to the sixth gate;
A fourth contact connected to the fourth p-type semiconductor region;
A fifth contact connected to the fourth n-type semiconductor region;
A sixth contact connected to the sixth n-type semiconductor region;
A first wiring interconnecting the first contact, the second contact, and the sixth contact;
A second wiring interconnecting the third contact, the fourth contact, and the fifth contact;
A first bit line connected to the seventh n-type semiconductor region and extending in the second direction;
A second bit line connected to the eighth n-type semiconductor region and extending in the second direction;
A word line connected to the third gate and the fourth gate and extending in the first direction;
Have
The third n-type semiconductor region, the fourth n-type semiconductor region, and the first gate constitute a first n-type transistor,
The fourth n-type semiconductor region, the seventh n-type semiconductor region, and the third gate constitute a third n-type transistor;
The fifth n-type semiconductor region, the sixth n-type semiconductor region, and the second gate constitute a second n-type transistor;
The sixth n-type semiconductor region, the eighth n-type semiconductor region, and the fourth gate constitute a fourth n-type transistor;
The third p-type semiconductor region, the fourth p-type semiconductor region, and the fifth gate constitute a first p-type transistor,
The fifth p-type semiconductor region, the sixth p-type semiconductor region, and the sixth gate constitute a second p-type transistor;
The first n-type transistor and the first p-type transistor constitute a first inverter,
The second n-type transistor and the second p-type transistor constitute a second inverter,
The first inverter and the second inverter constitute a flip-flop circuit,
The first gate and the fifth gate are formed of an integrated first conductor,
The second gate and the sixth gate are formed of an integral second conductor;
The third gate is formed of a third conductor;
The fourth gate is formed of a fourth conductor;
The second conductor and the third conductor are disposed on the fifth contact side with respect to the first conductor,
The first conductor and the fourth conductor are disposed on the sixth contact side with respect to the second conductor,
The first contact is disposed between the fourth n-type transistor and the first p-type transistor,
The third contact is disposed between the third n-type transistor and the second p-type transistor,
At least a part of the 4p type semiconductor region and at least a part of the sixth p type semiconductor region are arranged side by side in the first direction without being in contact with each other. Semiconductor device.   5. The semiconductor according to claim 1, wherein the first SRAM cell is formed in a rectangular region having a long side in the first direction and a short side in the second direction. 6. apparatus.   The semiconductor device according to claim 1, wherein the first n-type semiconductor region and the second n-type semiconductor region extend in the second direction.   The semiconductor device according to claim 1, wherein the first p-type semiconductor region and the second p-type semiconductor region extend in the second direction. The first contact and the second contact are formed by a conductor in a common contact hole straddling the fifth gate and the sixth p-type semiconductor region,
The said 3rd contact and the said 4th contact are formed of the conductor in the common contact hole straddling the said 6th gate and the said 4th p-type semiconductor region, The Claim 3 or 4 characterized by the above-mentioned. Semiconductor device. 9. The semiconductor device according to claim 1, wherein the first bit line and the second bit line are formed by a wiring layer one layer lower than the word line . The first contact and the second contact are formed by a conductor in a common contact hole straddling the fifth gate and the second drain,
The third contact and the fourth contact, according to claim 1, characterized in that it is formed by a conductor within a common contact hole extending over said sixth gate and the first drain, either 6 or 7 The semiconductor device according to claim 1. A first potential supply line for supplying a first potential;
A second potential supply line for supplying a second potential lower than the first potential;
A third potential supply line for supplying the second potential;
Further comprising
The first p-type transistor and the first n-type transistor are electrically connected in series between the first potential supply line and the second potential supply line;
11. The first p-type transistor and the second n-type transistor are electrically connected in series between the first potential supply line and the third potential supply line. The semiconductor device according to one item.   The semiconductor device according to claim 11, wherein the first potential supply line, the second potential supply line, and the third potential supply line extend in the second direction.   13. The semiconductor device according to claim 11, wherein the first potential supply line is disposed between the first bit line and the second bit line.   14. The first bit line, the second bit line, and the first potential supply line are disposed between the second potential supply line and the third potential supply line. The semiconductor device as described in any one.   The semiconductor device according to claim 1, wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are formed of polysilicon. . A seventh p-type semiconductor region disposed adjacent to the first SRAM cell in the second direction; an eighth p-type semiconductor region formed away from the seventh p-type semiconductor region in the first direction; A second SRAM cell having a ninth n-type semiconductor region and a tenth n-type semiconductor region disposed between the seventh p-type semiconductor region and the eighth p-type semiconductor region;
The seventh p-type semiconductor region and the 1p-type semiconductor region are integrally formed extending in the second direction, and the eighth p-type semiconductor region and the 2p-type semiconductor region are formed in the second direction. according to claim 1, characterized in that it is integrally formed to extend, the semiconductor device as claimed in any one 6,7 or 10. 17. The semiconductor device according to claim 16, wherein the layout of the first SRAM cell and the second SRAM cell is line-symmetric with respect to a boundary line between the first SRAM cell and the second SRAM cell. A second SRAM cell disposed adjacent to the first SRAM cell in the second direction;
16. The second SRAM cell according to claim 3, wherein the second SRAM cell has a layout symmetrical to the first SRAM cell with respect to a boundary line between the first SRAM cell and the second SRAM cell. Semiconductor device.

Images