JP4584773B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of normal memory blocks and a redundant memory block for relieving defects in the normal memory blocks.

  In general, a semiconductor memory device such as an SRAM (Static Random Access Memory) has a redundant memory block for relieving a defect of a normal memory block generated in a manufacturing process in order to improve a yield and reduce a chip cost. ing. In such a semiconductor memory device, a memory circuit (fuse circuit or the like) for storing a defective normal memory block is provided, and the normal memory block stored by the memory circuit becomes invalid, and a redundant memory The block becomes valid. Therefore, when a defect is detected in one of the normal memory blocks during a test in the manufacturing process, the defective normal memory block generated in the manufacturing process is relieved by storing the defective normal memory block in the memory circuit. The

  With the recent development of the semiconductor field, the capacity of memory circuits (semiconductor memory devices) mounted on system LSIs and the like has increased remarkably. For this reason, the relative variation of the transistors of the memory cell becomes large, and even if a failure is not detected in the test in the manufacturing process, the probability of the failure occurring due to the gradual deterioration of the characteristics of the memory cell on the user system. It is increasing. As a technique for solving this problem, a function for disabling a normal memory block specified by an external signal and enabling a redundant memory block is provided in a memory circuit, and the state is incorporated in a user system. When a defect is detected by a self-test using a BIST (Built-In Self Test) circuit or the like, an external signal indicating a defective normal memory block is input to the memory circuit, thereby causing a defect in the normal memory block generated on the user system. Techniques for relieving are known.

On the other hand, Patent Document 1 shows a defective state of a plurality of row regions, and a column redundancy control circuit for a semiconductor memory device having a latch circuit having a plurality of fuse elements connected in parallel to a common node via a selection transistor. Is disclosed. In such a column redundancy control circuit, it is only necessary to provide one latch circuit for a plurality of row regions, so that the circuit configuration can be simplified. Accordingly, the number of elements and the chip size in the semiconductor memory device can be reduced.
JP 2002-93188 A

A semiconductor memory device is desired to have both a redundant function based on the memory circuit as described above and a redundant function based on an external signal. However, if a dedicated circuit that embodies each function is provided individually, the chip size can be reduced. Will increase.
An object of the present invention is to realize both a redundancy function based on a memory circuit and a redundancy function based on an external signal without increasing the chip size of the semiconductor memory device.

In one embodiment of the present invention, a semiconductor memory device includes a plurality of memory blocks including a redundant memory block and two data blocks connected to two memory blocks of the memory blocks. A plurality of switch circuits for connecting a memory block to an external data line, a plurality of latch circuits having a first function for storing a defective memory block in advance in a nonvolatile manner and a second function for storing a defective memory block based on an external signal And a redundant control circuit that generates a switching signal to the switch circuit based on the output signal of the latch circuit. The redundancy control circuit includes a prohibition circuit that prohibits input of an external signal of the second function when the first function is used in the latch circuit.
In the semiconductor memory equipment associated with the present invention, a plurality of memory blocks includes a redundant memory block. The plurality of switch circuits are respectively connected to two memory blocks among the plurality of memory blocks. Each switch circuit connects one data line of two memory blocks to be connected to an external data line. The redundancy control circuit has a plurality of latch circuits having a function of storing a defective memory block in advance in a nonvolatile manner and a function of storing a defective memory block based on an external signal. The redundancy control circuit generates switching signals to the plurality of switch circuits based on the output signals of the plurality of latch circuits. The good preferable example of the semiconductor memory device related to the present invention, the redundancy control circuit has a decoder for generating a switching signal by decoding an output signal of a plurality of latch circuits to a plurality of switch circuits. Each switch circuit is provided for every two adjacent memory blocks.

  In the semiconductor memory device having such a configuration, for example, when a defect is detected in any of the memory blocks in a test in the manufacturing process, the defective memory block is stored in the latch circuit in a non-volatile manner. As a result, the data lines of the memory blocks (including the redundant memory block) excluding the defective memory block are connected to the external data lines. In other words, the memory block including the defect detected by the test in the manufacturing process becomes invalid and the redundant memory block becomes valid. That is, a redundant function based on the memory circuit can be realized.

  On the other hand, for example, when a defect is not detected in any of the memory blocks in a test in the manufacturing process, and a defect is detected by a self test on the user system, the defective memory block is stored in the latch circuit by an external signal. Thus, the data line of the memory block (including the redundant memory block) excluding the defective memory block is connected to the external data line by the switch circuit. In other words, the memory block including the defect detected by the self test on the user system becomes invalid and the redundant memory block becomes valid. That is, a redundant function based on an external signal can be realized.

  Since the latch circuit for the redundant function based on the memory circuit and the latch circuit for the redundant function based on the external signal are shared, it is more redundant than the case where a dedicated circuit that embodies each function is provided individually. The circuit configuration of the control circuit can be simplified. As a result, both the redundant function based on the memory circuit and the redundant function based on the external signal can be realized without increasing the chip size of the semiconductor memory device.

In another semiconductor memory equipment associated with the present invention, the redundancy control circuit, when there is a defect in any one of a plurality of normal memory blocks, the redundancy control signals of a plurality of bits for selecting a memory block to be accessed , Set to a logic level indicating a defective normal memory block. When the redundancy control signal from the redundancy control circuit indicates a defective normal memory block, the switching circuit invalidates the normal memory block and validates the redundant memory block. The plurality of latch circuits in the redundancy control circuit are provided for each bit of the redundancy control signal. Each latch circuit holds the logic level of the signal received at the input node, and sets the corresponding bit of the redundancy control signal to the held logic level. The plurality of nonvolatile memory circuits in the redundancy control circuit are provided corresponding to the latch circuits, respectively. Each nonvolatile memory circuit stores in advance a logic level indicating a defective normal memory block, and outputs a first latch setting signal of the stored logic level to an input node of the corresponding latch circuit. The plurality of input circuits in the redundancy control circuit are provided corresponding to the latch circuits, respectively. Each input circuit receives a second latch setting signal for changing the logic level held by the corresponding latch circuit, and outputs the second latch setting signal to the input node of the corresponding latch circuit.

  In the semiconductor memory device having such a configuration, for example, when a defect is detected in any of the normal memory blocks in a test in the manufacturing process, each of the logic levels indicating the defective normal memory block is stored in the nonvolatile memory circuit. Thus, when the first latch setting signal is temporarily output from the nonvolatile memory circuit to the input node of the latch circuit, the redundancy control signal from the redundancy control circuit (latch circuit) to the switching circuit is a defective normal memory block. Is set to a logical level indicating Therefore, the switching circuit invalidates the normal memory block including the defect detected by the test in the manufacturing process and enables the redundant memory block. That is, a redundant function based on the memory circuit can be realized.

  On the other hand, for example, when a defect is not detected in any of the normal memory blocks in the test in the manufacturing process, and the defect is detected by the self-test on the user system, the second latch setting signal indicates the defective normal memory block. By setting the logic level, if the second latch setting signal is temporarily output from the input circuit to the input node of the latch circuit, the redundancy control signal from the redundancy control circuit (latch circuit) to the switching circuit is defective. Set to a logic level indicating a memory block. Therefore, the switching circuit invalidates the normal memory block including the defect detected by the self-test on the user system and validates the redundant memory block. That is, a redundant function based on an external signal can be realized.

  The input node of the latch circuit receives both the first and second latch setting signals in common at the input node. That is, a latch circuit for a redundant function based on a memory circuit and a latch circuit for a redundant function based on an external signal are shared. For this reason, the circuit configuration of the redundant control circuit can be simplified as compared with the case where dedicated circuits that implement the respective functions are provided individually. As a result, both the redundant function based on the memory circuit and the redundant function based on the external signal can be realized without increasing the chip size of the semiconductor memory device.

The good preferable example of another semiconductor memory device related to the present invention, the defective signal generation circuit of the redundancy control circuit, the redundancy control signal activates a defect signal when indicating one of the normal memory block. The prohibition circuit of the redundancy control circuit prohibits the output operation of the second latch setting signal by the input circuit during the activation of the failure signal. As a result, when the nonvolatile memory circuit stores the logic level indicating the normal memory block including the defect detected by the test in the manufacturing process, the logic level held by the latch circuit is set to the first latch setting signal. There is no change from the logic level held on the basis. That is, when the redundant memory block is already enabled by the redundant function based on the memory circuit, the redundant function based on the external signal is disabled. For this reason, it is possible to avoid that the normal memory block including the defect detected by the test in the manufacturing process is erroneously enabled by changing the logic level held by the latch circuit by the redundancy function based on the external signal.

  In the semiconductor memory device of the present invention, both the redundancy function based on the memory circuit and the redundancy function based on the external signal can be realized without increasing the chip size.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The RAM 10 includes a main control circuit MC, memory blocks BLK1 to BLK16, a redundancy control circuit RC, switch circuits SW1 to SW15 (switching circuit), and OR circuits OR2 to OR15. The main control circuit MC sequentially captures a multi-bit address signal AD, a chip enable signal / CE and a write enable signal / WE in synchronization with the clock signal CK, and is common to the memory blocks BLK1 to BLK16 based on the captured signals. One of the plurality of word lines WL connected to each other, and a control signal CTL (column selection signal, sense amplifier enable signal, write amplifier enable signal, input enable signal and output enable to the memory blocks BLK1 to BLK16) Signal).

  The address signal AD is set to a logic level indicating a memory cell to be accessed when accessing the RAM 10 (write access and read access). The chip enable signal / CE is activated to “logic 0” when the RAM 10 is accessed. The write enable signal / WE is activated to “logic 0” at the time of write access to the RAM 10, and is deactivated to “logic 1” at the time of read access to the RAM 10.

  The memory blocks BLK1 to BLK15 are provided as normal memory blocks, respectively. The memory block BLK16 is provided as a redundant memory block for relieving defects in the memory blocks BLK1 to BLK15. The memory blocks BLK1 to BLK16 have the same circuit configuration. Although not shown, the memory block BLKi (i = 1 to 16) has a plurality of memory cells arranged in a matrix at intersections of the plurality of word lines WL and the plurality of bit lines. In addition, the memory block BLKi includes, for example, a column switch circuit that selects a bit line corresponding to a memory cell to be accessed and connects to a common data line in the memory block, and amplifies data transmitted to the common data line. Sense amplifier that outputs to the read-only data line in the block, write amplifier that amplifies the data transmitted to the write-only data line in the memory block and outputs to the common data line, read-only data line and write-only data line And a data input / output circuit for transferring data between the block data line BDi. The memory block BLKi operates these circuits in response to a control signal CTL from the main control circuit MC, thereby performing a data read operation and a data write operation between the memory cell to be accessed and the block data line BDi. .

  The redundancy control circuit RC includes a buffer BF0, a delay circuit DLY, a NAND circuit NA0, a three-state circuit TS0 to TS3 (input circuit), a NAND circuit NA1 (forbidden circuit), a fuse latch unit FLP, and a decoder DEC. The buffer BF0 receives the power-on reset signal POR and outputs it to the NAND circuit NA0 and the delay circuit DLY. For example, the power-on reset signal POR is activated to “logic 1” only for a predetermined period immediately after the RAM 10 is turned on. The delay circuit DLY delays the output signal of the buffer BF0 and outputs it to the NAND circuit NA0. NAND circuit NA0 outputs a negative logical product result of the output signal of buffer BF0 and the output signal of delay circuit DLY as reset signal / RST. Accordingly, the reset signal / RST is activated to “logic 0” after the delay time by the delay circuit DLY has elapsed since the activation of the power-on reset signal POR (actually, the output signal of the buffer BF0), and the power-on reset signal POR Deactivate to "logic 1" immediately after deactivation.

  The three-state circuits TS0 to TS3 receive external latch setting signals LS0 to LS3 (external signals, second latch setting signals) as signal lines LI0 to LI3 when the input control signal / IC from the NAND circuit NA1 indicates “logic 0”. Respectively. The signal lines LI0 to LI3 are respectively connected to common nodes NC0 to NC3 in the fuse latch unit FLP described in FIG. The three-state circuits TS0 to TS3 stop the output operation of the external latch setting signals LS0 to LS3 when the input control signal / IC indicates “logic 1”.

  NAND circuit NA1 outputs a negative logical product result of fuse status signal / FS (defective signal) from fuse latch unit FLP and external redundancy enable signal ERE as input control signal / IC. That is, when the fuse state signal / FS indicates “logic 1”, the NAND circuit NA1 inverts the external redundancy permission signal ERE and outputs it as the input control signal / IC. When the fuse state signal / FS indicates “logic 0”, the NAND circuit NA1 sets the input control signal / IC to “logic 1” regardless of the external redundancy enable signal ERE. Therefore, when the fuse state signal / FS indicates "logic 0", the output operation of the external latch setting signals LS0 to LS3 by the three-state circuits TS0 to TS3 is prohibited.

  Fuse latch unit FLP includes latch output signals LO0 to LO3 (redundancy control signals) set based on reset signal / RST from NAND circuit NA0 and external latch setting signals LS0 to LS3 from three-state circuits TS0 to TS3. A fuse status signal / FS is output. Details of the fuse latch portion FLP will be described with reference to FIG. The decoder DEC activates the select signal Sm to “logic 1” when the latch output signal LO [3: 0] from the fuse latch unit FLP indicates the decimal number “m” (m = 1 to 15). When the latch output signal LO [3: 0] indicates the decimal number “0”, the decoder DEC does not activate any of the select signals S1 to S15.

  The OR circuit OR2 activates the output signal to the switch circuit SW2 to “logic 1” when either the select signal S1 or the select signal S2 from the redundancy control circuit RC (decoder DEC) indicates “logic 1”. . The OR circuit OR3 (OR4 to OR15) is a switch circuit when either the output signal of the OR circuit OR2 (OR3 to OR14) or the select signal S3 (S4 to S15) from the redundancy control circuit RC indicates “logic 1”. The output signal to SW3 (SW4 to SW15) is activated to “logic 1”.

  The switch circuit SW1 connects the block data line BD1 and the external data line D1 of the memory block BLK1 when the select signal S1 (switching signal) from the redundancy control circuit RC indicates “logic 0”. The switch circuit SW1 connects the block data line BD2 of the memory block BLK2 and the external data line D1 when the select signal S1 indicates “logic 1”. When the output signal (switching signal) of the OR circuit OR2 (OR3 to OR15) indicates “logic 0”, the switch circuit SW2 (SW3 to SW15) displays the block data line BD2 (BD3 to BD3) of the memory block BLK2 (BLK3 to BLK15). BD15) and external data line D2 (D3 to D15) are connected. When the output signal of the OR circuit OR2 (OR3 to OR15) indicates “logic 1”, the switch circuit SW2 (SW3 to SW15) and the block data line BD3 (BD4 to BD16) of the memory block BLK3 (BLK4 to BLK16) The data line D2 (D3 to D15) is connected.

  When the latch output signal LO [3: 0] from the fuse latch unit FLP indicates the decimal number “0”, none of the select signals S1 to S15 from the decoder DEC is activated to “logic 1”. The output signals of the OR circuits OR2 to OR15 remain inactivated to "logic 0". Accordingly, when the latch output signal LO [3: 0] indicates the decimal number “0”, the switch circuits SW1 to SW15 connect the block data lines BD1 to BD15 to the external data lines D1 to D15, respectively.

  On the other hand, when the latch output signal LO [3: 0] indicates the decimal number “1”, the select signal S1 is activated to “logic 1”, so that the output signals of the OR circuits OR2 to OR15 become “logic 1”. Activated. Accordingly, when the latch output signal LO [3: 0] indicates the decimal number “1”, the switch circuits SW1 to SW15 connect the block data lines BD2 to BD16 to the external data lines D1 to D15, respectively. As a result, the memory block BLK1 becomes invalid and the memory block BLK16 becomes valid.

  Similarly, when the latch output signal LO [3: 0] indicates the decimal number “n” (n = 2 to 15), the select signal Sn is activated to “logic 1”, so that the OR circuits ORn to OR15 The output signal is activated to “logic 1”. Accordingly, when the latch output signal LO [3: 0] indicates the decimal number “n”, the switch circuits SW1 to SWn−1 connect the block data lines BD1 to BDn−1 to the external data lines D1 to Dn−1. The switch circuits SWn to SW15 connect the block data lines BDn + 1 to BD16 to the external data lines Dn to D15. As a result, the memory block BLKn becomes invalid and the memory block BLK16 becomes valid.

  FIG. 2 shows details of the fuse latch portion FLP of FIG. The fuse latch unit FLP includes fuse circuits FC0 to FC3 (nonvolatile memory circuits), latch circuits LC0 to LC3, and a NOR circuit NR (defective signal generation circuit). The fuse circuits FC0 to FC3 have the same circuit configuration, and each includes a buffer BF1, an inverter I0, I1, a pMOS transistor Q0, an nMOS transistor Q1, Q2, and a fuse F each formed of a two-stage inverter array. .

  In the fuse circuit FCj (j = 0 to 3), the pMOS transistor Q0 and the nMOS transistors Q1 and Q2 are connected in series between the power supply line VDD and the ground line VSS. Buffer BF1 receives reset signal / RST from NAND circuit NA0 (FIG. 1), and outputs it to the gate of pMOS transistor Q0 and inverter I0. Inverter I0 inverts the output signal of buffer BF1 and outputs the inverted signal to the gate of nMOS transistor Q1 and inverter I1. Inverter I1 inverts the output signal of inverter I0 and outputs it to the gate of nMOS transistor Q2. The fuse F is connected between the connection node of the nMOS transistors Q1 and Q2 and the ground line VSS. A connection node N0 (hereinafter referred to as an output node N0 of the fuse circuit FCj) of the pMOS transistor Q0 and the nMOS transistor Q1 is connected to a common node NCj connected to the signal line LIj.

  In such a fuse circuit FCj, both the pMOS transistor Q0 and the nMOS transistor Q1 are turned on and the nMOS transistor Q2 is turned off while the reset signal / RST is activated. At this time, if the fuse F is not blown, a current flows from the power supply line VDD to the ground line VSS via the pMOS transistor Q0, the nMOS transistor Q1, and the fuse F, so that “logic 0” is output to the output node N0 of the fuse circuit FCj. Is generated. On the other hand, when the fuse F is blown, no current flows from the power supply line VDD to the ground line VSS via the pMOS transistor Q0, the nMOS transistor Q1, and the fuse F, so that “logic” is output to the output node N0 of the fuse circuit FCj. A signal indicating 1 ″ is generated.

  Further, during the inactivation of the reset signal / RST, both the pMOS transistor Q0 and the nMOS transistor Q1 are turned off, and the nMOS transistor Q2 is turned on. Therefore, the signal generation operation for output node N0 as described above is not performed while reset signal / RST is inactive. Accordingly, the fuse circuit FCj outputs a logic level signal (first latch setting signal) corresponding to whether or not the fuse F is blown to the common node NCj only when the reset signal / RST indicates “logic 0”.

  The latch circuits LC0 to LC3 have the same circuit configuration and have inverters I2 to I4, respectively. In the latch circuit LCj (j = 0 to 3), one output of the inverters I2 and I3 is connected to the other input. Inverter I4 inverts the signal generated at the connection node between the output of inverter I2 and the input of inverter I3, and outputs the inverted signal as latch output signal LOj. A connection node N1 (hereinafter referred to as an input node N1 of the latch circuit LCj) of the input of the inverter I2 and the output of the inverter I3 is connected to the common node NCj. That is, the latch circuit LCj includes a signal output from the fuse circuit FCj during the activation of the reset signal / RST, and an external latch setting signal LSj output from the three-state circuit TSj during the activation of the input control signal / IC. Are received at the input node N1, and the signal received at the input node N1 is held and output as a latch output signal LOj. Therefore, the latch output signal LOj is initialized to “logic 0” when the fuse F of the fuse circuit FCj is not blown in association with the temporary activation of the reset signal / RST immediately after the RAM 10 is turned on. When the fuse F of the fuse circuit FCj is blown, it is initialized to “logic 1”. The NOR circuit NR activates the fuse state signal / FS to “logic 0” when at least one of the latch output signals LO0 to LO3 indicates “logic 1”.

  In the RAM 10 having the above configuration, as described with reference to FIG. 1, when the latch output signal LO [3: 0] indicates the decimal number “m” (m = 1 to 15), the memory block BLKm is invalidated. At the same time, the memory block BLK16 becomes valid. Therefore, in the test in the manufacturing process, for example, when a defect is detected in the memory block BLK2, the latch output signal LO [3: 0] is “0010” (corresponding to the decimal number “2”) immediately after the RAM 10 is turned on. By fusing the fuse F of the fuse circuit FC1 so as to be initialized, the defect of the memory block BLK2 generated in the manufacturing process can be relieved.

  Further, when no defect is detected in any of the memory blocks BLK1 to BLK15 in the test in the manufacturing process and any fuse F of the fuse circuits FC0 to FC3 is not blown, the latch output signal LO [3: 0] is stored in the RAM 10 Is initialized to “0000” immediately after the power is turned on. Therefore, immediately after the RAM 10 is turned on, the fuse state signal / FS is initialized to “logic 1”, and the external redundancy enable signal ERE is output as an input control signal / IC to the three-state circuits TS0 to TS3. Therefore, in the RAM 10 in which any fuse F of the fuse circuits FC0 to FC3 is not blown, for example, a failure of the memory block BLK2 is detected in a self-test in a state in which a system LSI having the RAM 10 is incorporated in a user system. In this case, the external redundancy enable signal ERE is set with the external latch setting signal LS [3: 0] set to “0010” so that the latch output signal LO [3: 0] is changed from “0000” to “0010”. By activating it, it is possible to relieve a defect in the memory block BLK2 that has occurred on the user system. Thus, the RAM 10 has both a redundancy function based on the fuse circuits FC0 to FC3 (fuse redundancy function) and a redundancy function based on the external latch setting signals LS0 to LS3 (external redundancy function).

  On the other hand, when a defect is detected in any of the memory blocks BLK1 to BLK15 in the test in the manufacturing process and at least one fuse F of the fuse circuits FC0 to FC3 is blown, the latch output signal LO [3: 0] Is initialized to other than “0000” immediately after the RAM 10 is powered on. Therefore, immediately after the RAM 10 is turned on, the fuse state signal / FS is initialized to “logic 0” and the input control signal / IC is fixed to “logic 1”. Thereby, the output operation of the external latch setting signals LS0 to LS3 by the three-state circuits TS0 to TS3 is prohibited. Therefore, in the RAM 10 in which at least one of the fuses F0 to FC3 is blown, the logic level of the latch output signal LO [3: 0] is changed by the external latch setting signal LS [3: 0]. There is nothing. Therefore, the memory block invalidated by blowing the fuse F in the test in the manufacturing process is not erroneously validated.

  FIG. 3 shows an operation example of the redundancy control circuit RC in the first embodiment (when any fuse F of the fuse circuits FC0 to FC3 is not blown). When the power supply of the system LSI on which the RAM 10 is mounted is turned on, the power-on reset signal POR is activated to “logic 1” (FIG. 3A). After the elapse of the delay time by the delay circuit DLY from the activation of the power-on reset signal POR, the reset signal / RST from the NAND circuit NA0 to the fuse latch unit FLP is activated to “logic 0” (FIG. 3B). . Since none of the fuses F of the fuse circuits FC0 to FC3 is blown, “0000” is indicated from the fuse circuits FC0 to FC3 to the input node N1 of the latch circuits LC0 to LC3 in response to the activation of the reset signal / RST. A signal is output. Therefore, the signal lines LI [3: 0] connected to the input nodes N1 (common nodes NC0 to NC3) of the latch circuits LC0 to LC3 are initialized to “0000” (FIG. 3C). Accordingly, the latch output signal LO [3: 0] from the redundancy control circuit RC is initialized to “0000” (FIG. 3D). As a result, the fuse state signal / FS from the fuse latch unit FLP to the NAND circuit NA1 is initialized to “logic 1” (FIG. 3E). When a predetermined time elapses after the system LSI is turned on, the power-on reset signal POR is deactivated to “logic 0” (FIG. 3F). Immediately after the power-on reset signal POR is deactivated, the reset signal / RST is deactivated to "logic 1" (FIG. 3 (g)).

  Thereafter, for example, when a defect in the memory block BLK2 is detected by a self test in a state where the system LSI is incorporated in the user system, the external latch setting signal LS is detected by a test control circuit or the like mounted on the system LSI together with the RAM 10. [3: 0] is set to “0010” (FIG. 3H). Then, the external redundancy permission signal ERE is activated to “logic 1” by the test control circuit (FIG. 3 (i)). Since the fuse state signal / FS is inactivated to "logic 1", the input control signal / IC from the NAND circuit NA1 to the three-state circuits TS0 to TS3 is "logic" with the activation of the external redundancy enable signal ERE. It is activated to 0 ″ (FIG. 3 (j)). As a result, the external latch setting signal LS [3: 0] indicating “0010” is output from the three-state circuits TS0 to TS3 to the input node N1 of the latch circuits LC0 to LC3. Therefore, the signal line LI [3: 0] is set to “0010”, and the latch output signal LO [3: 0] is also set to “0010” (FIGS. 3 (k) and (l)). As a result, the select signal S2 from the decoder DEC is activated to “logic 1”, the memory block BLK2 becomes invalid and the memory block BLK16 becomes valid. That is, the defect of the memory block BLK2 generated on the user system is relieved.

  FIG. 4 shows another operation example of the redundancy control circuit RC in the first embodiment (when the fuse F of the fuse circuit FC0 is blown). When the power supply of the system LSI having the RAM 10 is turned on, the power-on reset signal POR is activated to “logic 1” (FIG. 4A). After the elapse of the delay time by the delay circuit DLY from the activation of the power-on reset signal POR, the reset signal / RST from the NAND circuit NA0 to the fuse latch unit FLP is activated to “logic 0” (FIG. 4B). . Since fuse F of fuse circuit FC0 is blown, in response to activation of reset signal / RST, a signal indicating "0001" is output from fuse circuits FC0 to FC3 to input node N1 of latch circuits LC0 to LC3. The Therefore, the signal lines LI [3: 0] respectively connected to the input nodes N1 (common nodes NC0 to NC3) of the latch circuits LC0 to LC3 are initialized to “0001” (FIG. 4C). Accordingly, the latch output signal LO [3: 0] from the redundancy control circuit RC is initialized to “0001” (FIG. 4D). As a result, the fuse state signal / FS from the fuse latch unit FLP to the NAND circuit NA1 is initialized to “logic 0” (FIG. 4E). When a predetermined time elapses after the system LSI is turned on, the power-on reset signal POR is deactivated to “logic 0” (FIG. 4F). Immediately after the power-on reset signal POR is deactivated, the reset signal / RST is deactivated to "logic 1" (FIG. 4 (g)).

Here, it is assumed that the external redundancy enable signal ERE is activated to “logic 1” after the external latch setting signal LS [3: 0] is set to “0010” (FIG. 4 (h), (i )). Since the fuse state signal / FS is activated to “logic 0”, even if the external redundancy enable signal ERE is activated, the input control signal / IC from the NAND circuit NA1 to the three-state circuits TS0 to TS3 is “logic”. It is not activated to 0 ″ (FIG. 4 (j)). Therefore, the external latch setting signal LS [3: 0] indicating “0010” is not output from the three-state circuits TS0 to TS3 to the input node N1 of the latch circuits LC0 to LC3. Therefore, the signal line LI [3: 0] remains set to “0001”, and the latch output signal LO [3: 0] also remains set to “0001” (FIG. 4 (k), (l )). Therefore, the memory block BLK1 invalidated by the fusing of the fuse F of the fuse circuit FC0 in the test in the manufacturing process is not erroneously validated.

  FIG. 5 shows an example of a system LSI on which the RAM 10 of FIG. 1 is mounted. The system LSI 100 includes a user circuit 12, a BIST circuit 14, and a test control circuit 16 in addition to the RAM 10 of FIG. The user circuit 12 includes a CPU, a clock generation circuit, a reset generation circuit (not shown), and the like. The user circuit 12 sets a multi-bit user address signal ADU to a logic level indicating a desired memory cell and accesses a user chip enable signal and a user write enable signal (not shown) when the CPU 10 accesses the RAM 10. ) Are activated and deactivated at a desired timing. The user circuit 12 outputs desired write data to the data bus DB at the time of write access to the RAM 10 by the CPU, and is output from the RAM 10 to the data bus DB through the external data lines D1 to D15 at the time of read access to the RAM 10 by the CPU. Get read data. Further, the user circuit 12 outputs to the RAM 10 the clock signal CK generated by the clock generation circuit and the power-on reset signal POR generated by the reset generation circuit.

  The BIST circuit 14 includes a control unit 14a, a selector 14b, and a comparator 14c. The control unit 14a includes a control circuit, an address generator, a data generator, and the like. During the activation of the test enable signal TE from the test control circuit 16, the control circuit of the control unit 14a sequentially performs write access and read access while changing the access destination to the RAM 10, thereby allocating memory cells in the RAM 10. In order to sequentially test, a plurality of bits of the test address signal ADT are sequentially set to addresses sequentially generated by the address generator, and a test chip enable signal and a test write enable signal (not shown) are set at a desired timing. Activate and deactivate with. The control circuit of the control unit 14a sequentially outputs the test write data D1T to D15T sequentially generated by the data generator to the data bus DB in accordance with the write access to the RAM 10.

  The control circuit of the control unit 14a instructs the selector 14b to select the user address signal ADU (user chip enable signal and user write enable signal) while the test enable signal TE is inactivated. While the test enable signal TE is activated, the selection of the test address signal ADT (the test chip enable signal and the test write enable signal) is instructed.

  The selector 14b receives a user address signal ADU (user chip enable signal and user write enable signal) from the user circuit 12 or a test address signal ADT (for testing) from the control unit 14a in response to an instruction from the control unit 14a. One of the chip enable signal and the test write enable signal is selected and output as an address signal AD (chip enable signal and write enable signal) to the RAM 10.

  The comparator 14c receives the read data D1 to D15 output from the RAM 10 through the external data lines D1 to D15 to the data bus DB and the test write data D1T to D15T output from the control unit 14a to the data bus DB. Compare. For example, when both do not match, the comparator 14c activates the fail signal FAIL to the test control circuit 16 and sets the 4-bit fail bit signal FBIT to a logic level indicating a mismatched bit.

  The test control circuit 16 periodically activates a test enable signal TE to the BIST circuit 14 in order to test the RAM 10 in a state where the system LSI 100 is incorporated in the user system. In response to the activation of the fail signal FAIL from the BIST circuit 14, the test control circuit 16 stores the mismatched bits indicated by the fail bit signal FBIT from the BIST circuit 14. When the test circuit control circuit 16 recognizes the completion of the test of the RAM 10 by the BIST 14 and stores a mismatched bit, the test circuit control circuit 16 sends the external latch setting signal LS [3: 0] to the RAM 10 to the memory block corresponding to the bit. Then, the external redundancy permission signal ERE to the RAM 10 is activated. As a result, defects in the memory blocks BLK1 to BLK15 generated on the user system are remedied.

FIG. 6 shows a test flow in a manufacturing process for the system LSI 100 of FIG.
(Step S11) Before the assembly work, a primary test (probe test) of the RAM 10 by the tester device is performed. Thereafter, the test flow proceeds to step S12.
(Step S12) It is determined whether a defect is detected in any of the memory blocks BLK1 to BLK15 by the primary test. When a defect is detected by the primary test, the test flow moves to step S13. If no defect is detected by the primary test, the test flow proceeds to step S14.
(Step S13) The fuses F of the fuse circuits FC0 to FC3 are blown according to the memory block in which the failure is detected by the primary test (fuse redundancy). For example, when a defect is detected in the memory block BLK2 by the primary test, the fuse F of the fuse circuit FC1 is blown. Thereby, the defect of the memory block BLK2 generated in the manufacturing process is relieved. Thereafter, the test flow proceeds to step S14.
(Step S14) After the assembly work, a secondary test of the RAM 10 is performed by the tester device, and the test flow in the manufacturing process for the system LSI 100 is completed. If a failure is detected in any of the memory blocks BLK1 to BLK15 by the secondary test, the sample is treated as a defective product. If no failure is detected, the sample is shipped as a non-defective product.

FIG. 7 shows a test flow on the user system for the system LSI 100 of FIG.
(Step S21) The test control circuit 16 activates the test enable signal TE to the BIST circuit 14 in order to test the RAM 10. Thereby, the self test by the BIST circuit 14 is performed. Thereafter, the test flow proceeds to step S22.
(Step S22) The test control circuit 16 determines whether or not the mismatched bits detected in the self test are stored. That is, it is determined whether a defect is detected in any of the memory blocks BLK1 to BLK15 by the self test. If the test control circuit 16 stores the mismatched bits, the test flow moves to step S23. When the test control circuit 16 does not store mismatched bits, the test flow on the user system for the system LSI 100 is completed.
(Step S23) The test control circuit 16 sets the external latch setting signal LS [3: 0] to the RAM 10 to a logic level indicating a memory block corresponding to the stored mismatched bits, and The redundancy permission signal ERE is activated. As a result, the defective memory block generated on the user system is relieved, and the test flow on the user system for the system LSI 100 is completed. Such a test flow composed of steps S21 to S23 is periodically performed on the user system.

  FIG. 8 shows an example of a RAM having only a fuse redundancy function. The same elements as those described in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. The RAM 10a is the same as the RAM 10 of FIG. 1 except that it has a redundant control circuit RCa instead of the redundant control circuit RC. The redundancy control circuit RCa is identical to the redundancy control circuit RC of FIG. 1 except that the three-state circuits TS0 to TS3 and the NAND circuit NA1 are omitted and that the fuse latch unit FLPa is provided instead of the fuse latch unit FLP. Are the same. The fuse latch unit FLPa outputs latch output signals LO0 to LO3 set based on the reset signal / RST from the NAND circuit NA0.

FIG. 9 shows details of the fuse latch portion FLPa of FIG. The fuse latch portion FLPa is the same as the fuse latch portion FLP in FIG. 2 except that the signal lines LI0 to LI3 and the NOR circuit NR are omitted. Therefore, the RAM 10a has only a redundant function based on the fuse circuits FC0 to FC3.
FIG. 10 shows an example of a RAM having only an external redundancy function. The same elements as those described in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. The RAM 10b is the same as the RAM 10 in FIG. 1 except that the redundant control circuit RCb is provided instead of the redundant control circuit RC. The redundancy control circuit RCb is the same as the redundancy control circuit RC of FIG. 1 except that it has an inverter IV0 and a latch part LP instead of the NAND circuit NA1 and the fuse latch part FLP. Inverter IV0 inverts external redundancy permission signal ERE and outputs the inverted signal to three-state circuits TS0 to TS3 as input control signal / IC. The latch part LP outputs latch output signals LO0 to LO3 set based on the reset signal / RST from the NAND circuit NA0 and the external latch setting signals LS0 to LS3 from the three-state circuits TS0 to TS3.

  FIG. 11 shows details of the latch portion LP of FIG. The latch unit LP includes an inverter IV1 and latch circuits LC0a to LC3a. Inverter IV1 inverts and outputs reset signal / RST from NAND circuit NA0 (FIG. 10). The latch circuits LC0a to LC3a have the same circuit configuration. The latch circuit LCja (j = 0 to 3) is configured by adding an nMOS transistor Q4 to the latch circuit LCj of FIG. In the latch circuit LCja, the nMOS transistor Q4 is connected between the connection node N1 of the input of the inverter I2 and the output of the inverter I3 and the ground line VSS. The gate of nMOS transistor Q4 receives the output signal of inverter IV1 (a signal obtained by inverting reset signal / RST).

  The latch circuit LCja having such a configuration is configured such that a signal (a signal indicating “logic 0”) generated by turning on the nMOS transistor Q4 during the activation of the reset signal / RST and the input control signal / IC during the activation of the input control signal / IC. The node N1 receives both the external latch setting signal LSj output from the three-state circuit TSj, holds the signal received at the node N1, and outputs it as a latch output signal LOj. Therefore, the RAM 10b has only a redundant function based on the external latch setting signals LS0 to LS3. For example, by mounting such a RAM 10b in the system LSI 100 of FIG. 5 in place of the RAM 10, defects in the memory blocks BLK1 to BLK15 generated on the user system can be remedied as in the RAM 10. If the redundant control circuits RCa (FIG. 8) and RCb (FIG. 10) as described above are juxtaposed in the RAM, both the fuse redundant function and the external redundant function can be realized, but the circuit scale of the RAM increases. Therefore, the chip size of the system LSI on which the RAM is mounted increases.

  On the other hand, in the above-described RAM 10 (FIG. 1), the latch circuit LCj includes a signal output from the fuse circuit FCj during the activation of the reset signal / RST and a three-state during the activation of the input control signal / IC. Both the external latch setting signal LSj output from the circuit TSj is received at the input node N1, and the signal received at the input node N1 is held and output as the latch output signal LOj. That is, the latch circuit for the fuse redundancy function and the latch circuit for the external redundancy function are shared. For this reason, the circuit configuration of the redundancy control circuit RC (that is, the circuit configuration of the RAM 10) can be simplified. As a result, both the fuse redundancy function and the external redundancy function can be realized without increasing the chip size of the system LSI 100 on which the RAM 10 is mounted.

  FIG. 12 shows a second embodiment of the present invention. In describing the second embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The RAM 20 is the same as the RAM 10 of the first embodiment (FIG. 1) except that it has a main control circuit MC2 instead of the main control circuit MC. Accordingly, the RAM 20 includes memory blocks BLK1 to BLK16, switch circuits SW1 to SW15, and OR circuits OR2 to OR15 (not shown) in addition to the main control circuit MC2 and the redundancy control circuit RC.

  The main control circuit MC2 has an 8-bit address register AR, a predecoder PD, and a memory block control circuit MBC. When the scan mode signal SMD indicates “logic 0”, the address register AR performs an operation of taking in the 8-bit address signals AD0 to AD7 in synchronization with the clock signal CK. When the scan mode signal SMD indicates “logic 1”, the address register AR performs an operation of taking in the scan input signal SI in synchronization with the scan clock signal SCK. The address register AR outputs output signals RO0 to RO7 according to the captured signal. Output signals RO0 to RO3 of the address register AR are input to the three-state circuits TS0 to TS3 in the redundancy control circuit RC, respectively, instead of the external latch setting signals LS0 to LS3 of the first embodiment.

  The predecoder PD decodes the output signals RO0 to RO7 of the address register AR and outputs the decoding result to the memory block control circuit MBC. The memory block control circuit MBC is common to the memory blocks BLK1 to BLK16 based on the address decoding result by the predecoder PD and the chip enable signal / CE and the write enable signal / WE fetched in synchronization with the clock signal CK. One of the plurality of word lines WL to be connected is activated and a control signal CTL for the memory blocks BLK1 to BLK16 is generated.

  FIG. 13 shows details of the address register AR of FIG. The address register AR has scan flip-flops FF0 to FF7 (register circuits) corresponding to the address signals AD0 to AD7, respectively. The flip-flops FF0 to FF7 have the same circuit configuration and have a mode terminal MD, a clock terminal C, a scan clock terminal SC, a data input terminal D, a scan data input terminal SD, and a data output terminal Q.

  The flip-flop FFk (k = 0 to 7) sequentially receives the signal received at the data input terminal D in synchronization with the rising edge of the signal received at the clock terminal C when the signal received at the mode terminal MD indicates “logic 0”. Capture and output from the data output terminal Q. When the signal received at the mode terminal MD indicates “logic 1”, the flip-flop FFk sequentially takes in the signal received at the scan data input terminal SD in synchronization with the rising edge of the signal received at the scan clock terminal SC. Output from Q. That is, flip-flop FFk has a normal mode when a signal received at mode terminal MD indicates “logic 0” and a scan mode when a signal received at mode terminal MD indicates “logic 1”.

  Accordingly, when the scan mode signal SMD indicates “logic 0”, the flip-flop FF0 sequentially takes in the address signal AD0 and outputs it as the output signal RO0 in synchronization with the rising edge of the clock signal CK. When the scan mode signal SMD indicates “logic 1”, the flip-flop FF0 sequentially takes the scan input signal SI in synchronization with the rising edge of the scan clock signal SCK and outputs it as the output signal RO0.

  When the scan mode signal SMD indicates “logic 0”, the flip-flops FF1 to FF7 sequentially take in the address signals AD1 to AD7 and output them as output signals RO1 to RO7 in synchronization with the rising edge of the clock signal CK. When the scan mode signal SMD indicates “logic 1”, the flip-flops FF1 to FF7 sequentially receive the output signals RO0 to RO6 of the preceding flip-flops FF0 to FF6 in synchronization with the rising edge of the scan clock signal SCK. Output as output signals RO1 to RO7. That is, the flip-flops FF0 to FF7 form a scan chain.

  In the RAM 20 having the above configuration, as described with reference to FIG. 12, the output signals AR0 to AR3 of the address register AR are input to the three-state circuits TS0 to TS3 in the redundancy control circuit RC, respectively. Therefore, it is assumed that no defect is detected in any of the memory blocks BLK1 to BLK15 in a test in the manufacturing process, and a defect is detected in any of the memory blocks BLK1 to BLK15 by a self test on the user system. In such a case, for example, in a state where the scan mode signal SMD is set to “logic 1” by the test control circuit mounted on the system LSI together with the RAM 20, the memory block in which the output signals RO0 to RO3 of the address register AR are defective. As shown in the figure, after the logic level of the scan input signal SI is sequentially set in synchronization with the scan clock signal SCK, the external redundancy enable signal ERE is activated to perform the same operation on the user system as in the RAM 10 of the first embodiment. The generated defects of the memory blocks BLK1 to BLK15 can be remedied. Even in the second embodiment as described above, the same effect as in the first embodiment can be obtained.

In the first and second embodiments, an example in which the present invention is applied to a system LSI chip on which a RAM is mounted has been described. However, the present invention is not limited to such an embodiment. For example, the present invention may be applied to a single RAM chip.
As mentioned above, although this invention was demonstrated in detail, the above-mentioned embodiment and its modification are only examples of this invention, and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

1 is a block diagram showing a first embodiment of the present invention. It is a block diagram which shows the detail of the fuse latch part of FIG. FIG. 6 is a timing diagram illustrating an operation example of the redundancy control circuit according to the first embodiment. FIG. 10 is a timing chart showing another operation example of the redundancy control circuit in the first embodiment. FIG. 2 is a block diagram showing an example of a system LSI on which the RAM of FIG. 1 is mounted. FIG. 6 is a flowchart showing a test flow in a manufacturing process for the system LSI of FIG. 5. FIG. 6 is a flowchart showing a test flow on the user system for the system LSI of FIG. 5. It is a block diagram which shows an example of RAM which has only a fuse redundant function. It is a block diagram which shows the detail of the fuse latch part of FIG. It is a block diagram which shows an example of RAM which has only an external redundancy function. It is a block diagram which shows the detail of the latch part of FIG. It is a block diagram which shows 2nd Embodiment of this invention. It is a block diagram which shows the detail of the address register of FIG.

Explanation of symbols

BF0, BF1 Buffers BLK1-BLK16 Memory block DLY Delay circuit F Fuse FC0-FC3 Fuse circuit FLP Fuse latch unit I0-I4 Inverter LC0-LC3 Latch circuit MBC Memory block control circuit MC, MC2 Main control circuit NA0, NA1 NAND circuit NR NOR Circuit OR2-OR15 OR circuit PD predecoder Q0 pMOS transistor Q1, Q2 nMOS transistor RC redundancy control circuit SW1-SW15 switch circuit TS0-TS3 three-state circuit 10, 20 RAM
12 User circuit 14 BIST circuit 14a Control unit 14b Selector 14c Comparator 16 Test control circuit 100 System LSI

Claims (4)

A plurality of memory blocks including redundant memory blocks;
A plurality of switch circuits connected to two of the memory blocks, respectively, and connecting one data line of the two connected memory blocks to an external data line;
A plurality of latch circuits having a first function for storing a defective memory block in advance in a nonvolatile manner and a second function for storing a defective memory block based on an external signal, and based on an output signal of the latch circuit A redundant control circuit for generating a switching signal to the switch circuit ,
The semiconductor memory device , wherein the redundancy control circuit includes a prohibition circuit that prohibits the input of the external signal of the second function when the first function is used in the latch circuit . The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the redundancy control circuit includes a decoder that decodes an output signal of the latch circuit to generate the switching signal. The semiconductor memory device according to claim 1.
Each of the switch circuits is provided for every two memory blocks adjacent to each other. Multiple normal memory blocks;
A redundant memory block;
A redundancy control circuit for setting a multi-bit redundancy control signal for selecting a memory block to be accessed to a logic level indicating the defective normal memory block when a defect exists in any of the normal memory blocks;
A switching circuit for invalidating the normal memory block and validating the redundant memory block when the redundant control signal indicates a defective normal memory block;
The redundant control circuit includes:
A plurality of latch circuits each provided for each bit of the redundancy control signal, holding a logic level of a signal received at an input node, and setting a corresponding bit of the redundancy control signal to a holding logic level;
A plurality of latch circuits provided in correspondence with the latch circuits, each of which stores in advance a logic level indicating a defective normal memory block, and outputs a first latch setting signal of the stored logic level to an input node of the corresponding latch circuit. A nonvolatile memory circuit of
A plurality of input circuits provided corresponding to the latch circuits, respectively, for receiving a second latch setting signal for changing a logic level held by the corresponding latch circuit and outputting the second latch setting signal to an input node of the corresponding latch circuit ;
A defect signal generation circuit that activates a defect signal when the logical level of the first latch setting signal stored in the nonvolatile memory circuit indicates a defective normal memory block;
A semiconductor memory device comprising: a prohibition circuit for prohibiting the output operation of the second latch setting signal by the input circuit during the activation of the defective signal .

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