JP4585685B2 - Semiconductor device test apparatus control method / semiconductor device test apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control method of a semiconductor device test apparatus configured to test a semiconductor device such as a memory, which is constituted by a semiconductor integrated circuit (hereinafter referred to as a semiconductor device).
[0002]
[Prior art]
FIG. 3 shows a schematic configuration of the semiconductor device test apparatus. The semiconductor device test apparatus is roughly composed of a tester 100, a test head 200, and a handler 400. A performance board 300 is detachably attached to the test head 200. An IC socket SK is mounted on this performance board 300, and the device under test is automatically conveyed and brought into contact with the IC socket SK to execute a test.
[0003]
The tester 100 operates according to a test program stored in the main controller 101 and tests a device under test mounted on the performance board 300. That is, the tester 100 and the test head 200 are connected by the cable KB, the test pattern signal is sent from the tester 100 to the device under test that is in contact with the IC socket SK through the cable KB, and the response signal is again taken into the tester 100 through the cable KB. The response signal is compared with an expected value pattern on the tester 100 side, and a determination operation such as detecting the occurrence of inconsistency and identifying a defective portion of the device under test is executed.
[0004]
A controller 401 is also mounted on the handler 400, and the controller 401 executes control of the semiconductor device transfer operation, control required for testing, and the like.
FIG. 4 is a flowchart showing the operation sequence of the tester 100 and the handler 400.
Step SP0 shows a state in which the device under test is transported toward the test head 200 by the handler 400 in a single test process. This state is referred to as a device carry-in process here.
[0005]
Step SP1 shows a device setting process in which the device under test is dropped from the handler 400 into the IC socket SK provided in the test head 200, and the pins of the device under test and the pins of the IC socket are set in contact with each other.
Step SP2 is a test start request signal SRQ transmission step of transmitting a test start request signal SRQ requesting the test start from the handler 400 to the tester 100.
Step SP3 inquires the number of devices under test loaded in the device loading step SP0 from the tester 100 side, for example, from the tester 100 side, and the placement of the devices under test during transportation (for example, the placement of devices on the tray) prior to the start of the test. , Send and receive the data. By sending and receiving this data, the tester 100 collates the number of IC sockets SK provided in the test head 200 with the number of devices to be tested, and whether or not all the IC sockets SK are mounted with devices under test or a part of them. Identify whether the IC socket is empty. This exchange of data is referred to as a first communication process, and a process of determining whether a device under test is attached to all of the IC sockets or an IC socket where no device under test is attached is referred to as a first data processing step. I will decide.
[0006]
In step SP4, a test pattern is transmitted from the tester 100 to the test head 200, and an operation test of the device under test is performed. During the test, the test pattern signal is sequentially transmitted from the tester 100, and the response signal is returned from the test head 200 to the tester 100. The tester 100 compares the response signal returned from the test head 200 with the expected value, and determines pass / fail.
In step SP5, a pass / fail judgment map is created according to the test result. Hereinafter, this section is referred to as a second data processing step.
[0007]
At the same time, the pass / fail judgment map created by the tester 100 is sent to the handler 400. Hereinafter, this process is referred to as a second communication process.
In step SP6, the handler 400 executes an operation of removing the device under test from the IC socket SK. This process will be referred to as a device removal process.
In step SP7, the handler 400 sorts the device under test into a non-defective product and a defective product according to the pass / fail judgment result sent from the tester 100, and carries out the device under test from the test head 200 while classifying the device under test into the non-defective product and defective product storage section. Hereinafter, this process is referred to as a device carry-out process.
[0008]
When the device carry-out process of step SP7 is completed, the process returns to step SP0, and a new device under test carry-in process is started.
[0009]
[Problems to be solved by the invention]
Since the test of the semiconductor device tests the whole amount of the manufactured semiconductor device, the amount is enormous. For this reason, there are attempts to increase the number of devices under test to be tested at once as much as possible, or to increase the speed of the test process to be performed at step SP4 as much as possible to test a large number of semiconductor devices in a short time. Various things have been done.
Attempts to speed up the test process executed in step SP4 and reduce the test time are already approaching the limit, and other methods for reducing the test time are required.
[0010]
In each process shown in FIG. 4, the test process for testing the device under test has already been speeded up because it is sufficient to send and receive electrical signals. On the other hand, the device under test is transported to the IC socket SK of the test head 200, and the semiconductor device is removed from the IC socket SK after the operation of attaching to the IC socket SK and after the test is finished, and classifying it into a good product and a defective product. Since the work to carry out the device under test is a process executed by the machine, it is difficult to increase the speed. However, if the speed of transporting the device under test in the handler 400 is increased, the number of devices to be tested increases as the number of devices under test increases. Therefore, even if the time required for transport is slightly reduced, the test time of the semiconductor device is greatly increased. The effect that can be shortened is obtained.
[0011]
An object of the present invention is to propose a control method of a semiconductor device test apparatus that can shorten the test time of a semiconductor device.
[0012]
[Means for Solving the Problems]
According to the first aspect of the present invention, data is exchanged between the tester and the handler, the semiconductor device is tested by operating the tester and the handler, and the device under test is classified and stored on the handler side according to the test result. In the semiconductor device test apparatus that repeats the operation to
A control method of a semiconductor device test apparatus is proposed that executes a communication process for transferring data between a tester and a handler during a device transfer process of a handler.
[0013]
According to the second aspect of the present invention, data is exchanged between the tester and the handler, the tester and the handler are operated to test the semiconductor device, and the device under test is classified and stored on the handler side according to the test result. In a semiconductor device test apparatus that repeats operations,
A control method for a semiconductor device test apparatus is proposed that executes both a communication process for transferring data between a tester and a handler during a device transfer process of a handler and a data processing process in the tester.
[0014]
According to a third aspect of the present invention, in the method for controlling a semiconductor device testing apparatus according to the first aspect, the communication process executed together with the device transporting process is performed before and after the test process. A control method is proposed.
According to a fourth aspect of the present invention, in the method for controlling a semiconductor device test apparatus according to the second aspect, the communication step and the data processing step executed together with the device transfer step are performed both before and after the test step. A control method for device test equipment is proposed.
[0015]
According to the fifth aspect of the present invention, data is exchanged between the tester and the handler, the tester and the handler are operated to test the semiconductor device, and the device under test is classified and stored on the handler side according to the test result. In a semiconductor device test apparatus that repeats operations,
Proposed is a semiconductor device testing apparatus configured to execute both a communication process for transferring data between a tester and a handler during a handler device transfer process and a data processing process in the tester.
[0016]
[Action]
According to the control method of the present invention, the communication process for transferring data between the tester and the handler and / or the data processing process on the tester side or both of them are executed during the transport process of the semiconductor device of the handler. The time required for the test can be shortened. As a result, since the number of testable semiconductor devices per unit time can be increased, there is an advantage that the test efficiency can be improved.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a flowchart for explaining the most desirable control method of the semiconductor device testing apparatus according to the present invention. A feature of the present invention is that in the device carry-in process and device carry-out process shown in steps SP0 and SP5, the first communication process and the first data processing process, and the second data processing process and the second communication process are performed simultaneously with these processes. This is a control method for executing. The primary purpose of the first communication step is to notify the tester 100 from the handler 400 whether or not the number of devices under test to be tested is equal to the number of IC sockets SK provided in the test head 200. . Therefore, in the device carry-in process, the number of devices under test being transported toward the test head 200 is counted during transport, and the number of semiconductor devices under test being transported and the arrangement status of the devices under test are measured by the tester 100. 1st communication process is achieved by notifying to.
[0018]
The tester 100 executes the first data processing step when the number of devices under test being conveyed toward the test head 200 is notified in the first communication step. In the first data processing step, devices to be tested are attached to all sockets of the IC socket SK provided in the test head 200, or when the number of devices under test is smaller than the number of sockets, the device under test being transported Which IC socket SK is mounted with the device under test and which IC socket is not mounted with the device under test is identified from the device arrangement.
[0019]
These first communication process and first data processing process are executed during actual operation of the device carrying-in process, and when the device carrying-in process is completed, the first data processing process can also be terminated.
When the device carrying-in process is completed, each device under test is aligned and dropped into the IC socket SK. After confirming whether or not the device is correctly contacted, the pressure contactor contacts the device under test. The pins of the device under test and the pins of the IC socket SK are brought into electrical contact by pressure contact, and the contact state is maintained in a stable state. This state is the device setting process shown in step SP1.
[0020]
A test start request signal SRQ shown in step SP2 is transmitted from the handler 400 in a state where the IC socket SK of the device under test is stably in contact with the IC socket SK, and is sent to the tester 100.
When the tester 100 provides the test start request signal SRQ from the handler 400, the tester 100 executes the test process indicated by step SP3.
When the test process is completed, the handler 400 executes a device removal process indicated by step SP4. The device removal step refers to a situation in which the device under test is removed from the IC socket SK on the test head 200 and the device under test is delivered from the test head 200 to the transport apparatus.
[0021]
When the device under test is delivered to the transport device and the carry-out of the device under test is started, step SP5 is being executed.
In the present invention, the second data processing step and the second communication step are executed during the device carry-out step. In the second data processing step, the pass / fail determination result determined by the logical comparator provided in the tester 100 is sent to the handler 400 in the second communication step.
The handler 400 stores the semiconductor devices under test in the respective storage units while sorting the semiconductor devices under test into non-defective products and defective products during the transport period based on the pass / fail judgment results sent from the tester 100.
[0022]
As described above, the first communication step, the first data processing step, and the first data processing step are performed in parallel with the device carry-in step shown at step SP0 executed before the test step and the device transfer step SP5 executed after the test step shown at step SP3. Since the two data processing steps and the second communication step are respectively performed, the time required to execute the first communication step and the first data processing step, the time T1 required for executing the first communication step and the first data processing step, the second data processing step, and the second communication step are determined. The time corresponding to the time T2 required to execute the two communication means can be shortened. Actually, T1 + T2 is about 0.1 to 0.2 seconds.
[0023]
As a result, if the time required for testing a semiconductor device is conventionally 1 second, for example, 1 second−0.2 seconds = 0.8 seconds, and the device under test is tested in about 80% of the conventional time. Will be able to. Even if the time for shortening is 0.2 seconds at most, it can be easily understood that the effect appears as the test is repeated.
Although the most preferable embodiment is shown in the embodiment shown in FIG. 1, the control method shown in FIG. 2 can also be adopted. The control method shown in FIG. 2 executes only the first communication process in the device carry-in process, the first data processing process is executed after the device carry-in process, the second data processing process is executed after the device removal process, and then Shows an example of a control method in which the device carry-out step and the second communication step are simultaneously executed in parallel.
[0024]
Thus, even when controlled, the time required for the first communication step and the second communication step can be shortened.
[0025]
【The invention's effect】
As described above, according to the present invention, other steps are executed during the device transfer step, so the time required for the steps executed simultaneously can be subtracted from the entire test time. Therefore, since the time required for the test can be shortened, the repetition cycle of the test can be accelerated, and a large amount of semiconductor devices can be tested in a short time, and the effect is very practical. .
[Brief description of the drawings]
FIG. 1 is a flowchart for explaining a control method of a semiconductor device test apparatus according to the present invention;
FIG. 2 is a flowchart for explaining a modified embodiment of the present invention.
FIG. 3 is a block diagram for explaining an outline of a semiconductor device testing apparatus.
FIG. 4 is a flowchart for explaining a control method of a conventional semiconductor device test apparatus;
[Explanation of symbols]
100 Tester 101 Main controller 200 Test head 300 Performance board 400 Handler 401 Controller SK IC socket

Claims (5)

Test and test the multiple devices under test by operating the tester and handler between the tester and handler connected to the test head equipped with multiple devices under test and operating the tester and handler. In the control method of the semiconductor device test apparatus that repeats the operation of classifying and storing the device under test on the handler side,
During the process of transporting the device under test between the handler and the test head, the number of devices under test transported toward the test head between the tester and the handler, the arrangement of the devices under test on the tray , and the tester A control method for a semiconductor device test apparatus, characterized in that a communication process for exchanging data related to a data processing result is executed. Test and test the multiple devices under test by operating the tester and handler between the tester and handler connected to the test head equipped with multiple devices under test and operating the tester and handler. In the control method of the semiconductor device test apparatus that repeats the operation of classifying and storing the device under test on the handler side,
During the process of transporting the device under test between the handler and the test head, the number of devices under test transported toward the test head between the tester and the handler, the arrangement of the devices under test on the tray , and the tester A control method for a semiconductor device test apparatus, characterized in that both a communication process for exchanging data relating to a data processing result and a data processing process in the tester are executed. 2. The method of controlling a semiconductor device test apparatus according to claim 1, wherein the communication process executed together with the device transport process is executed both before the test process and after the test process. . 3. The semiconductor device test apparatus control method according to claim 2, wherein the communication step and the data processing step executed together with the device transport step are executed both before the test step and after the test step. Device control method. Test and test the multiple devices under test by operating the tester and handler between the tester and handler connected to the test head equipped with multiple devices under test and operating the tester and handler. In a semiconductor device test apparatus that repeats the operation of classifying and storing devices under test on the handler side,
During the process of transporting the device under test between the handler and the test head, the number of devices under test transported toward the test head between the tester and the handler, the arrangement of the devices under test on the tray , and the tester A semiconductor device testing apparatus characterized in that both a communication process for exchanging data relating to a data processing result and a data processing process in the tester are executed.

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