JP4592670B2 - Integrated circuit element - Google Patents

Description

  The present invention relates to an integrated circuit element such as a fine CMOS integrated circuit having a built-in power supply voltage conversion circuit for converting (eg, stepping down) a power supply voltage.

  A CMOS integrated circuit device has a structure in which a transistor is suitable for microfabrication, and a power supply current at rest is very small. Therefore, the CMOS integrated circuit element is characterized by high integration, low power consumption, and a power supply voltage decreasing with miniaturization.

  In recent years, as integrated circuit elements have advanced in miniaturization technology, high-integrated elements exceeding the number of millions to 10 million transistors have been commercialized using minute transistors having a channel length of 0.25 microns or less. . When the scale of integrated circuit elements is increased in this way, an enormous number of test patterns are required to select non-defective products, which not only makes it difficult to generate them, but also increases the number of defects that are difficult to detect in function tests using test patterns. Tend. For example, defects such as open signal lines, shorts between signal lines, and transistor leakage cannot be completely detected by conventional function tests. An Iddq test has been developed as a method for testing a region that cannot be completely detected by such a function test.

  The Iddq test is a method of measuring a minute power supply current flowing through a CMOS integrated circuit element in a stationary state and detecting a failure based on the magnitude of the measured current value. The test target is all transistors connected to the power supply. Therefore, it is a test with very high parallelism, and a high defect detection rate can be achieved by using it in combination with a function test.

A more detailed problem of the Iddq test is described in Non-Patent Document 1, for example.
US Pat. No. 5,493,234 “Voltage Down Converter for Semiconductor Memory Device” Young N. Oh "Iddq Testing: Issues Present and Future" IEEE DESIGN & TEST OF COMPUTER "Jerry M. Soden et al. Vol13, No4, 1996 pp.61-65

  However, since the Iddq test needs to measure a minute current, the measurement speed needs to be sufficiently slow, and there is a problem that it takes too much test time to be applied to a mass production test. While the function test is performed at a test frequency of several tens of MHz to several hundreds of MHz, the Iddq test has a problem of being as slow as several hundred Hz to several tens of kHz.

  Further, the power supply voltage of the CMOS integrated circuit element has been lowered in order to ensure the reliability in accordance with the miniaturization of the transistor. In order to use these low-voltage elements in combination with other power supply voltage elements, an interface circuit that converts the signal level is required. For this interface circuit, a plurality of power supply voltages must be supplied. On the other hand, even elements that are miniaturized from the viewpoint of cost reduction and compatibility of equipment are required to operate with the same voltage as before, that is, a single power supply, and as an integrated circuit element, a power supply voltage conversion circuit is required. An integrated power supply voltage step-down circuit has been devised. A conventional voltage step-down circuit for a dynamic random access memory is described in Patent Document 1, for example.

  For example, the power supply voltage of a 0.25 μm CMOS integrated circuit element is about 2.5V, but the mainstream power supply voltage of electronic equipment is 3.3V or 5V. A dynamic random access memory is a typical example of an element in which a step-down circuit is integrated.

  However, with the progress of miniaturization of transistors, the off-state current of the transistors increases and the degree of integration improves. In addition, a 0.35 μm generation CMOS integrated circuit element has a background current of several μA and 1.8 μm. In the generation, a background current of a value of several tens of mA is predicted to flow regardless of the presence or absence of defects. Further, a leak current of several hundred nA to several μA or more due to a defect detected by the Iddq test tends to be reduced by miniaturization of the element. That is, in a CMOS integrated circuit element that has been miniaturized, a leak current due to a defect is buried in the fluctuation of the background current and cannot be detected. That is, if the variation in the background current becomes larger than the normal defect current, it is difficult to determine whether the current threshold is good or not, and the effectiveness of the Iddq test is impaired.

  In addition, as a main power supply structure of a fine CMOS integrated circuit of 0.25 μm or more, it is necessary to provide a power supply voltage step-down circuit inside the element as described above.

  In this structure, the power supply voltage of the internal circuit does not need to be supplied from the outside of the element, so that the optimum internal operating voltage can be set according to the miniaturization of the transistor and the compatibility is high, and the power supply voltage supplied from the outside fluctuates. However, the internal circuit voltage is excellent in that a step-down circuit can absorb fluctuations in the power supply voltage and achieve a wide power supply voltage operation margin.

  However, this structure, which integrates the power supply voltage step-down circuit inside the element, not only can not directly measure the current flowing through the internal circuit from the outside, but also has a large noise due to the steady current consumed by the step-down circuit and the feedback loop of the step-down circuit. The measurement of minute currents in internal circuits that are generated and become difficult due to an increase in background current makes the Iddq test even more difficult.

  SUMMARY OF THE INVENTION A first object of the present invention is to provide an integrated circuit element including a power supply voltage conversion circuit, which can directly measure an external current flowing in an internal circuit for an Iddq test.

  A second object of the present invention is to provide an integrated circuit element capable of measuring an internal circuit current at high speed for an Iddq test without being buried in a large background current due to a transistor leakage current. .

In order to solve the above problems, Integrated Circuit elements of the present invention includes a power supply voltage converting means for supplying power from the first power supply wiring to convert the supply voltage to the second power supply wiring, the second power supply wiring An integrated circuit element that operates in synchronization with a clock provided with a power supply current measurement circuit that measures a power supply current flowing through the power supply, and includes a clock generation circuit to which a power supply current measurement signal is input, and is generated within the integrated circuit The clock period is selectively extended by the current measurement signal, and the power supply current is measured within the selected and extended clock period.

  According to this configuration, the current flowing in the internal circuit for the Iddq test can be taken out to the outside. In addition, since the power supply current measurement circuit is built in, the inductance component is smaller than in the case of the external power supply current measurement circuit, and high-speed power supply current measurement is possible.

In addition, the element can be brought into a quiescent state within the extended clock cycle, and the quiescent power supply current can be measured. In addition, since the clock is selectively extended, the current measurement time can be shortened as compared with the case where all the clocks are extended. In addition, a clock expansion signal is generated inside the device by a self-diagnostic function ( Built In Self Test) circuit integrated in the integrated circuit, so that current measurement can be performed at the time of self-diagnosis, and high reliability. The integrated circuit device can be provided.

  In the above configuration, it is preferable to output a current value proportional to the power supply current flowing through the second power supply wiring as an output of the power supply current measurement circuit as an external signal or an internal signal of the integrated circuit element.

  According to this configuration, the power supply current of the internal circuit connected to the second power supply wiring can be amplified and output to the outside of the element in the form of a current. Is possible, and is less susceptible to noise.

  In the above configuration, the current value is proportional to the difference between the current proportional to the reference current supplied from the outside of the integrated circuit element as the output of the power supply current measuring circuit and the current proportional to the current flowing through the second power supply wiring. Is preferably output as an external signal or an internal signal of the integrated circuit element.

  According to this configuration, by appropriately setting the reference current, the current value obtained by subtracting the background current of the internal circuit can be taken out of the device, and the S / N ratio of the defect current to the background current can be improved. Can do.

  In the above configuration, the integrated circuit outputs a logic signal indicating the magnitude relationship between the reference current supplied from the outside of the integrated circuit element as the output of the power supply current measuring circuit and the current value proportional to the current flowing through the second power supply wiring. It is preferable to output as an external signal or internal signal of the element.

  According to this configuration, since the power supply current of the internal circuit connected to the second power supply wiring can be amplified and output as a logic signal in comparison with the magnitude of the reference current, the output is performed with a very small voltage. Compared to, high-speed processing is possible, and it is less susceptible to noise. Furthermore, by appropriately setting the reference current, it can be output as a logic signal in consideration of the background current of the internal circuit, and the S / N ratio of the defect current to the background current can be improved.

In the above configuration, the power supply current is measured in synchronization with a clock cycle power current measuring circuit is decompressed, it is preferable that the difference of the power supply current values between different phases in the same clock as the measured value.

According to this configuration, the background current of the internal circuit that varies from element to element can be automatically subtracted, and the influence of the background current can be avoided. Moreover, the quality value can be determined by comparing the difference value of the power supply current with an upper limit value and a lower limit value.

  In the above configuration, it is preferable to output a current value proportional to a difference in power supply current value between different phases in the same clock as an external signal or an internal signal of the integrated circuit element.

  According to this configuration, the power supply current of the internal circuit connected to the second power supply wiring can be amplified and output to the outside of the element in the form of a current. Is possible, and is less susceptible to noise.

  In the above configuration, a logic signal indicating a magnitude relationship between a current proportional to a reference current supplied from an external pad and a current value proportional to a difference between power supply current values between different phases in the same clock is integrated circuit element. It is preferable to output as an external signal or an internal signal.

  According to this configuration, since the power supply current of the internal circuit connected to the second power supply wiring can be amplified and output as a logic signal in comparison with the magnitude of the reference current, the output is performed with a very small voltage. Compared to, high-speed processing is possible, and it is less susceptible to noise. Furthermore, by appropriately setting the reference current, it can be output as a logic signal in consideration of the background current of the internal circuit, and the S / N ratio of the defect current to the background current can be improved.

According to Integrated Circuit elements of the present invention, it is possible to retrieve the current flowing in the internal circuit for Iddq test outside. In addition, since the power supply current measurement circuit is built in, the inductance component is smaller than in the case of the external power supply current measurement circuit, and high-speed power supply current measurement is possible.

  In addition, the element can be brought into a quiescent state within the extended clock cycle, and the quiescent power supply current can be measured. Further, since the clock is selectively extended, the current measurement time can be shortened as compared with the case where all the clocks are extended. Further, if a clock expansion signal is generated inside the device, current measurement can be performed as a self-diagnosis function (BIST) inside the integrated circuit, and a highly reliable integrated circuit can be provided.

  In addition, the background current of the internal circuit that varies from element to element can be automatically subtracted, so that it is not affected by the background current.

  As described above, according to the present invention, even if a large background current due to a transistor leakage current exists, the S / N ratio of the defect current to the background current can be improved only by adding a small circuit. In addition, a defective current can be detected at high speed, and a highly reliable integrated circuit element can be provided at low cost.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an integrated circuit element according to an embodiment of the present invention. In FIG. 1, the integrated circuit element 1 is provided with a power supply pad 10, a ground pad 6, a power supply current measurement output pad 8, and many other signal pads 12. The power supply pad 10 is connected to a first power supply wiring 11 to which a power supply voltage VDD1 is applied from the outside, and is connected to a second power supply wiring 3 through a power supply voltage conversion circuit (power supply voltage step-down circuit) 2. . The voltage VDD1 of the first power supply wiring 11 is stepped down by the power supply voltage conversion circuit 2 serving as power supply voltage conversion means, and supplies the voltage VDD2 to the second power supply wiring 3. An internal circuit 4 that is a main circuit of the integrated circuit element 1 is connected between the second power supply wiring 3 and the ground wiring (potential VSS) 5 connected to the ground pad 6.

  The power supply voltage conversion circuit 2 steps down the voltage to a desired voltage by controlling the gate voltage of the power supply driving P-channel transistor Q1 connected between the first power supply wiring 11 and the second power supply wiring 3. While the internal circuit 4 is in operation, the power supply current constantly fluctuates, so the gate voltage of the power supply driving P-channel transistor Q1 always fluctuates, but becomes a constant value when the internal circuit 4 is stationary.

  The power source current measuring circuit 9 is a current measuring P channel transistor Q2 (channel width) in which a gate and a source electrode are connected in common to a power source driving P channel transistor Q1 (channel width / channel length = W1 / L1). Current (Idout = (W2 / W1) * Iddd) proportional to the current (Idddq) flowing through the internal circuit 4 from the drain of / channel length = W2 / L2) to the power supply current measurement output pad 8 as the power supply current measurement output 7 Output.

  In order for the P channel transistors Q1 and Q2 of the power supply current measuring circuit 9 to normally operate as a current mirror, the power supply P channel transistor Q1 is in a saturation region with respect to the static power supply current Iddq and the power supply voltage VDD2 of the internal circuit 4. It is necessary to be.

  With the above configuration, the minute power supply current Iddq of the internal circuit 4 is amplified and output in the form of current to the outside of the element, so that higher-speed processing is possible than output with a minute voltage, and it is less susceptible to noise. . Further, the method of outputting a current to the outside of the element is faster and faster than the output as a logical value via the A / D conversion circuit, and is practical in cost.

  Further, since the power supply of the internal circuit 4 is concentrated on the power supply voltage conversion circuit 2, the power supply current measurement circuit 9 can be reduced in size by providing the power supply current measurement circuit 9 in the vicinity of the power supply voltage conversion circuit 2.

  FIG. 2 shows a second embodiment of the present invention in which a power source current measuring circuit 9B provided with a reference current input 14 is used in the power source current measuring circuit 9 in the configuration of FIG. 1 and a reference current input pad is added to the integrated circuit element 1. It is a block diagram which shows the structure of the integrated circuit element in a form. In FIG. 2, in the power supply current measuring circuit 9B, a current (∝Iref) proportional to the reference current Iref input from the outside by the P-type transistors Q3 and Q4 connected in a current mirror and a static power supply current Iddq of the internal circuit 4 are proportional. Is detected by differentially connected N-type transistors Q5 and Q6, and the current value Iddout (= k1 * Iref−k2 * Idddq) is output to the power supply current measurement output 7. .

  Here, by setting an appropriate value for the reference current Iref, a current value obtained by subtracting most of the background current of the internal circuit 4 can be taken out of the element. As the value of the reference current Iref, the value of the power supply current is measured by changing some of the values, and the value of the absolute value of the power supply current is the smallest.

  3 outputs a logic signal indicating the magnitude relationship between the reference current Iref and the current (∝Idddq) proportional to the quiescent power supply current Iddq of the internal circuit 4 as the output of the power supply current measurement output pad 8 in the configuration of FIG. It is a block diagram which shows the structure of the integrated circuit element in the 3rd Embodiment of this invention using the power supply current measuring circuit 9C made into. In this embodiment, by changing the value of the reference current Iref little by little to obtain the value of the reference current Iref at the boundary where the logic of the power supply current measurement output pad 8 is inverted, the static power supply current Iddq flowing through the internal circuit 4 is obtained. Measure the value. R1 and r2 are resistors for converting each current into a voltage. CP is a comparator.

  This configuration is an effective method for measuring power supply current when it is difficult to measure current.

  FIG. 4 is a block diagram showing a configuration of an integrated circuit element according to the fourth embodiment of the present invention in which a plurality of internal circuits 4 and 41 are connected to independent power supply lines in the configuration of FIG. In FIG. 4, the first power supply wiring 11 is connected to the second power supply wiring 3 with the power supply voltage VDD2 and the third power supply wiring 15 with the power supply voltage VDD3 via the power supply voltage conversion circuits 2 and 21, respectively. Yes. The internal circuit 4 is connected to the second power supply wiring 3 and the internal circuit 41 is connected to the third power supply wiring 15, and the static power supply currents flow at the values of Iddq1 and Iddq2, respectively. The power supply current measuring circuit 9D outputs the difference Iddq1-Iddq2 between the stationary power supply currents Iddq1 and Iddq2 as the power supply current measurement output 7 from the power supply current measurement output pad 8.

  According to this configuration, the main component of the leakage current of the internal circuit, that is, the background current at the time of Iddq measurement, is the sub-threshold current of the transistor, and the total channel width (W) of the transistors constituting the internal circuits 4 and 41 is made uniform. As a result, the background currents of the internal circuits 4 and 41 can be made substantially equal to each other, and the background current that varies from element to element can be automatically subtracted and output by the integrated circuit element of the fine transistor.

  In order to make the background currents of the internal circuits 4 and 41 more uniform, it is necessary to match the total channel widths (W) of the P-channel and N-channel transistors that are turned off in the internal circuits 4 and 41 when measuring the static power supply.

  FIG. 5 is a timing chart of the current measurement of the integrated circuit element in the embodiment of the present invention. In FIG. 5, the horizontal axis represents time, (a) is the waveform of the power supply current measurement signal, (b) is the waveform of the clock signal of the internal circuit, (c) is the activation signal of the power supply current measurement circuit, (d) Is the current waveform flowing through the internal circuit, and (e) is the output waveform of the measured power supply current.

  First, in synchronization with the rising edge of the power supply current measurement signal, the clock having the cycle T1 is expanded in cycle 3 to T2. In the extended cycle 3, the activation signal of the power source current measuring circuit is generated for the sampling time tm after the time T1, with the settling time ts, and the power source current measurement value is output to the outside of the element. The clock cycle T1 is a cycle in which the integrated circuit element functions normally. Since the state of the internal circuit transitions in the middle of the cycle, the transition current flows, but at the end of the cycle, all state transitions are completed. The current is close to the quiescent power supply current. In the extended cycle 3, the measurement of the power supply current is started after the settling time ts when the fluctuation of the power supply line is stopped from the time T1 when all the state transitions are completed. Thus, in order to selectively extend the clock, the current measurement time can be shortened as compared with the case where all the clocks are extended. Further, by generating a power supply current measurement signal, that is, a clock expansion signal inside the integrated circuit element, the current measurement can be executed as a self-diagnosis function (BIST) inside the integrated circuit, and a highly reliable integrated circuit is provided. be able to.

  Here, the relationship between each signal in FIG. 5 and the circuits in FIGS. 1 to 4 will be described. An integrated circuit element that operates in synchronization with a clock includes a clock generator, and an internal circuit operates in synchronization with the clock. The clock is supplied from the clock generator to the internal circuit.

  The current measurement signal is supplied to the clock generator from the outside of the integrated circuit element. When a BIST circuit (self-diagnostic circuit) is integrated in an integrated circuit element, a current measurement signal is generated at a timing programmed in advance from the BIST circuit and supplied to a clock generator.

  The activation signal is generated from the clock generator with a current measurement signal as a trigger with a desired delay and pulse width, and is supplied to the current measurement circuit. The current measurement circuit outputs a significant power supply current measured during a period in which the activation signal is activated.

  Next, the configuration and operation of the clock expansion means for performing clock expansion will be described with reference to FIGS. For example, as shown in FIG. 12, in the clock generation circuit 121, the clock expansion is realized by providing a strobe circuit 122 based on 2-input AND logic at the output terminal of the clock. According to this circuit, the clock pulse is fixed to 0 while the strobe signal is fixed to 0. The strobe signal is generated with a delay and a pulse width triggered by the power supply current measurement signal. By transitioning the strobe signal during the zero period of the clock signal, the clock is extended to an integral multiple of the clock cycle. 13A shows a clock input to the strobe circuit 122, FIG. 13B shows a strobe signal input to the strobe circuit 122, and FIG. 13C shows a clock output from the strobe circuit 122. Yes.

  When the power supply current is measured by the LSI tester, it is not necessary to extend the clock by the internal signal. This is because the clock is supplied from the LSI tester and the necessary cycle can be extended on the LSI tester side.

  Next, the quality determination of the current measurement of the integrated circuit element in the embodiment of the present invention will be described using FIG. 6 and FIG. FIG. 6 is an explanatory diagram of pass / fail judgment in the conventional Iddqt test. FIG. 4A shows the clock waveform of the internal circuit, and four cycles are shown. FIG. 2B shows a power supply current waveform of the internal circuit corresponding to the same. In FIG. 5B, a large transition current flows in the middle of each cycle, but a constant quiescent power supply current Iddq flows near the end of the cycle. The reason why the value of Iddq varies in each cycle is because the potentials of nodes constituting the internal circuit are different. For example, a defect such as a short circuit of a wiring or a gate oxide film is not detected as a defect unless the circuit is set in a logic state in which current flows due to these defects. FIG. 4C shows the Iddq value obtained for each cycle, and an Iddq value exceeding the pass / fail judgment value Iddqj is regarded as defective. In this example, cycle 3 has an Iddq value exceeding pass / fail judgment value Iddqj, and this sample is a defective product. In this way, when the background current is small, the quality determination is relatively easy.

  FIG. 7 is an explanatory diagram for determining whether or not the current measurement is good in the fine CMOS integrated circuit element. In FIG. 7, (a) is a clock waveform of the internal circuit and shows four cycles. (B), (c), and (d) are power supply current waveforms of the internal circuits of samples A, B, and C, respectively. Sample A is a good sample with a large background current, Sample B has a relatively low background current but has an abnormal Iddq value in cycle 3, and Sample C is a good sample with a standard background current It is.

  In a fine CMOS integrated circuit element, since the background current is sufficiently larger than the defect current, the pass / fail judgment value Iddqj cannot be simply judged as shown in FIG.

  FIG. 7E shows the Iddq value obtained for each cycle. When the pass / fail judgment value Iddqj is set so that the Iddq value of the sample B in cycle 3 is detected as defective, all the samples are displayed. It becomes defective.

  FIG. 7F shows the difference in Iddq value between adjacent cycles for each sample. According to the current measurement of the integrated circuit element in the embodiment of the present invention, the upper limit value is Iddqu and the lower limit value. If there is a difference in the Iddq value within the range of Iddql, the sample B is detected as defective because it exceeds the upper limit value Iddqu and the lower limit value Iddql in cycle 3 -cycle 2 and cycle 4 -cycle 3, respectively. This means that the smaller the variation in the background current from cycle to cycle, the higher the defect detection sensitivity. Further, the difference in the Iddq value is not limited between adjacent cycles, and the same effect can be obtained between arbitrary cycles. Further, when the variation of the background current for each cycle is large, the defect current can be detected effectively by taking the difference between the cycles of the equivalent background current value.

  FIG. 8 is a schematic diagram showing a circuit configuration of an integrated circuit element according to the fifth embodiment of the present invention, and FIG. 9 is a circuit diagram showing a specific configuration of the first differential amplifier circuit 83 in FIG.

  As shown in FIG. 8, the integrated circuit element includes first, second and third P-channel transistors 85, 90 and 92, first and second differential amplifier circuits 83 and 88, and a reference voltage generator. The circuit 97 includes a first power supply line 91 to which electric power is supplied from the outside and a second power supply line 95 to which an internal circuit 94 is connected. The source electrode and the drain electrode of the first and second P-channel transistors 85 and 90 for supplying power are connected in parallel between the first power supply line 91 and the second power supply line 95 to measure current. The source electrode of the third P channel transistor 92 is connected to the first power supply line 91, the output terminal of the first differential amplifier circuit 83 is connected to the gate of the first P channel transistor 85, and the second The output terminal of the differential amplifier circuit 88 is connected to the gates of the second and third P-channel transistors 90 and 92, and the second power supply line 95 is connected to the positive terminals of the first and second differential amplifier circuits 83 and 88. The reference voltage output terminal 97A of the reference voltage generation circuit 97 is fed back to the inverting input terminals 82 and 86, and is connected to the inverting input terminals 81 and 87 of the first and second differential amplifier circuits 83 and 88. Dynamic amplification circuit 83 is shut off A voltage for cutting off the first P-channel transistor 85 is output by the force signal 96, and the second P-channel transistor 92 is drained from the second power supply line 95 with the first P-channel transistor 85 being cut off. A current proportional to the current flowing through the internal circuit 94 is taken out.

  In the above configuration, the first P-channel transistor 85 and the first differential amplifier circuit 83 constitute a first power supply step-down circuit for supplying power to the internal circuit 94, and the second P-channel transistor 90 and the second differential amplifier circuit 83 The differential amplifier circuit 88 constitutes a second power supply step-down circuit for supplying power when the internal circuit 94 is stationary, and the second P-channel transistor 90 and the third P-channel transistor 92 constitute a current mirror circuit. ing.

  When a current flows through the internal circuit 94 and the potential of the second power supply line 95 falls below the output voltage of the reference voltage generation circuit 97 (<the voltage supplied to the first power supply line 91), the first and second differences. The output voltages of the dynamic amplifier circuits 83 and 88 are lowered, the gate potentials of the first and second P-channel transistors 85 and 90 are changed in the direction of decreasing the transistor impedance, and the potential of the second power supply line 95 is raised. Work to let you. Conversely, when the potential of the second power supply line 95 rises above the output voltage of the reference voltage generation circuit 97, the output voltages of the first and second differential amplifier circuits 83 and 88 rise, and the first and second P The potentials of the gates of the channel transistors 85 and 90 change in the direction in which the transistors are cut off, and the increase in the potential of the second power supply line 95 is suppressed. Eventually, the potential of the second power supply line 95 is controlled to become the output voltage of the reference voltage generation circuit 97. 98 is the ground.

  During the state transition of the internal circuit 94, the cutoff input signal 96 is kept at the potential of the first power supply line 91. In this state, the first differential amplifier circuit 83 performs a normal operation. When the cutoff input signal 96 is set to the ground potential when the internal circuit 94 becomes stationary, the current source transistor N3 constituting the first differential input amplifier circuit 83 is biased by the analog switch TG2 as shown in FIG. Disconnected from the voltage 99, the analog switch TG1 cuts off the gate to the ground potential. Further, the pull-up transistor P3 is turned on, and the output 84 is forcibly set to the voltage of the first power supply line 91. For this reason, the first P-channel transistor 85 is cut off, and the power supply current or the like that flows in the internal circuit 94 at rest flows only through the second P-channel transistor 90.

  In FIG. 9, P-channel transistors P1 and P2 and N-channel transistors N1 and N2 constitute the main part of the differential amplifier circuit, and a non-inverting input 82 and an inverting input 81 are connected to the gates of the N-channel transistors N1 and N2. Each has been added.

  The first power supply step-down circuit for supplying power generates a large noise on the second power supply line 95 in order to increase the transient response of the power supply. On the other hand, since the second power supply step-down circuit that supplies the quiescent power supply current does not need high-speed transient response, noise generated in the second power supply line 95 can be suppressed to a low level. That is, at the time of measuring a stationary power supply, the first power supply step-down circuit for supplying power with a large noise is stopped, and only the second power supply step-down circuit with low noise is activated.

  The transistor size is designed so that the second P-channel transistor 90 is always in the saturation region, and is proportional to the current flowing through the second P-channel transistor 90 from the drain of the third P-channel transistor 92 having a common gate electrode. The current output 93 can be taken out. At this time, the third P-channel transistor 92 needs to be biased to about the voltage of the second power supply line 95.

  The second P-channel transistor 90 and the third P-channel transistor 92 have the same channel length L in order to improve the accuracy of the power supply current, and the channel width W of the third P-channel transistor 92 in order to obtain a current gain. Is set to N times the second P-channel transistor 90 (N is an arbitrary numerical value). The current output 93 is proportional to the ratio of the channel width W of the second and third P-channel transistors 90 and 92. When the quiescent power supply current of the internal circuit 94 is Iddq, the current output 93 has a value of N * Idddq. . Since the size of the second P-channel transistor 90 does not need to supply a large transient current, it can be made sufficiently smaller than the size of the first P-channel transistor 85. For example, the size of the second P-channel transistor 90 can be set to about 1/100 of the size of the first P-channel transistor 85. Therefore, the size of the third P-channel transistor 92 can be made larger than the size of the second P-channel transistor 90, and the leakage current of the internal circuit 94 that flows at rest can be amplified and output. With the amplified current output 93, it is possible to determine whether the current value is good or not at high speed. The reduction in the size of the second P-channel transistor 90 contributes to the increase in the current amplification gain of the third P-channel transistor 92.

  FIG. 10 is a schematic diagram showing a circuit configuration of an integrated circuit element according to the sixth embodiment of the present invention in which the configuration of FIG. 8 is improved. In this integrated circuit element, the output terminal of the second differential amplifier circuit 88 is connected to the gates of the second and third P-channel transistors 90 and 92 through the low-pass filter 100, so that the second differential amplifier. The fluctuation of the output of the circuit 88 becomes more gradual, and a stable current output 93 is obtained. Other effects are the same as those of FIG.

  FIG. 11 is a schematic diagram showing a circuit configuration of an integrated circuit element according to the seventh embodiment of the present invention. In FIG. 11, a second P-channel transistor 90 and a third P-channel transistor 103, and a second P-channel transistor 90 and a fourth P-channel transistor 104 are each a transistor pair having a current mirror configuration. The gates of the fourth P-channel transistors 103 and 104 are connected to gate voltage storage means 102 and 105 each consisting of a capacitor, and the second differential amplifier circuit 88 is connected via the low-pass filter 100 and the analog switches 101A and 101B, respectively. Is connected to the output end of.

  The analog switches 101A and 101B are opened and closed by control signals 110 and 111. For example, when the analog switch 101A connected to the gate of the third P-channel transistor 103 is opened, the potential of the gate of the second P-channel transistor 90 is transmitted to the gate of the third P-channel transistor 103 and configured by a capacitor. Is written in the gate voltage storage means 102. When the analog switch 101A is closed, the gate potential is held at a value just before the analog switch 101A is closed, and the drain of the third P-channel transistor 103 flows to the third P-channel transistor 103 just before the analog switch 101A is closed. The current output (I2) 109 that has been output is output. Similarly, the current output (I1) 108 is also output to the fourth P-channel transistor 104. By changing the timing of closing the analog switches 101A and 101B, the values of the internal currents at any two different times can be obtained at the same time. A current difference I0 (= I1-I2) between any two times, that is, any clock cycle can be obtained by the current difference circuit 106, and the background current generated between the clocks as described in FIG. Can be deducted.

  8, 10 and 11, the same reference voltage is applied to the inverting input terminals of the first and second differential amplifier circuits 83 and 88, but the reference voltage generating circuits having different output voltages are connected to each other. By doing so, the power supply voltage at the time of measuring the quiescent power supply current can be set lower than that during normal circuit operation. Since the circuit state transition has been completed during the measurement of the stationary power supply, there is no problem in the circuit operation even if the power supply voltage is lowered to some extent. If the power supply voltage at the time of measuring the quiescent power supply current is set lower than that during normal circuit operation, the background current due to the leakage current of the transistor decreases together with the power supply voltage, so that the detection of a defective current can be facilitated.

  In each of the above embodiments, the power supply voltage applied from the outside is stepped down and used as the power supply voltage of the internal circuit. However, the present invention is also applied to the case where the power supply drive P-channel transistor does not step down. It can be applied and the same effect can be obtained.

  Since the integrated circuit element according to the present invention can extract the current flowing in the internal circuit to the outside for the Iddq test and has a built-in power supply current measuring circuit, the inductance component is an external power supply current measuring circuit. It is useful as a fine CMOS integrated circuit or the like having a built-in power supply voltage conversion circuit for converting (stepping down, etc.) the power supply voltage.

It is a block diagram which shows the structure of the 1st integrated circuit element in embodiment of this invention. It is a block diagram which shows the structure of the 2nd integrated circuit element in embodiment of this invention. It is a block diagram which shows the structure of the 3rd integrated circuit element in embodiment of this invention. It is a block diagram which shows the structure of the 4th integrated circuit element in embodiment of this invention. It is a timing diagram of the current measurement of the integrated circuit element in the embodiment of the present invention. It is explanatory drawing about the quality determination of the current measurement of the integrated circuit element in embodiment of this invention. It is explanatory drawing about the quality determination of the current measurement of the integrated circuit element in embodiment of this invention. It is the schematic which shows the circuit structure of the integrated circuit element in the 5th Embodiment of this invention. FIG. 9 is a circuit diagram showing a specific configuration of a first differential amplifier circuit in the integrated circuit element of FIG. 8. It is the schematic which shows the circuit structure of the integrated circuit element in the 5th Embodiment of this invention. It is the schematic which shows the circuit structure of the integrated circuit element in the 7th Embodiment of this invention. It is a circuit diagram which shows the specific structure of a clock expansion | extension means. It is a time chart which shows operation | movement of a clock expansion | extension means.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit element 2 Power supply voltage conversion circuit 3 2nd power supply wiring 4 Internal circuit 5 Ground wiring 6 Ground pad 7 Power supply current measurement output 8 Power supply current measurement output pad 9, 9B, 9C, 9D Power supply current measurement circuit 10 For power supply Pad 11 First power supply wiring 12 Signal pad 81 Inverted input terminal 82 Normal input terminal 83 First differential amplifier circuit 84 Output 85 First P-channel transistor 86 Inverted input terminal 87 Normal input terminal 88 First Differential amplifier circuit 89 Output 90 9th P-channel transistor 91 1st power supply line 92 3rd P-channel transistor 93 Current output 94 Internal circuit 95 2nd power supply line 96 Cutoff input signal 97 Reference voltage generating circuit 98 Ground 99 Bias voltage 100 Low-pass filter 101A, 101B Analog switch 102 Gate voltage storage means 103 3 of the P-channel transistor 104 fourth P-channel transistor 105 gate voltage storing means 106 current difference circuit 107 current output 108 current output 109 current output 110 and 111 control signals

Claims (7)

A clock provided with power supply voltage conversion means for converting power supply voltage from the first power supply wiring to the second power supply wiring to supply power, and a power supply current measuring circuit for measuring the power supply current flowing through the second power supply wiring. An integrated circuit element operating synchronously,
It has a clock generation circuit to which a power supply current measurement signal is input,
By the power supply current measurement signals generated by the integrated circuit inside, selectively extending the clock period,
An integrated circuit device, wherein a power supply current is measured within the selected and extended clock period. 2. The integrated circuit element according to claim 1, wherein a current value proportional to the power supply current flowing through the second power supply wiring is output as an external signal or an internal signal of the integrated circuit element as an output of the power supply current measuring circuit . A current value proportional to the difference between the current proportional to the reference current supplied from the outside of the integrated circuit element as the output of the power supply current measuring circuit and the current proportional to the current flowing through the second power supply wiring is an external signal of the integrated circuit element. 2. The integrated circuit element according to claim 1, wherein the integrated circuit element is output as an internal signal . A logic signal indicating a magnitude relationship between a reference current supplied from the outside of the integrated circuit element as an output of the power supply current measuring circuit and a current value proportional to a current flowing through the second power supply wiring is an external signal or an internal signal of the integrated circuit element. integrated circuit device according to claim 1, wherein the output as. 2. The integrated circuit according to claim 1, wherein the power supply current measuring circuit measures a power supply current in synchronization with the expanded clock cycle, and uses a difference between power supply current values between different phases in the same clock as a measured value. Circuit element. 6. The integrated circuit element according to claim 5, wherein a current value proportional to a difference between power supply current values between different phases in the same clock is output as an external signal or an internal signal of the integrated circuit element. A logic signal indicating a magnitude relationship between a current proportional to a reference current supplied from an external pad and a current value proportional to a difference between power supply current values between different phases in the same clock is used as an external signal or an internal signal of an integrated circuit element. 6. The integrated circuit element according to claim 5, wherein the integrated circuit element is output.

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