JP4593540B2 - HDLC multiple monitor device - Google Patents

Description

  The present invention relates to an HDLC multiple monitor apparatus for displaying and displaying HDLC message frames on a plurality of transmission paths on a single terminal.

  FIG. 6 shows a conventional HDLC multiple monitor apparatus of this type (not related to a known literature). In FIG. 6, message frames transmitted and received between the master nodes BSC1a, 1b, and 1c and slave nodes BS2a, 2b, and 2c in the network via the three transmission lines X, Y, and Z are displayed on the line monitors 3a, 3b. , 3c are collected and stored, and the message information is displayed on the monitor terminal 4 based on the information.

  In the line monitors 3a, 3b, and 3c, one of the line monitors is a master, and clock supply and synchronization timing are given to the other line monitors using the synchronization control signal C, and time stamps are assigned to all the line monitors. Time synchronization is performed to match the internal timer.

  An example of a message frame group transmitted and received between BSC1 and BS2 is shown in FIG. In FIG. 2, [1] and [2] are instructions and responses for new line settings, [3] and [4] are instructions and responses for changing line settings, and [5] and [6] are instructions for releasing line settings. And a response. The message information [1] to [6] is transmitted / received to / from the transmission path X and the transmission path Z, and the message information [1] [2] [5] [6] is transmitted / received to the transmission path Y. .

  FIG. 7 shows the relationship between the generation order of message frames in the transmission path X, transmission path Y, and transmission path Z and the display order of time stamps given by the line monitor. Message frames are generated in the three transmission paths in the order of (1) 'to (16)'. In order to identify the time sequence of message frames, the line monitors 3a, 3b, 3c generally have a time stamp function, and the time stamp is added by checking the error detection code processing at the end of the message frame. Therefore, it is performed after the message frame is received. The time stamp application positions by the line monitors 3a, 3b, 3c are shown by (1) to (16) in FIG. This time stamp information is associated with the message frame and stored as log information M in the line monitors 3a, 3b, 3c.

  The log information accumulated in the line monitors 3a, 3b, 3c is transferred to the monitor terminal 4 by daisy chain connection of the line monitors 3a, 3b, 3c. The monitor terminal 4 collects log information of the transmission line X from the line monitor 3a, collects log information of the transmission line Y from the line monitor 3b, collects log information of the transmission line Z from the line monitor 3c, and refers to the time of the time stamp. Determine the message display order.

  Since the time stamping of the line monitor is performed after the message frame is received, in the case of the message display that occurs at the same time on a plurality of transmission paths, a phenomenon may occur in which the display result on the monitor terminal 4 is reversed. A specific example thereof is shown in FIG. In message frames X [2] and Z [1], the actual message generation order is Z [1], X [2], but the display order on monitor terminal 4 is X [2], Z [1. The order is reversed. Similarly, order inversion occurs in the message frames of X [3] and Z [2], X [4] and Y [5] and Z [3], and X [5] and Z [4].

  Note that none of the prior arts related to the present invention relates to monitor display of HDLC message frames, and processing on the sending side is required, but when data conversion processing such as encryption processing is parallelized In order to avoid overtaking of packets due to the length of processing delay due to the packet length, a technique for determining the transmission time to the data conversion device based on the order information and the reception time information given to the packet (for example, Patent Document 1) or a technique for sending time stamp information added to packet data, and guaranteeing a common time as a common reference axis between information for each node based on this time stamp information (see, for example, Patent Document 2) It has been known.

Japanese Unexamined Patent Publication No. 2003-218938 (pages 4-5, FIG. 1) Japanese Patent Publication No. 07-058999 (2nd page-4th page)

  In the conventional HDLC multiple monitor apparatus shown in FIG. 6, when a message frame on a plurality of transmission paths is observed by one monitor terminal, if the message frame is generated on the plurality of transmission paths at the same time, the message frame is displayed on the monitor. If the result is reversed, there is no problem if message frames that occur at the same time do not affect each other. However, if there is a mutual effect, the problem cannot be displayed correctly in the order in which the message frames occur, making it difficult to analyze the problem. There is.

  Therefore, an object of the present invention is to display the display result of message information on the monitor terminal so that it matches the actual message frame generation order even when message frames on multiple transmission paths occur at the same time. An object of the present invention is to provide an HDLC multiple monitor device that can be used.

  The HDLC multiple monitor apparatus of the present invention is an HDLC multiple monitor apparatus that displays message frames on a plurality of transmission paths on one monitor terminal (4 in FIG. 1), between the transmission path and the line monitor (3 in FIG. 1). The transmission path identification frame including the input time stamp information indicating the message detection time on the transmission path and the output time stamp information indicating the output time of the transmission path identification frame is added to the message frame and sent to the line monitor at a higher rate than the message frame. A multiplex circuit (100 in FIG. 1) for multiplex output is provided, and the line monitor assigns the respective time stamp information after each reception of the transmission path identification frame and the message frame, and adds the transmission path identification frame and the message frame. Accumulate time stamp information as log information and output to monitor terminal And Rukoto, monitor terminal, using input and output time stamp information in the time stamp and the transmission path identification frame of the captured line monitor grant from the line monitor, characterized by arithmetic processing of the message frame generation time.

  More specifically, the multiplex circuit (100 in FIG. 1) has a timer counter (104 in FIG. 1) that displays the time as a count value, a transmission line message frame, and a count value in a one-to-one correspondence with the transmission line. The message frame is detected from the memory (101 in FIG. 1) that latches and stores the input time stamp information as the input time stamp information and the transmission path signal input from the transmission path, and at the detection timing, first the timer count value and then the message frame Is stored in the memory, and whether the message frame stored in the memory can be read is checked corresponding to the transmission path. When the message frame is stored in the memory and is determined to be read out, the transmission path identification frame control signal is first Subsequently, transmission is performed by a memory control unit (102 in FIG. 1) that outputs a selection unit control signal and a transmission path identification frame control signal. A transmission path identification frame generator (103 in FIG. 1) that generates transmission path identification information in the identification frame and latches the timer count value at the time when the transmission path identification frame is output to generate output time stamp information. The message frame and the input time stamp information are selected from the output of the memory by the selection unit control signal, and the transmission path identification information and the output time stamp information are selected from the output of the transmission path identification frame generation unit, respectively. And a selection unit (105 in FIG. 1) that outputs the transmission path identification frame to the line monitor as a multiplexed circuit output signal at a higher rate than the input message frame.

  In the multiplexing circuit (100 in FIG. 1), the transmission path identification frame is added immediately before the message frame.

  Further, the monitor terminal (4 in FIG. 1) is a value obtained by subtracting the message detection time on the transmission path from the transmission path identification frame output time to the frame length of the transmission path identification frame from the time stamp of the transmission path identification frame provided by the line monitor. The message frame generation time is calculated by subtracting the multiplex circuit delay time obtained by adding.

  The HDLC multiplex monitor apparatus of the present invention is provided with a multiplex circuit having a function of adding a transmission line identification frame having input / output time stamp information to a message frame, and inputs it to a monitor terminal via a line monitor. A configuration in which the actual message frame occurrence time is calculated and estimated from the time stamp information given by inputting the frame and the transmission path identification frame to the line monitor and the input / output time stamp information in the transmission path identification frame As a result, the display result of the message information is displayed in the same order as the actual message frame generation order, and the analysis performance at the monitor terminal can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of configuration]
The configuration of the HDLC multiple monitor apparatus of the present invention is shown in FIG. In FIG. 1, message frames transmitted / received between the master nodes BSC1a, 1b, 1c and the slave nodes BS2a, 2b, 2c in the network via the three transmission lines X, Y, Z are routed through the multiplexing circuit 100. Are collected and stored by the line monitor 3 and the message information is displayed on the monitor terminal 4 based on the information. The multiplexing circuit 100 has a function of multiplexing and outputting the message frames on the transmission lines X, Y, and Z, and outputting a transmission line identification frame immediately before the message frame of the output signal.

  The multiplexing circuit 100 includes a memory 101 that stores message frames of transmission paths X, Y, and Z, a memory control unit 102 that controls the memory 101, an identification frame generation unit 103 that generates transmission path identification frames, and a transmission path identification A timer counter 104 for generating time stamp information in the frame, and a selection unit 105 that selects and outputs a message frame and a transmission path identification frame multiplexed under the control of the memory control unit 102.

  The components of the multiplex circuit 100 will be described in more detail. The memory 101 is composed of memories 101a, 101b, and 101c having a one-to-one correspondence with the transmission lines X, Y, and Z. In response to the memory control signal S1, the memories 101a, 101b, and 101c latch and store the timer count value S2 as input time stamp information in addition to the message frames of the transmission lines X, Y, and Z, and the stored input time stamp information The message frame is output to the selection unit 105 as memory output signals S3a, S3b, and S3c.

  The memory control unit 102 detects a message frame from transmission path signals input from the transmission paths X, Y, and Z. The timer count value S2 and then the message frame are stored in the memory 101 by the memory control signal S1 at the message frame detection timing. Further, the memory control unit 102 checks whether the message frame stored in the memory 101 can be read out in the order of the memory 101a, the memory 101b, and the memory 101c.

  When it is determined that the message frame has been stored in the memory 101 and can be read out, the transmission path identification frame control signal S4 is first output to the transmission path identification frame generation unit 103, and then the selection unit control signal S6 is output to the selection unit 105. The transmission path identification frame control signal S4 includes information for identifying the transmission paths X, Y, and Z.

  FIG. 3 shows the structure of the transmission path identification frame. As is apparent from FIG. 3, ST bits are arranged at the beginning and end of the transmission path identification frame, and transmission path identification information, input time stamp information, output time stamp information, and FCS bits are arranged in this order.

  When the transmission path identification frame control signal S4 is input, the transmission path identification frame generation unit 103 generates ST bits and transmission path identification information in the transmission path identification frame. The output time stamp information is generated by latching the timer count value S2 at the time when the transmission path identification frame is output. The generated ST bit, transmission path identification information, and output time stamp information are output to selection section 105 as identification frame output signal S5. The timer counter 104 is a counter that displays time with a count value.

  The selection unit 105 selects a message frame and input time stamp information from the memory output signal S3 and other information from the identification frame output signal S5 according to the selection unit control signal S6, and generates a transmission path identification frame. Specifically, ST bits, transmission path identification information, input time stamp information, and output time stamp information are inserted into predetermined bit positions of the transmission path identification frame shown in FIG. 3, and FCS bits are generated from these information. . The message frame and the generated transmission path identification frame are output to the line monitor 3 at a higher rate than the input message frame as the multiplexed circuit output signal S7. As a result, in the multiplex circuit output signal S7, the transmission path identification frame can be added immediately before the corresponding message frame.

  When the transmission line identification frame and the message frame output from the multiplexing circuit 100 are input, the line monitor 3 gives time stamp information after each reception. Then, the transmission path identification frame, the message frame, and the assigned time stamp information are accumulated as log information and output to the monitor terminal 4.

  The monitor terminal 4 inputs the log information M from the line monitor 3, and based on the time stamp information given to the transmission path identification frame and the input / output time stamp information in the transmission path identification frame, the message output time (estimated value) By performing the calculation, the message frame generation time between BSC1 and BS2 is estimated. The monitor terminal 4 determines the display order of the message information from the result of the message output time (estimated value). As a result, the display result of the message information on the monitor terminal 4 can be displayed in exact agreement with the actual message frame generation order, and the analysis performance at the monitor terminal 4 can be improved.

[Description of operation]
Next, the operation of the HDLC multiple monitor apparatus will be described. Again, an example of a message frame group transmitted and received between BSC1 and BS2 is as shown in FIG. In FIG. 2, a setting request SetUP_REQ is first sent from BSC1 to BS2 ([1]), and a setting request response SetUP_RSP is sent from BS2 to BSC1 ([2]). Subsequently, there is a reset request ReConf_REQ for instructing the line setting change from BSC1 to BS2 ([3]), and a reset request response ReConf_RSP is sent from BS2 to BSC1 ([4]). Finally, there is a line setup release request Rel_REQ from BSC1 to BS2 ([5]), and a release request response Rel_RSP is sent from BS2 to BSC1 ([6]). The message information [1] to [6] is transmitted / received to / from the transmission path X and the transmission path Z, and the message information [1] [2] [5] [6] is transmitted / received to the transmission path Y. .

  FIG. 4 shows the time relationship between the generation order of message frames in the transmission path X, transmission path Y, and transmission path Z and the multiplex circuit output signal S7. The message frame generation order in the transmission path X, transmission path Y, and transmission path Z is the order from (1) 'to (16)'. The transmission path signal between BSC1 and BS2 is input to the multiplexing circuit 100, and the message frame is stored in the memory 101. The transmission path signal is also input to the memory control unit 102, and the memory control unit 102 detects a message frame. The timer count value S2 is latched by the memory control signal S1 at the message frame detection timing, and the latched timer count value S2 is stored in the memory 101 as input time stamp information.

  When the message frame is stored in the memory 101 and the memory control unit 102 determines that it can be read, the transmission channel identification frame control signal S4 is first transmitted to the transmission channel identification frame generation unit 103, and then the selection unit control signal S6 is selected. Output to the unit 105. In response to the transmission channel identification frame control signal S4, the identification frame generation unit 103 inserts the ST bit, transmission channel identification information, and output time stamp information into a predetermined bit position of the transmission channel identification frame and inputs them to the selection unit 105. To do. The input time stamp information is read from the memory 101 and input to the selection unit 105.

  The selection unit 105 generates a transmission line identification frame by selecting input time stamp information from the memory output signal S3 and other information from the identification frame output signal S5 in accordance with the control signal S6 from the memory control unit 102 to generate a line monitor. 3 outputs the multiplex circuit output signal S7. The message frame is read from the memory 101 and output to the line monitor 3 via the selection unit 105 as a part of the multiplexed circuit output signal S7 to the line monitor 3 at a higher rate than the input message frame.

  Referring to FIG. 4, in the multiplexed circuit output signal S7, the transmission path identification frame is added immediately before the corresponding message frame. FIG. 5 shows the time relationship between the input message frame and the multiplex circuit output signal S7 together with the time stamp assigned to the line monitor.

  In FIG. 5, an input time stamp T1 is indicated by input time stamp information in the transmission path identification frame, and indicates a message reception time. The output time stamp T2 is indicated by the output time stamp information in the transmission path identification frame, and indicates the transmission path identification frame output time. On the other hand, the time stamp T3 is a time stamp given to the line monitor for the transmission line identification frame, and the time stamp T4 is a time stamp given to the line monitor for the message frame. Therefore, T3-T2 = T5 is the frame length of the transmission path identification frame.

  The transmission path identification frame and message frame output from the multiplexing circuit 100 are accumulated as log information in the line monitor 3, and the time stamps attached to the transmission path identification frame and message frame are also accumulated as log information. The monitor terminal 4 inputs the log information M from the line monitor 3, and based on the time stamp information given to the transmission path identification frame and the input / output time stamp information in the transmission path identification frame, the message output time ( Estimated value) T5 is calculated. The value in [] indicates the multi-circuit delay time.

T5 = T3- [T5 + (T2-T1)]
Then, the display order of the message information is determined based on the calculated message output time (estimated value) T5. As a result, the monitor terminal 4 can display the message information in the order in which the messages are generated regardless of the length of the message frame.

The block diagram which shows the structure of the HDLC multiple monitor apparatus of this invention The figure which shows an example of the general message frame group transmitted / received between a master node and a slave node The figure which shows the structure of the transmission-line identification frame in this invention Timing chart of HDLC multiple monitor device of the present invention The figure which shows the time relationship of the input message frame and multiple circuit output signal S7 in this invention 1 is a diagram showing an example of a conventional HDLC multiple monitor device Timing chart of HDLC multiple monitor device shown in FIG.

Explanation of symbols

1 Master node (BSC)
2 Slave node (BS)
3 Line monitor 4 Monitor terminal
100 multiple circuits
101 memory
102 Memory controller
103 Identification frame generator
104 timer counter
105 Selection unit C Synchronization control signal M Log information X, Y, Z Transmission path S1 Memory control signal S2 Timer counter value S3 Memory output signal S4 Identification frame control signal S5 Identification frame output signal S6 Selection unit control signal S7 Multiplex circuit output signal

Claims (4)

In an HDLC multiple monitor device that displays message frames on multiple transmission paths on one monitor terminal,
A transmission path identification frame including input time stamp information indicating a message detection time on the transmission path and output time stamp information indicating a transmission path identification frame output time is added to the message frame between the transmission path and the line monitor. And a multiplex circuit for multiplex output to the line monitor at a higher rate than the message frame,
The line monitor adds time stamp information after each reception of the transmission path identification frame and message frame, accumulates the transmission path identification frame and message frame, and the added time stamp information as log information. Output to
The monitor terminal computes the message frame occurrence time using the time stamp provided by the line monitor acquired from the line monitor and the input / output time stamp information in the transmission path identification frame. Multiple monitor device. The multiplexing circuit is:
A timer counter that displays the time as a count value;
A memory that latches and stores the count value as the input time stamp information in addition to the message frame of the transmission path in a one-to-one correspondence with the transmission path;
The message frame is detected from the transmission line signal input from the transmission line, and at the detection timing, first the timer count value and then the message frame are stored in the memory, and the message frame stored in the memory can be read. If the message frame is stored in the memory and it is determined that the message frame can be read out, first, a memory control unit that outputs a transmission channel identification frame control signal and then a selection unit control signal;
Based on the transmission path identification frame control signal, transmission path identification information in the transmission path identification frame is generated, and the timer count value is latched at the time when the transmission path identification frame is output to generate the output time stamp information. A transmission line identification frame generation unit;
A message frame and input time stamp information are selected from the output of the memory, and transmission path identification information and output time stamp information are selected from the output of the transmission path identification frame generation section, respectively, according to the selection unit control signal, and are generated as a message frame. 2. The HDLC multiple monitor apparatus according to claim 1, further comprising: a selection unit that outputs the transmission path identification frame as a multiple circuit output signal to the line monitor at a higher rate than the input message frame.   3. The HDLC multiple monitor apparatus according to claim 1, wherein the transmission line identification frame is added immediately before the message frame in the multiplexing circuit. The monitor terminal adds a value obtained by subtracting a message detection time on the transmission path from a transmission time of the transmission path identification frame to a frame length of the transmission path identification frame from a time stamp of the transmission path identification frame by the line monitor addition. 4. The HDLC multiplex monitor apparatus according to claim 1, wherein the message frame generation time is calculated by subtracting the multiplex circuit delay time obtained in this manner.

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